JP2016138838A - Hall element drive circuit and sensor circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce switching noise generated when a flow direction of drive current to a Hall element is switched.SOLUTION: A Hall element drive circuit includes; a signal switching unit 2 which is located between a power supply unit 6 that outputs drive current I1 and a Hall element 5 and is controlled to be switched either to a first switching state in which the drive current I1 is supplied to a first terminal pair 5a, 5c of the Hall element 5, or to a second switching state in which the drive current I1 is supplied to a second terminal pair 5b, 5c; a switching controller 4 for controlling the signal switching unit 2 to switch between the switching states; and a switch 3 which is located between the power supply unit 6 and the signal switching unit 2 and is controlled to be switched either to an ON state in which the drive current I1 from the power supply unit 6 is allowed to be outputted to the signal switching unit 2 or to an OFF state in which output of the drive current I1 to the signal switching unit 2 is blocked. The switching unit 4 is configured to provide the above mentioned control to the switch 3 and to provide switching control to the signal switching unit 2 only while the switch 3 is in the OFF state.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a hall element driving circuit for driving a hall element and a sensor circuit having the hall element driving circuit.

  As this type of sensor circuit, a sensor circuit disclosed in Patent Document 1 below is known. This sensor circuit switches the flow direction of excitation current (drive current) supplied to the Hall element (direction of excitation current flowing through the Hall element) and the detection direction of Hall voltage, thereby offsetting the Hall element and its peripheral circuits. It has a configuration to cancel. The sensor circuit also has a switch for switching between the direction in which the excitation current flows and the direction in which the Hall voltage is detected. For this reason, in this sensor circuit, an undesirable surge noise is generated when the switch is switched. In order to eliminate the influence of this switching noise, in this sensor circuit, first, the sampling operation of the sample-and-hold circuit is performed with the clock generated in the middle part of the switching cycle (that is, the switch circuit is temporally changed). Sampling is performed outside the switching operation).

  However, transient fluctuations may be induced in the output signal of the Hall voltage detection amplifier (Hall amplifier) for a relatively long period of time due to the switching noise. If the transitional fluctuation continues for more than the time interval from the switching operation to the start of the sampling operation, the influence of switching noise may remain during the sampling operation of the sample and hold circuit. Therefore, this sensor circuit employs a configuration that reduces the effect of switching noise on the sample-and-hold circuit by substantially reducing the amplifier gain of the amplifier described above during the switch switching operation.

Japanese Patent No. 3022995 (page 3-5, Fig. 3-4)

  However, the sensor circuit described above has the following problems to be solved. That is, in this sensor circuit, four single-pole double-throw switches are provided as switches for switching the exciting current flow direction and the Hall voltage detection direction, and two single-pole switches for switching the exciting current flow direction. One single-pole double-throw switch of the double-throw switches is disposed between the power supply voltage and the two contacts of the Hall element, and the other single-pole double-throw switch is connected to the ground and the other two of the Hall element. It is arranged between the contacts.

  Specifically, the one single-pole double-throw switch described above has one of each of the two contact pairs diagonally opposed to the Hall element in a state where the power supply voltage is constantly applied to the common contact (c contact). The a and b contacts are connected to the contacts. The other single-pole double-throw switch has its a and b contacts connected to the other contact of each of the two contact pairs in a state where the common contact (c contact) is always applied to the ground. Has been.

  Therefore, in the sensor circuit described above, in the state where the excitation current (drive current) flows through one contact pair of the Hall element, the excitation current is configured to be switched from the one contact pair to the other contact pair. In this sensor circuit, the switching noise generated when switching the direction of flow of this exciting current becomes large, and even if it has various configurations adopted in the above-mentioned conventional sensor circuit, the influence of the switching noise is reduced. There is a problem to be solved that cannot be cut.

  The present invention has been made to solve such a problem, and provides a Hall element drive circuit and a sensor circuit that can reduce switching noise generated when the flow direction of the drive current (excitation current) to the Hall element is switched. The main purpose is to do.

  In order to achieve the above object, a Hall element drive circuit according to claim 1 is provided between a power supply unit that outputs a drive current supplied to a Hall element having a first terminal pair and a second terminal pair, and the Hall element. And switching to one of a first switching state in which the driving current is supplied to the first terminal pair and a second switching state in which the driving current is supplied to the second terminal pair. A signal switching unit to be controlled, and a switching control unit for controlling the transition of the signal switching unit from the first switching state to the second switching state and the transition from the second switching state to the first switching state; An on-state that is disposed between the power supply unit and the signal switching unit and permits output of the drive current from the power supply unit to the signal switching unit , And the signal off of the drive current A switch unit that is controlled to be switched to any one of an off state that prevents output to the unit, and the switching control unit is configured to switch the switch unit from the on state to the off state, and to turn off the switch unit. Control of the transition from the state to the ON state is performed, and switching control for the signal switching unit is executed only during a period in which the switch unit is transitioned to the OFF state.

  According to a second aspect of the present invention, there is provided a sensor circuit according to the first aspect, the first detection voltage generated between the second terminal pair in the first switching state, and the second switching state. And a signal processing unit for detecting the Hall voltage of the Hall element in which the offset voltage for the Hall element is canceled by performing signal processing on the second detection voltage generated between the first terminal pair.

  According to the Hall element drive circuit according to claim 1 and the sensor circuit according to claim 2, since the switch portion is provided, the signal switching portion is switched between the two switching states in a state where the drive current is not supplied. Since switching from one of the two to the other (switching the direction of flow of the drive current flowing through the Hall element) is possible, switching noise generated at the time of switching compared to a configuration in which the drive current is supplied Can be greatly reduced.

2 is a configuration diagram of a Hall element drive circuit 1 and a sensor circuit 8. FIG. 6 is a waveform diagram for explaining operations of the Hall element drive circuit 1 and the sensor circuit 8. FIG. It is a block diagram of the Hall element drive circuit 1 and the sensor circuit 8A. It is a block diagram of Hall element drive circuit 1A and sensor circuit 8B. It is a block diagram of the Hall element drive circuit 1 and the sensor circuit 8C. It is a wave form diagram for demonstrating operation | movement of the Hall element drive circuit 1 and the sensor circuit 8C.

  Hereinafter, embodiments of the Hall element drive circuit and the sensor circuit will be described with reference to the accompanying drawings.

  First, each configuration of the Hall element drive circuit and the sensor circuit will be described with reference to the drawings.

  First, the configuration of the Hall element drive circuit 1 as the Hall element drive circuit shown in FIG. 1 will be described. The hall element drive circuit 1 includes a signal switching unit 2, a switch unit 3, and a switching control unit 4, and is provided on any one of the first terminal pair 5a, 5c and the second terminal pair 5b, 5d of the hall element 5. On the other hand, the drive current I1 from the power supply unit 6 is switched (the flow direction of the drive current I1 to the Hall element 5 is switched) and can be supplied.

  The hall element 5 driven by the hall element drive circuit 1 is formed in a shape in which the plan view has a symmetrical shape such as a square or a cross shape, and the above terminal pairs 5a and 5b are formed at the four corners. , 5c, 5d are arranged counterclockwise or clockwise (in this example, counterclockwise as an example). The Hall element 5 is supplied with the drive current I1 in a state where the drive current I1 is supplied to any one of the first terminal pair 5a, 5c and the second terminal pair 5b, 5d. A voltage proportional to the magnetic flux density of the magnetic flux passing through the Hall element 5 (hereinafter also referred to as Hall voltage Vh) is generated between the other terminal pair that is not.

  However, the Hall element 5 has a characteristic that an offset voltage Vos having a substantially constant voltage value is generated between the other terminals even when the magnetic flux density is zero due to manufacturing variations. Because of this characteristic, the Hall element 5 outputs the detection voltage Vd including the offset voltage Vos together with the Hall voltage Vh from between the terminal pair to which the drive current I1 is not supplied. In the following, the detection voltage Vd output from between the first terminal pair 5a, 5c is referred to as a second detection voltage Vd2 (= −Vh + Vos) and output from between the second terminal pair 5b, 5d. This is expressed as a first detection voltage Vd1 (= Vh + Vos).

  In this case, the power supply unit 6 is constituted by a constant voltage DC power supply or a constant current DC power supply, and outputs a constant voltage or a constant current to the Hall element 5. In this example, as an example, the power supply unit 6 is configured by a constant voltage DC power supply, and supplies the drive current I1 to the Hall element 5 by outputting the constant voltage V1 to the Hall element 5. May be configured by a constant current DC power supply, and a drive current I1 as a constant current may be supplied to the Hall element 5.

  The Hall element drive circuit 1 includes a first detection voltage Vd1 generated between the second terminal pair 5b and 5d when the drive current I1 is supplied to the first terminal pair 5a and 5c, and the drive current I1. Is switched to and output the second detection voltage Vd2 generated between the first terminal pair 5a and 5c in a state in which is supplied to the second terminal pair 5b and 5d. The Hall element drive circuit 1 constitutes a sensor circuit 8 together with the Hall element 5 and a signal processing unit 7 described later.

  Specifically, the signal switching unit 2 includes four switches (single-pole double-throw switches as an example) 11, 12, 13, and 14 as an example, and the switch 11 has a c contact via the switch unit 3 as a power source. The contact a is connected to one terminal 5a of the first terminal pair 5a, 5c, and the contact b is connected to one terminal 5d of the second terminal pair 5b, 5d. Thus, it is disposed between the power supply unit 6 and the Hall element 5. The switch 12 has its c contact connected to the reference potential (ground G) of the Hall element drive circuit 1, its a contact connected to the other terminal 5c of the first terminal pair 5a, 5c, and b The contact is connected to the other terminal 5b of the second terminal pair 5b, 5d, so that it is disposed between the reference potential (ground G) and the Hall element 5.

  Further, the switch 13 is connected to the signal processing unit 7 (specifically, the non-inverting input terminal of the differential amplifier 21 that constitutes a part of the signal processing unit 7), and the contact c is connected to the switch 13. The signal processing unit 7 and the Hall element 5 are connected to one terminal 5d of the second terminal pair 5b, 5d and its b contact is connected to one terminal 5a of the first terminal pair 5a, 5c. Between the two. The switch 14 has a contact c connected to the signal processing unit 7 (specifically, the inverting input terminal of the differential amplifier 21 constituting a part of the signal processing unit 7), and the contact a is the second. The terminal 5b is connected to the other terminal 5b of the terminal pair 5b and 5d, and the contact b is connected to the other terminal 5c of the first terminal pair 5a and 5c, so that the signal processing unit 7 and the Hall element 5 are connected. It is arranged. Each of these switches 11 to 14 has the a contact connected to the c contact during the Hi level period of the control signal CLK1 output from the switching control unit 4, and the b contact connected to the c contact during the Low level period of the control signal CLK1. It is controlled so that

  The switch unit 3 is configured by one switch (single-pole double-throw switch as an example) as an example, the c contact is connected to the c contact of the switch 11, and the a contact is connected to the output terminal of the power supply unit 6. The b contact is connected to the reference potential (ground G), so that it is disposed between the power supply unit 6 and the signal switching unit 2. In the switch unit 3, the contact a is connected to the contact c during the Hi level period of the control signal CLK2 output from the switching control unit 4 (ON to allow output of the drive current I1 from the power supply unit 6 to the signal switching unit 2). On the other hand, the b-contact is connected to the c-contact during the low level period of the control signal CLK2 (the off state in which the output of the drive current I1 from the power supply unit 6 to the signal switching unit 2 is blocked (stopped)) Switching control to be performed). In addition, about the switch part 3, it can replace with a single pole double throw switch and can also use a single pole single throw switch. In this case, the switch unit 3 connects the c contact of the switch 11 to the output terminal of the power supply unit 6 when in the on state, and shifts the c contact of the switch 11 to the open state when in the off state.

  The switching control unit 4 generates four control (switching) signals CLK1, CLK2, CLK3, and CLK4 at the timing shown in FIG. 2, and outputs the control signal CLK1 to the switches 11, 12, 13, and 14 for control. The signal CLK2 is output to the switch unit 3, and the control signal CLK3 is output to the signal processing unit 7 (specifically, a sample-and-hold circuit 22 described later that constitutes a part of the signal processing unit 7) and controlled. The signal CLK4 is output to the signal processing unit 7 (specifically, a sample-and-hold circuit 23 described later that constitutes a part of the signal processing unit 7).

  In this example, as an example, the switching control unit 4 outputs the control signal CLK1 as a pulse signal having a constant frequency (for example, several tens of kHz (40 kHz as an example)) and a duty ratio of 0.5. Further, the switching control unit 4 has a frequency twice the frequency of the control signal CLK1 with respect to the control signal CLK2, and immediately before the switching timing from the Low level period to the Hi level period of the control signal CLK1. Only the predetermined period T3 immediately after that and the predetermined period T4 immediately after the predetermined period T1, and the predetermined period T2 immediately thereafter, and the switching timing from the Hi level period to the Low level period are set to the Low level. It is output as a pulse signal whose period becomes Hi level.

  Further, the switching control unit 4 has the same frequency as that of the control signal CLK1 with respect to the control signal CLK3. As an example, the switching control unit 4 has a predetermined time (control signal CLK1 of the control signal CLK1) only at an intermediate timing of the Hi level period of the control signal CLK1. It is output as a pulse signal that becomes Hi level only for a time shorter than the Hi level period, and becomes Low level during the remaining period. Further, the switching control unit 4 has the same frequency as that of the control signal CLK1 with respect to the control signal CLK4. As an example, the switching control unit 4 has a predetermined time (control signal CLK1 of the control signal CLK1) only at an intermediate timing of the Low level period of the control signal CLK1. It is output as a pulse signal that becomes Hi level only for a time shorter than the Hi level period, and becomes Low level during the remaining period.

  Next, the configuration of the sensor circuit 8 as the sensor circuit shown in FIG. 1 will be described. The sensor circuit 8 includes the Hall element driving circuit 1, the Hall element 5, a power supply unit 6, and a signal processing unit 7, and an output voltage proportional to the magnetic flux density of the magnetic flux passing through the Hall element 5 (the offset described above). The voltage Vout is output without including the voltage Vos and including only the Hall voltage Vh. The power supply unit 6 can also be provided outside the sensor circuit 8.

  As an example, the signal processing unit 7 includes a differential amplifier 21, sample-and-hold circuits 22 and 23, and a subtraction circuit 24, and an offset voltage for the Hall element 5 based on the first detection voltage Vd1 and the second detection voltage Vd2. The Hall voltage Vh is detected by executing signal processing for canceling Vos. In this case, the differential amplifier 21 has its non-inverting input terminal connected to the c contact of the switch 13 and its inverting input terminal connected to the c contact of the switch 14. As an example, the differential amplifier 21 has an amplification factor of 1 so that one of the first detection voltage Vd1 and the second detection voltage Vd2 output via the switches 13 and 14 as will be described later. (The voltage selected by the switches 13 and 14) is output as the third detection voltage Vd3.

  The sample and hold circuit 22 detects and holds the voltage of the third detection voltage Vd3 during the high level period of the control signal CLK3, and outputs it as the sampling voltage Vsh1. On the other hand, the sample and hold circuit 23 detects and holds the voltage of the third detection voltage Vd3 in the high level period of the control signal CLK4, and outputs it as the sampling voltage Vsh2.

  The subtraction circuit 24 outputs the output voltage Vout by detecting the difference between the two sampling voltages Vsh1 and Vsh2. In this example, as an example, the subtraction circuit 24 includes a differential amplifier 24a, input resistors 24b and 24c connected to its inverting input terminal and non-inverting input terminal, and a ground connected between the non-inverting input terminal and the ground G. The resistor 24d is provided with a feedback resistor 24e connected between the inverting input terminal and the output terminal. The input resistors 24b and 24c are defined to have the same resistance value. In addition, the ground resistance 24d and the feedback resistance 24e are respectively defined to have the same resistance value, and in this example, as an example, are defined to have a resistance value that is ½ of the resistance values of the input resistances 24b and 24c. With this configuration, the subtracting circuit 24 detects a difference between the sampling voltages Vsh1 and Vsh2, and an amplification factor (an example in this example) obtained by dividing the difference by the resistance value of the feedback resistor 24e by the resistance value of the input resistor 24b. As 0.5) and output as an output voltage Vout.

  Next, operations of the Hall element drive circuit 1 and the sensor circuit 8 will be described with reference to the drawings.

  In the state where the switching control circuit outputs the control signals CLK1 to CLK4 as shown in FIG. 2 at the above timing, the control signal CLK1 is switched from the Low level to the Hi level, and the period A2 (the driving current I1 is changed to the second level). Period A1 (period of transition to the first switching state in which the drive current I1 is supplied to the first terminal pairs 5a and 5c) is started after the period of transition to the second switching state to be supplied to the terminal pairs 5b and 5d is completed. In this case, the control signal CLK2 is maintained at the Low level in the predetermined periods T1 and T2 before and after the timing when the control signal CLK1 switches from the Low level to the Hi level. For this reason, since the switch unit 3 is controlled by the control signal CLK2 so that the contact c is connected to the contact b, the constant voltage V1 output from the power supply unit 6 is supplied to the switch 11. Stopped (in this example, the contact c of the switch 11 is connected to the ground G via the switch unit 3).

  As a result, the switches 11 and 12 are switched from the state in which the c contact is connected to the b contact to the state in which the c contact is connected to the a contact by the control signal CLK1 in a state where the drive current I1 is not supplied. Therefore, compared with the configuration in which the connection state of the contacts of the switches 11 and 12 is switched while the drive current I1 is supplied, the switching noise generated when switching the contact state of the contacts is greatly reduced. The switches 13 and 14 are also switched from the state where the c contact is connected to the b contact by the control signal CLK1 to the state where the c contact is connected to the a contact.

  As shown in FIG. 2, when the predetermined period T2 starting immediately after the start of the period A1 ends, the control signal CLK2 switches from the Low level to the Hi level. For this reason, the switch unit 3 is in a state in which the c contact is connected to the a contact (the constant voltage V1 from the power supply unit 6 is supplied to the c contact of the switch 11 via the switch unit 3 by this control signal CLK2. ). Thus, a current path from the power supply unit 6 to the ground G via the switch unit 3, the switch 11, the first terminal pair 5 a and 5 c of the hall element 5 and the switch 12 during the high level period of the control signal CLK 2. Is formed, and the drive current I1 flows through this current path (that is, the drive current I1 flows through the first terminal pair 5a and 5c of the Hall element 5). Therefore, as shown in FIG. 2, the first detection voltage Vd1 (= Vh + Vos) is generated between the second terminal pair 5b and 5d of the Hall element 5 during the high level period of the control signal CLK2. The 1 detection voltage Vd1 is output to the signal processing unit 7 via the switches 13 and 14.

  In the signal processing unit 7, as shown in FIG. 2, first, the differential amplifier 21 inputs and amplifies the first detection voltage Vd1, and the third detection voltage Vd3 is supplied to each of the sample and hold circuits 22 and 23. Output. In this period A1, the control signal CLK3 becomes Hi level at almost the intermediate timing of the Hi level period of the control signal CLK2. For this reason, as shown in FIG. 2, the sample and hold circuit 22 detects and holds the input voltage (Vh + Vos) of the third detection voltage Vd3 at the timing when the control signal CLK3 becomes Hi level, and performs sampling. Output as voltage Vsh1.

  As shown in FIG. 2, after that, the control signal CLK2 changes from the Hi level to the Low level when a predetermined period T3 (a period that starts before the period A1 ends and ends when the period A1 ends) starts. Switch. For this reason, the switch unit 3 is switched to a state in which the c contact is connected to the b contact (a state in which the c contact of the switch 11 is connected to the ground G via the switch unit 3) by the control signal CLK2. Thereby, the supply of the drive current I1 to the first terminal pair 5a, 5c of the Hall element 5 is stopped.

  After that, as shown in FIG. 2, the control signal CLK1 switches from the Hi level to the Low level, the period A1 ends, and the period A2 starts. Also in the predetermined period T4 after the timing when the control signal CLK1 switches from the Hi level to the Low level, the control signal CLK2 is maintained at the Low level following the predetermined period T3. As a result, the switches 11 and 12 are switched from the state in which the c contact is connected to the a contact to the state in which the c contact is connected to the b contact by the control signal CLK1 in a state where the drive current I1 is not supplied. Therefore, compared with the configuration in which the connection state of the contacts of the switches 11 and 12 is switched while the drive current I1 is supplied, the switching noise generated when switching the contact state of the contacts is greatly reduced. The switches 13 and 14 are also switched from the state where the c contact is connected to the a contact to the state where the c contact is connected to the b contact by the control signal CLK1.

  As shown in FIG. 2, when the predetermined period T4 starting immediately after the start of the period A2 ends, the control signal CLK2 switches from the Low level to the Hi level. For this reason, the switch unit 3 is in a state in which the c contact is connected to the a contact (the constant voltage V1 from the power supply unit 6 is supplied to the c contact of the switch 11 via the switch unit 3 by this control signal CLK2. ). Thus, a current path from the power supply unit 6 to the ground G via the switch unit 3, the switch 11, the second terminal pair 5 b and 5 d of the hall element 5 and the switch 12 during the high level period of the control signal CLK 2. Is formed, and the drive current I1 flows through this current path (that is, the drive current I1 flows through the second terminal pair 5b and 5d of the Hall element 5). For this reason, as shown in FIG. 2, the second detection voltage Vd2 (= −Vh + Vos) is generated between the first terminal pair 5a and 5c of the Hall element 5 during the high level period of the control signal CLK2. The second detection voltage Vd2 is output to the signal processing unit 7 via the switches 13 and 14.

  In the signal processing unit 7, as shown in FIG. 2, the differential amplifier 21 inputs and amplifies the second detection voltage Vd2, and outputs it to the sample and hold circuits 22 and 23 as the third detection voltage Vd3. . In this period A2, the control signal CLK4 becomes Hi level at a timing almost in the middle of the Hi level period of the control signal CLK2. Therefore, as shown in FIG. 2, the sample and hold circuit 23 detects and holds the input voltage (−Vh + Vos) of the third detection voltage Vd3 at the timing when the control signal CLK4 becomes Hi level. Output as the sampling voltage Vsh2.

  As shown in FIG. 2, after that, the control signal CLK2 changes from the Hi level to the Low level when a predetermined period T1 (a period that starts before the end of the period A2 and ends when the period A2 ends) starts. Switch. For this reason, the switch unit 3 is switched to a state in which the c contact is connected to the b contact (a state in which the c contact of the switch 11 is connected to the ground G via the switch unit 3) by the control signal CLK2. Thereby, the supply of the drive current I1 to the first terminal pair 5a, 5c of the Hall element 5 is stopped.

  In the signal processing unit 7, as shown in FIG. 2, the subtraction circuit 24 detects the difference (2 × Vh) between the sampling voltages Vsh1 and Vsh2 output from the sample and hold circuits 22 and 23 as described above. And amplify (0.5 times) and output as an output voltage Vout (= Vh).

  Thereafter, the Hall element drive circuit 1 and the signal processing unit 7 repeat the above operation, so that the sensor circuit 8 outputs the output voltage Vout while updating the output voltage Vout at the cycle of the control signal CLK2.

  As described above, the Hall element drive circuit 1 and the sensor circuit 8 are arranged between the power supply unit 6 and the signal switching unit 2 and output the drive current I1 from the power supply unit 6 to the signal switching unit 2. The switching control unit 4 includes a switch unit 3 that is controlled to be switched to any one of an on state that is allowed and an off state that blocks output of the drive current I1 to the signal switching unit 2. Switching control (from the first switching state to the second switching state) for the signal switching unit 2 only during the period of transition to the off state (the period including the predetermined periods T1 and T2 and the period including the predetermined periods T3 and T4). Switching control and switching control from the second switching state to the first switching state).

  Therefore, according to the Hall element drive circuit 1 and the sensor circuit 8, the switches 11 and 12 of the signal switching unit 2 constituting a part of the Hall element drive circuit 1 are switched in a state where the drive current I1 is not supplied ( The terminal pair for supplying the driving current I1 is switched from one of the first terminal pair 5a, 5c and the second terminal pair 5b, 5d to the other (that is, the flow direction of the driving current I1 flowing through the Hall element 5 is switched). Therefore, the switching noise (switching noise) generated at the time of switching can be greatly reduced as compared with the configuration in which switching is performed while the drive current I1 is supplied. Further, since the supply of the drive current I1 to the Hall element 5 is stopped in the period including the predetermined periods T1 and T2 and the period including the predetermined periods T3 and T4, the power consumption in the Hall element 5 is correspondingly reduced. As a result, the power consumption of the entire sensor circuit 8 can be reduced.

  In the above example, the signal processing unit 7 using the non-differential output type differential amplifier 21 is employed. However, as in the sensor circuit 8A shown in FIG. 3, the differential output type differential amplifier is used. A configuration in which the signal processing unit 7A using 21A is combined with the Hall element drive circuit 1 can also be adopted. In the signal processing unit 7A having this configuration, as shown in the figure, two sample-and-hold circuits 22a and 22b that execute a sampling operation with a control signal CLK3 and two sample-and-holds that execute a sampling operation with a control signal CLK4. The circuits 23a and 23b are connected to the output terminal of the differential amplifier 21A. In addition, about the same structure as the sensor circuit 8, the same code | symbol is attached | subjected and the overlapping description is abbreviate | omitted.

  In the Hall element drive circuit 1, the first detection voltage Vd 1 and the second detection voltage Vd 2 output from between the terminal pairs of the Hall element 5 are switched by switches 13 and 14 as shown in FIGS. The signal output unit 7 (7A) outputs a single differential amplifier 21 (21A). However, as in the signal processing unit 7B of the sensor circuit 8B shown in FIG. When combined with a signal processing unit in which dedicated differential amplifiers 21 and 21 are provided in front of each of the circuits 22 and 23, the switches 13 and 14 are omitted as in the Hall element drive circuit 1A shown in FIG. A signal switching unit 2A having a configuration may be employed. In addition, about the structure same as the sensor circuit 8, the same code | symbol is attached | subjected and the overlapping description is abbreviate | omitted.

  Although not shown, even in the configuration using the differential output type differential amplifier 21A as in the signal processing unit 7A of the sensor circuit 8A shown in FIG. 3, two differential amplifiers 21A are used. A sensor circuit can be configured in combination with the Hall element drive circuit 1A described above.

  Further, in the signal processing units 7, 7A, 7B of the sensor circuits 8, 8A, 8B, two first detection voltages Vd1 (= Vh + Vos) and second detection voltage Vd2 (= −Vh + Vos) output from the Hall element 5 are used. The signal processing of canceling the offset voltage Vos for the Hall element 5 is performed by subtracting the two sampling voltages Vsh1 and Vsh2 obtained by sampling (2) in the subtracting circuit 24, as shown in FIG. By performing signal processing such as synchronous detection and filtering on the two first detection voltages Vd1 (= Vh + Vos) and the second detection voltage Vd2 (= −Vh + Vos) as in the signal processing unit 7C of the sensor circuit 8C. , The output voltage (voltage including only the Hall voltage Vh, not including the offset voltage Vos) Vo It is also possible to adopt a configuration in which output a t.

  Hereinafter, the sensor circuit 8C will be described with reference to FIGS. In addition, about the structure same as the sensor circuit 8, the same code | symbol is attached | subjected and the overlapping description is abbreviate | omitted.

  In the sensor circuit 8C, the switching control unit 4 generates four control (switching) signals CLK1, CLK2, CLK5, and CLK6 at the timing shown in FIG. 6, and for the control signal CLK1, the switches 11, 12, 13, 14, the control signal CLK 2 is output to the switch unit 3, the control signal CLK 5 is output to the sample and hold circuit 22 of the signal processing unit 7 C, and the control signal CLK 6 is synchronized detection described later of the signal processing unit 7 C. Output to the circuit 25.

  The signal processing unit 7C includes a differential amplifier 21, a sample and hold circuit 22, a synchronous detection circuit 25, and a filter (low-pass filter) 26 as an example. In this case, as shown in FIG. 5, the sample-and-hold circuit 22 controls the control signal CLK5 that becomes Hi level at each of the Hi level timing of the control signal CLK3 and the Hi level timing of the control signal CLK4. Based on the above, the voltage of the third detection voltage Vd3 output from the differential amplifier 21 is detected and held, and is output as the sampling voltage Vsh shown in FIG.

  As an example, the synchronous detection circuit 25 receives the sampling voltage Vsh, amplifies it with a gain of −1 and outputs it as a sampling voltage −Vsh (see FIG. 5), and two sampling voltages Vsh and −Vsh. These voltages Vsh and -Vsh are alternately switched in synchronization with the control signal CLK6 (clock signal having the same frequency as the sampling voltages Vsh and -Vsh and the same phase as the sampling voltage Vsh) at the timing shown in FIG. And a switch 25b that outputs the detection signal Vdet (see FIG. 6). In this case, as shown in the figure, for example, the switch 25b outputs the detection signal Vdet by switching to the sampling voltage Vsh during the Hi level period and switching to the sampling voltage −Vsh during the Low level period.

  The filter 26 inputs the detection signal Vdet and averages it to output the output voltage Vout.

  Here, as shown in FIG. 6, the sampling voltage Vsh output from the sample and hold circuit 22 is a period of the control signal CLK5 as a sampling clock, and the voltage value is changed from the voltage value (Vh + Vos) to this voltage value (Vh + Vos). This is a signal that shifts to a voltage value (−Vh + Vos) having a polarity opposite to that of (Vh + Vos) and from a voltage value (−Vh + Vos) to a voltage value (Vh + Vos). The sampling voltage -Vsh is a signal having a polarity opposite to that of the sampling voltage Vsh. Further, as illustrated in FIG. 6, the switch 25 b has, as an example, a waveform during a period when the voltage value (Vh + Vos) at the sampling voltage Vsh and a waveform during a period when the voltage value (Vh−Vos) at the sampling voltage −Vsh are obtained. It switches and outputs as a detection signal Vdet.

  As a result, the detection signal Vdet shifts from the voltage value (Vh + Vos) to the voltage value (Vh−Vos) and from the voltage value (Vh−Vos) to the voltage value (Vh + Vos) in the cycle of the control signal CLK5. Signal. Therefore, the detection signal Vdet is averaged by the filter 26, whereby the average voltage value is converted into the output voltage Vout that becomes the voltage Vh as shown by the bold broken line in FIG.

  Although not shown, the sensor circuit 8C also employs a configuration using a differential output type differential amplifier 21A as in the sensor circuit 8A described above, or like the sensor circuit 8B described above. A configuration in which the switches 13 and 14 are omitted may be employed.

  In the above example, the Hall element 5 is integrally disposed in the sensor circuits 8, 8A, 8B, and 8C. However, the sensor circuit having the Hall element 5 as a separate member also has the above-described Hall. The element driving circuit 1 can be applied. Moreover, about each switch 11-14, 25b and the switch part 3, a mechanical switch, a relay, and a semiconductor switch (a transistor, FET, etc.) can be used.

1,1A Hall element drive circuit
2,2A signal switching part
3 Switch part
4 Switching control unit
5 Hall element 5a, 5c Terminal pair 5b, 5d Terminal pair
6 Power supply
7, 7A, 7B, 7C Signal processor
8, 8A, 8B, 8C Sensor circuit I1 Drive current Vh Hall voltage Vos Offset voltage

Claims (2)

Provided between the Hall element and a power supply unit that outputs a drive current to be supplied to a Hall element having a first terminal pair and a second terminal pair, and supplies the drive current to the first terminal pair A signal switching unit that is controlled to be switched to any one of a first switching state and a second switching state that supplies the driving current to the second terminal pair;
A hall element drive circuit comprising: a switching control unit that controls transition of the signal switching unit from the first switching state to the second switching state and transition from the second switching state to the first switching state. Because
An on-state that is disposed between the power supply unit and the signal switching unit and allows the drive current from the power supply unit to be output to the signal switching unit, and the drive current to the signal switching unit It has a switch part that is controlled to be switched to any one of the off states that block the output,
The switching control unit controls the transition of the switch unit from the on state to the off state, and the transition from the off state to the on state, and the switch unit is transitioned to the off state. A hall element driving circuit that executes switching control for the signal switching unit only.   2. The Hall element drive circuit according to claim 1, a first detection voltage generated between the second terminal pair in the first switching state, and the first terminal pair in the second switching state. A sensor circuit comprising: a signal processing unit configured to detect a Hall voltage of the Hall element in which an offset voltage of the Hall element is canceled by performing signal processing on the generated second detection voltage.

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