JP2016127155A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device with a high reliability.SOLUTION: A transistor has: a first insulating layer; a first conductive layer provided on the first insulating layer; a second insulating layer provided on the first insulating layer and the first conductive layer; a third insulating layer provided on the second insulating layer; an oxide semiconductor layer provided on the third insulating layer; a second conductive layer and a third conductive layer provided on the third insulating layer and the oxide semiconductor layer; a fourth insulating layer provided on the third insulating layer, the second conductive layer, the oxide semiconductor layer and the third conductive layer; and a fifth insulating layer provided on the second insulating layer and the fourth insulating layer. A capacitive element has an oxide conductive layer, a fifth insulating layer, and a fourth conductive layer provided on the fifth insulating layer. The oxide conductive layer contains the same metal elements as the oxide semiconductor layer. The oxide conductive layer has a hydrogen concentration higher than that of the oxide semiconductor layer. The fifth insulating layer is provided so as to cover the third insulating layer and an end of the fourth insulating layer. The fifth insulating layer is contacted with the second insulating layer. The fifth insulating layer has a high coatability.SELECTED DRAWING: Figure 1

Description

One embodiment of the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter). Therefore, the technical field of one embodiment of the present invention disclosed in this specification more specifically includes a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an input device, an input / output device, a driving method thereof, Alternatively, the production method thereof can be given as an example.

Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A semiconductor element such as a transistor, a semiconductor circuit, an arithmetic device, and a memory device are one embodiment of the semiconductor device. An imaging device, a display device, a liquid crystal display device, a light emitting device, an electro-optical device, a power generation device (including a thin film solar cell, an organic thin film solar cell, and the like) and an electronic device may include a semiconductor device.

Displays using thin film transistors are widely used in the world and are indispensable for people's lives. In addition, these displays are thin and light, and are indispensable for portable and wearable information terminals.

In addition, a display device having a display region (pixel portion) and a peripheral circuit (drive portion) in the same substrate has become widespread. For example, Patent Document 1 discloses a technique in which a transistor including an oxide semiconductor is used for a display region and a peripheral circuit. By simultaneously forming the display region and the peripheral circuit, the manufacturing cost can be reduced.

In addition, the market demand for high-definition displays is strong, and 4K displays are gaining popularity in the market.

JP 2007-123861 A

When mounting a display device on a portable terminal, it is required to secure a display area as large as possible on the viewing side (display surface side) from the viewpoint of visibility and design. In order to widen the display area, it is necessary to make the frame, which is an area outside the display area and to the edge of the substrate, as narrow as possible.

On the other hand, the drive circuit that exists in the periphery of the display area is located in the frame area. If the display area is widened and the frame portion is narrowed, the drive circuit will be closer to the edge of the substrate, and intrusion of atmospheric components, etc. As a result, the reliability of the transistor characteristics of the drive circuit is lowered, and the circuit operation may become unstable.

An object of one embodiment of the present invention is to provide a highly reliable semiconductor device.

An object of one embodiment of the present invention is to provide a highly reliable display device.

Another object of one embodiment of the present invention is to provide a display device with high operation stability in a peripheral circuit portion.

Another object of one embodiment of the present invention is to provide a display device with a narrow frame.

Another object of one embodiment of the present invention is to provide a display device with a high aperture ratio.

Another object of one embodiment of the present invention is to provide a high-definition display device.

Another object of one embodiment of the present invention is to provide a display device that can reduce power consumption.

Another object of one embodiment of the present invention is to provide a display device with a large area.

Another object is to provide a novel display device or the like.

Note that the description of these problems does not disturb the existence of other problems. Note that one embodiment of the present invention does not have to solve all of these problems. Issues other than these will be apparent from the description of the specification, drawings, claims, etc., and other issues can be extracted from the descriptions of the specification, drawings, claims, etc. It is.

One embodiment of the present invention is a semiconductor device including a transistor and a capacitor, the transistor including a first insulating layer, a first conductive layer provided over the first insulating layer, A second insulating layer provided on the first insulating layer and the first conductive layer, a third insulating layer provided on the second insulating layer, and an oxidation provided on the third insulating layer A semiconductor layer; a second conductive layer and a third conductive layer provided over the third insulating layer and the oxide semiconductor layer; a third insulating layer; a second conductive layer; an oxide semiconductor layer; A fourth insulating layer provided over the third conductive layer; and a fifth insulating layer provided over the second insulating layer and the fourth insulating layer. A conductive layer; a fifth insulating layer; and a fourth conductive layer provided over the fifth insulating layer. The oxide conductive layer is made of the same gold as the oxide semiconductor layer. The oxide conductive layer containing an element has a higher hydrogen concentration than the oxide semiconductor layer, and the fifth insulating layer is provided to cover the third insulating layer and the end of the fourth insulating layer. The semiconductor device is characterized in that the second insulating layer and the fifth insulating layer are in contact with each other, and the fifth insulating layer has high coverage.

Another embodiment of the present invention is a semiconductor device including a transistor and a capacitor, and the transistor includes a first insulating layer, a first conductive layer provided over the first insulating layer, and the like. , A first insulating layer, a second insulating layer provided on the first conductive layer, a third insulating layer, an oxide semiconductor layer provided on the third insulating layer, a third insulating layer, Over the insulating layer, the second conductive layer, and the third conductive layer provided over the oxide semiconductor layer, over the third insulating layer, the second conductive layer, the oxide semiconductor layer, and the third conductive layer A fourth insulating layer provided on the fourth insulating layer; a fifth insulating layer provided on the fourth insulating layer; a second insulating layer; a sixth insulating layer provided on the fifth insulating layer; The capacitor element includes an oxide conductive layer, a fourth insulating layer, and a fourth conductive layer provided on the fourth insulating layer. The oxide conductive layer is oxidized Half The oxide layer includes the same metal element as the body layer, the hydrogen concentration of the oxide conductive layer is higher than that of the oxide semiconductor layer, and the fifth insulating layer includes end portions of the third insulating layer and the fourth insulating layer. The sixth insulating layer is provided so as to cover an end of the fifth insulating layer, and the second insulating layer, the fifth insulating layer, and the sixth insulating layer are covered. The sixth insulating layer is a semiconductor device which is in contact with the layer and has high coverage.

The fifth insulating layer desirably has a barrier property against water, hydrogen, and oxygen.
be able to.

The fifth insulating layer is preferably a silicon nitride film.
be able to.

The sixth insulating layer is preferably an aluminum oxide film.

According to another embodiment of the present invention, a first insulating layer is formed, a first conductive film is formed over the first insulating layer, and the first conductive film is selectively formed using a first resist mask. The first conductive layer is formed by etching, the second insulating layer and the third insulating layer are formed in that order on the first conductive layer, and the oxide semiconductor is formed on the third insulating layer. A film is formed, and the oxide semiconductor film is selectively etched using the second resist mask to form a first oxide semiconductor layer and a second oxide semiconductor layer, and a third insulating layer The first oxide semiconductor layer is formed by forming a second conductive film over the first oxide semiconductor layer and the second oxide semiconductor layer and selectively etching using the third resist mask. Forming a second conductive layer and a third conductive layer in contact with each other, and forming a third insulating layer and a first oxide semiconductor Forming a fourth insulating film over the layer, the second oxide semiconductor layer, the second conductive layer, and the third conductive layer; forming an oxide conductive film over the fourth insulating film; By adding oxygen to the first oxide semiconductor layer and the second oxide semiconductor layer through the film, removing the oxide conductive film by etching, and selectively etching using the fourth resist mask Forming a fourth insulating layer having an opening through which the second oxide semiconductor layer is exposed, and forming a fifth insulating layer on the second insulating layer, the fourth insulating layer, and the second oxide semiconductor layer; Forming an oxide conductive layer by diffusing impurities from the fifth insulating layer to the second oxide semiconductor layer, forming a third conductive film on the fifth insulating layer, By selectively etching using the resist mask, the fourth conductive layer is formed in a region overlapping with the oxide conductive layer. A method of manufacturing a semiconductor device which is characterized in that formed.

According to another embodiment of the present invention, a first insulating layer is formed, a first conductive film is formed over the first insulating layer, and the first conductive film is selectively formed using a first resist mask. The first conductive layer is formed by etching, the second insulating layer and the third insulating layer are formed in that order on the first conductive layer, and the oxide semiconductor is formed on the third insulating layer. A film is formed, and the oxide semiconductor film is selectively etched using the second resist mask to form a first oxide semiconductor layer and a second oxide semiconductor layer, and a third insulating layer The first oxide semiconductor layer is formed by forming a second conductive film over the first oxide semiconductor layer and the second oxide semiconductor layer and selectively etching using the third resist mask. Forming a second conductive layer and a third conductive layer in contact with each other, and forming a third insulating layer and a first oxide semiconductor Forming a fourth insulating film over the layer, the second oxide semiconductor layer, the second conductive layer, and the third conductive layer; forming an oxide conductive film over the fourth insulating film; By adding oxygen to the first oxide semiconductor layer and the second oxide semiconductor layer through the film, removing the oxide conductive film by etching, and selectively etching using the fourth resist mask Forming a fourth insulating layer having an opening through which the second oxide semiconductor layer is exposed, and forming a fifth insulating layer on the second insulating layer, the fourth insulating layer, and the second oxide semiconductor layer; Forming an oxide conductive layer by diffusing impurities from the fifth insulating layer to the second oxide semiconductor layer, forming a third conductive film on the fifth insulating layer, The first oxide semiconductor layer and the oxide conductive layer are selectively etched using a resist mask. A fourth conductive layer formed in a region, a method of manufacturing a semiconductor device, which comprises forming the insulating layer of the sixth to the fifth insulating layer and the fourth conductive layer.

The fifth insulating layer is preferably formed by an atomic layer deposition (ALD) method.

Alternatively, it is desirable to form the fifth insulating layer by a plasma ALD method.

In addition, it is desirable to form a silicon nitride film as the fifth insulating film.

In addition, it is desirable to form an aluminum oxide film as the sixth insulating film.

In addition, it is desirable that the fourth insulating layer be formed by a plasma chemical vapor deposition (CVD) method and the fifth insulating layer be formed by a plasma ALD method.

A structure using the semiconductor device, a microphone, a speaker, and a housing can be employed.

Note that other aspects of the present invention are described in the following embodiments and drawings.

By using one embodiment of the present invention, a highly reliable semiconductor device can be provided.

By using one embodiment of the present invention, a highly reliable display device can be provided.

Alternatively, by using one embodiment of the present invention, a display device with high operational stability of the peripheral circuit portion can be provided.

Alternatively, according to one embodiment of the present invention, a display device with a narrow frame can be provided.

Alternatively, according to one embodiment of the present invention, a display device with a high aperture ratio can be provided.

Alternatively, according to one embodiment of the present invention, a high-definition display device can be provided.

Alternatively, according to one embodiment of the present invention, a display device capable of suppressing power consumption can be provided.

Alternatively, according to one embodiment of the present invention, a display device with a large area can be provided.

Alternatively, a new display device or the like can be provided.

Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. It should be noted that the effects other than these are naturally obvious from the description of the specification, drawings, claims, etc., and it is possible to extract the other effects from the descriptions of the specification, drawings, claims, etc. It is.

4A and 4B are a top view and cross-sectional views illustrating a transistor and a capacitor of one embodiment of the present invention. 4A and 4B are cross-sectional views illustrating a transistor of one embodiment of the present invention. 4A and 4B are cross-sectional views illustrating a transistor of one embodiment of the present invention. The cross-sectional schematic diagram for demonstrating the film-forming principle. The cross-sectional schematic diagram of a film-forming apparatus and the upper surface schematic diagram of the manufacturing apparatus provided with one chamber of the film-forming apparatus. 1 is a schematic cross-sectional view of a film forming apparatus. 1 is a schematic cross-sectional view of a film forming apparatus. 9A to 9D are cross-sectional views illustrating a method for manufacturing a transistor and a capacitor of one embodiment of the present invention. Sectional drawing for demonstrating the manufacturing method of the transistor of 1 aspect of this invention, and a capacitive element 4A and 4B are a top view and cross-sectional views illustrating a transistor and a capacitor of one embodiment of the present invention. 4A and 4B are a top view and cross-sectional views illustrating a transistor and a capacitor of one embodiment of the present invention. 4A and 4B are a top view and cross-sectional views illustrating a display device of one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a display device of one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a display device of one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a display device of one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a display device of one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a display device of one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a display device of one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a display device of one embodiment of the present invention. 4A and 4B are cross-sectional views illustrating a transistor of one embodiment of the present invention. 4A and 4B are a top view and a circuit diagram illustrating a display device of one embodiment of the present invention. The top view which showed the positional relationship of the wiring of a pixel, a transistor, and a touch sensor. FIG. 10 is a top view illustrating an input device of one embodiment of the present invention. FIG. 10 is a top view illustrating an input device of one embodiment of the present invention. FIG. 10 is a top view illustrating an input device of one embodiment of the present invention. FIG. 10 is a top view illustrating an input device of one embodiment of the present invention. FIG. 10 is a circuit diagram illustrating an input device of one embodiment of the present invention. FIG. 10 is a circuit diagram illustrating an input device of one embodiment of the present invention. 8A and 8B illustrate a method for forming a CAAC-OS. FIG. 6 illustrates a crystal of InMZnO ₄ . 8A and 8B illustrate a method for forming a CAAC-OS. 8A and 8B illustrate a method for forming a CAAC-OS. 8A and 8B illustrate a method for forming an nc-OS. FIG. 11 is a top view of a display module to which a semiconductor device of one embodiment of the present invention is applied. FIG. 11 illustrates an electronic device of one embodiment of the present invention. FIG. 11 illustrates an electronic device of one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a display device of one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a display device of one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a display device of one embodiment of the present invention.

Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in structures of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated.

<Additional notes regarding the description explaining the drawings>

In this specification, the terms and phrases such as “above” and “below” are used for convenience in describing the positional relationship between components with reference to the drawings. Moreover, the positional relationship between components changes suitably according to the direction which draws each structure. Therefore, the present invention is not limited to the words and phrases described in the specification, and can be appropriately rephrased depending on the situation.

Further, the terms “upper” and “lower” do not limit that the positional relationship between the components is directly above or directly below, and is in direct contact with each other. For example, the expression “electrode B on the insulating layer A” does not require the electrode B to be formed in direct contact with the insulating layer A, and another configuration between the insulating layer A and the electrode B. Do not exclude things that contain elements.

In this specification, “parallel” refers to a state in which two straight lines are arranged at an angle of −10 ° to 10 °. Therefore, the case of −5 ° to 5 ° is also included. Further, “substantially parallel” means a state in which two straight lines are arranged at an angle of −30 ° to 30 °. “Vertical” refers to a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included. Further, “substantially vertical” means a state in which two straight lines are arranged at an angle of 60 ° to 120 °.

In this specification, when a crystal is trigonal or rhombohedral, it is represented as a hexagonal system.

In the drawings, the size, the layer thickness, or the region is shown in an arbitrary size for convenience of explanation. Therefore, it is not necessarily limited to the scale. Note that the drawings are schematically shown for the sake of clarity, and are not limited to the shapes or values shown in the drawings.

In the drawings, some components may be omitted from the top view (also referred to as a plan view or a layout view) or a perspective view in order to clarify the drawing.

In addition, “same” may have the same area or the same shape. Moreover, since it is assumed that it does not become the completely same shape on the relationship of a manufacturing process, it can paraphrase that it is the same even if it is substantially the same.

<Additional notes on paraphrased descriptions>

In this specification and the like, when describing a connection relation of a transistor, one of a source and a drain is referred to as “one of a source and a drain” (or a first electrode or a first terminal), and the source and the drain The other is referred to as “the other of the source and the drain” (or the second electrode or the second terminal). This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. Note that the names of the source and the drain of the transistor can be appropriately rephrased depending on the situation, such as a source (drain) terminal or a source (drain) electrode.

Further, in this specification and the like, the terms “electrode” and “wiring” do not functionally limit these components. For example, an “electrode” may be used as part of a “wiring” and vice versa. Furthermore, the terms “electrode” and “wiring” include a case where a plurality of “electrodes” and “wirings” are integrally formed.

In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A channel region is provided between the drain (drain terminal, drain region or drain electrode) and the source (source terminal, source region or source electrode), and a current flows through the drain, channel region, and source. Is something that can be done.

Here, since the source and the drain vary depending on the structure or operating conditions of the transistor, it is difficult to limit which is the source or the drain. Therefore, a portion that functions as a source and a portion that functions as a drain are not referred to as a source or a drain, but one of the source and the drain is denoted as a first electrode, and the other of the source and the drain is denoted as a second electrode. There is a case.

Note that the ordinal numbers “first”, “second”, and “third” used in this specification are added to avoid confusion between components, and are not limited in number. To do.

Further, in this specification and the like, an IC (integrated circuit) is formed on a substrate of a display panel, for example, by attaching FPC (Flexible Printed Circuits) or TCP (Tape Carrier Package) or the like to the substrate by a COG (Chip On Glass) method. ) May be called a display device.

The terms “film” and “layer” can be interchanged with each other depending on circumstances or circumstances. For example, the term “conductive layer” may be changed to the term “conductive film”. Alternatively, for example, the term “insulating film” may be changed to the term “insulating layer” in some cases.

<Notes on the definition of words>
Below, the definition of a phrase is demonstrated.

<About connection>

In this specification, “A and B are connected” includes not only those in which A and B are directly connected but also those that are electrically connected. Here, A and B are electrically connected. When there is an object having some electrical action between A and B, it is possible to send and receive electrical signals between A and B. It says that.

In addition, these expression methods are examples, and are not limited to these expression methods. Here, it is assumed that X, Y, Z1, and Z2 are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, and the like).

Note that the content described in one embodiment (may be a part of content) is different from the content described in the embodiment (may be a part of content) and / or one or more Application, combination, replacement, or the like can be performed on the content described in another embodiment (or part of the content).

Note that the contents described in the embodiments are the contents described using various drawings or the contents described in the specification in each embodiment.

Note that a drawing (or part thereof) described in one embodiment may be another part of the drawing, another drawing (or part) described in the embodiment, and / or one or more. More diagrams can be formed by combining the diagrams (may be a part) described in another embodiment.

(Embodiment 1)
In this embodiment, structural examples of transistors are described.

<Configuration Example of Transistor 50>

1A, 1B, and 1C are top views and cross-sectional views of a transistor and a capacitor. A cross-sectional view along dashed-dotted line X1-X2 in FIG. 1A corresponds to FIG. A cross-sectional view along dashed-dotted line Y1-Y2 in FIG. 1A corresponds to FIG.

The transistor 50 includes an insulating layer 110 formed over the substrate 100, a conductive layer 120 formed over the insulating layer 110, an insulating layer 131 and an insulating layer 130 formed over the conductive layer 120, and the insulating layer 130 The oxide semiconductor layer 140 formed on the conductive layer 150, the conductive layer 150 and the conductive layer 160 formed over the oxide semiconductor layer 140 and having electrical connection, the insulating layer 130, the conductive layer 150, the oxide semiconductor layer 140, and the conductive layer. The insulating layer 170 formed over the layer 160 and the insulating layer 131 and the insulating layer 180 formed over the insulating layer 170 are provided. In the structure described above, since the oxide semiconductor layer 140 is in contact with the conductive layer 150 and the conductive layer 160, the heat dissipation effect is high with respect to heat generated in the oxide semiconductor layer 140 during the operation of the transistor 50. Have

<< Substrate 100 >>
There is no particular limitation on the material or the like of the substrate 100, but it is necessary to have at least heat resistance enough to withstand subsequent heat treatment. Further, it is desirable that the substrate 100 has high translucency.

An organic material, an inorganic material, or a composite material such as an organic material and an inorganic material can be used for the substrate 100. For example, an inorganic material such as glass, ceramics, or metal can be used for the substrate 100.

Specifically, alkali-free glass, soda-lime glass, potash glass, crystal glass, or the like can be used for the substrate 100. Specifically, an inorganic oxide film, an inorganic nitride film, an inorganic oxynitride film, or the like can be used for the substrate 100. For example, silicon oxide, silicon nitride, silicon oxynitride, alumina, or the like can be used for the substrate 100. Stainless steel, aluminum, or the like can be used for the substrate 100.

In addition, a single layer material or a material in which a plurality of layers are stacked can be used for the substrate 100. For example, a material in which a base material and an insulating film that prevents diffusion of impurities contained in the base material are stacked can be used for the substrate 100. Specifically, glass and a material in which one or a plurality of films selected from a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or the like that prevents diffusion of impurities contained in the glass are stacked are applied to the substrate 100 it can. Alternatively, a material in which a resin and a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like that prevents diffusion of impurities that pass through the resin are stacked can be applied to the substrate 100.

<< Insulating layer 110 >>
Note that the insulating layer 110 serving as a base film is formed using silicon oxide, silicon oxynitride, silicon nitride, silicon nitride oxide, gallium oxide, hafnium oxide, yttrium oxide, aluminum oxide, aluminum oxynitride, or the like. . Note that by using silicon nitride, gallium oxide, hafnium oxide, yttrium oxide, aluminum oxide, or the like for the insulating layer 110, the substrate 100 can be moved to the oxide semiconductor layer 140 such as an impurity, typically an alkali metal, water, or hydrogen. Can be suppressed. The insulating layer 110 is formed on the substrate 100. Further, the insulating layer 110 may not be formed.

<< Conductive layer 120 >>
The conductive layer 120 having a function as a gate electrode is a metal element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, nickel, iron, cobalt, tungsten, or an alloy containing the above metal element as a component, Alternatively, it is formed using a nitride film. Further, it may be formed using a metal element selected from one or more of manganese and zirconium. The conductive layer 120 may have a single-layer structure or a stacked structure including two or more layers. For example, a single layer structure of an aluminum film containing silicon, a single layer structure of a copper film containing manganese, a two layer structure in which a titanium film is laminated on an aluminum film, a two layer structure in which a titanium film is laminated on a titanium nitride film, and nitriding Two-layer structure in which tungsten film is laminated on titanium film, two-layer structure in which tungsten film is laminated on tantalum nitride film or tungsten nitride film, two-layer structure in which copper film is laminated on tantalum nitride or titanium nitride, manganese A two-layer structure in which a copper film is laminated on a copper film, a two-layer structure in which a copper film is laminated on an alloy of molybdenum and titanium, a titanium film, and an aluminum film is laminated on the titanium film; There are a three-layer structure in which a titanium film is formed, a three-layer structure in which a copper film is laminated on a copper film containing manganese, and a copper film containing manganese is further formed thereon. Alternatively, an alloy film or nitride film selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be used.

<< Insulating layer 130 >>
The insulating layer 130 functions as a gate insulating film. Examples of the insulating layer 130 include aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and oxide. An insulating film containing one or more types of tantalum can be used. The insulating layer 130 may be a stack of the above materials. Note that the insulating layer 130 may contain lanthanum (La), nitrogen, zirconium (Zr), or the like as impurities.

<< Insulating layer 131 >>
The gate insulating layer can be formed by stacking an insulating layer 130 and an insulating layer 131. The insulating layer 131 includes, for example, aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and oxide. An insulating film containing one or more types of tantalum can be used. The insulating layer 131 may be a stack of the above materials. Note that the insulating layer 131 may contain lanthanum (La), nitrogen, zirconium (Zr), or the like as an impurity. By using the insulating layer 131, entry of hydrogen, water, or the like into the oxide semiconductor layer 140 from the outside can be prevented.

Note that the insulating layer 130 and the insulating layer 131 are preferably films formed of different materials. By using different materials, the selectivity at the time of etching differs. For example, when the insulating layer 170 and the insulating layer 130 are formed using a silicon oxynitride film and the insulating layer 131 and the insulating layer 180 are formed using a silicon nitride film, the insulating layer 170 and the insulating layer 130 are etched using the same material. However, since the progress of the etching changes when the insulating layer 131 is exposed, the etching can be stopped in the middle of the insulating layer 131. Next, when the insulating layer 180 is formed, the transistor 50 can be surrounded by the insulating layer 131 and the insulating layer 180, and entry of hydrogen, water, or the like can be prevented. Accordingly, the reliability of transistor characteristics can be improved, and the operation of the peripheral circuit can be stabilized even when the display device has a narrow frame.

<< Oxide Semiconductor Layer 140 >>
The oxide semiconductor layer 140 is formed using a metal oxide containing at least In or Zn. The area of the upper surface of the oxide semiconductor layer 140 is preferably the same as or smaller than the area of the upper surface of the conductive layer 120.

<Oxide semiconductor>
Examples of the oxide semiconductor used for the oxide semiconductor layer 140 include an In—Ga—Zn-based oxide, an In—Al—Zn-based oxide, an In—Sn—Zn-based oxide, and an In—Hf—Zn-based oxide. In-La-Zn-based oxide, In-Ce-Zn-based oxide, In-Pr-Zn-based oxide, In-Nd-Zn-based oxide, In-Sm-Zn-based oxide, In-Eu- Zn-based oxide, In-Gd-Zn-based oxide, In-Tb-Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Zn-based oxide, In-Tm-Zn-based oxide, In-Yb-Zn-based oxide, In-Lu-Zn-based oxide, In-Sn-Ga-Zn-based oxide, In-Hf-Ga-Zn-based oxide, In -Al-Ga-Zn-based oxide, In-Sn-Al-Zn-based oxide, In- n-Hf-Zn-based oxide, In-Hf-Al-Zn-based oxide can be used an In-Ga-based oxide.

Note that here, an In—Ga—Zn-based oxide means an oxide containing In, Ga, and Zn as its main components, and there is no limitation on the ratio of In, Ga, and Zn. Moreover, metal elements other than In, Ga, and Zn may be contained.

Note that when the oxide semiconductor layer 140 is formed using In-M-Zn oxide, the atomic ratio in In and M when the sum of In and M is 100 atomic% is preferably higher than 25 atomic% in In. , M is less than 75 atomic%, more preferably, In is higher than 34 atomic% and M is less than 66 atomic%.

The oxide semiconductor layer 140 has an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more. In this manner, the off-state current of the transistor 50 can be reduced by using an oxide semiconductor with a wide energy gap.

The thickness of the oxide semiconductor layer 140 is 3 nm to 200 nm, preferably 3 nm to 100 nm, more preferably 3 nm to 50 nm.

In the case where the oxide semiconductor layer 140 is formed using In-M-Zn oxide (M is Al, Ga, Y, Zr, La, Ce, Ti, Ge, or Nd), In-M-Zn oxide As for the atomic number ratio of the metal elements of the sputtering target used for forming, M may be a natural number or may not be a natural number. For example, the atomic ratio of the metal element of the target is In: M: Zn = 1: 1: 1, In: M: Zn = 1: 1: 1.2, In: M: Zn = 1: 1: 1. It is desirable that In: M: Zn = 2: 1: 3, In: M: Zn = 3: 1: 2, and In: M: Zn = 4: 2: 4.1. Note that the atomic ratio of the metal elements of the oxide semiconductor layer 140 to be formed includes a variation of plus or minus 40% of the atomic ratio of the metal elements included in the sputtering target as an error. Note that by using a target including an In—Ga—Zn oxide, preferably a polycrystalline target including an In—Ga—Zn oxide, a CAAC-OS (C Axis Crystalline Oxide Semiconductor) film, which will be described later, and a microcrystal An oxide semiconductor film can be formed.

<< Laminated oxide semiconductor >>
Note that the oxide semiconductor layer 140 may include a stack of a plurality of oxide semiconductor films having different atomic ratios of metal elements. For example, in the transistor 51, as illustrated in FIG. 2A, oxide semiconductor layers 141 and 142 may be sequentially stacked over the insulating layer 130. Alternatively, in the transistor 52, as illustrated in FIG. 2B, oxide semiconductor layers 143, 141, and 142 may be stacked in this order over the insulating layer 130. The oxide semiconductor layer 141 can include a material similar to that of the oxide semiconductor layer 140. In addition, the oxide semiconductor layer 142 and the oxide semiconductor layer 143 may have the same composition or different composition in the atomic ratio of the metal element to that of the oxide semiconductor layer 141. For example, when the oxide semiconductor layer 142 and the oxide semiconductor layer 143 are In-M-Zn oxides (M is Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd), In the target used for forming the oxide semiconductor layer 142 and the oxide semiconductor layer 143, In: M: Zn = 1: 1: 1, In: M: Zn = 1: 1: 1.2, and In: M : Zn = 1: 1: 1.5, In: M: Zn = 2: 1: 3, In: M: Zn = 3: 1: 2, In: M: Zn = 4: 2: 4.1, etc. In addition to the same composition as the oxide semiconductor layer 140, In: M: Zn = 1: 3: 2, 1: 3: 4, 1: 3: 6, 1: 3: 8, 1: 4: 4, 1: 4: 5, 1: 4: 6, 1: 4: 7, 1: 4: 8, 1: 5: 5, 1: 5: 6, 1: 5: 7, 1: 5: 8, 1: 6: 8, 1: 6: 4, 1: : There is 6 and the like.

<About hydrogen concentration>
In addition, hydrogen contained in the oxide semiconductor layer reacts with oxygen bonded to a metal atom to be water, and forms oxygen vacancies in a lattice from which oxygen is released (or a portion from which oxygen is released). When hydrogen enters the oxygen vacancies, electrons serving as carriers may be generated. In some cases, a part of hydrogen is bonded to oxygen bonded to a metal atom, so that an electron serving as a carrier is generated. Therefore, a transistor including an oxide semiconductor containing hydrogen is likely to be normally on. Hydrogen contained in the oxide semiconductor layer 140 reacts with oxygen bonded to a metal atom to become water, and forms oxygen vacancies in a lattice from which oxygen is released (or a portion from which oxygen is released). When hydrogen enters the oxygen vacancies, electrons serving as carriers may be generated. In some cases, a part of hydrogen is bonded to oxygen bonded to a metal atom, so that an electron serving as a carrier is generated. Therefore, a transistor including an oxide semiconductor containing hydrogen is likely to be normally on.

Therefore, it is preferable that hydrogen be reduced as much as possible along with oxygen vacancies in the oxide semiconductor layer 140 and its interface. For example, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) at the oxide semiconductor layer 140 and its interface is 1 × 10 ¹⁶ atoms / cm ³ or more and 2 × 10 ²⁰ atoms / cm ^3. Or less, preferably 1 × 10 ¹⁶ atoms / cm ³ or more and 5 × 10 ¹⁹ atoms / cm ³ or less, more preferably 1 × 10 ¹⁶ atoms / cm ³ or more and 1 × 10 ¹⁹ atoms / cm ³ or less, more preferably 1 × It is desirable to set it to 10 ¹⁶ atoms / cm ³ or more and 5 × 10 ¹⁸ atoms / cm ³ or less. As a result, the transistor 50 can have electrical characteristics (also referred to as normally-off characteristics) in which the threshold voltage is positive.

<About carbon and silicon concentration>
In addition, when silicon or carbon which is one of Group 14 elements is included in the oxide semiconductor layer 140 and its interface, oxygen vacancies increase in the oxide semiconductor layer 140, and an n-type region is formed. . Therefore, it is desirable to reduce the concentrations of silicon and carbon in the oxide semiconductor layer 140 and its interface. For example, the concentration of silicon or carbon obtained by SIMS in the oxide semiconductor layer 140 and each interface is 1 × 10 ¹⁶ atoms / cm ³ or more and 1 × 10 ¹⁹ atoms / cm ³ or less, preferably 1 × 10 ¹⁶ atoms. / Cm ³ or more and 5 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × 10 ¹⁶ atoms / cm ³ or more and 2 × 10 ¹⁸ atoms / cm ³ or less. As a result, the transistor 50 has electrical characteristics (also referred to as normally-off characteristics) in which the threshold voltage is positive.

<Concentration of alkali metal>
Further, when alkali metal and alkaline earth metal are combined with an oxide semiconductor, carriers may be generated, which may increase off-state current of the transistor. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the oxide semiconductor layer 140 and each interface. For example, the concentration of alkali metal or alkaline earth metal obtained by secondary ion mass spectrometry at the oxide semiconductor layer 140 and each interface is 1 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ^16. Desirably, atoms / cm ³ or less. As a result, the transistor 50 has electrical characteristics (also referred to as normally-off characteristics) in which the threshold voltage is positive.

<About nitrogen concentration>
In addition, when nitrogen is contained in the oxide semiconductor layer 140 and each interface, electrons as carriers are generated, the carrier density is increased, and an n-type region is formed. As a result, a transistor including an oxide semiconductor containing nitrogen is likely to be normally on. Therefore, nitrogen is preferably reduced as much as possible in the oxide semiconductor layer 140 and each interface. For example, the nitrogen concentration obtained by SIMS in the oxide semiconductor layer 140 and each interface is 1 × 10 ¹⁵ atoms / cm ³ or more and 5 × 10 ¹⁹ atoms / cm ³ or less, preferably 1 × 10 ¹⁵ atoms / cm ³ or more, 5 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × 10 ¹⁵ atoms / cm ³ or more and 1 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × 10 ¹⁵ atoms / cm ³ or more and 5 × 10 ¹⁷ atoms / cm ³ or less is preferable. As a result, the transistor 50 has electrical characteristics (also referred to as normally-off characteristics) in which the threshold voltage is positive.

<About carrier density>
By reducing impurities in the oxide semiconductor layer 140, the carrier density of the oxide semiconductor layer 140 can be reduced. Therefore, the oxide semiconductor layer 140 has a carrier density of 1 × 10 ¹⁵ pieces / cm ³ or less, preferably 1 × 10 ¹³ pieces / cm ³ or less, more preferably less than 8 × 10 ¹¹ pieces / cm ³ , more preferably. Is less than 1 × 10 ¹¹ pieces / cm ³ , most preferably less than 1 × 10 ¹⁰ pieces / cm ³ , and 1 × 10 ⁻⁹ pieces / cm ³ or more.

By using an oxide semiconductor with a low impurity concentration and a low density of defect states as the oxide semiconductor layer 140, a transistor having more excellent electric characteristics can be manufactured. Here, low impurity concentration and low defect level density (low oxygen deficiency) are referred to as high purity intrinsic or substantially high purity intrinsic. An oxide semiconductor that is highly purified intrinsic or substantially highly purified intrinsic has few carrier generation sources, and thus may have a low carrier density. Therefore, a transistor in which a channel region is formed in the oxide semiconductor layer 140 formed using the oxide semiconductor tends to have electrical characteristics (also referred to as normally-off characteristics) in which the threshold voltage is positive. In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has a low density of defect states, and thus may have a low density of trap states. In addition, a transistor in which the oxide semiconductor layer 140 is formed using a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor has extremely low off-state current, and a voltage between the source electrode and the drain electrode (drain voltage) In the range of 1V to 10V, it is possible to obtain the characteristic that the off-state current is not more than the measurement limit of the semiconductor parameter analyzer, that is, not more than 1 × 10 ⁻¹³ A, and further the characteristic fluctuation can be suppressed.

Note that the transistor 50 in which an oxide semiconductor is used for the oxide semiconductor layer 140 is specified by the channel width of the transistor when the voltage between the source and the drain is, for example, about 0.1 V, 5 V, or 10 V. The reduced off current can be reduced to several yA / μm to several zA / μm.

When the transistor 50 connected to the display element (e.g., the liquid crystal element 80) uses a transistor with extremely small leakage current in the off state, the time during which an image signal can be held can be extended. For example, image signal writing is performed at a frequency of 11.6 μHz (once per day) or more and less than 0.1 Hz (0.1 per second), preferably 0.28 mHz (once per hour) or more and 1 Hz (1 Images can be retained even with a frequency less than once per second). As a result, the frequency of writing image signals can be reduced. As a result, the power consumption of the display panel 20 can be reduced. Of course, the image signal can be written at a frequency of 1 Hz or more, preferably 30 Hz (30 times per second) or more, more preferably 60 Hz (60 times per second) or more and less than 960 Hz (960 times per second). .

For the above reasons, by using a transistor including an oxide semiconductor, a display panel with high reliability and low power consumption can be manufactured.

In a transistor including an oxide semiconductor, the oxide semiconductor layer 140 can be formed by a sputtering method, a MOCVD (Metal Organic Chemical Deposition) method, a PLD (Pulse Laser Deposition) method, or the like. When a film is formed by sputtering, it can be used as a display device having a large area.

Note that a semiconductor layer formed of silicon or silicon germanium may be used for the oxide semiconductor layer 140. A semiconductor layer formed of silicon or silicon germanium can have an amorphous structure, a polycrystalline structure, or a single crystal structure as appropriate.

<< Conductive layer 150, Conductive layer 160 >>
The conductive layer 150 and the conductive layer 160 each function as a source electrode, a drain electrode, or an electrode of a capacitor. The conductive layer 150 and the conductive layer 160 are a metal element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten, or an alloy containing the above metal element as a component, or a nitride film. It is formed using. Further, it may be formed using a metal element selected from one or more of manganese and zirconium. The conductive layer 150 and the conductive layer 160 may have a single-layer structure or a stacked structure including two or more layers. For example, a single layer structure of an aluminum film containing silicon, a single layer structure of a copper film containing manganese, a two layer structure in which a titanium film is laminated on an aluminum film, a two layer structure in which a titanium film is laminated on a titanium nitride film, and nitriding A two-layer structure in which a tungsten film is stacked on a titanium film, a two-layer structure in which a tungsten film is stacked on a tantalum nitride film or a tungsten nitride film, a two-layer structure in which a copper film is stacked on a copper film containing manganese, and a titanium film A three-layer structure in which an aluminum film is laminated on the titanium film and a titanium film is further formed thereon, a copper film is laminated on the copper film containing manganese, and a copper film containing manganese is further formed thereon. There are three-layer structures. Alternatively, an alloy film or nitride film selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be used.

<< Insulating layer 170 >>
The insulating layer 170 has a function of protecting the channel region of the transistor. The insulating layer 170 is formed using silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, or the like, silicon nitride, nitride It is formed using a nitride insulating film such as aluminum. The insulating layer 170 can have a single-layer structure or a stacked structure.

The insulating layer 170 is preferably formed using an oxide insulating film containing more oxygen than that in the stoichiometric composition. Part of oxygen is released by heating from the oxide insulating film containing oxygen in excess of that in the stoichiometric composition. An oxide insulating film containing oxygen in excess of the stoichiometric composition has a surface temperature of 100 ° C. or higher and 700 ° C. or lower, or 100 ° C. or higher and 500 ° C. or lower in TDS (Thermal Desorption Spectroscopy) analysis. The oxide insulating film has a desorption amount of oxygen atoms in the range of 1.0 × 10 ¹⁸ atoms / cm ³ or more, preferably 3.0 × 10 ²⁰ atoms / cm ³ or more. By the heat treatment, oxygen contained in the insulating layer 170 can be moved to the oxide semiconductor layer 140, and oxygen vacancies in the oxide semiconductor layer 140 can be reduced.

<< Insulating layer 180 >>
By providing an insulating film having a barrier property against oxygen, hydrogen, water, or the like from the outside as the insulating layer 180, diffusion of oxygen from the oxide semiconductor layer 140 to the outside, and from the outside to the oxide semiconductor layer 140 Intrusion of hydrogen, water, etc. can be prevented. For example, insulation including one or more of aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide A membrane can be used. The insulating layer 180 may be a stacked layer of the above materials. Note that the insulating layer 180 may contain lanthanum (La), nitrogen, zirconium (Zr), or the like as impurities. For example, when a silicon nitride film is formed on the insulating layer 180 by a plasma ALD method, the barrier property can be further improved because the covering property with respect to unevenness is good. Accordingly, a highly reliable transistor can be formed.

Alternatively, the hydrogen concentration contained in the insulating layer 180 is 1 × 10 ¹⁹ atoms / cm ³ or more and less than 1 × 10 ²² atoms / cm ³ , preferably 1 × 10 ¹⁹ atoms / cm ³ or more and 1 × 10 ²¹ atoms / cm 3. Desirably less than ³ . In the case where the insulating layer 180 contains a large amount of hydrogen, hydrogen may enter the display panel from the insulating layer 180, which may deteriorate the characteristics of the peripheral circuit. Therefore, by having the above concentration as the hydrogen concentration in the protective film, the high-purity insulating layer 180 can be provided, hydrogen can be prevented from entering the display panel, and the operation stability and reliability of the peripheral circuit can be improved. Can be improved.

<< Conductive layer 190 >>
The conductive layer 190 is formed using a conductive film that transmits visible light. As the conductive film that transmits light with visible light, a material containing one kind selected from indium (In), zinc (Zn), and tin (Sn) may be used, for example. As a conductive film having a light-transmitting property with respect to visible light, typically, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, or indium oxide containing titanium oxide is used. Further, a conductive oxide such as an indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide containing silicon oxide can be used.

<Dual gate structure>
As the transistor 50, a transistor 53 which is a modified example can be used. This will be described with reference to FIG. A transistor 53 illustrated in FIG. 3 has a dual-gate structure.

3A, 3B, and 3C are a top view and a cross-sectional view of the transistor 53. FIG. 3A is a top view of the transistor 53, FIG. 3B is a cross-sectional view taken along the dashed-dotted line XX ′ in FIG. 3A, and FIG. It is sectional drawing between dashed-dotted lines YY 'of A). Note that in FIG. 3A, the substrate 100, the insulating layer 110, the insulating layer 130, the insulating layer 170, the insulating layer 180, and the like are omitted for clarity.

3A to 3C includes an insulating layer 131 which functions as a gate insulating film provided over the conductive layer 120 which functions as a gate electrode over the insulating layer 110, and an insulating layer 131. The oxide semiconductor layer 140 which overlaps with the conductive layer 120 with the layer 130 interposed therebetween, the conductive layers 150 and 160 in contact with the oxide semiconductor layer 140, and the insulation over the oxide semiconductor layer 140, the conductive layer 150, and the conductive layer 160 The layer 170, the insulating layer 180 over the insulating layer 170, and the conductive layer 190 having a function as a back gate electrode provided over the insulating layer 180 are included. As shown in FIG. 3C, the conductive layer 120 is electrically connected to the conductive layer 190 in the opening 191 of the insulating layer 131, the insulating layer 130, the insulating layer 170, and the insulating layer 180. You can also. Note that the opening 191 is not provided and the conductive layer 120 and the conductive layer 520 are not electrically connected to each other.

<Configuration Example of Capacitance Element 60>
The capacitor 60 includes an oxide conductive layer 400, an insulating layer 180, and a conductive layer 190. The oxide conductive layer 400 functions as one electrode of the capacitor 60. The conductive layer 190 functions as the other electrode of the capacitor 60. An insulating layer 180 is provided between the oxide conductive layer 400 and the conductive layer 190.

<< Oxide Conductive Layer 400 >>
In addition, when the transistor 50 is a transistor including an oxide semiconductor, the oxide conductive layer 400 can be formed over the insulating layer 130 with the same material as the oxide semiconductor layer 140. In this case, the oxide conductive layer 400 is formed by processing a film formed at the same time as the oxide semiconductor layer 140. Therefore, the oxide conductive layer 400 includes an element similar to that of the oxide semiconductor layer 140. In addition, the oxide semiconductor layer 140 has a similar crystal structure or a different crystal structure. Further, by providing the film formed at the same time as the oxide semiconductor layer 140 with impurities or oxygen vacancies, conductivity can be imparted and the oxide conductive layer 400 is obtained. Typical examples of the impurity contained in the oxide conductive layer 400 include one or more of a rare gas, hydrogen, boron, nitrogen, fluorine, aluminum, and phosphorus. Representative examples of noble gases include helium, neon, argon, krypton, and xenon. Note that although the oxide conductive layer 400 has an example of conductivity, one embodiment of the present invention is not limited thereto. In some cases or depending on circumstances, the oxide conductive layer 400 may not necessarily have conductivity. That is, the oxide conductive layer 400 may have characteristics similar to those of the oxide semiconductor layer 140.

As described above, the oxide semiconductor layer 140 and the oxide conductive layer 400 are both formed over the insulating layer 130 but have different impurity concentrations. Specifically, the oxide conductive layer 400 has a higher impurity concentration than the oxide semiconductor layer 140. For example, in the oxide semiconductor layer 140, the hydrogen concentration obtained by secondary ion mass spectrometry is 5 × 10 ¹⁹ atoms / cm ³ or less, preferably 5 × 10 ¹⁸ atoms / cm ³ or less, preferably 1 × 10 ^18. atoms / cm ³ or less, preferably 5 × 10 ¹⁷ atoms / cm ³ or less, preferably 1 × 10 ¹⁶ atoms / cm ³ or less. On the other hand, in the oxide conductive layer 400, the hydrogen concentration obtained by secondary ion mass spectrometry is 8 × 10 ¹⁹ atoms / cm ³ or more, preferably 1 × 10 ²⁰ atoms / cm ³ or more, preferably 5 × 10 ^20. atoms / cm ³ or more. In addition, as compared with the oxide semiconductor layer 140, the concentration of hydrogen contained in the oxide conductive layer 400 is twice or 10 times or more.

Further, when the oxide semiconductor film formed at the same time as the oxide semiconductor layer 140 is exposed to plasma, the oxide semiconductor film can be damaged and oxygen vacancies can be formed. For example, when a film is formed over the oxide semiconductor film by a plasma CVD method or a sputtering method, the oxide semiconductor film is exposed to plasma, and oxygen vacancies are generated. Alternatively, in the etching treatment for forming the opening in the insulating layer 170, the oxide semiconductor film is exposed to plasma, so that oxygen vacancies are generated. Alternatively, when the oxide semiconductor film is exposed to plasma of a mixed gas of oxygen and hydrogen, hydrogen, a rare gas, ammonia, or the like, oxygen vacancies are generated. Further, by adding an impurity to the oxide semiconductor film, the impurity can be added to the oxide semiconductor film while oxygen vacancies are formed. As a method for adding impurities, there are an ion doping method, an ion implantation method, a plasma treatment method, and the like. In the case of a plasma treatment method, plasma is generated in a gas atmosphere containing an impurity to be added, and plasma treatment is performed so that accelerated impurity ions collide with the oxide semiconductor film and oxygen vacancies are formed in the oxide semiconductor film. Can be formed.

When an impurity, for example, hydrogen, is contained in an oxide semiconductor film in which oxygen vacancies are formed by addition of an impurity element, hydrogen enters the oxygen vacancy site and a donor level is formed in the vicinity of the conduction band. As a result, the oxide semiconductor film has high conductivity and becomes a conductor. A conductive oxide semiconductor film can be referred to as an oxide conductive film. That is, it can be said that the oxide semiconductor layer 140 is formed using an oxide semiconductor, and the oxide conductive layer 400 is formed using an oxide conductor film. It can also be said that the oxide conductive layer 400 is formed using a highly conductive oxide semiconductor film. It can also be said that the oxide conductive layer 400 is formed using a highly conductive metal oxide film.

Note that the insulating layer 180 preferably contains hydrogen. Since the oxide conductive layer 400 is in contact with the insulating layer 180, the insulating layer 180 contains hydrogen, so that the hydrogen in the insulating layer 180 is diffused into the oxide semiconductor film formed at the same time as the oxide semiconductor layer 140. be able to. As a result, impurities can be added to the oxide semiconductor film formed at the same time as the oxide semiconductor layer 140, so that the conductivity of the oxide conductive layer 400 can be increased. For example, for the insulating layer 180, by using a plasma ALD method, the amount of released hydrogen is reduced while containing hydrogen, so that a region where a highly conductive metal oxide is formed is controlled and stable transistor characteristics are obtained. Can be obtained.

With the above method, the oxide conductive layer 400 is formed at the same time as the oxide semiconductor layer 140, and conductivity is imparted after formation. With this configuration, manufacturing cost can be reduced.

Note that generally, an oxide semiconductor film has a large energy gap and thus has a light-transmitting property with respect to visible light. On the other hand, the oxide conductor film is an oxide semiconductor film having a donor level in the vicinity of the conduction band. Therefore, the influence of absorption due to the donor level is small, and the light transmittance is comparable to that of an oxide semiconductor film with respect to visible light.

Note that from the above, the conductive layer 190 and the oxide conductive layer 400 have a light-transmitting property. Therefore, the capacitive element 60 can be a translucent capacitive element as a whole, and can increase the aperture ratio when used in a display device.

Note that the structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 2)
<Description of manufacturing method>
Hereinafter, a transistor applicable to one embodiment of the present invention, a manufacturing method related to a capacitor, a deposition apparatus applicable to deposition of a semiconductor layer, an insulating layer, a conductive layer, and the like will be described.

<CVD deposition and ALD deposition>
In a film forming apparatus using a conventional CVD method, at the time of film formation, one or more kinds of reaction source gases (precursors) are simultaneously supplied to a chamber. In a film formation apparatus using the ALD method, a precursor for reaction is sequentially introduced into a chamber, and film formation is performed by repeating the order of gas introduction. For example, each switching valve (also called a high-speed valve) is switched to supply two or more types of precursors to the chamber in order, and an inert gas (argon, or other) is provided after the first precursor so that a plurality of types of precursors are not mixed. Nitrogen etc.) are introduced, and the second precursor is introduced. Further, the second precursor can be introduced after the first precursor is discharged by evacuation instead of introducing the inert gas.

FIG. 4A, FIG. 4B, FIG. 4C, and FIG. 4D show the film formation process of the ALD method. The first precursor 601 is adsorbed on the surface of the substrate (see FIG. 4A), and a first single layer is formed (see FIG. 4B). At this time, a metal atom or the like contained in the precursor can be bonded to a hydroxyl group present on the substrate surface. An alkyl group such as a methyl group or an ethyl group may be bonded to the metal atom. Reacting with the second precursor 602 introduced after exhausting the first precursor 601 (see FIG. 4C), the second single layer is laminated on the first single layer to form a thin film. (See FIG. 4D). For example, when an oxidizing agent is included as the second precursor, a chemical reaction occurs between a metal atom present in the first precursor or an alkyl group bonded to the metal atom and the oxidizing agent, and the oxide film Can be formed.

In addition, the ALD method is a film formation method based on a surface chemical reaction, and is further formed by the precursor adsorbing to the film formation surface and the self-stopping mechanism acting. For example, a precursor such as trimethylaluminum reacts with a hydroxyl group (OH group) present on the deposition surface. At this time, since only a surface reaction due to heat occurs, the precursor comes into contact with the film formation surface, and metal atoms or the like in the precursor can be adsorbed on the film formation surface through thermal energy. In addition, the precursor has a high vapor pressure, is thermally stable at the stage before film formation, does not self-decompose, and has a feature of fast chemical adsorption to the substrate. In addition, since the precursor is introduced as a gas, it is possible to form a film with good coverage even in a region having a high aspect ratio unevenness as long as the alternately introduced precursor has sufficient time for diffusion. it can.

Further, in the ALD method, a thin film having excellent step coverage can be formed by repeating the introduction of the precursor several times until the desired thickness is obtained while controlling the introduction using a valve or an exhaust pump. Since the thickness of the thin film can be adjusted by the number of repetitions, precise film thickness adjustment is possible. Further, by increasing the exhaust capacity, the film formation rate can be increased, and the impurity concentration in the film can be further reduced.

The ALD method includes an ALD method using heat (thermal ALD method) and an ALD method using plasma (plasma ALD method). In the thermal ALD method, a precursor reaction is performed using thermal energy, and in the plasma ALD method, the precursor reaction is performed in a radical state.

The ALD method can form a very thin film with high accuracy. The surface having unevenness is also characterized by high surface coverage and high film density.

Further, the thermal ALD method can suppress the generation of defects in the film because there is no plasma damage.

<Plasma ALD method>
In addition, the plasma ALD method is a film forming method with excellent reactivity, and can be formed at a lower temperature than the thermal ALD method. In the plasma ALD method, for example, a film can be formed at a temperature of 100 degrees or less without reducing the film formation speed. In the plasma ALD method, reactivity is increased by radicalizing an inert material such as N ₂ with plasma, so that not only oxides but also nitrides and metals can be formed.

In plasma ALD, the oxidizing power of the oxidizing agent can be increased. As a result, when the film is formed, the precursor remaining in the film or the organic components desorbed from the precursor can be reduced, and carbon, chlorine, hydrogen, etc. in the film can be reduced, and the impurity concentration can be reduced. Can have a low membrane.

Further, in the case where a light emitting element (such as an organic EL element) is used as the display element, there is a possibility that the deterioration of the light emitting element is accelerated when the process temperature is high. Here, since the process temperature can be lowered by using the plasma ALD method, deterioration of the light-emitting element can be suppressed.

In addition, the plasma ALD method is a method of promoting a reaction by plasma. As a method, a direct plasma ALD method in which a film formation substrate is directly exposed to plasma and a plasma source are installed outside a film formation chamber and generated in the region. There is a remote plasma ALD method in which the radical species transported to the substrate. For example, in the remote plasma ALD method, ICP (Inductively Coupled Plasma) or the like is used, and a film is generated on a deposition target substrate or a deposition target substrate by generating a plasma away from the deposition target substrate. Plasma damage to the applied film can be suppressed.

In addition, by using the plasma ALD method, the film can be made more dense and barrier properties against moisture intrusion and the like can be improved.

In addition, by using the plasma ALD method, the reactivity is increased and the deposition rate can be improved as compared with the thermal ALD apparatus.

As described above, the plasma ALD method can form a film with high surface coverage and high barrier properties, and can prevent moisture from entering from the outside. Therefore, since the reliability of the driver operation of the peripheral circuit is improved at the edge of the panel (the reliability of the transistor characteristics is improved), stable operation is possible even when the frame is narrow.

<Description of ALD device>
FIG. 5A shows an example of a film formation apparatus using the ALD method. A film formation apparatus using the ALD method includes a film formation chamber (chamber 1701), raw material supply units 1711a and 1711b, high-speed valves 1712a and 1712b as flow controllers, raw material introduction ports 1713a and 1713b, and a raw material discharge port. 1714 and an exhaust device 1715. The raw material introduction ports 1713a and 1713b installed in the chamber 1701 are connected to the raw material supply units 711a and 711b through supply pipes and valves, respectively. The raw material discharge port 1714 is connected through the discharge pipes and valves and pressure regulators. The exhaust device 1715 is connected.

There is a substrate holder 1716 provided with a heater inside the chamber, and a substrate 1700 to be deposited is placed on the substrate holder.

In the raw material supply units 1711a and 1711b, a raw material gas is formed from a solid raw material or a liquid raw material by a vaporizer or a heating means. Alternatively, the raw material supply units 1711a and 1711b may be configured to supply a gaseous raw material gas.

Moreover, although the example which has provided the raw material supply parts 1711a and 1711b is shown, it is not specifically limited, You may provide three or more. Further, the high-speed valves 1712c and 1712d can be precisely controlled with time, and are configured to supply either the source gas or the inert gas. The high-speed valves 1712c and 1712d are flow rate controllers for raw material gas, and can also be said to be flow rate controllers for inert gas.

5A, the substrate 1700 is carried onto the substrate holder 1716, the chamber 1701 is hermetically sealed, and then the substrate 700 is heated to a desired temperature (for example, 100 ° C. by heating the substrate holder 1716). The thin film is formed on the substrate surface by repeating the supply of the source gas, the exhaust by the exhaust device 1715, the supply of the inert gas, and the exhaust by the exhaust device 1715.

In the film formation apparatus shown in FIG. 5A, a material selected from hafnium, aluminum, tantalum, zirconium, or the like by appropriately selecting a raw material (such as a volatile organometallic compound) prepared in the raw material supply portions 1711a and 1711b. An insulating layer including an oxide containing the above elements (including a composite oxide) can be formed. Specifically, an insulating layer including hafnium oxide, an insulating layer including aluminum oxide, an insulating layer including hafnium silicate, or an insulating layer including aluminum silicate A film can be formed. In addition, by appropriately selecting raw materials (such as volatile organometallic compounds) prepared in the raw material supply units 1711a and 1711b, thin films such as metal layers such as tungsten layers and titanium layers and nitride layers such as titanium nitride layers can be formed. A film can also be formed.

For example, in the case where a hafnium oxide layer is formed by a film forming apparatus using the ALD method, a liquid containing a solvent and a hafnium precursor compound (hafnium alkoxide solution, typically tetrakisdimethylamide hafnium (TDMAH)) is vaporized. Two kinds of gases, that is, a raw material gas and ozone (O ₃ ) as an oxidizing agent are used. In this case, the first source gas supplied from the source supply unit 711a is TDMAH, and the second source gas supplied from the source supply unit 711b is ozone. Note that the chemical formula of tetrakisdimethylamide hafnium is Hf [N (CH ₃ ) ₂ ] ₄ . Other materials include tetrakis (ethylmethylamide) hafnium. Note that nitrogen has a function of eliminating a charge trap level. Therefore, when the source gas contains nitrogen, hafnium oxide having a low charge trapping level density can be formed.

In the case of forming an aluminum oxide layer by a film forming apparatus using the ALD method, a precursor that vaporizes a liquid (TMA or the like) containing a solvent and an aluminum precursor compound and _two precursors of H ₂ O as an oxidizing agent are used. Is used. In this case, the first source gas supplied from the source supply unit 711a is TMA, and the second source gas supplied from the source supply unit 1711b is H ₂ O. Note that the chemical formula of trimethylaluminum is Al (CH ₃ ) ₃ . Other material liquids include tris (dimethylamido) aluminum, triisobutylaluminum, aluminum tris (2,2,6,6-tetramethyl-3,5-heptanedionate) and the like.

<Multi-chamber ALD deposition system>
FIG. 5B illustrates an example of a multi-chamber ALD film formation apparatus including at least one film formation apparatus illustrated in FIG.

The manufacturing apparatus illustrated in FIG. 5B can continuously form a stacked film without exposure to the air, and prevents impurities from entering and improves throughput.

The manufacturing apparatus illustrated in FIG. 5B includes at least a load chamber 1702, a transfer chamber 1720, a pretreatment chamber 1703, a chamber 1701 which is a film formation chamber, and an unload chamber 1706. Note that chambers (including load chambers, processing chambers, transfer chambers, film formation chambers, unload chambers, etc.) of manufacturing equipment are inert gases (nitrogen gas, etc.) with controlled dew points in order to prevent moisture from adhering. Is preferably filled, and desirably the reduced pressure is maintained.

The chambers 1704 and 1705 may be a film formation apparatus that uses the same ALD method as the chamber 1701, a film formation apparatus that uses a plasma CVD method, or a film formation apparatus that uses a sputtering method. Alternatively, a film formation apparatus using a metal organic chemical vapor deposition (MOCVD) method may be used.

For example, an example of forming a stacked film using the film formation apparatus using the plasma CVD method as the chamber 1704 and the film formation apparatus using the MOCVD method as the chamber 1705 is described below.

In FIG. 5B, the top view of the transfer chamber 1720 shows an example of a hexagonal shape. However, depending on the number of layers of the laminated film, the manufacturing apparatus may be connected to more chambers as more polygons. Good. In FIG. 5B, the top surface shape of the substrate is shown as a rectangle, but it is not particularly limited. Further, although a single wafer type example is shown in FIG. 5B, a batch type film forming apparatus which forms a plurality of substrates at a time may be used.

<Description of plasma ALD apparatus>
A schematic diagram of the plasma ALD apparatus 850 is shown in FIG. The plasma ALD apparatus 850 includes a plasma source 851, a chamber 853, a first precursor supply unit 855, a second precursor supply unit 857, a first precursor introduction valve 859, a precursor introduction valve 861, a gate valve 863, a heater 865, A film forming substrate 867 and a pump 869 are provided. The first precursor is supplied from the first precursor supply unit 855 into the chamber through the first precursor introduction valve 859 and the pipe, and is heated by the heater 865. Adsorbed to the film substrate 867. At this time, the gas remaining in the chamber is exhausted out of the chamber by the gate valve 863 and the pump 869.

Subsequently, the second precursor is introduced from the second precursor supply unit 855 into the plasma source via the precursor introduction valve 859 and the piping. As the plasma source 851, an ICP or the like is used. Radical species are generated from the second precursor in the plasma source, the radical species are introduced into the chamber, a reaction occurs in the deposition target substrate 867, and a film is formed. At this time, the gas remaining in the chamber is exhausted out of the chamber by the gate valve 863 and the pump 869.

By repeating the above process using the first precursor and the second precursor, a film with a desired film thickness can be formed on the deposition target substrate 867.

In the precursor supply unit 855 and the precursor supply unit 857, a raw material gas is formed from a solid raw material or a liquid raw material by a vaporizer, a heating means, or the like. Alternatively, the precursor supply unit 855 and the precursor supply unit 857 may be configured to supply a gaseous source gas.

In the case where a silicon nitride layer is formed by a film formation apparatus using a plasma ALD method, tetrachlorosilane, dichlorosilane, hexachlorodisilane, tetraethoxysilane, tris (tert-butoxy) silanol, tris (tert-) are used as the first precursor. Pentoxy) silanol, etc. can be used. In addition, ammonia, hydrazine, nitrogen, or the like can be used as the second precursor. The first precursor is supplied from the precursor supply unit 855, and the second precursor is supplied from the precursor supply unit 857.

<Large area ALD deposition system>
In addition, by using the plasma ALD method, a film can be formed even on a large-area substrate. FIGS. 7A and 7B are schematic views of another configuration of the ALD film forming apparatus. A plasma gas (precursor) can be introduced into the chamber 820 through the introduction port 810, and film formation can be performed on the substrate 800 by the ALD method from above and below via the plasma generation source 830. The plasma generation source 830 may be provided inside the chamber or outside the chamber. As a film formation method, the film can be formed while being fixed in a chamber as shown in FIG. 7A, or the film can be formed while flowing a substrate in an inline method as shown in FIG. 7B. it can. By using the plasma ALD method, a film can be formed over a large area with high throughput.

In order to uniformly form the side surface of the display panel to be formed on the periphery, the display panel may be placed on a susceptor or the like, or a cassette jig and substrate for housing the display panel. Point contact, line contact, or surface contact may be performed in the vicinity of the side surface portion.

Note that the structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.
<Formation of Insulating Layer 110>
In FIG. 8A, an insulating layer 110 is formed over the substrate 100. The insulating layer 110 can be formed by a plasma CVD method, a thermal CVD method (MOCVD method, ALD method), a sputtering method, or the like.

In this embodiment, a 200-nm-thick silicon oxynitride film can be used as the insulating layer 110 by a plasma CVD method.

<Formation of Conductive Layer 120>
Next, a conductive film 120 a (not illustrated) is formed over the insulating layer 110. The conductive film 120a can be formed by a sputtering method, a CVD method, or the like. Note that in the case where a film is formed by a sputtering method, the power during film formation is 100 kW or less, preferably 60 kW or less, more preferably 20 kW, in order to suppress reduction in damage to the insulating layer 110.

In this embodiment, the conductive film 120a can be a tungsten film with a thickness of 200 nm formed by a sputtering method.

Next, a mask is formed over the conductive film 120a by a lithography process. The conductive film 120a is selectively etched using the mask, and the resist mask is removed. Thus, the conductive layer 120 can be formed (see FIG. 8B).
<Formation of Insulating Layer 130 and Insulating Layer 131>
Next, the insulating layer 131 and the insulating layer 130 are formed (see FIG. 8C). The insulating layer 130 and the insulating layer 131 can be formed by a sputtering method, a CVD method (plasma CVD method, MOCVD method, ALD method, or the like), an MBE method, or the like. For the insulating layer 130 and the insulating layer 131, an insulating film can be formed as appropriate by using a method similar to that of the insulating layer 110.

In this embodiment, 50 nm of silicon oxynitride can be formed as the insulating layer 130 by a plasma CVD method. Further, 400 nm of silicon nitride can be formed as the insulating layer 131 by a plasma CVD method.

<Formation of Oxide Semiconductor Layer 140>
Subsequently, an oxide semiconductor film 140a to be the oxide semiconductor layer 140 is formed over the insulating layer 130 (not illustrated). The oxide semiconductor film 140a can be formed by a sputtering method, an MOCVD method, a PLD method, or the like, and is more preferably formed by a sputtering method. As the sputtering method, an RF sputtering method, a DC sputtering method, an AC sputtering method, or the like can be used. In the sputtering method, a parallel plate method or a counter target method (counter electrode method) can be used. In the case of the sputtering method using the facing target method, the substrate is hardly exposed to plasma, so that damage during film formation is difficult. Accordingly, the oxide semiconductor film 140a with high crystallinity can be formed.

For example, in the case where the oxide semiconductor film 140a is formed by a sputtering method, each chamber in the sputtering apparatus is provided with an adsorption-type vacuum exhaust pump such as a cryopump so as to remove water that is an impurity for the oxide semiconductor as much as possible. It is preferable that a high vacuum (up to about 5 × 10 ⁻⁷ Pa to 1 × 10 ⁻⁴ Pa) can be obtained using the substrate, and the substrate to be formed can be heated to 100 ° C. or higher, preferably 400 ° C. or higher. Alternatively, it is preferable to combine a turbo molecular pump and a cold trap so that a gas containing a carbon component or moisture does not flow backward from the exhaust system into the chamber. Further, an exhaust system combining a turbo molecular pump and a cryopump may be used.

In order to obtain a high-purity intrinsic oxide semiconductor, it is necessary not only to evacuate the chamber to a high vacuum but also to increase the purity of the sputtering gas. Oxygen gas or argon gas used as a sputtering gas has a dew point of −40 ° C. or lower, preferably −80 ° C. or lower, more preferably −100 ° C. or lower. Can be prevented as much as possible.

As a sputtering gas, a rare gas (typically argon), oxygen, a rare gas, and a mixed gas of oxygen are appropriately used. Note that in the case of a mixed gas of a rare gas and oxygen, it is preferable to increase the gas ratio of oxygen to the rare gas.

In the case where the oxide semiconductor layer 140 is stacked as illustrated in FIG. 2, the oxide semiconductor film 141a (not illustrated) may have a larger indium content than the oxide semiconductor film 142a (not illustrated). Good. In oxide semiconductors, heavy metal s orbitals mainly contribute to carrier conduction, and by increasing the In content, more s orbitals overlap. Is higher in mobility than an oxide having a composition equivalent to or less than Ga. Therefore, by using an oxide containing a large amount of indium for the oxide semiconductor layer 141, a transistor with high mobility can be realized.

In the case where the oxide semiconductor film 141a and the oxide semiconductor film 142a are formed by a sputtering method, for example, the oxide semiconductor film 141a and the oxide semiconductor film 142a are exposed to the air by using a multi-chamber sputtering apparatus. It is possible to form a film continuously without doing this. In that case, unnecessary impurities or the like can be prevented from entering the interface between the oxide semiconductor film 141a and the oxide semiconductor film 142a, and the interface state can be reduced. As a result, the electrical characteristics of the transistor, in particular, the characteristics can be stabilized in the reliability test.

Note that when the oxide semiconductor film is formed, for example, when a sputtering method is used, the substrate temperature is 150 ° C. or higher and 750 ° C. or lower, preferably 150 ° C. or higher and 450 ° C. or lower, more preferably 200 ° C. or higher and 420 ° C. or lower. By forming the oxide semiconductor film, a CAAC-OS film can be formed.

In this embodiment, as the oxide semiconductor film 140a, an In—Ga—Zn oxide film with a target composition of In: Ga: Zn = 1: 1: 1 (atomic ratio) is formed to a thickness of 35 nm by a sputtering method.

Next, a resist mask is formed over the oxide semiconductor film 140a by a lithography process. The mask has the same or smaller area than the mask over which the conductive layer 120 is formed, and the oxide semiconductor film 140a is selectively etched with the mask, and the resist mask is removed. Thus, the oxide semiconductor layer 140 can be formed (see FIG. 8D). Note that an oxide semiconductor layer 145 (described later) which is to be the oxide conductive layer 400 in a later step is formed at the same time as the oxide semiconductor layer 140 is formed.

Next, heat treatment may be performed to desorb water, hydrogen, and the like contained in the insulating layer 110. As a result, the concentration of water, hydrogen, and the like contained in the insulating layer 110 to be formed later can be reduced, and the amount of diffusion of water, hydrogen, and the like into the oxide semiconductor layer 140 is reduced by heat treatment. be able to. Note that the heat treatment may be performed after the oxide semiconductor film 140a is formed.

The temperature of the heat treatment is typically 250 ° C. or higher and lower than the substrate strain point, preferably 300 ° C. or higher and 650 ° C. or lower, more preferably 350 ° C. or higher and 550 ° C. or lower. The treatment time is 3 minutes to 24 hours, preferably 30 minutes to 4 hours, at the set temperature.

The heat treatment can be performed in an inert gas atmosphere containing nitrogen or a rare gas such as helium, neon, argon, xenon, or krypton. Alternatively, after heating in an inert gas atmosphere, heating may be performed in an oxygen atmosphere or dry air (air having a dew point of −80 ° C. or lower, preferably −100 ° C. or lower, preferably −120 ° C. or lower). Alternatively, it may be performed in a reduced pressure state. In addition to the dry air, it is preferable that hydrogen, water, and the like are not contained in the inert gas and oxygen. Typically, the dew point is −80 ° C. or lower, preferably −100 ° C. or lower.

Note that in the heat treatment, an apparatus for heating an object to be processed by heat conduction or heat radiation from a heating element such as a resistance heating element may be used instead of an electric furnace. For example, a rapid thermal annealing (RTA) device such as a GRTA (Gas Rapid Thermal Anneal) device or an LRTA (Lamp Rapid Thermal Anneal) device can be used. The LRTA apparatus is an apparatus that heats an object to be processed by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp. The GRTA apparatus is an apparatus that performs heat treatment using a high-temperature gas. As the high-temperature gas, a rare gas such as argon or an inert gas such as nitrogen is used.

By forming the oxide semiconductor film while heating, and further by performing heat treatment after the oxide semiconductor film is formed, the hydrogen concentration in the oxide semiconductor film is 2 × 10 ²⁰ atoms / cm ³ or less. , Preferably 5 × 10 ¹⁹ atoms / cm ³ or less, more preferably 1 × 10 ¹⁹ atoms / cm ³ or less, preferably less than 5 × 10 ¹⁸ atoms / cm ³ , preferably 1 × 10 ¹⁸ atoms / cm ³ or less, more preferably May be 5 × 10 ¹⁷ atoms / cm ³ or less, more preferably 1 × 10 ¹⁶ atoms / cm ³ or less.

<Formation of Conductive Layer 150 and Conductive Layer 160>
Next, the conductive layer 150 and the conductive layer 150a to be the conductive layer 160 are formed over the insulating layer 110 and the oxide semiconductor layer 140 (not illustrated). The conductive film 150a is formed by sputtering, chemical vapor deposition (CVD) (metal organic chemical deposition (MOCVD), metal chemical vapor deposition, atomic layer deposition (ALD), or plasma chemical vapor deposition (plasma CVD). For example, a vapor deposition method, a pulsed laser deposition (PLD) method, or the like.

In this embodiment, a stacked film of a tungsten film with a thickness of 50 nm, an aluminum film with a thickness of 400 nm, and a titanium film with a thickness of 200 nm can be formed as the conductive film 150a by a sputtering method.

Next, a resist mask is formed by a lithography process, and the conductive film 150a is selectively etched using the resist mask, so that the conductive layer 150 and the conductive layer 160 are formed. The resist mask is removed. (See FIG. 8E).

Note that after the conductive layer 150 and the conductive layer 160 are formed, a cleaning process may be performed in order to remove an etching residue. By performing this cleaning treatment, a short circuit between the conductive layer 150 and the conductive layer 160 can be suppressed. The cleaning treatment can be performed using an alkaline solution such as a TMAH (Tetramethylammonium Hydroxide) solution or an acidic solution such as diluted hydrofluoric acid, oxalic acid, or phosphoric acid. Note that part of the oxide semiconductor layer 123 is etched by the cleaning treatment, so that a recess is formed. Further, the region damaged by the plasma damage of the oxide semiconductor layer 140 can be removed by the cleaning treatment.

<Formation of Insulating Layer 170>
Next, the conductive layer 150 and the insulating layer 170 are formed over the oxide semiconductor layer 140 and the conductive layer 160 (see FIG. 9A). The insulating layer 170 is formed using a condition in which oxygen is easily added in a later step of adding oxygen. The insulating layer can be formed by a sputtering method, a CVD method, an evaporation method, or the like. Note that in the CVD method, an oxide insulating film to which oxygen is easily added can be formed by setting the deposition temperature to 350 ° C. or lower, preferably 300 ° C. or lower, more preferably 250 ° C. or lower. In addition, when the pressure in the treatment chamber is set to 40 Pa or higher, preferably 100 Pa or higher, more preferably 200 Pa or higher, an oxide insulating film to which oxygen is easily added can be formed.

For example, the temperature at which the substrate 100 is held is 220 ° C., silane with a flow rate of 50 sccm, and dinitrogen monoxide with a flow rate of 2000 sccm are used as the source gas, the pressure in the chamber is 20 Pa, and the high-frequency power supplied to the parallel plate electrodes is 13.56 MHz and 100 W. A silicon oxynitride film can be formed by a plasma CVD method with a power density of 5.3 × 10 ⁻² W / cm ² . Subsequently, the temperature for holding the substrate 100 is 220 ° C., silane having a flow rate of 160 sccm and dinitrogen monoxide having a flow rate of 4000 sccm are used as source gases, the pressure in the processing chamber is 200 Pa, and high-frequency power supplied to the parallel plate electrodes is 13. The silicon oxynitride film can be formed by a plasma CVD method with a frequency of 56 MHz and 1500 W (power density is 8 × 10 ⁻¹ W / cm ² ).

Next, heat treatment may be performed. The temperature of the heat treatment is typically 150 ° C. or higher and lower than the substrate strain point, preferably 200 ° C. or higher and 450 ° C. or lower, more preferably 300 ° C. or higher and 450 ° C. or lower. Through the heat treatment, water, hydrogen, and the like contained in the insulating layer 170 can be released.

For example, heat treatment can be performed at 350 ° C. for 1 hour in a mixed gas atmosphere containing nitrogen and oxygen.
<Addition of oxygen>

Next, after an intermediate film 175 is formed over the insulating layer 170, oxygen 177 is added to the insulating layer 170 through the intermediate film 175 (see FIG. 9B). Further, oxygen 177 can be added to the oxide semiconductor layer 140. Note that oxygen is also added to the intermediate film 175 in this step.

The intermediate film 175 includes at least one selected from indium, zinc, titanium, aluminum, tungsten, tantalum, and molybdenum. Further, the intermediate film 175 includes the above-described metal, an alloy including the above-described metal element, an alloy combining the above-described metal elements, a metal oxide including the above-described metal element, a metal nitride including the above-described metal element, Alternatively, a conductive material such as a metal nitride oxide containing the above metal element may be used, and more oxygen can be added to the insulating layer 170.

Note that the intermediate film 175 is preferably formed by a sputtering method.

The intermediate film 175 is, for example, a tantalum nitride film, a titanium film, an indium tin oxide (hereinafter also referred to as ITO) film, an aluminum film, or an oxide semiconductor film (for example, an IGZO film (In: Ga: Zn = 1: 4: 5). (Atomic ratio))) and the like. Further, the intermediate film 175 can be formed by a sputtering method. The thickness of the intermediate film 175 is preferably 1 nm to 20 nm, or 2 nm to 10 nm. For example, as the intermediate film 175, indium tin oxide (Indium Tin SiO2 Doped Oxide: hereinafter referred to as an ITSO film) to which silicon oxide with a thickness of 5 nm is added can be used.

As a method for adding oxygen 177, there are an ion doping method, an ion implantation method, a plasma treatment method, and the like. Further, when the oxygen 177 is added, the oxygen 177 can be effectively added to the insulating layer 170 by applying a bias to the substrate 100 side. Further, oxygen 177 can be added to the oxide semiconductor layer 140. As the bias, for example, the power density may be 1 W / cm ² or more and 5 W / cm ² or less. By providing the intermediate film 175 over the insulating layer 170 and adding oxygen 177, the intermediate film 175 functions as a protective film that suppresses release of oxygen from the insulating layer 170 during the addition of oxygen 177. Therefore, more oxygen can be added to the insulating layer 170 and the oxide semiconductor film 17. In addition, oxygen is released from the insulating layer 170 in heat treatment performed after the insulating layer 170 is formed and before the intermediate film 175 is formed. Therefore, oxygen vacancies in the oxide semiconductor film 17 remain if the insulating layer 170 does not contain enough oxygen to reduce oxygen vacancies in the oxide semiconductor film 17. Thus, by adding oxygen to the insulating layer 170 through the intermediate film 175, the amount of oxygen vacancies in the oxide semiconductor layer 140 can be reduced.

In addition, when oxygen is introduced by plasma treatment, the amount of oxygen introduced into the insulating layer 170 can be increased by exciting oxygen with a microwave to generate high-density oxygen plasma.

Next, heat treatment may be performed. The temperature of the heat treatment is typically 150 ° C. or higher and lower than the substrate strain point, preferably 200 ° C. or higher and 450 ° C. or lower, more preferably 300 ° C. or higher and 450 ° C. or lower.

In the heat treatment, oxygen contained in the insulating layer 170 moves to the oxide semiconductor layer 140, so that the amount of oxygen vacancies in the oxide semiconductor layer 140 can be reduced. Note that since the intermediate film 175 functions as an oxygen barrier film, oxygen in the insulating layer 170 is not easily released to the outside in the heat treatment. Therefore, oxygen in the insulating layer 170 can be efficiently transferred to the oxide semiconductor layer 140.

Thereafter, the intermediate film 175 may be removed. As a method for removing the intermediate film 175, there are a dry etching method, a wet etching method, a method in which the dry etching method and the wet etching method are combined, and the like.

Subsequently, a resist mask is formed over the insulating layer 170 using photolithography, and the region and the peripheral insulating layer 170 are removed by etching to form the capacitor 60 (see FIG. 9C).

<Formation of Insulating Layer 180>
Subsequently, an insulating layer 180 is formed (see FIG. 9D). The insulating layer 180 can be formed by a plasma CVD method, a sputtering method, an evaporation method, an ALD method, or the like.

For example, it is desirable to form a silicon nitride film using a plasma ALD method. By using the plasma ALD method, a film can be formed with high coverage with respect to unevenness. Further, hydrogen in the silicon nitride film diffuses into the oxide semiconductor layer 140, whereby the conductivity of the oxide semiconductor layer is improved and the oxide conductive layer 400 can be formed. Further, when the oxide semiconductor layer 145 is irradiated with plasma at the time of film formation by a plasma ALD method, the conductivity of the oxide semiconductor layer 145 can be reduced. Therefore, by forming a silicon nitride film using a plasma ALD method, an insulating layer and a conductive layer with high barrier properties can be formed, so that a highly reliable transistor can be obtained.

Note that in the case where the insulating layer 180 is formed using the plasma ALD method, the insulating layer 180 may be formed only on the front surface side (the formation surface side of the transistor 50) of the substrate 100, or the side surface and the back surface (the surface on which the transistor 50 is not formed). ) Side may also be formed. In order to suppress formation of the insulating layer 180 on the side surface (including the chamfered portion) and the back surface, a metal mask, a mask using an organic material, or an inorganic material can be used.

<Formation of Conductive Layer 190>
Next, a conductive film 190a is formed over the insulating layer 180 (not shown). Note that opening treatment may be performed before the conductive film 190a is formed, if necessary.

The conductive film 190a can be formed by a sputtering method, an MOCVD method, an evaporation method, or the like.

For example, an ITSO film with a thickness of 100 nm can be used as the conductive film 190a.

After the conductive film 190a is formed, a mask is formed by a lithography process. With the use of the mask, the conductive film 190a can be selectively etched to form the conductive layer 190 (see FIG. 9E).

Next, heat treatment may be performed. The heat treatment is typically 150 ° C. or higher and lower than the substrate strain point, preferably 250 ° C. or higher and 500 ° C. or lower, more preferably 200 ° C. or higher and 350 ° C. or lower.
For example, heat treatment can be performed at 250 ° C. for 1 hour in an oxygen atmosphere.

Through the above steps, the localized state density of the oxide semiconductor film is reduced, so that a transistor having excellent electrical characteristics can be manufactured. In addition, a highly reliable transistor with little change in electrical characteristics due to aging and stress tests can be manufactured.

Note that the structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 3)
In this embodiment, modification examples of the semiconductor device and the capacitor described in Embodiments 1 and 2 are described.

<Modification Example 1 of Transistor>
10A and 10B are a top view of a transistor 54 and a capacitor 64 which are modifications of the semiconductor device, and a cross-sectional view in the direction of dashed-dotted line X3-X4.

<< Insulating layer 195 >>
The transistor 54 and the capacitor 64 are different from the transistor 50 and the capacitor 60 in that an insulating layer 195 is provided over the conductive layer 190. Another difference is that the conductive layer 190 extends not only as an electrode of the capacitor element but also from the capacitor element to the transistor, and has a function as a back gate electrode of the transistor. In addition, by providing an insulating film having a barrier property against oxygen, hydrogen, water, or the like from the outside as the insulating layer 195, diffusion of oxygen from the oxide semiconductor layer 140 to the outside and the oxide semiconductor layer 140 from the outside can be performed. Intrusion of hydrogen, water, etc. into the water can be prevented. For example, insulation including one or more of aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide A membrane can be used. The insulating layer 195 may be a stack of the above materials. Note that the insulating layer 195 may contain lanthanum (La), nitrogen, zirconium (Zr), or the like as impurities. For example, an aluminum oxide film is preferably formed as the insulating layer 195 by an ALD method. Since the covering property with respect to the unevenness is good, the barrier property can be enhanced. Thereby, the electrical characteristics of the transistor, in particular, the reliability can be improved.

Note that in the case where the insulating layer 195 is provided, the insulating layer 180 can be formed by a plasma CVD method, whereby the hydrogen concentration can be increased, and the oxide conductive layer 400 having stable conductivity can be formed, and The coverage can be improved.

<Modification Example 2 of Transistor>
11A and 11B are a top view of a transistor 55 and a capacitor 65 which are modifications of the semiconductor device, and a cross-sectional view in the direction of dashed-dotted line X5-X6.

The transistor 55 and the capacitor 65 are different from the transistor 50 and the capacitor 60 in that an insulating layer 195 is provided over the conductive layer 190. In addition, after the insulating layer 180 is processed by etching using an area mask wider than the upper surface of the insulating layer 170, the conductive layer 190 is formed, and the insulating layer 195 is further formed. Different. With this structure, the barrier property against hydrogen, water, and oxygen can be further improved, and the electrical characteristics, particularly reliability, of the transistor can be further improved.

Note that the structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 4)
In this embodiment, details of a display device including the transistor and the capacitor described in Embodiments 1, 2, and 3 are described with reference to drawings.

12A and 12B are examples of a top view and a cross-sectional view of the display device 10. Note that FIG. 12A illustrates a typical structure including the display panel 20, the display region 21, the peripheral circuit 22, and the FPC.

FIG. 12B is a cross-sectional view taken along broken lines A-A ′, B-B ′, C-C ′, and D-D ′ in FIG. A-A 'indicates a peripheral portion of the display device, B-B' indicates a peripheral circuit portion, C-C 'indicates a display area, and D-D' indicates a connection portion with the FPC.

<Configuration example of transmissive liquid crystal panel>
As a display panel mounted on the display device, a transmissive liquid crystal panel can be used as shown in FIG. In the display device illustrated in FIG. 12B, a liquid crystal element 80 is used as a display element. Further, the display device 10 includes a polarizing plate 103, a polarizing plate 303, a backlight 104, and a protective substrate 302, which are bonded to each other with an adhesive layer 373, an adhesive layer 374, an adhesive layer 375, and an adhesive layer 376. .

As other examples of the liquid crystal panel, a reflective type, a transflective type, a direct view type, a projection type, or the like can be used.

<Transistor 50, Capacitance Element 60>
For the transistor 50 and the capacitor 60, the materials and manufacturing methods described in Embodiments 1 and 2 can be used. Note that a planarization film, an insulating film, a conductive layer, or the like can be provided over the transistor 50 and the capacitor 60.

<Peripheral structure>
Note that with the display device 10 having a configuration such as the transistor 50 and the capacitor 60, the operation of the peripheral circuit can be stabilized even when the display device has a narrow frame.

<Structure of Transistor 550 and Capacitance Element 560>
The transistor 550 is a transistor that forms a peripheral circuit portion. The transistor 550 can be formed in the same manner as the transistor 50 or can have the dual gate structure shown in the transistor 55. Further, the capacitor 560 may be formed in the same process as the capacitor 60, or the conductive layer 120, the conductive layer 150, or the conductive layer 190, the insulating layer 130, the insulating layer 131, the insulating layer 170, and the insulating layer. The layers 180 may be combined.

In the case where the insulating layer 180 is formed using the plasma ALD method, the insulating layer 180 can be formed only on elements such as the transistor 50 and the capacitor element 60, or can be formed on the back surface side of the substrate 100 as shown in FIG. You can also. It may be formed also on the side surface portion and the back surface side. In order to suppress the formation of the insulating layer 180 on the side surface (including the chamfered portion), the back surface, and the connection portion with the FPC, a metal mask, a mask using an organic material, or an inorganic material can be used.

In addition, the display device can include the transistor and the capacitor described in Embodiment 3. For example, a transistor 54 and a capacitor 64 can be provided as shown in FIG. 14, or a transistor 55 and a capacitor 65 can be provided as shown in FIG. Note that the transistor 554 in FIG. 14 can have the same structure as the transistor 54 and the capacitor 564 can have the same structure as the capacitor 64. The transistor 555 in FIG. 15 can have the same structure as the transistor 55 and the capacitor 565 can have the same structure as the capacitor 65.

Further, a planarization film can be provided over the above-described transistor and the capacitor. As the planarization film, an inorganic material or an organic material can be used. For example, silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride and other oxide insulating films, silicon nitride, aluminum nitride, etc. It is formed using a heat-resistant organic material such as a nitride insulating film, polyimide resin, acrylic resin, polyimide amide resin, benzocyclobutene resin, polyamide resin, or epoxy resin.
<< Substrate 300 >>
The substrate 300 can have a material similar to that of the substrate 100.

<< Conductive layer 380 >>
The conductive layer 380 is formed using a conductive film that transmits visible light. As the conductive film that transmits light with visible light, a material containing one kind selected from indium (In), zinc (Zn), and tin (Sn) may be used, for example. As a conductive film having a light-transmitting property with respect to visible light, typically, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, or indium oxide containing titanium oxide is used. Further, a conductive oxide such as an indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide containing silicon oxide can be used.

<< Insulating layer 330 >>
The insulating layer 330 has a planarization function. The insulating layer 330 can be formed using an inorganic material or an organic material. For example, silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride and other oxide insulating films, silicon nitride, aluminum nitride, etc. It is formed using a heat-resistant organic material such as a nitride insulating film, polyimide resin, acrylic resin, polyimide amide resin, benzocyclobutene resin, polyamide resin, or epoxy resin.

<< Colored layer 360 >>
The colored layer 360 is a colored layer that transmits light in a specific wavelength band. For example, a color filter that transmits light in a red, green, blue, or yellow wavelength band can be used. Each colored layer is formed at a desired position using a variety of materials by a printing method, an inkjet method, an etching method using a photolithography method, or the like. In a white pixel, a transparent or white resin may be disposed so as to overlap the light emitting element.

<Light shielding layer 18>
A light-shielding material can be used for the light-shielding layer 18. For example, an inorganic film such as a black chrome film can be used for the light shielding layer 18 in addition to a resin in which a pigment is dispersed and a resin containing a dye. Carbon black, an inorganic oxide, a composite oxide containing a solid solution of a plurality of inorganic oxides, or the like can be used for the light shielding layer 18.

<< Spacer 240 >>
An insulating material can be used for the spacer 240. For example, an inorganic material, an organic material, or a material in which an inorganic material and an organic material are stacked can be used. Specifically, a film containing silicon oxide, silicon nitride, or the like, acrylic, polyimide, or a photosensitive resin can be used.

<< Adhesive layer 370 >>
An inorganic material, an organic material, a composite material of an inorganic material and an organic material, or the like can be used for the adhesive layer 370.

For example, an organic material such as a photocurable adhesive, a reactive curable adhesive, a thermosetting adhesive, and / or an anaerobic adhesive can be used for the adhesive layer 370. In addition, each adhesive agent can also be used independently or can also be used in combination.

The photo-curable adhesive refers to an adhesive that is cured by, for example, ultraviolet rays, electron beams, visible light, infrared rays, or the like.

Specifically, epoxy resin, acrylic resin, silicone resin, phenol resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, EVA (ethylene vinyl acetate) resin, silica, etc. An adhesive containing the adhesive layer 370 can be used.

In particular, when a photo-curing adhesive is used, the curing speed of the material is fast, and the working time can be shortened. Moreover, since hardening is started by irradiating light, the influence by a film-forming process can be suppressed. Further, it can be cured at a low temperature, and the working environment can be easily controlled. As described above, by using a photo-curing adhesive, the process can be shortened and processed at low cost.

<< FPC42 >>
The FPC 42 is electrically connected to the conductive layer 190 through the anisotropic conductive film 510. An image signal or the like can be supplied from the FPC 42 to a driver circuit including the transistor 550, the capacitor 560, and the like.

<Liquid crystal element 80>
The liquid crystal element 80 can be driven in a TN (Twisted Nematic) mode. The liquid crystal layer 390 can control the alignment of liquid crystal molecules included in the liquid crystal layer 390 by receiving an electric field from the conductive layer 190 and the conductive layer 380, and functions as the liquid crystal element 80.

Note that although not illustrated in FIG. 12, an alignment film may be provided on each of the conductive layer 190 and the conductive layer 380 on the side in contact with the liquid crystal layer 390.

With the above structure, a highly reliable display device can be provided.
<< Liquid crystal element 81 >>
As a driving method of the liquid crystal element, a liquid crystal element 81 using lateral electric field driving can be used as shown in FIG. The liquid crystal element 81 can be driven in an FFS (Fringe Field Switching) mode. The liquid crystal layer 390 can control the alignment of liquid crystal molecules included in the liquid crystal layer 390 by receiving an electric field from the conductive layer 190 and has a function as the liquid crystal element 81.

Examples of other driving methods of a display device using a liquid crystal element include an STN mode, a VA mode, an ASM (Axial Symmetrical Aligned Micro-cell) mode, an OCB (Optically Compensated Birefringence) mode, and an FLC (Ferroelectric) mode. AFLC (Anti Ferroelectric Liquid Crystal) mode, MVA mode, PVA (Patterned Vertical Alignment) mode, IPS (In Plane Switching) mode, TBA (Transverse Bend Alignment) mode, etc. may be used. In addition to the above-described driving methods, there are ECB (Electrically Controlled Birefringence) mode, PDLC (Polymer Dispersed Liquid Crystal) mode, PNLC (Polymer Network Liquid Host mode), and other driving methods for the display device. However, the present invention is not limited to this, and various liquid crystal elements and driving methods thereof can be used.

Further, the liquid crystal element 80 may be formed of a liquid crystal composition including a liquid crystal exhibiting a nematic phase and a chiral agent. In this case, it becomes a cholesteric phase or a blue phase (Blue Phase). A liquid crystal exhibiting a blue phase has a response speed as short as 1 msec or less and is optically isotropic. Therefore, alignment treatment is unnecessary and viewing angle dependency is small.

In the embodiment of the present invention, a liquid crystal element is illustrated as a display element, but a light-emitting element can also be used. An organic EL element or the like can be used as the light emitting element. By using the organic EL element, a high-definition and stereoscopic display can be manufactured.

<Combination with touch sensor of display device>
The display device 10 can form a touch panel in combination with a touch sensor. 17, 18, and 19 are cross-sectional views of the touch panel. The electrode of the touch sensor may be an on-cell type formed on the viewing side (front side) of the substrate 300, or an in-cell type formed on the inner side (display element side) as shown in FIG. As shown in FIGS. 18 and 19, a conductive layer 410, a conductive layer 430, an insulating layer 420, and an insulating layer 440 can be used as electrodes (wirings) for a touch sensor. For the wiring for the touch sensor, the conductive layer 380 used in the display panel can be used, and an on-cell touch panel can be formed in combination.

<< Conductive layers 410, 430 >>
The conductive layer 410 is a metal element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten, or an alloy containing the above metal element as a component, or a combination of the above metal elements. It is formed using an alloy or the like. Further, it may be formed using a metal element selected from one or more of manganese and zirconium. The conductive layer may have a single-layer structure or a stacked structure including two or more layers. For example, a single layer structure of an aluminum film containing silicon, a single layer structure of a copper film containing manganese, a two layer structure in which a titanium film is laminated on an aluminum film, a two layer structure in which a titanium film is laminated on a titanium nitride film, and nitriding A two-layer structure in which a tungsten film is stacked on a titanium film, a two-layer structure in which a tungsten film is stacked on a tantalum nitride film or a tungsten nitride film, a two-layer structure in which a copper film is stacked on a copper film containing manganese, and a titanium film A three-layer structure in which an aluminum film is laminated on the titanium film and a titanium film is further formed thereon, a copper film is laminated on the copper film containing manganese, and a copper film containing manganese is further formed thereon. There are three-layer structures.

Alternatively, an alloy film or nitride film selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be used. Alternatively, as a conductive film such as the conductive layer 410, that is, a material that can be used for a wiring or an electrode included in the touch panel, a transparent conductive film (eg, ITO) containing indium oxide, tin oxide, zinc oxide, or the like can be given. It is done. In addition, as a material that can be used for the wiring and electrodes constituting the touch panel, for example, a lower resistance value is preferable. As an example, silver, copper, aluminum, carbon nanotube, graphene, metal halide (such as silver halide), or the like may be used. Furthermore, a metal nanowire configured using a plurality of conductors that are very thin (for example, a diameter of several nanometers) may be used. Or you may use the metal mesh which made the conductor a mesh shape. As an example, Ag nanowire, Cu nanowire, Al nanowire, Ag mesh, Cu mesh, Al mesh, or the like may be used.

For example, when Ag nanowires are used for the wiring and electrodes constituting the touch panel, the transmittance in visible light can be 89% or more, and the sheet resistance value can be 40Ω / □ or more and 100Ω / □ or less. In addition, metal nanowires, metal meshes, carbon nanotubes, graphene, and the like, which are examples of materials that can be used for the wiring and electrodes included in the touch panel described above, have high transmittance in visible light; For example, it may be used as a pixel electrode or a common electrode. A similar film can be used for the conductive layer 430.

<< Insulating layers 420, 440 >>
The insulating layer 420 can be formed using an inorganic material or an organic material. For example, silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride and other oxide insulating films, silicon nitride, aluminum nitride, etc. It is formed using a heat-resistant organic material such as a nitride insulating film, polyimide resin, acrylic resin, polyimide amide resin, benzocyclobutene resin, polyamide resin, or epoxy resin. For the insulating layer 440, a film similar to 420 can be used.

<Organic EL panel>
In addition, the display device 10 using the light-emitting element 70 as a display element can be manufactured.

37, 38, and 39 are cross-sectional views of a display device using a light-emitting element. A portion used in common with a liquid crystal panel such as a transistor can be formed in a similar manner.

<< Light-emitting element 70 >>
As the light-emitting element 70, an element capable of self-emission can be used, and an element whose luminance is controlled by current or voltage is included in its category. For example, a light emitting diode (LED), an organic EL element, an inorganic EL element, or the like can be used. For example, an organic EL element including a lower electrode, an upper electrode, and a layer containing a light-emitting organic compound (hereinafter also referred to as an EL layer 250) between the lower electrode and the upper electrode can be used for the light-emitting element 70.

The light emitting element may be any of a top emission type, a bottom emission type, and a dual emission type. A conductive film having a property of transmitting visible light is used for the electrode from which light is extracted. In addition, a conductive film that reflects visible light is used for the electrode from which light is not extracted.

When a voltage higher than the threshold voltage of the light-emitting element is applied between the lower electrode made of the conductive layer 220 and the upper electrode made of the conductive layer 260, holes are injected into the EL layer 250 from the anode side and electrons from the cathode side. Is injected. The injected electrons and holes are recombined in the EL layer 250, and the light-emitting substance contained in the EL layer 250 emits light.

The EL layer 250 includes at least a light emitting layer. The EL layer 250 is a layer other than the light-emitting layer, such as a substance having a high hole-injecting property, a substance having a high hole-transporting property, a hole blocking material, a substance having a high electron-transporting property, a substance having a high electron-injecting property, or a bipolar property A layer containing a substance (a substance having a high electron transporting property and a high hole transporting property) or the like may be further included.

The EL layer 250 can use either a low molecular compound or a high molecular compound, and may contain an inorganic compound. The layers constituting the EL layer 250 can be formed by a method such as a vapor deposition method (including a vacuum vapor deposition method), a transfer method, a printing method, an ink jet method, or a coating method.

The light emitting element may contain two or more light emitting substances. Thereby, for example, a white light emitting element can be realized. For example, white light emission can be obtained by selecting the light emitting material so that the light emission of each of the two or more light emitting materials has a complementary color relationship. For example, a light-emitting substance that emits light such as R (red), G (green), B (blue), Y (yellow), or O (orange), or spectral components of two or more colors of R, G, and B A light-emitting substance that emits light containing can be used. For example, a light-emitting substance that emits blue light and a light-emitting substance that emits yellow light may be used. At this time, the emission spectrum of the luminescent material that emits yellow light preferably includes green and red spectral components. The emission spectrum of the light-emitting element 70 preferably has two or more peaks in the visible wavelength range (for example, 350 nm to 750 nm or less, or 400 nm to 800 nm or less).

The EL layer 250 may include a plurality of light emitting layers. In the EL layer 250, the plurality of light-emitting layers may be stacked in contact with each other or may be stacked via a separation layer. For example, a separation layer may be provided between the fluorescent light emitting layer and the phosphorescent light emitting layer.

The separation layer can be provided, for example, to prevent energy transfer (particularly triplet energy transfer) by a Dexter mechanism from an excited state of the phosphorescent material generated in the phosphorescent light emitting layer to the fluorescent material in the fluorescent light emitting layer. The separation layer may have a thickness of about several nm. Specifically, the thickness is 0.1 nm to 20 nm, or 1 nm to 10 nm, or 1 nm to 5 nm. The separation layer includes a single material (preferably a bipolar substance) or a plurality of materials (preferably a hole transport material and an electron transport material).

The separation layer may be formed using a material included in the light emitting layer in contact with the separation layer. This facilitates the production of the light emitting element and reduces the driving voltage. For example, when the phosphorescent light-emitting layer is formed of a host material, an assist material, and a phosphorescent material (guest material), the separation layer may be formed using the host material and the assist material. In other words, the separation layer has a region not containing a phosphorescent material, and the phosphorescent light-emitting layer has a region containing a phosphorescent material. Thereby, the separation layer and the phosphorescent light emitting layer can be deposited with or without the phosphorescent material. Further, with such a structure, the separation layer and the phosphorescent light emitting layer can be formed in the same chamber. Thereby, manufacturing cost can be reduced.

<Microcavity adjusting layer 230>
A light emitting element 70 in FIG. 37 is an example in which a microresonator structure is combined with a light emitting element. For example, the microresonator structure may be configured using the lower electrode and the upper electrode of the light emitting element 70, and specific light may be efficiently extracted from the light emitting element.

Specifically, a reflective film that reflects visible light is used for the lower electrode, and a semi-transmissive / semi-reflective film that transmits part of visible light and reflects part of it is used for the upper electrode. And an upper electrode is arrange | positioned with respect to a lower electrode so that the light which has a predetermined wavelength can be taken out efficiently.

For example, the lower electrode functions as a lower electrode or an anode of the light emitting element. Alternatively, the lower electrode has a function of adjusting the optical distance so that desired light from the light emitting layer can resonate and the wavelength thereof can be increased. Note that the layer 230 for adjusting the optical distance is not limited to the lower electrode, and the optical distance may be adjusted by at least one layer constituting the light emitting element. The layer 230 for adjusting the optical distance is formed using, for example, indium oxide, indium tin oxide (ITO), indium zinc oxide, zinc oxide (ZnO), zinc oxide to which gallium is added, or the like. be able to.

When the microresonator structure is combined, a semi-transmissive / semi-reflective electrode can be used as the upper electrode of the light emitting element. The semi-transmissive / semi-reflective electrode is formed of a conductive material having reflectivity and a conductive material having translucency. Examples of the conductive material include a conductive material having a visible light reflectance of 20% to 80%, preferably 40% to 70%, and a resistivity of 1 × 10 ⁻² Ω · cm or less. Can be mentioned. The semi-transmissive / semi-reflective electrode can be formed using one or more kinds of conductive metals, alloys, conductive compounds, and the like. In particular, it is preferable to use a material having a small work function (3.8 eV or less). For example, elements belonging to Group 1 or Group 2 of the periodic table (alkali metals such as lithium and cesium, alkaline earth metals such as calcium and strontium, magnesium, etc.), and alloys containing these elements (eg, Ag-Mg) Al-Li), rare earth metals such as europium and ytterbium, alloys containing these rare earth metals, aluminum, silver, and the like can be used.

Note that the electrodes may be formed using an evaporation method or a sputtering method, respectively. In addition, it can be formed using a discharge method such as an inkjet method, a printing method such as a screen printing method, or a plating method.

Note that a method other than the microresonator structure can be used as the structure of the organic EL. For example, a separate coating method in which the light emitting colors of the light emitting elements are different and a white EL method in which light is emitted using a material that emits white light can be used.

<Partition 245>
An insulating material can be used for the partition wall 245. For example, an inorganic material, an organic material, or a material in which an inorganic material and an organic material are stacked can be used. Specifically, a film containing silicon oxide, silicon nitride, or the like, acrylic, polyimide, or a photosensitive resin can be used.

<< Conductive layer 200 >>
The conductive layer 200 is a metal element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten, or an alloy containing the above metal element as a component, or a combination of the above metal elements. It is formed using an alloy or the like. Further, it may be formed using a metal element selected from one or more of manganese and zirconium. The conductive layer 200 may have a single-layer structure or a stacked structure including two or more layers. For example, a single layer structure of an aluminum film containing silicon, a single layer structure of a copper film containing manganese, a two layer structure in which a titanium film is laminated on an aluminum film, a two layer structure in which a titanium film is laminated on a titanium nitride film, and nitriding A two-layer structure in which a tungsten film is stacked on a titanium film, a two-layer structure in which a tungsten film is stacked on a tantalum nitride film or a tungsten nitride film, a two-layer structure in which a copper film is stacked on a copper film containing manganese, and a titanium film A three-layer structure in which an aluminum film is laminated on the titanium film and a titanium film is further formed thereon, a copper film is laminated on the copper film containing manganese, and a copper film containing manganese is further formed thereon. There are three-layer structures. Alternatively, an alloy film or nitride film selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be used.

<< Insulating layer 210 >>
The insulating layer 210 has a function of planarization. The insulating layer 210 can be formed using an inorganic material or an organic material. For example, silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride and other oxide insulating films, silicon nitride, aluminum nitride, etc. It is formed using a heat-resistant organic material such as a nitride insulating film, polyimide resin, acrylic resin, polyimide amide resin, benzocyclobutene resin, polyamide resin, or epoxy resin.

<< Conductive layer 220 >>
As the conductive layer 220 that reflects visible light, for example, a metal material such as aluminum, gold, platinum, silver, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, or palladium, or an alloy including these metal materials is used. Can be used. In addition, lanthanum, neodymium, germanium, or the like may be added to the metal material or alloy. Also, alloys containing aluminum (aluminum alloys) such as aluminum and titanium alloys, aluminum and nickel alloys, aluminum and neodymium alloys, aluminum, nickel, and lanthanum alloys (Al-Ni-La), silver and copper Or an alloy containing silver such as an alloy of silver, palladium and copper (also referred to as Ag-Pd-Cu or APC), an alloy of silver and magnesium, or the like. An alloy containing silver and copper is preferable because of its high heat resistance. Furthermore, the oxidation of the aluminum alloy film can be suppressed by stacking the metal film or the metal oxide film in contact with the aluminum alloy film. Examples of the material for the metal film and metal oxide film include titanium and titanium oxide. Alternatively, the conductive film that transmits visible light and a film made of a metal material may be stacked. For example, a laminated film of silver and ITO, a laminated film of an alloy of silver and magnesium and ITO, or the like can be used.

<< Conductive layer 260 >>
The conductive layer 260 that transmits visible light is formed using, for example, indium oxide, indium tin oxide (ITO), indium zinc oxide, zinc oxide (ZnO), zinc oxide to which gallium is added, or the like. can do. In addition, a metal material such as gold, silver, platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium, or titanium, an alloy including these metal materials, or a nitride of these metal materials (for example, Titanium nitride) can also be used by forming it thin enough to have translucency. In addition, a stacked film of the above materials can be used as a conductive layer. For example, it is preferable to use a laminated film of silver and magnesium alloy and ITO because the conductivity can be increased. Further, graphene or the like may be used.

<Different organic EL panel>
Further, the organic EL element can also be manufactured using a separate coating method as shown in FIG. 30 is different from FIG. 30 in that an EL layer 250 is formed on the conductive layer 220 by a separate coating method.

<Flexible display device>
In addition, the display device can be manufactured over flexible substrates 101 and 301 as illustrated in FIG.
The flexible substrate and the display device can be attached using the adhesive layer 370. Thereby, the touch panel has flexibility and can be bent or a curved touch panel can be realized. Furthermore, since the thickness of the substrate can be reduced, the weight of the touch panel can be reduced.

<Example of flexible display manufacturing method>
Here, a method for manufacturing a flexible display device is described.

Here, for convenience, a configuration including pixels and circuits, a configuration including an optical member such as a color filter, or a configuration including a touch sensor is referred to as an element layer. The element layer includes, for example, a display element, and may include an element such as a wiring electrically connected to the display element, a transistor used for a pixel or a circuit, in addition to the display element.

Here, a support (for example, the substrate 101 or the substrate 301) including an insulating surface on which an element layer is formed is referred to as a base material.

As a method of forming an element layer on a base material having a flexible insulating surface, a method of forming an element layer directly on the base material, and an element layer after forming an element layer on a support base material And a method of peeling the support substrate and transferring the element layer to the substrate.

When the material which comprises a base material has heat resistance with respect to the heat concerning the formation process of an element layer, when an element layer is directly formed on a base material, since a process is simplified, it is preferable. At this time, it is preferable to form the element layer in a state in which the base material is fixed to the support base material, because it is easy to transport the device inside and between the devices.

In the case of using a method in which an element layer is formed on a supporting substrate and then transferred to the substrate, a peeling layer and an insulating layer are first stacked on the supporting substrate, and an element layer is formed on the insulating layer. Then, a support base material and an element layer are peeled and it transfers to a base material. At this time, a material that causes peeling in the interface between the support base and the release layer, the interface between the release layer and the insulating layer, or the release layer may be selected.

For example, a layer including a refractory metal material such as tungsten and a layer including an oxide of the metal material are stacked as the separation layer, and a layer in which a plurality of silicon nitrides or silicon oxynitrides are stacked over the separation layer is used. preferable. It is preferable to use a refractory metal material because the degree of freedom in forming the element layer is increased.

Peeling may be performed by applying a mechanical force, etching the peeling layer, or dropping a liquid on a part of the peeling interface to permeate the entire peeling interface. Alternatively, peeling may be performed by applying heat to the peeling interface using a difference in thermal expansion.

In the case where peeling is possible at the interface between the support base and the insulating layer, the peeling layer may not be provided. For example, glass is used as a supporting substrate, an organic resin such as polyimide is used as an insulating layer, a part of the organic resin is locally heated using a laser beam or the like, and a starting point of peeling is formed. Peeling may be performed at the interface of the insulating layer. Alternatively, a metal layer is provided between the support base and the insulating layer made of an organic resin, and the metal layer is heated by passing an electric current through the metal layer, whereby peeling is performed at the interface between the metal layer and the insulating layer. May be. At this time, an insulating layer made of an organic resin can be used as a base material.

Examples of flexible base materials include polyester resins such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile resins, polyimide resins, polymethyl methacrylate resins, polycarbonate (PC) resins, and polyether sulfones. (PES) resin, polyamide resin, cycloolefin resin, polystyrene resin, polyamideimide resin, polyvinyl chloride resin and the like. In particular, a material having a low thermal expansion coefficient is preferably used. For example, a polyamideimide resin, a polyimide resin, PET, or the like having a thermal expansion coefficient of 30 × 10 ⁻⁶ / K or less can be suitably used. In addition, a substrate in which a fibrous body is impregnated with a resin (also referred to as a prepreg) or a substrate in which an inorganic filler is mixed with an organic resin to reduce the thermal expansion coefficient can be used.

When a fibrous body is included in the material, a high-strength fiber of an organic compound or an inorganic compound is used for the fibrous body. The high-strength fiber specifically refers to a fiber having a high tensile modulus or Young's modulus, and representative examples include polyvinyl alcohol fiber, polyester fiber, polyamide fiber, polyethylene fiber, aramid fiber, Examples include polyparaphenylene benzobisoxazole fibers, glass fibers, and carbon fibers. Examples of the glass fiber include glass fibers using E glass, S glass, D glass, Q glass, and the like. These may be used in the form of a woven fabric or a non-woven fabric, and a structure obtained by impregnating the fiber body with a resin and curing the resin may be used as a flexible substrate. When a structure made of a fibrous body and a resin is used as the flexible substrate, it is preferable because reliability against breakage due to bending or local pressing is improved.

Alternatively, glass, metal, or the like thin enough to have flexibility can be used for the base material. Alternatively, a composite material in which glass and a resin material are bonded together may be used.

For example, in the case of the configuration shown in FIG. 39, after the first release layer and the insulating layer 112 are formed in this order on the first support base material, the upper layer structure is formed. Separately from this, a second release layer and an insulating layer 312 are formed in this order on the second support substrate, and then an upper structure is formed. Subsequently, the first support substrate and the second support substrate are bonded together by the adhesive layer 370. After that, the second supporting substrate and the second peeling layer are removed by peeling at the interface between the second peeling layer and the insulating layer 312, and the insulating layer 312 and the substrate 301 are bonded to each other with the adhesive layer 372. In addition, the first supporting base material and the first peeling layer are removed by peeling at the interface between the first peeling layer and the insulating layer 112, and the insulating layer 112 and the substrate 101 are bonded to each other with the adhesive layer 371. Note that either side may be peeled and bonded first.

The above is the description of the method for manufacturing the flexible display device.

Note that the structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 5)
In this embodiment, a modification example of the transistor structure described in Embodiments 1 and 3 is described.

<Channel protection type and top gate structure>
Although the transistor 50 and the like illustrated in FIG. 12B are bottom-gate transistors, the invention is not limited thereto. As modified examples of the transistor 50, a transistor 57 is illustrated in FIG. 20A, a transistor 58 is illustrated in FIG. 20B, and a transistor 59 is illustrated in FIG. In FIG. 12B, the transistor 50 is shown as a channel etch type, but as shown in the cross-sectional views of FIGS. 20A and 20B, the channel protection type transistor 58 provided with an insulating layer 165 is also used. Alternatively, a top-gate transistor 59 can be formed as shown in the cross-sectional view of FIG.

Note that all the transistors 52 included in the peripheral circuit (such as a gate driver) may have the same structure or two or more kinds of structures. In addition, the plurality of transistors 50 included in the pixel portion may all have the same structure, or two or more kinds of structures.

Alternatively, the transistor described in this embodiment is an example in which a transistor including an oxide semiconductor is used; however, one embodiment of the present invention is not limited thereto. In some cases or depending on circumstances, one embodiment of the present invention may use a transistor including a semiconductor material different from an oxide semiconductor.

For example, a transistor including a Group 14 element, a compound semiconductor, an oxide semiconductor, or the like can be used for the oxide semiconductor layer 140. Specifically, a transistor including a semiconductor containing silicon, a semiconductor containing gallium arsenide, an organic semiconductor, or the like can be used.

For example, single crystal silicon, polysilicon, amorphous silicon, or the like can be applied to the semiconductor layer of the transistor.

Note that the structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 6)
In this embodiment, an example of a structure of the display panel of one embodiment of the present invention will be described with reference to FIGS.

<Configuration example>
FIG. 21A is a top view of a display device of one embodiment of the present invention, and FIG. 21B can be used when a liquid crystal element is applied to a pixel of the display device of one embodiment of the present invention. It is a circuit diagram for demonstrating a pixel circuit. FIG. 21C is a circuit diagram illustrating a pixel circuit that can be used when an organic EL element is applied to a pixel of the display device of one embodiment of the present invention.

The transistor provided in the pixel portion can be formed according to the above embodiment mode. In addition, since the transistor can easily be an n-channel transistor, a part of the driver circuit that can be formed using an n-channel transistor is formed over the same substrate as the transistor in the pixel portion. In this manner, a highly reliable display device can be provided by using the transistor described in the above embodiment for the pixel portion and the driver circuit.

An example of a top view of the active matrix display device is shown in FIG. A pixel portion 701, a scan line driver circuit 702, a scan line driver circuit 703, and a signal line driver circuit 704 are provided over a substrate 700 of the display device. In the pixel portion 701, a plurality of signal lines are extended from the signal line driver circuit 704 and a plurality of scanning lines are extended from the scanning line driver circuit 702 and the scanning line driver circuit 703. Note that pixels each having a display element are provided in a matrix in the intersection region between the scan line and the signal line. In addition, the substrate 700 of the display device is connected to a timing control circuit (also referred to as a controller or a control IC) through a connection portion such as an FPC.

In FIG. 21A, the scan line driver circuit 702, the scan line driver circuit 703, and the signal line driver circuit 704 are formed over the same substrate 700 as the pixel portion 701. For this reason, the number of components such as a drive circuit provided outside is reduced, so that cost can be reduced. Further, when a drive circuit is provided outside the substrate 700, it is necessary to extend the wiring, and the number of connections between the wirings increases. In the case where a driver circuit is provided over the same substrate 700, the number of connections between the wirings can be reduced, so that reliability or yield can be improved.

<Liquid crystal display device>
An example of a circuit configuration of the pixel is shown in FIG. Here, a pixel circuit that can be applied to a pixel of a VA liquid crystal display device is shown as an example.

This pixel circuit can be applied to a configuration having a plurality of pixel electrode layers in one pixel. Each pixel electrode layer is connected to a different transistor, and each transistor is configured to be driven by a different gate signal. Thereby, the signals applied to the individual pixel electrode layers of the multi-domain designed pixels can be controlled independently.

The gate wiring 712 of the transistor 716 and the gate wiring 713 of the transistor 717 are separated so that different gate signals can be given. On the other hand, the data line 714 is used in common by the transistor 716 and the transistor 717. The transistors described in the above embodiments can be used as appropriate as the transistors 716 and 717. Thereby, a highly reliable liquid crystal display device can be provided.

The shapes of the first pixel electrode layer electrically connected to the transistor 716 and the second pixel electrode layer electrically connected to the transistor 717 are described. The shapes of the first pixel electrode layer and the second pixel electrode layer are separated by a slit. The first pixel electrode layer has a V-shaped shape, and the second pixel electrode layer is formed so as to surround the outside of the first pixel electrode layer.

A gate electrode of the transistor 716 is connected to the gate wiring 712, and a gate electrode of the transistor 717 is connected to the gate wiring 713. Different gate signals are given to the gate wiring 712 and the gate wiring 713 so that the operation timings of the transistors 716 and 717 are different, whereby the alignment of the liquid crystal can be controlled.

Further, a storage capacitor may be formed using the capacitor wiring 710, a gate insulating film functioning as a dielectric, and a capacitor electrode electrically connected to the first pixel electrode layer or the second pixel electrode layer.

The multi-domain structure includes a first liquid crystal element 718 and a second liquid crystal element 719 in one pixel. The first liquid crystal element 718 includes a first pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween, and the second liquid crystal element 719 includes a second pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween. Consists of.

Note that the pixel circuit illustrated in FIG. 21B is not limited thereto. For example, a switch, a resistor, a capacitor, a transistor, a sensor, a logic circuit, or the like may be newly added to the pixel illustrated in FIG.

<Organic EL display device>
Another example of the circuit configuration of the pixel is shown in FIG. Here, a pixel structure of a display device using an organic EL element is shown.

In the organic EL element, by applying a voltage to the light-emitting element, electrons are injected from one of the pair of electrodes and holes from the other into the layer containing the light-emitting organic compound, and a current flows. Then, by recombination of electrons and holes, the light-emitting organic compound forms an excited state, and emits light when the excited state returns to the ground state. Due to such a mechanism, such a light-emitting element is referred to as a current-excitation light-emitting element.

FIG. 21C illustrates an example of an applicable pixel circuit. Here, an example in which two n-channel transistors are used for one pixel is shown. Note that the metal oxide film of one embodiment of the present invention can be used for a channel formation region of an n-channel transistor. In addition, digital time grayscale driving can be applied to the pixel circuit.

An applicable pixel circuit configuration and pixel operation when digital time gray scale driving is applied will be described.

The pixel 720 includes a switching transistor 721, a driving transistor 722, a light-emitting element 724, and a capacitor 723. In the switching transistor 721, the gate electrode layer is connected to the scanning line 726, the first electrode (one of the source electrode layer and the drain electrode layer) is connected to the signal line 725, and the second electrode (the source electrode layer and the drain electrode layer) Is connected to the gate electrode layer of the driving transistor 722. In the driving transistor 722, the gate electrode layer is connected to the power supply line 727 via the capacitor 723, the first electrode is connected to the power supply line 727, and the second electrode is connected to the first electrode (pixel electrode) of the light emitting element 724. It is connected. The second electrode of the light emitting element 724 corresponds to the common electrode 728. The common electrode 728 is electrically connected to a common potential line formed over the same substrate.

Transistors described in other embodiments can be used as appropriate as the switching transistor 721 and the driving transistor 722. Thereby, an organic EL display device with high reliability can be provided.

The potential of the second electrode (common electrode 728) of the light-emitting element 724 is set to a low power supply potential. Note that the low power supply potential is lower than the high power supply potential supplied to the power supply line 727. For example, GND, 0V, or the like can be set as the low power supply potential. A high power supply potential and a low power supply potential are set so as to be equal to or higher than the threshold voltage in the forward direction of the light emitting element 724, and by applying the potential difference to the light emitting element 724, a current is passed through the light emitting element 724 to emit light. Note that the forward voltage of the light-emitting element 724 refers to a voltage for obtaining desired luminance, and includes at least a forward threshold voltage.

Note that the capacitor 723 can be omitted by substituting the gate capacitance of the driving transistor 722. With respect to the gate capacitance of the driving transistor 722, a capacitance may be formed between the channel formation region and the gate electrode layer.

Next, a signal input to the driving transistor 722 will be described. In the case of the voltage input voltage driving method, a video signal that causes the driving transistor 722 to be sufficiently turned on or off is input to the driving transistor 722. Note that a voltage higher than the voltage of the power supply line 727 is applied to the gate electrode layer of the driving transistor 722 in order to operate the driving transistor 722 in a linear region. In addition, a voltage equal to or higher than a value obtained by adding the threshold voltage Vth of the driving transistor 722 to the power supply line voltage is applied to the signal line 725.

In the case of performing analog gradation driving, a voltage equal to or higher than the value obtained by adding the threshold voltage Vth of the driving transistor 722 to the forward voltage of the light emitting element 724 is applied to the gate electrode layer of the driving transistor 722. Note that a video signal is input so that the driving transistor 722 operates in a saturation region, and a current is supplied to the light-emitting element 724. Further, in order to operate the driving transistor 722 in the saturation region, the potential of the power supply line 727 is set higher than the gate potential of the driving transistor 722. By making the video signal analog, current corresponding to the video signal can be passed through the light-emitting element 724 to perform analog gradation driving.

Note that the structure of the pixel circuit is not limited to the pixel structure illustrated in FIG. For example, a switch, a resistor, a capacitor, a sensor, a transistor, a logic circuit, or the like may be added to the pixel circuit illustrated in FIG.

When the transistor illustrated in the above embodiment is applied to the circuit illustrated in FIG. 21, the source electrode (first electrode) is electrically connected to the low potential side, and the drain electrode (second electrode) is electrically connected to the high potential side. It is assumed that it is connected. Further, the potential of the first gate electrode is controlled by a control circuit or the like, and the potential exemplified above can be input to the second gate electrode, such as a potential lower than the potential applied to the source electrode by a wiring (not shown). do it.

For example, in this specification and the like, a display element, a display device that is a device including a display element, a light-emitting element, and a light-emitting device that is a device including a light-emitting element have various forms or have various elements. Can do. The display element, the display device, the light emitting element, or the light emitting device includes, for example, an EL element (an EL element including an organic substance and an inorganic substance, an organic EL element, an inorganic EL element), an LED (white LED, red LED, green LED, blue LED, etc. ), Transistor (transistor that emits light in response to current), electron-emitting device, liquid crystal device, electronic ink, electrophoretic device, grating light valve (GLV), plasma display (PDP), MEMS (micro electro mechanical system) , Display devices using digital micromirror devices (DMD), DMS (digital micro shutter), IMOD (interference modulation) devices, shutter-type MEMS display devices, optical interference-type MEMS display devices, electrowetting Tinging element, pressure Ceramic display, has at least one such display device using a carbon nanotube. In addition to these, a display medium in which contrast, luminance, reflectance, transmittance, or the like is changed by an electric or magnetic action may be included.

An example of a display device using an EL element is an EL display. As an example of a display device using an electron-emitting device, there is a field emission display (FED), a SED type flat display (SED: Surface-Conduction Electron-Emitter Display), or the like. As an example of a display device using a liquid crystal element, there is a liquid crystal display (a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, a direct view liquid crystal display, a projection liquid crystal display) and the like. An example of a display device using electronic ink, electronic powder fluid (registered trademark), or an electrophoretic element is electronic paper. Note that in the case of realizing a transflective liquid crystal display or a reflective liquid crystal display, part or all of the pixel electrode may have a function as a reflective electrode. For example, part or all of the pixel electrode may have aluminum, silver, or the like. Further, in that case, a memory circuit such as an SRAM can be provided under the reflective electrode. Thereby, power consumption can be further reduced.

In addition, when using LED, you may arrange | position graphene or graphite under the electrode and nitride semiconductor of LED. Graphene or graphite may be a multilayer film in which a plurality of layers are stacked. Thus, by providing graphene or graphite, a nitride semiconductor, for example, an n-type GaN semiconductor layer having a crystal can be easily formed thereon. Furthermore, a p-type GaN semiconductor layer having a crystal or the like can be provided thereon to form an LED. Note that an AlN layer may be provided between graphene or graphite and an n-type GaN semiconductor layer having a crystal. Note that the GaN semiconductor layer of the LED may be formed by MOCVD. However, by providing graphene, the GaN semiconductor layer included in the LED can be formed by a sputtering method.

Note that the structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 7)
In this embodiment, an example of a structure of the touch panel of one embodiment of the present invention will be described with reference to FIGS.

<Positional relationship between transistor and touch sensor wiring>
FIG. 22 is a top view showing the positional relationship between the wiring of the pixel, transistor, and touch sensor. The conductive layer 410 that is an electrode for the touch sensor can be disposed so as to overlap the signal line 91 and the scanning line 92, for example, or can be disposed in parallel without overlapping. Further, although an example in which the conductive layer 410 which is the wiring of the touch sensor is not overlapped with the transistor 50 and the capacitor element 61 is shown, they can be stacked. Further, although the conductive layer 410 is disposed without overlapping the pixel 24, the conductive layer 410 may be disposed so as to overlap. Further, the conductive layer 430 and the conductive layer 380 that can serve as electrodes of the touch sensor can have the same arrangement.

<Configuration example of sensor electrode>
Hereinafter, a more specific configuration example of the input device 90 having a function as a touch sensor will be described with reference to the drawings.

FIG. 23A shows a schematic top view of the input device 90. The input device 90 includes a plurality of electrodes 931, a plurality of electrodes 932, a plurality of wirings 941, and a plurality of wirings 942 on a substrate 930. The substrate 930 is provided with an FPC 950 that is electrically connected to each of the plurality of wirings 941 and the plurality of wirings 942. FIG. 23A illustrates an example in which an IC 951 is provided in the FPC 950.

FIG. 23B is an enlarged view of a region surrounded by an alternate long and short dash line in FIG. The electrode 931 has a shape in which a plurality of rhombus electrode patterns are arranged in the horizontal direction on the paper surface. The rhomboid electrode patterns arranged in a row are electrically connected to each other. Similarly, the electrode 932 has a shape in which a plurality of rhombus electrode patterns are arranged in the vertical direction on the paper surface, and the rhombus electrode patterns arranged in a row are electrically connected to each other. In addition, the electrode 931 and the electrode 932 partially overlap each other and intersect each other. At this intersection, an insulator is sandwiched so that the electrode 931 and the electrode 932 are not electrically short-circuited.

In addition, as illustrated in FIG. 23C, the electrode 932 may include a plurality of electrodes 933 having a rhombus shape and a bridge electrode 934. The island-shaped electrodes 933 are arranged side by side in the vertical direction on the paper surface, and two adjacent electrodes 933 are electrically connected by a bridge electrode 934. With such a structure, the electrode 933 and the electrode 931 can be formed at the same time by processing the same conductive film. Therefore, variations in the film thickness can be suppressed, and variations in resistance value and light transmittance of each electrode can be suppressed depending on the location. Note that although the electrode 932 includes the bridge electrode 934 here, the electrode 931 may have such a configuration.

Further, as shown in FIG. 23D, the inside of the rhomboid electrode pattern of the electrodes 931 and 932 shown in FIG. 23B may be hollowed out so that only the outline portion remains. At this time, in the case where the width of the electrode 931 and the electrode 932 is narrow enough to be invisible to the user, a light-shielding material such as a metal or an alloy may be used for the electrode 931 and the electrode 932 as described later. Alternatively, the electrode 931 or the electrode 932 illustrated in FIG. 23D may include the bridge electrode 934.

One electrode 931 is electrically connected to one wiring 941. One electrode 932 is electrically connected to one wiring 942. Here, one of the electrode 931 and the electrode 932 corresponds to the row wiring, and the other corresponds to the column wiring.

As an example, FIGS. 24A, 24B, 24C, and 24D are schematic views in which a part of the electrode 931 or the electrode 932 is enlarged. The electrode can have various shapes.

FIGS. 25A, 25B, and 25C illustrate an example in which an electrode 936 and an electrode 937 having a thin upper surface shape are used instead of the electrode 931 and the electrode 932. FIG. FIG. 25A shows an example in which linear electrodes 36 and electrodes 937 are arranged in a lattice pattern. In FIGS. 25B and 25C, the electrodes 936 and 937 are arranged in a zigzag shape.

26 (A), (B), and (C) are enlarged views of a region surrounded by a one-dot chain line in FIG. 25 (B), and FIG. 26 (B) is an enlarged view of a region surrounded by the one-dot chain line in FIG. D) (E) and (F) respectively. Each figure shows an electrode 936, an electrode 937, and an intersection 938 where these intersect. As shown in FIGS. 26B and 26E, the linear portions of the electrodes 936 and 937 in FIGS. 26A and 26D may be meandering so as to have corners, As shown in FIGS. 26 (C) and 26 (F), the shape may meander so that the curve is continuous.

<Configuration example of in-cell type touch panel>
Hereinafter, a configuration example of a touch panel in which a touch sensor is incorporated in a display unit having a plurality of pixels will be described. Here, an example in which a liquid crystal element is used as a display element provided in a pixel is shown.

FIG. 27A is an equivalent circuit diagram in part of a pixel circuit provided in the display portion of the touch panel exemplified in this configuration example.

One pixel includes at least a transistor 3503 and a liquid crystal element 3504. A wiring 3501 is electrically connected to the gate of the transistor 3503 and a wiring 3502 is electrically connected to one of the source and the drain.

The pixel circuit includes a plurality of wirings extending in the X direction (for example, a wiring 3510_1 and a wiring 3510_2) and a plurality of wirings extending in the Y direction (for example, the wiring 3511), which are provided so as to cross each other. And a capacitance is formed between them.

In addition, among some pixels provided in the pixel circuit, one electrode of a liquid crystal element provided in each of a plurality of adjacent pixels is electrically connected to form one block. The blocks are classified into two types: island-shaped blocks (for example, block 3515_1 and block 3515_2) and line-shaped blocks (for example, block 3516) extending in the Y direction. In FIG. 27A, only a part of the pixel circuit is shown, but actually these two types of blocks are repeatedly arranged in the X direction and the Y direction.

The wiring 3510_1 (or 3510_2) extending in the X direction is electrically connected to the island-shaped block 3515_1 (or block 3515_2). Note that although not illustrated, the wiring 3510_1 extending in the X direction electrically connects a plurality of island-shaped blocks 3515_1 arranged discontinuously along the X direction via line-shaped blocks. The wiring 3511 extending in the Y direction is electrically connected to the line-shaped block 3516.

FIG. 27B is an equivalent circuit diagram illustrating a connection configuration of a plurality of wirings 3510 extending in the X direction and a plurality of wirings 3511 extending in the Y direction. An input voltage or a common potential can be input to each of the wirings 3510 extending in the X direction. In addition, a ground potential can be input to each of the wirings 3511 extending in the Y direction, or the wiring 3511 and the detection circuit can be electrically connected.

Hereinafter, the operation of the touch panel described above will be described with reference to FIGS.

Here, one frame period is divided into a writing period and a detection period. The writing period is a period in which image data is written to the pixels, and wirings 3510 (also referred to as gate lines) are sequentially selected. On the other hand, the detection period is a period during which sensing by the touch sensor is performed, and the wiring 3510 extending in the X direction is sequentially selected and an input voltage is input.

FIG. 28A is an equivalent circuit diagram in the writing period. In the writing period, a common potential is input to both the wiring 3510 extending in the X direction and the wiring 3510 extending in the Y direction.

FIG. 28B is an equivalent circuit diagram at a certain point in the detection period. In the detection period, each of the wirings 3511 extending in the Y direction is electrically connected to the detection circuit. In addition, among the wirings 3510 extending in the X direction, an input voltage is input to selected ones, and a common potential is input to the other wirings.

Note that the driving method exemplified here can be applied not only to the in-cell method but also to the touch panel exemplified above, and can be used in combination with the method shown in the above driving method example.

As described above, it is preferable to provide the image writing period and the period for sensing by the touch sensor independently. Thereby, it is possible to suppress a decrease in sensitivity of the touch sensor due to noise at the time of pixel writing.

Note that the structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 8)
In this embodiment, the structure of the oxide semiconductor film is described.

<Film formation method>
An example of a CAAC-OS film formation method is described below.

FIG. 29A is a schematic view of a deposition chamber. The CAAC-OS can be formed by a sputtering method.

As shown in FIG. 29A, the substrate 5220 and the target 5230 are arranged to face each other. There is plasma 5240 between the substrate 5220 and the target 5230. A heating mechanism 5260 is provided below the substrate 5220. Although not shown, the target 5230 is bonded to the backing plate. A plurality of magnets are arranged at positions facing the target 5230 via the backing plate. A sputtering method that uses a magnetic field to increase the deposition rate is called a magnetron sputtering method.

A distance d (also referred to as a target-substrate distance (T-S distance)) between the substrate 5220 and the target 5230 is 0.01 m or more and 1 m or less, preferably 0.02 m or more and 0.5 m or less. The film formation chamber is mostly filled with a film forming gas (for example, oxygen, argon, or a mixed gas containing oxygen at a ratio of 5% by volume or more), and is 0.01 Pa to 100 Pa, preferably 0.1 Pa to 10 Pa. Controlled. Here, by applying a voltage of a certain level or higher to the target 5230, discharge starts and plasma 5240 is confirmed. Note that a high-density plasma region is formed in the vicinity of the target 5230 by a magnetic field. In the high-density plasma region, ions 5201 are generated by ionizing the deposition gas. The ion 5201 is, for example, an oxygen cation (O ⁺ ) or an argon cation (Ar ⁺ ).

The target 5230 has a polycrystalline structure having a plurality of crystal grains, and any one of the crystal grains includes a cleavage plane. As an example, FIG. 30 illustrates a crystal structure of InMZnO ₄ (the element M is, for example, aluminum, gallium, yttrium, or tin) included in the target 5230. Note that FIG. 30 shows a crystal structure of InMZnO ₄ when observed from a direction parallel to the b-axis. In the InMZnO ₄ crystal, a repulsive force is generated between two adjacent M—Zn—O layers because the oxygen atom has a negative charge. Therefore, the InMZnO ₄ crystal has a cleavage plane between two adjacent M—Zn—O layers.

The ions 5201 generated in the high-density plasma region are accelerated toward the target 5230 by the electric field and eventually collide with the target 5230. At this time, pellets 5200 which are flat or pellet-like sputtered particles are peeled from the cleavage plane (see FIG. 29A). The pellet 5200 is a portion sandwiched between two cleavage planes shown in FIG. Therefore, when only the pellet 5200 is extracted, the cross section becomes as shown in FIG. 29B and the upper surface becomes as shown in FIG. 29C. Note that the structure of the pellet 5200 may be distorted by the impact of the collision of the ions 5201. Note that the particles 5203 are also ejected from the target 5230 as the pellet 5200 is peeled off. A particle 5203 has an aggregate of one atom or several atoms. Therefore, the particles 5203 can also be referred to as atomic particles.

The pellet 5200 is a flat or pellet-like sputtered particle having a triangular plane, for example, a regular triangular plane. Alternatively, the pellet 5200 is a flat or pellet-like sputtered particle having a hexagonal plane, for example, a regular hexagonal plane. However, the shape of the pellet 5200 is not limited to a triangle or a hexagon. For example, there are cases where a plurality of triangles are combined. For example, there may be a quadrangle (for example, a rhombus) in which two triangles (for example, regular triangles) are combined.

The thickness of the pellet 5200 is determined according to the type of deposition gas. For example, the pellet 5200 has a thickness of 0.4 nm to 1 nm, preferably 0.6 nm to 0.8 nm. For example, the pellet 5200 has a width of 1 nm or more. For example, the ion 5201 is caused to collide with the target 5230 including an In-M-Zn oxide. Then, the pellet 5200 having three layers of an M—Zn—O layer, an In—O layer, and an M—Zn—O layer is peeled off. Note that the particles 5203 are also ejected from the target 5230 as the pellet 5200 is peeled off. A particle 5203 has an aggregate of one atom or several atoms. Therefore, the particles 5203 can also be referred to as atomic particles.

When the pellet 5200 passes through the plasma 5240, the surface may be negatively or positively charged. For example, the pellet 5200 may receive a negative charge from O ^{2− in the} plasma 5240. As a result, oxygen atoms on the surface of the pellet 5200 may be negatively charged. In addition, the pellet 5200 may grow by being combined with indium, the element M, zinc, oxygen, or the like in the plasma 5240 when passing through the plasma 5240.

The pellets 5200 and the particles 5203 that have passed through the plasma 5240 reach the surface of the substrate 5220. Note that part of the particles 5203 has a small mass and may be discharged to the outside by a vacuum pump or the like.

Next, deposition of pellets 5200 and particles 5203 on the surface of the substrate 5220 will be described with reference to FIG.

First, the first pellet 5200 is deposited on the substrate 5220. Since the pellet 5200 has a flat plate shape, the pellet 5200 is deposited with the planar side facing the surface of the substrate 5220 (see FIG. 31A). At this time, the charge on the surface of the pellet 5200 on the substrate 5220 side is released through the substrate 5220.

Next, the second pellet 5200 reaches the substrate 5220. At this time, since the surface of the first pellet 5200 and the surface of the second pellet 5200 are charged, forces that repel each other are generated (see FIG. 31B).

As a result, the second pellet 5200 is deposited on the surface of the substrate 5220 slightly away from the first pellet 5200 (see FIG. 31C). By repeating this, innumerable pellets 5200 are deposited on the surface of the substrate 5220 by a thickness corresponding to one layer. In addition, a region where the pellet 5200 is not deposited is generated between the pellet 5200 and another pellet 5200.

Next, the particle 5203 reaches the surface of the substrate 5220 (see FIG. 31D).

The particles 5203 cannot be deposited on an active region such as the surface of the pellet 5200. Therefore, the pellet 5200 is deposited so as to fill an undeposited region. Then, the particles 5203 grow in the horizontal direction between the pellets 5200 (also referred to as lateral growth), whereby the pellets 5200 are connected. In this manner, the particles 5203 are deposited until a region where the pellet 5200 is not deposited is filled. This mechanism is similar to the deposition mechanism of the atomic layer deposition (ALD) method.

Note that there are a plurality of possibilities for the lateral growth of the particles 5203 between the pellets 5200. For example, as shown in FIG. 31E, there is a mechanism of coupling from the side surface of the first M-Zn-O layer. In this case, after the first M-Zn-O layer is formed, the In-O layer and the second M-Zn-O layer are connected one by one in order (first mechanism).

Alternatively, for example, as illustrated in FIG. 32A, first, one of the particles 5203 is bonded to one side surface of the first M—Zn—O layer. Next, as illustrated in FIG. 32B, one particle 5203 is bonded to one side surface of the In—O layer. Next, as illustrated in FIG. 32C, one particle 5203 may be bonded and bonded to one side surface of the second M-Zn-O layer (second mechanism). 32A, 32B, and 32C may be connected at the same time (third mechanism).

As described above, the above three types are considered as the mechanism of the lateral growth of the particles 5203 between the pellets 5200. However, there is a possibility that the particles 5203 grow laterally between the pellets 5200 by other mechanisms.

Therefore, even when the plurality of pellets 5200 are oriented in different directions, the formation of crystal grain boundaries is suppressed by filling the spaces between the plurality of pellets 5200 while laterally growing the particles 5203. In addition, since the particles 5203 smoothly connect between the plurality of pellets 5200, different crystal structures are formed from single crystals and polycrystals. In other words, a crystal structure having strain is formed between minute crystal regions (pellets 5200). As described above, since the region between the crystal regions is a distorted crystal region, it is considered inappropriate to refer to the region as an amorphous structure.

When the particles 5203 finish filling the space between the pellets 5200, a first layer having the same thickness as the pellet 5200 is formed. A new first pellet 5200 is deposited on the first layer. A second layer is then formed. Further, by repeating this, a thin film structure having a stacked body is formed (see FIG. 29D).

Note that the manner in which the pellets 5200 are deposited also varies depending on the surface temperature of the substrate 5220 and the like. For example, when the surface temperature of the substrate 5220 is high, the pellet 5200 undergoes migration on the surface of the substrate 5220. As a result, the proportion of the pellet 5200 and another pellet 5200 that are connected without the particle 5203 interposed therebetween increases, so that a CAAC-OS with high orientation is obtained. The surface temperature of the substrate 5220 in forming the CAAC-OS is 100 ° C. or higher and lower than 500 ° C., preferably 140 ° C. or higher and lower than 450 ° C., more preferably 170 ° C. or higher and lower than 400 ° C. Accordingly, it can be seen that even when a large-area substrate of the eighth generation or higher is used as the substrate 5220, warping or the like hardly occurs.

On the other hand, when the surface temperature of the substrate 5220 is low, the pellet 5200 is less likely to cause migration on the surface of the substrate 5220. As a result, the pellets 5200 are stacked to form an nc-OS (nanocrystalline Oxide Semiconductor) having low orientation (see FIG. 33). In the nc-OS, since the pellet 5200 is negatively charged, the pellet 5200 may be deposited at regular intervals. Therefore, although the orientation is low, a slight regularity results in a dense structure as compared with an amorphous oxide semiconductor.

In CAAC-OS, one large pellet may be formed when the gap between pellets is extremely small. The inside of one large pellet has a single crystal structure. For example, the size of the pellet may be 10 nm to 200 nm, 15 nm to 100 nm, or 20 nm to 50 nm when viewed from above.

It is considered that the pellet 5200 is deposited on the surface of the substrate 5220 by the above model. Even when the formation surface does not have a crystal structure, a CAAC-OS film can be formed, which indicates that the growth mechanism is different from that of epitaxial growth. The CAAC-OS and the nc-OS can form a film evenly even when the glass substrate has a large area. For example, the CAAC-OS can be formed even when the surface of the substrate 5220 (formation surface) has an amorphous structure (eg, amorphous silicon oxide).

Further, it can be seen that even when the surface of the substrate 5220 which is the formation surface is uneven, the pellets 5200 are arranged along the shape.

Note that the structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 9)

<Module>
A display module to which the semiconductor device of one embodiment of the present invention is applied is described below with reference to FIGS.

A display module 8000 shown in FIG. 34 includes a touch sensor 8004 connected to the FPC 8003, a display device 8006 connected to the FPC 8005, a backlight unit 8007, a frame 8009, and a printed circuit board 8010 between the upper cover 8001 and the lower cover 8002. And a battery 8011. Note that the backlight unit 8007, the battery 8011, the touch sensor 8004, and the like may not be provided.

The semiconductor device of one embodiment of the present invention can be used for the display device 8006, for example.

The shapes and dimensions of the upper cover 8001 and the lower cover 8002 can be changed as appropriate in accordance with the sizes of the touch sensor 8004 and the display device 8006.

The touch sensor 8004 can be formed using a resistive touch panel or a capacitive touch panel superimposed on the display device 8006. In addition, the counter substrate (sealing substrate) of the display device 8006 can have a touch panel function. Alternatively, an optical sensor can be provided in each pixel of the display device 8006 to provide an optical touch panel. Alternatively, a touch sensor electrode may be provided in each pixel of the display device 8006 to form a capacitive touch panel.

The backlight unit 8007 has a light source 8008. The light source 8008 may be provided at the end of the backlight unit 8007 and a light diffusing plate may be used.

The frame 8009 may have a function as an electromagnetic shield for blocking electromagnetic waves generated by the operation of the printed circuit board 8010 in addition to the protective function of the display device 8006. The frame 8009 may have a function as a heat sink.

The printed circuit board 8010 includes a power supply circuit, a signal processing circuit for outputting a video signal and a clock signal. The power source for supplying power to the power supply circuit may be an external commercial power source or a power source using a battery 8011 provided separately. When a commercial power source is used, the battery 8011 is not necessarily provided.

Further, the display module 8000 may be additionally provided with a member such as a polarizing plate, a retardation plate, and a prism sheet.

Note that the structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 10)

<Electronic equipment>
In this embodiment, examples of electronic devices to which the display device which is one embodiment of the present invention can be applied will be described with reference to FIGS.

As an electronic device to which the display device is applied, for example, a television device (also referred to as a television or a television receiver), a monitor for a computer, a digital camera, a digital video camera, a digital photo frame, a mobile phone (a mobile phone, a mobile phone) Also referred to as a telephone device), portable game machines, portable information terminals, sound reproduction devices, large game machines such as pachinko machines, and the like. Specific examples of these electronic devices are shown in FIGS.

FIG. 35A illustrates a portable game machine including a housing 7101, a housing 7102, a display portion 7103, a display portion 7104, a microphone 7105, speakers 7106, operation keys 7107, a stylus 7108, and the like. The display device according to one embodiment of the present invention can be used for the display portion 7103 or the display portion 7104. With the use of the light-emitting device according to one embodiment of the present invention for the display portion 7103 or the display portion 7104, a portable game machine that has an excellent usability and is unlikely to deteriorate in quality can be provided. Note that although the portable game machine illustrated in FIG. 35A includes two display portions 7103 and 7104, the number of display portions included in the portable game device is not limited thereto.

FIG. 35B illustrates a smart watch, which includes a housing 7302, a display portion 7304, operation buttons 7311 and 7312, a connection terminal 7313, a band 7321, a clasp 7322, and the like. A display device, an information input device, or a touch panel according to one embodiment of the present invention can be used for the display portion 7304.

FIG. 35C illustrates a portable information terminal which includes an operation button 7503, an external connection port 7504, a speaker 7505, a microphone 7506, a display portion 7502, and the like in addition to a display portion 7502 incorporated in a housing 7501. The display device according to one embodiment of the present invention can be used for the display portion 7502. Note that since the display portion 7502 can have extremely high definition, the display portion 7502 can display 8k while being small and medium-sized, and a very clear image can be obtained.

FIG. 35D illustrates a video camera, which includes a first housing 7701, a second housing 7702, a display portion 7703, operation keys 7704, a lens 7705, a connection portion 7706, and the like. The operation key 7704 and the lens 7705 are provided in the first housing 7701, and the display portion 7703 is provided in the second housing 7702. The first housing 7701 and the second housing 7702 are connected by a connection portion 7706, and the angle between the first housing 7701 and the second housing 7702 can be changed by the connection portion 7706. is there. The video on the display portion 7703 may be switched in accordance with the angle between the first housing 7701 and the second housing 7702 in the connection portion 7706. The imaging device of one embodiment of the present invention can be provided at a position where the lens 7705 is focused. The display device according to one embodiment of the present invention can be used for the display portion 7703.

FIG. 35E illustrates a curved display, which includes a display portion 7802 incorporated in a housing 7801, operation buttons 7803, a speaker 7804, and the like. The display device according to one embodiment of the present invention can be used for the display portion 7802.

FIG. 35F illustrates digital signage, which includes a display portion 7902 installed on a utility pole 7901. The display device according to one embodiment of the present invention can be used for the display portion 7902.

FIG. 36A illustrates a laptop personal computer, which includes a housing 8121, a display portion 8122, a keyboard 8123, a pointing device 8124, and the like. The display device according to one embodiment of the present invention can be applied to the display portion 8122. Note that since the display portion 8122 can have very high definition, the display portion 8122 can display 8k while being small and medium-sized, and a very clear image can be obtained.

FIG. 36B illustrates the appearance of an automobile 9700. FIG. 36C illustrates a driver seat of the automobile 9700. The automobile 9700 includes a vehicle body 9701, wheels 9702, a dashboard 9703, lights 9704, and the like. The display device or the input / output device of one embodiment of the present invention can be used for a display portion of an automobile 9700 or the like. For example, the display device 9710 to the display portion 9715 illustrated in FIG. 36C can be provided with the display device, the input / output device, or the touch panel of one embodiment of the present invention.

The display portion 9710 and the display portion 9711 are display devices or input / output devices provided on a windshield of an automobile. The display device or the input / output device of one embodiment of the present invention is a so-called see-through state in which an electrode of the display device or the input / output device is made of a light-transmitting conductive material so that the opposite side can be seen through. Display devices or input / output devices. If the display device or the input / output device is in a see-through state, the view is not hindered even when the automobile 9700 is driven. Thus, the display device or the input / output device of one embodiment of the present invention can be provided on the windshield of the automobile 9700. Note that in the case where a transistor for driving the display device or the input / output device is provided in the display device or the input / output device, an organic transistor using an organic semiconductor material, a transistor using an oxide semiconductor, or the like, A transistor having a light-transmitting property may be used.

A display portion 9712 is a display device provided in the pillar portion. For example, the field of view blocked by the pillar can be complemented by displaying an image from the imaging means provided on the vehicle body on the display portion 9712. A display portion 9713 is a display device provided in the dashboard portion. For example, by displaying an image from an imaging unit provided on the vehicle body on the display portion 9713, the view blocked by the dashboard can be complemented. That is, by projecting an image from the imaging means provided outside the automobile, the blind spot can be compensated and safety can be improved. Also, by displaying a video that complements the invisible part, it is possible to confirm the safety more naturally and without a sense of incongruity.

FIG. 36D shows the interior of an automobile in which bench seats are used for the driver seat and the passenger seat. The display portion 9721 is a display device or an input / output device provided in the door portion. For example, the field of view blocked by the door can be complemented by displaying an image from an imaging unit provided on the vehicle body on the display portion 9721. The display portion 9722 is a display device provided on the handle. The display unit 9723 is a display device provided at the center of the seat surface of the bench seat. Note that the display device can be installed on a seating surface or a backrest portion, and the display device can be used as a seat heater using heat generated by the display device as a heat source.

The display portion 9714, the display portion 9715, or the display portion 9722 can provide various other information such as navigation information, a speedometer and a tachometer, a travel distance, an oil supply amount, a gear state, and an air conditioner setting. In addition, display items, layouts, and the like displayed on the display unit can be changed as appropriate according to the user's preference. Note that the above information can also be displayed on the display portion 9710 to the display portion 9713, the display portion 9721, and the display portion 9723. The display portions 9710 to 9715 and the display portions 9721 to 9723 can also be used as lighting devices. The display portions 9710 to 9715 and the display portions 9721 to 9723 can also be used as heating devices.

The display portion to which the display device of one embodiment of the present invention is applied may be a flat surface. In this case, the display device of one embodiment of the present invention may have a curved surface or a structure that does not have flexibility.

Note that the structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

DESCRIPTION OF SYMBOLS 10 Display apparatus 17 Oxide semiconductor film 18 Light shielding layer 20 Display panel 21 Display area 22 Peripheral circuit 24 Pixel 36 Electrode 42 FPC
50 transistor 51 transistor 52 transistor 53 transistor 54 transistor 55 transistor 57 transistor 58 transistor 59 transistor 60 capacitor element 61 capacitor element 64 capacitor element 65 capacitor element 70 light emitting element 80 liquid crystal element 81 liquid crystal element 90 input device 91 signal line 92 scanning line 100 substrate DESCRIPTION OF SYMBOLS 101 Substrate 103 Polarizing plate 104 Backlight 110 Insulating layer 112 Insulating layer 120 Conductive layer 120a Conductive film 123 Oxide semiconductor layer 130 Insulating layer 131 Insulating layer 140 Oxide semiconductor layer 140a Oxide semiconductor film 141 Oxide semiconductor layer 141a Oxide semiconductor Film 142 oxide semiconductor layer 142a oxide semiconductor film 143 oxide semiconductor layer 145 oxide semiconductor layer 150 conductive layer 150a conductive film 160 conductive layer 165 insulating layer 170 insulating layer 175 Intermediate film 177 Oxygen 180 Insulating layer 190 Conductive layer 190a Conductive film 191 Opening 195 Insulating layer 200 Conductive layer 210 Insulating layer 220 Conductive layer 230 Layer 240 Spacer 245 Partition 250 EL layer 260 Conductive layer 300 Substrate 301 Substrate 302 Protective substrate 303 Polarizing plate 312 Insulating layer 330 Insulating layer 360 Colored layer 370 Adhesive layer 371 Adhesive layer 372 Adhesive layer 373 Adhesive layer 375 Adhesive layer 376 Adhesive layer 380 Conductive layer 390 Liquid crystal layer 400 Oxide conductive layer 410 Conductive layer 420 Insulating layer 430 Conductive layer 440 Insulating layer 510 Anisotropic conductive film 520 Conductive layer 550 Transistor 554 Transistor 555 Transistor 560 Capacitor element 564 Capacitor element 565 Capacitor element 601 Precursor 602 Precursor 700 Substrate 701 Pixel portion 702 Scan line driver circuit 703 Inspection line driving circuit 704 Signal line driving circuit 710 Capacitor wiring 711a Raw material supply part 711b Raw material supply part 712 Gate wiring 713 Gate wiring 714 Data line 716 Transistor 717 Transistor 718 Liquid crystal element 719 Liquid crystal element 720 Pixel 721 Switching transistor 722 Driving transistor 723 Capacitance element 724 Light emitting element 725 Signal line 726 Scan line 727 Power line 728 Common electrode 800 Substrate 810 Inlet 830 Plasma generation source 850 Plasma ALD apparatus 851 Plasma source 853 Chamber 855 Precursor supply section 857 Precursor supply section 859 Precursor introduction valve 861 Precursor Introduction valve 863 Gate valve 865 Heater 867 Deposition substrate 869 Pump 930 Substrate 931 Electrode 932 Electrode 933 Electrode 934 Bridge electrode 936 Electrode 937 Electrode 938 Intersection 941 Wiring 942 Wiring 950 FPC
951 IC
1700 Substrate 1701 Chamber 1702 Load chamber 1703 Pretreatment chamber 1704 Chamber 1705 Chamber 1706 Unload chamber 1711a Raw material supply portion 1711b Raw material supply portion 1712a High speed valve 1712b High speed valve 1712c High speed valve 1712d High speed valve 1713a Raw material introduction port 1713b Raw material introduction port 1714 Raw material discharge Exit 1715 Exhaust device 1716 Substrate holder 1720 Transport chamber 3501 Wiring 3502 Wiring 3503 Transistor 3504 Liquid crystal element 3510 Wiring 3510_1 Wiring 3510_2 Wiring 3511 Wiring 3515_1 Block 3515_2 Block 3516 Block 5200 Pellet 5201 Ion 5203 Particle 5220 Substrate 5230 Target 5240 Plasma housing 260 Heating mechanism 7101 Body 7102 Body 7103 Display portion 7104 Display portion 7105 Microphone 7106 Speaker 7107 Operation key 7108 Stylus 7302 Case 7304 Display portion 7311 Operation button 7312 Operation button 7313 Connection terminal 7321 Band 7322 Gold 7501 Case 7502 Display portion 7503 Operation button 7504 External connection port 7505 Speaker 7506 Microphone 7701 Housing 7702 Housing 7703 Display unit 7704 Operation key 7705 Lens 7706 Connection unit 7801 Housing 7802 Display unit 7803 Operation button 7804 Speaker 7901 Telephone pole 7902 Display unit 8000 Display module 8001 Upper cover 8002 Lower cover 8003 FPC
8004 Touch sensor 8005 FPC
8006 Display device 8007 Backlight unit 8008 Light source 8009 Frame 8010 Printed circuit board 8011 Battery 8121 Case 8122 Display unit 8123 Keyboard 8124 Pointing device 9700 Car 9701 Car body 9702 Wheel 9703 Dashboard 9704 Light 9710 Display unit 9711 Display unit 9712 Display unit 9713 Display unit 9714 Display unit 9715 Display unit 9721 Display unit 9722 Display unit 9723 Display unit

Claims (13)

A semiconductor device having a transistor and a capacitor,
The transistor is
A first insulating layer;
A first conductive layer provided on the first insulating layer;
A second insulating layer provided on the first insulating layer and the first conductive layer;
A third insulating layer provided on the second insulating layer;
An oxide semiconductor layer provided on the third insulating layer;
A second conductive layer and a third conductive layer provided on the third insulating layer and the oxide semiconductor layer;
A fourth insulating layer provided on the third insulating layer, the second conductive layer, the oxide semiconductor layer, and the third conductive layer;
A second insulating layer and a fifth insulating layer provided on the fourth insulating layer,
The capacitive element is
An oxide conductive layer;
The fifth insulating layer;
A fourth conductive layer provided on the fifth insulating layer,
The oxide conductive layer includes the same metal element as the oxide semiconductor layer,
The oxide conductive layer has a higher hydrogen concentration than the oxide semiconductor layer,
The fifth insulating layer is provided so as to cover end portions of the third insulating layer and the fourth insulating layer,
The second insulating layer and the fifth insulating layer are in contact with each other;
The semiconductor device according to claim 5, wherein the fifth insulating layer has high coverage. A semiconductor device having a transistor and a capacitor,
The transistor includes a first insulating layer;
A first conductive layer provided on the first insulating layer;
The first insulating layer, the second insulating layer provided on the first conductive layer, and the third insulating layer;
An oxide semiconductor layer provided on the third insulating layer;
The third insulating layer, a second conductive layer provided on the oxide semiconductor layer, and a third conductive layer;
A fourth insulating layer provided on the third insulating layer, the second conductive layer, the oxide semiconductor layer, and the third conductive layer;
A fifth insulating layer provided on the fourth insulating layer;
A second insulating layer, a sixth insulating layer provided on the fifth insulating layer, and
The capacitive element includes an oxide conductive layer,
The fourth insulating layer;
A fourth conductive layer provided on the fourth insulating layer,
The oxide conductive layer includes the same metal element as the oxide semiconductor layer,
The oxide conductive layer has a higher hydrogen concentration than the oxide semiconductor layer,
The fifth insulating layer is provided so as to cover end portions of the third insulating layer and the fourth insulating layer,
The sixth insulating layer is provided so as to cover an end of the fifth insulating layer,
The second insulating layer is in contact with the fifth insulating layer and the sixth insulating layer;
The semiconductor device according to claim 6, wherein the sixth insulating layer has high coverage. 3. The semiconductor device according to claim 1, wherein the fifth insulating layer has a barrier property against water, hydrogen, and oxygen. 4. The semiconductor device according to claim 1, wherein the fifth insulating layer is a silicon nitride film. 5. 5. The semiconductor device according to claim 2, wherein the sixth insulating layer is an aluminum oxide film. Forming a first insulating layer;
Forming a first conductive film on the first insulating layer;
A first conductive layer is formed by selectively etching the first conductive film using a first resist mask;
Forming a second insulating layer and a third insulating layer in this order on the first conductive layer;
Forming an oxide semiconductor film on the third insulating layer;
Forming the first oxide semiconductor layer and the second oxide semiconductor layer by selectively etching the oxide semiconductor film using a second resist mask;
Forming a second conductive film on the third insulating layer, the first oxide semiconductor layer, and the second oxide semiconductor layer;
Forming a second conductive layer and a third conductive layer in contact with the first oxide semiconductor layer by selectively etching using a third resist mask;
Forming a fourth insulating film on the third insulating layer, the first oxide semiconductor layer, the second oxide semiconductor layer, the second conductive layer, and the third conductive layer;
Forming an intermediate film on the fourth insulating film;
Oxygen is added to the first oxide semiconductor layer and the second oxide semiconductor layer through the intermediate film,
Removing the intermediate film by etching;
By selectively etching using a fourth resist mask, a fourth insulating layer having an opening from which the second oxide semiconductor layer is exposed is formed.
Forming a fifth insulating layer on the second insulating layer, the fourth insulating layer, and the second oxide semiconductor layer;
An impurity conductive layer is formed by diffusing impurities from the fifth insulating layer to the second oxide semiconductor layer;
Forming a third conductive film on the fifth insulating layer;
A method for manufacturing a semiconductor device, wherein a fourth conductive layer is formed in a region overlapping with the oxide conductive layer by selective etching using a fifth resist mask. Forming a first insulating layer;
Forming a first conductive film on the first insulating layer;
A first conductive layer is formed by selectively etching the first conductive film using a first resist mask;
Forming a second insulating layer and a third insulating layer in this order on the first conductive layer;
Forming an oxide semiconductor film on the third insulating layer;
Forming the first oxide semiconductor layer and the second oxide semiconductor layer by selectively etching the oxide semiconductor film using a second resist mask;
Forming a second conductive film on the third insulating layer, the first oxide semiconductor layer, and the second oxide semiconductor layer;
Forming a second conductive layer and a third conductive layer in contact with the first oxide semiconductor layer by selectively etching using a third resist mask;
Forming a fourth insulating film on the third insulating layer, the first oxide semiconductor layer, the second oxide semiconductor layer, the second conductive layer, and the third conductive layer;
Forming an intermediate film on the fourth insulating film;
Oxygen is added to the first oxide semiconductor layer and the second oxide semiconductor layer through the intermediate film,
Removing the intermediate film by etching;
By selectively etching using a fourth resist mask, a fourth insulating layer having an opening from which the second oxide semiconductor layer is exposed is formed.
Forming a fifth insulating layer on the second insulating layer, the fourth insulating layer, and the second oxide semiconductor layer;
An impurity conductive layer is formed by diffusing impurities from the fifth insulating layer to the second oxide semiconductor layer;
Forming a third conductive film on the fifth insulating layer;
By selectively etching using a fifth resist mask, a fourth conductive layer is formed in a region overlapping with the first oxide semiconductor layer and the oxide conductive layer,
A method for manufacturing a semiconductor device, comprising: forming a sixth insulating layer on the fifth insulating layer and the fourth conductive layer. 8. The method for manufacturing a semiconductor device according to claim 6, wherein the fifth insulating film is formed by an ALD method. 9. The method for manufacturing a semiconductor device according to claim 6, wherein the fifth insulating film is formed by a plasma ALD method. 10. The method for manufacturing a semiconductor device according to claim 6, wherein a silicon nitride film is formed as the fifth insulating film. 11. The method for manufacturing a semiconductor device according to claim 7, wherein an aluminum oxide film is formed as the sixth insulating film. 12. The method for manufacturing a semiconductor device according to claim 7, wherein the fifth insulating film is formed by a plasma CVD method, and the sixth insulating layer is formed by a plasma ALD method. An electronic apparatus comprising: the semiconductor device according to claim 1; a microphone; a speaker; and a housing.