JP2016119536A - Spread spectrum clock generator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a spread spectrum clock generator (SSCG) capable of continuously performing a down-spread operation.SOLUTION: The SSCG calculates a cumulative delay maximum value in a delay line based on the number of cycles of an output clock and a modulation step width, and calculates the number of input clocks to be thinned based on a period of the input clock and the cumulative delay maximum value in the delay line. A thinning timing signal is generated based on the number of cycles of the output clock and the number of input clocks to be thinned, and the input clocks during a period in which the thinning timing signal is asserted are thinned and outputted as a thinned output clock. A delay step number selection signal is generated based on a modulation pattern for generating an output clock of a down-spread output frequency, the thinned output clock is delayed by a delay cell with the number of steps corresponding to the delay step number selection signal and outputted as an output clock.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a spread spectrum clock generator (hereinafter also referred to as SSCG (Spread Spectrum Clock Generator)) that modulates the frequency of an output clock by changing the delay value of an input clock every cycle.

  FIG. 15 is a block diagram showing an example of the configuration of a conventional SSCG. The SSCG 70 shown in the figure is a digital SSCG described in Patent Documents 1 and 2, and includes a delay line 72 and a delay line control unit 74.

  In SSCG 70, every cycle of input clock CLKIN in accordance with a modulation pattern for generating output clock CLKOUT having an output frequency of center spread, which is set in advance by delay line control unit 74 in accordance with the modulation period and degree of modulation of output clock CLKOUT. In addition, a delay stage number selection signal S [n: 0] for sequentially changing the delay value of the input clock CLKIN is generated.

  As shown in FIG. 16, the delay line 72 includes a plurality of delay cells 76 [n: 0] connected in series, and for each cycle of the input clock CLKIN, a delay stage number selection signal S [n: 0]. ], The input clock CLKIN is delayed by the number of delay cells 76 [n: 0] corresponding to the number of stages, and output as the output clock CLKOUT. In this way, by changing the delay value of the input clock CLKIN, the frequency (that is, the period) of the output clock CLKOUT is modulated with a constant modulation period.

  The SSCG 70 has an effect that electromagnetic interference (EMI (Electro-Magnetic Interference)) can be reduced by periodically modulating the frequency of the output clock CLKOUT for each cycle of the input clock CLKIN.

  The modulation profile of the SSCG 70, that is, how the period of the output clock CLKOUT is modulated is determined by the modulation period and the degree of modulation. The modulation period represents the period of the modulation pattern, and is defined by the number of cycles M of the output clock CLKOUT included in one modulation period in the SSCG 70. The modulation degree represents the ratio of the change in the cycle of the output clock CLKOUT to the cycle of the input clock CLKIN, and is defined by the modulation step width ΔT per cycle in the SSCG 70.

  When the delay value in the first cycle is 0, the cycle of the output clock CLKOUT in that cycle is the cycle Tin of the input clock CLKIN. When the delay value of the second cycle is ΔT, the cycle of the output clock CLKOUT is Tin + ΔT, and when the delay value of the third cycle is 2ΔT, the cycle of the output clock CLKOUT is Tin + 2 · ΔT. That is, in the SSCG 70, for each cycle, the difference between the delay value of the output clock CLKOUT of the previous cycle and the delay value of the output clock CLKOUT of that cycle becomes the change in the cycle of the output clock CLKOUT.

Here, assuming that the cycle Tin [ns] of the input clock CLKIN, the modulation cycle Tmod [ns] of the output clock CLKOUT, and the modulation factor R [%], in the SSCG 70, the cycle number M and the modulation step width ΔT of the output clock CLKOUT are: Calculated by equation (1).
M = Tmod / Tin
ΔT = (Tin * R) / (M / 4) (1)

In this case, a center spread modulation profile is realized in which the period Tout [ns] of the output clock CLKOUT varies within the range calculated by the equation (2) according to the modulation pattern.
Tout = Tin−ΔT * (M / 4) to Tin + ΔT * (M / 4) (2)

For example, when the cycle Tin = 10 ns of the input clock CLKIN, the modulation cycle Tmod = 440 ns of the output clock CLKOUT, and the modulation factor R = ± 11%, the number of cycles M of the output clock CLKOUT and the modulation step width ΔT are expressed by the equation (3). Street.
Number of cycles of output clock CLKOUT M = 440/10 = 44
Modulation step width ΔT = (10 * 0.11) / (44/4) = 0.1 ns Equation (3)

  17A, 17B, and 17C are graphs showing examples of changes in the output frequency, the output cycle, and the accumulated delay value of the output clock CLKOUT of the conventional SSCG shown in FIG. . These graphs represent the output frequency, output period, and accumulated delay value of the output clock CLKOUT in the case of the above numerical example, and the respective vertical axes represent the output frequency [MHz], the output period [ns], and the accumulated delay. The value [ΔT] is represented, and the horizontal axis represents time [t].

In the case of the above numerical example, the output frequency of the output clock CLKOUT is 1 in the range of about 90.1 MHz to about 112.4 MHz, centering on the frequency of the input clock CLKIN = 100 MHz, as shown in the graph of FIG. Change (increase / decrease) every cycle.
That is, during the downspread period, the frequency gradually decreases from 100 MHz, reaches a minimum value of about 90.1 MHz at a quarter of one modulation period, and increases sequentially from the minimum value to ½ of one modulation period. Return to 100 MHz at the timing. Subsequently, during the upspread period, the frequency gradually increases from 100 MHz, reaches a maximum value of about 112.4 MHz at 3/4 timing of one modulation cycle, and decreases sequentially from the maximum value to 100 MHz at the timing of 1 modulation cycle. Return to.

On the other hand, the output cycle of the output clock CLKOUT changes (increases / decreases) every cycle in the range of 8.9 ns to 11.1 ns with the cycle of the input clock CLKIN = 10 ns as shown in the graph of FIG. )
That is, in the period of the down spread, it gradually increases from 10 ns, reaches a maximum value of 11.1 ns at a quarter timing of one modulation period, and decreases sequentially from the maximum value to a timing of ½ of one modulation period. Return to 10ns. Subsequently, during the up-spread period, it gradually decreases from 10 ns, reaches a minimum value of 8.9 ns at the timing of 3/4 of one modulation period, and increases gradually from the minimum value to 10 ns at the timing of one modulation period. Return.

The accumulated delay value of the output clock CLKOUT changes (increases / decreases) every cycle in the range of 0 * ΔT to 121 * ΔT, as shown in FIG.
In other words, it gradually increases from 0 * ΔT during the downspread period, reaches a maximum value of 121 * ΔT at half the timing of one modulation period, and sequentially decreases from the maximum value during the upspread period to 1 Return to 0 * ΔT at the timing of the modulation period.

  Subsequently, Table 1 shows the time [ns], the cycle number [#] of the input clock CLKIN, the stage number difference [ΔT], the accumulated delay stage number [ΔT], and the delay stage number selection signal S [ n: 0].

The stage number difference is the number of stages of the delay cell 76 used to delay the input clock CLKIN in the previous cycle and the number of stages of the delay cell 76 used to delay the input clock CLKIN in the current cycle. Represents the difference.
The cumulative delay stage number represents the stage number of the delay cell 76 used for delaying the input clock CLKIN in each cycle of the output clock CLKOUT included in one modulation period of the output clock CLKOUT.

  From the difference in the number of stages, it can be seen that the SSCG 70 realizes a center spread modulation profile. Further, when looking at the accumulated delay stage number, in the SSCG 70, in one modulation period of the output clock CLKOUT, the accumulated delay stage number increases from the minimum value 0 to the maximum value 121, and then decreases from the maximum value 121 to the minimum value. It can be seen that the value returns to zero. That is, since the input clock CLKIN is not delayed at the end of one modulation period, the center spread operation can be performed continuously.

The center spread modulation profile requires a circuit that operates with the output clock CLKOUT of the SSCG 70 to operate at a higher clock frequency than when the SSCG 70 is not used, which makes circuit design difficult and increases the circuit scale.
In addition, the existing LSI that is used together with the LSI that is currently under development with the SSCG 70 installed is required to operate at a higher clock frequency than when the SSCG 70 is not used, so the upper limit of the operating frequency is exceeded and the existing LSI is used. The problem of being unable to occur may occur.

In this case, it is conceivable that the down spread modulation profile realized by the analog SSCG is realized by the digital SSCG 70.
However, in the conventional digital SSCG 70, as shown in FIG. 5C, the cumulative delay value increased to the maximum value by the down spread operation is reduced to the minimum value by the up spread operation, and then the next modulation cycle is started. Need to migrate. Therefore, there is a problem that it is difficult to continuously perform only the downspread operation.

JP 2008-227613 A JP 2011-146663 A

  An object of the present invention is to provide a spread spectrum clock generator capable of solving the problems of the prior art and continuously performing a down spread operation.

In order to achieve the above object, the present invention is a spread spectrum clock generator that modulates the frequency of an output clock at a constant modulation period by changing the delay value of the input clock every cycle of the input clock. And
A delay line that has a plurality of delay cells connected in series, delays the thinned output clock by the number of delay cells corresponding to the delay stage number selection signal that changes the delay value of the input clock, and outputs the delayed output clock as the output clock When,
The delay stage number selection signal is generated for each cycle of the input clock based on a modulation pattern that generates an output clock having a down spread output frequency that is preset according to the modulation period and modulation degree of the output clock. A delay stage number setting circuit that calculates a cumulative delay maximum value Dmax in the delay line based on the output clock cycle number M and a modulation step width ΔT calculated based on the modulation pattern And a delay line control unit having a decimation timing signal generation circuit that generates a decimation timing signal representing a period of decimation of the input clock based on the number M of cycles of the output clock and the decimation number U of the input clock;
An input clock period calculation unit for calculating the period of the input clock;
A clock decimation number calculation unit for calculating the decimation number U of the input clock based on the cycle of the input clock and the accumulated delay maximum value Dmax in the delay line;
A clock decimation unit that decimates the input clock during a period in which the decimation timing signal is asserted, and outputs the decimation output clock.
The delay cell is configured by connecting a plurality of basic delay cells in series, a delay value by the basic delay cell in one stage is D0, and a delay value by the delay cell in one stage is connected in series. The present invention provides a spread spectrum clock generator characterized in that the time is equal to a value obtained by multiplying the number of basic delay cells by the delay value D0 of the one-stage basic delay cell.

Here, the delay stage number setting circuit includes:
A control counter that outputs a count value obtained by counting up the number of cycles of the input clock;
A stage number difference calculation circuit for calculating the stage number difference of each cycle of the output clock included in one modulation period corresponding to the count value of the control counter based on the modulation pattern for each cycle of the input clock. When,
An accumulated delay stage number calculating circuit for accumulating and adding the stage number differences of all the cycles of the output clock included in one modulation period for each cycle of the input clock, and calculating the accumulated delay stage number in each cycle;
It is preferable to include a decoder that decodes the accumulated delay stage number in each cycle and generates the delay stage number selection signal corresponding to the accumulated delay stage number.

  In addition, the input clock cycle calculation unit rounds out a period corresponding to an integral multiple of the delay value D0 of the basic delay cell in the period of one cycle of the input clock, and discards the remaining period as an invalid period. It is preferable that a first multiple P representing how many times a period of one cycle of the input clock corresponds to the delay value D0 of the basic delay cell is calculated.

  The cumulative delay maximum value calculation circuit preferably calculates the cumulative delay maximum value Dmax by Dmax = (M / 2) * (M / 2) * ΔT.

  In addition, when the modulation step width ΔT corresponds to the delay value C * D0 by the C-stage basic delay cells connected in series, the maximum accumulated delay value Dmax is calculated as follows. It is preferable to calculate the second multiple Q representing how many times the delay value D0 of the basic delay cell corresponds to Q = (M / 2) * (M / 2) * C.

  Further, it is preferable that the clock thinning number calculation unit calculates the thinning number U by rounding up a value after the decimal point of U = Q / P.

The decimation timing signal generation circuit asserts the decimation timing signal after the input clock of the cycle in which the count value of the control counter is counted up from 0 to (M−1) is input to the delay line. Then, after the input clock of the cycle in which the count value of the control counter is up-counted from (M−1) to (M−1) + U is thinned, the thinning timing signal is negated.
The control counter is preferably initialized to 0 in synchronization with an input clock of a cycle next to a cycle in which the count value of the control counter is up-counted to (M−1) + U.

The present invention is also a spread spectrum clock generator that modulates the frequency of the output clock at a constant modulation period by changing the delay value of the input clock every cycle of the input clock.
A plurality of basic delay cells connected in series, and the decimation output clock is delayed by the basic delay cells of the number of stages corresponding to the pre-delay stage number selection signal for changing the delay value of the input clock as a pre-delay output clock Output pre-delay line,
A delay line that has a plurality of delay cells connected in series, delays the thinned output clock by the number of delay cells corresponding to the delay stage number selection signal that changes the delay value of the input clock, and outputs the delayed output clock as the output clock When,
A pre-delay stage number setting circuit that generates the pre-delay stage number selection signal for each modulation period, and an output clock having an output frequency that is preset according to the modulation period and modulation degree of the output clock and having a down spread. A delay stage number setting circuit that generates the delay stage number selection signal for each cycle of the input clock based on a modulation pattern, and the pre-delay stage number selection signal for each modulation period based on the modulation pattern. Pre-delay stage number setting circuit, a maximum accumulated delay value calculation circuit for calculating a maximum accumulated delay value Dmax in the delay line based on the number M of output clock cycles and a modulation step width ΔT calculated based on the modulation pattern , And an initial value U0 of the number of cycles M of the output clock and the thinning-out number of the input clock. Is calculated, and the current based on the thinning-out number U of the modulation period, the delay line control unit having a thinning-out timing signal generating circuit for generating a thinned-out timing signal representative of the period for thinning out the input clock,
An input clock period calculation unit for calculating the period of the input clock;
A clock decimation number calculation unit for calculating an initial value U0 of the decimation number of the input clock based on the cycle of the input clock and the accumulated delay maximum value Dmax in the delay line;
A clock decimation unit that decimates the input clock during a period in which the decimation timing signal is asserted, and outputs the decimation output clock.
The delay cell is configured by connecting a plurality of basic delay cells in series, a delay value by the basic delay cell in one stage is D0, and a delay value by the delay cell in one stage is connected in series There is provided a spread spectrum clock generator characterized in that the time is equal to a value obtained by multiplying the number of basic delay cells and the delay value D0 of the one-stage basic delay cell.

  Here, it is preferable that the delay cell is configured by connecting a plurality of the basic delay cells in series, and a delay value by one stage of the delay cells is set to a time equal to the modulation step width ΔT. .

The pre-delay stage number setting circuit is
Of the accumulated delay maximum value Dmax, the pre-delay basic stage number TRIM_BASE representing the remaining period excluding the period corresponding to the number of periods of one cycle of the input clock included in the accumulated delay maximum value Dmax is expressed as TRIM_BASE = Q− A pre-delay basic stage number calculation circuit calculated by P * U;
A pre-delay stage number calculating circuit that calculates the pre-delay stage number TRIM in the next modulation period by adding the pre-delay basic stage number TRIM_BASE and the pre-delay stage number in the current modulation period for each modulation period;
It is preferable that a first decoder that decodes the pre-delay stage number TRIM in each modulation period to generate the pre-delay stage number selection signal corresponding to the pre-delay stage number TRIM is provided.

The delay stage number setting circuit includes:
A control counter that outputs a count value obtained by counting up the number of cycles of the input clock;
A stage number difference calculation circuit for calculating the stage number difference of each cycle of the output clock included in one modulation period corresponding to the count value of the control counter based on the modulation pattern for each cycle of the input clock. When,
An accumulated delay stage number calculating circuit for accumulating and adding the stage number differences of all the cycles of the output clock included in one modulation period for each cycle of the input clock, and calculating the accumulated delay stage number in each cycle;
It is preferable to include a second decoder that decodes the accumulated delay stage number in each cycle and generates the delay stage number selection signal corresponding to the accumulated delay stage number.

  In addition, the input clock period calculation unit rounds out the period corresponding to an integral multiple of the delay value D0 of the basic delay cell in the period of one cycle of the input clock, and discards the remaining period as an invalid period. Thus, it is preferable to calculate a first multiple P indicating how many times the period of one cycle of the input clock corresponds to the delay value D0 of the basic delay cell.

  The cumulative delay maximum value calculation circuit preferably calculates the cumulative delay maximum value Dmax by Dmax = (M / 2) * (M / 2) * ΔT.

  In addition, when the modulation step width ΔT corresponds to the delay value C * D0 by the C-stage basic delay cells connected in series, the maximum accumulated delay value Dmax is calculated as follows. It is preferable to calculate the second multiple Q representing how many times the delay value D0 of the basic delay cell corresponds to Q = (M / 2) * (M / 2) * C.

  Further, it is preferable that the clock thinning number calculation unit calculates the initial value U0 of the thinning number by rounding down a value after the decimal point of U0 = Q / P.

The decimation timing signal generation circuit asserts the decimation timing signal after the input clock of the cycle in which the count value of the control counter is counted up from 0 to (M−1) is input to the delay line. When the pre-delay stage number TRIM in the current modulation period is less than or equal to the first multiple P, the count value of the control counter is up-counted from (M−1) to (M−1) + U. After the input clock is thinned, the thinning timing signal is negated.
The pre-delay stage number calculation circuit updates the pre-delay stage number TRIM to TRIM = TRIM + TRIM_BASE after the decimation timing signal is negated,
The control counter is preferably initialized to 0 in synchronization with an input clock of a cycle next to a cycle in which the count value of the control counter is up-counted to (M−1) + U.

The decimation timing signal generation circuit asserts the decimation timing signal after the input clock of the cycle in which the count value of the control counter is counted up from 0 to (M−1) is input to the delay line. If the pre-delay stage number TRIM in the current modulation period is larger than the first multiple P, the decimation number U is updated to U = U + 1, and the count value of the control counter is (M−1) After the input clock of the cycle up-counted from (M−1) + U is thinned, the thinning timing signal is negated.
The pre-delay stage number calculation circuit updates the pre-delay stage number TRIM to TRIM = TRIM + TRIM_BASE-P after the decimation timing signal is negated,
The control counter is preferably initialized to 0 in synchronization with an input clock of a cycle next to a cycle in which the count value of the control counter is up-counted to (M−1) + U.

Since the present invention realizes a down spread only modulation profile with a digital SSCG, it is not necessary to increase the operating clock frequency as compared with a conventional SSCG that realizes a center spread modulation profile. Therefore, circuit design can be facilitated, an increase in circuit scale can be suppressed, and the diversion range of existing design circuits and existing LSIs can be expanded.
Further, the present invention has an advantage that the silicon area can be reduced and a dedicated pad and a dedicated pin are not required as compared with an analog SSCG that realizes a modulation profile with only a down spread.
Furthermore, the present invention realizes a modulation profile that modulates the output clock cycle more smoothly than the case of delaying the period of the output clock by the unit of the modulation step width ΔT by delaying the input clock by the unit of the delay value by the basic delay cell. can do.

It is a block diagram of a 1st embodiment showing the composition of SSCG of the present invention. FIG. 2 is a circuit diagram illustrating an example of a configuration of a delay line illustrated in FIG. 1. FIG. 2 is a block diagram illustrating an example of a configuration of a delay line control unit illustrated in FIG. 1. FIG. 4 is a block diagram illustrating an example of a configuration of a delay stage number setting circuit illustrated in FIG. 3. (A), (B), and (C) are graphs of examples showing the output frequency, output period, and cumulative delay value of the output clock of the SSCG of the present embodiment shown in FIG. 1, and (D) is FIG. 5 is an example timing chart illustrating operations of an input clock, a thinning timing signal, a thinning output clock, and an output clock of the SSCG of the present embodiment shown in FIG. It is a flowchart of an example showing operation | movement of SSCG shown in FIG. It is a flowchart of an example showing operation | movement of SSCG shown in FIG. It is a block diagram of 2nd Embodiment showing the structure of SSCG of this invention. FIG. 9 is an exemplary circuit diagram illustrating a configuration of a pre-delay line illustrated in FIG. 8. FIG. 9 is a block diagram illustrating an example of a configuration of a delay line control unit illustrated in FIG. 8. FIG. 11 is a block diagram illustrating an example of a configuration of a pre-delay stage number setting circuit illustrated in FIG. 10. (A) is an example graph showing the output period of the output clock, and (B) is an example timing chart showing the operations of the input clock, the thinning timing signal, the thinning output clock, the pre-delayed output clock, and the output clock. is there. It is a flowchart of an example showing operation | movement of SSCG shown in FIG. It is a flowchart of an example showing operation | movement of SSCG shown in FIG. It is a block diagram of an example showing the structure of the conventional SSCG. FIG. 16 is a circuit diagram illustrating an example of a configuration of a delay line illustrated in FIG. 15. (A), (B), and (C) are examples of graphs representing the output frequency, output period, and accumulated delay value of the output clock of the conventional SSCG shown in FIG.

  In the following, the spread spectrum clock generator of the present invention will be described in detail based on preferred embodiments shown in the accompanying drawings.

FIG. 1 is a block diagram of the first embodiment showing the configuration of the SSCG of the present invention. The SSCG 10 shown in the figure modulates the frequency (period) of the output clock CLKOUT with a constant modulation period by changing (increasing or decreasing) the delay value of the input clock CLKIN for each cycle of the input clock CLKIN. .
The SSCG 10 includes a delay line 12, a delay line control unit 14, an input clock period calculation unit 16, a clock decimation number calculation unit 18, and a clock decimation unit 20.

The delay line 12 delays the thinned output clock MCLKOUT in accordance with the delay stage number selection signal S [n: 0] (n is an integer equal to or greater than 0) and outputs it as the output clock CLKOUT.
As shown in FIG. 2, the delay line 12 of the present embodiment corresponds to each of (n + 1) delay cells 22 [n: 0] and delay cells 22 [n: 0] connected in series. And (n + 1) AND circuits 24 [n: 0] provided.

  Each delay cell 22 [i] (i is an integer satisfying 0 ≦ i ≦ n) is configured by connecting a plurality of basic delay cells (not shown) in series. The delay value due to the one-stage basic delay cell is D0, and the delay value due to the one-stage delay cell 22 [i] is the number of basic delay cells connected in series to form the delay cell 22 [i]. This is a value obtained by multiplying the delay value D0 of the basic delay cell in one stage. Here, the case where the delay value by the delay cell 22 [i] in one stage is equal to the modulation step width ΔT (D0 ≦ ΔT) will be described.

  The input terminal of the first delay cell 22 [n] is connected to the power supply, and the output clock CLKOUT is output from the output terminal of the final delay cell 22 [0]. The decimation output clock MCLKOUT is input from one of the input terminals of the AND circuit 24 [n: 0] from the clock decimation unit 20, and the corresponding number of delay stages is input from the delay line control unit 14 to the other input terminal. The selection signal S [n: 0] is input. The output signal of the AND circuit 24 [n: 0] is input to the control input terminal of the corresponding delay cell 22 [n: 0].

  The delay stage number selection signal S [n: 0] is, for example, a signal in which only one is in an active state per cycle, or in the present embodiment, a signal that is in the active state at a high level.

  In the delay line 12, when the delay stage number selection signal S [i] becomes high level in the active state, the thinned output clock MCLKOUT is input as the input clock CLKIN to the delay line 12 via the AND circuit 24 [i]. i]. Thus, the thinned output clock MCLKOUT is delayed by the number of delay cells 22 [i] corresponding to the delay stage number selection signal S [i] and output as the output clock CLKOUT.

  When i = 0, that is, when the delay stage number selection signal S [0] becomes an active high level, the thinned output clock MCLKOUT is input to the delay cell 22 [0] via the AND circuit 24 [0]. . In this case, the thinned output clock MCLKOUT is not delayed by the delay cell 22 [0], that is, as shown in Table 2, the delay value becomes 0 * ΔT, passes through the delay cell 22 [0], and is output as it is. It is output as the clock CLKOUT.

  On the other hand, when i = 1 to n, when the delay stage number selection signal S [i] becomes an active high level, the thinned output clock MCLKOUT is input to the delay cell 22 [i] via the AND circuit 24 [i]. Is done. In this case, the thinned output clock MCLKOUT passes through the delay cell 22 [i] and is delayed by the delay value i * ΔT by the delay cell 22 [i−1: 0] as shown in Table 2, and is output as the output clock CLKOUT. Is output.

Subsequently, the delay line control unit 14 generates the delay stage number selection signal S [n: 0], calculates the accumulated delay maximum value Dmax in the delay line 12, and generates the thinning timing signal GATE.
As shown in FIG. 3, the delay line control unit 14 includes a delay stage number setting circuit 26, a cumulative delay maximum value calculation circuit 28, and a thinning timing signal generation circuit 30.

  The delay stage number setting circuit 26 is set for each cycle of the input clock CLKIN based on a modulation pattern that is set in advance according to the modulation period and the modulation degree of the output clock CLKOUT and generates the output clock CLKOUT having an output frequency of down spread. The delay stage number selection signal S [n: 0] for sequentially changing the delay value of the input clock CLKIN in units of the delay value ΔT of the delay cell 22 [i] is generated.

  As shown in FIG. 4, the delay stage number setting circuit 26 includes a control counter 32, a stage number difference calculation circuit 34, an accumulated delay stage number calculation circuit (cumulative adder) 36 including an adder 38 and an accumulated delay stage number latch 40, And a decoder 42.

The control counter 32 counts up the number of cycles of the input clock CLKIN and sequentially outputs the count value CTRL_COUNT.
The count value CTRL_COUNT is also used by the thinning timing signal generation circuit 30 as shown in FIG.

  The stage number difference calculation circuit 34 sequentially calculates the stage number difference of each cycle of the output clock CLKOUT included in one modulation period corresponding to the count value CTRL_COUNT based on the modulation pattern for each cycle of the input clock CLKIN. Is.

The accumulated delay stage number calculating circuit 36 sequentially accumulates and adds the stage number differences of all the cycles of the output clock CLKOUT included in one modulation period for each cycle of the input clock CLKIN, and calculates the accumulated delay stage number in each cycle. To do.
In the case of this embodiment, cumulative addition is performed by a cumulative adder constituted by an adder 38 and a cumulative delay stage number latch 40.

  The decoder 42 decodes the accumulated delay stage number in each cycle, and sequentially generates a delay stage number selection signal S [n: 0] corresponding to the accumulated delay stage number.

  Subsequently, the accumulated delay maximum value calculation circuit 28 of the delay line control unit 14 calculates the maximum accumulated delay in the delay line 12 based on the number M of cycles of the output clock CLKOUT and the modulation step width ΔT calculated based on the modulation pattern. The value Dmax is calculated.

  The method for calculating the maximum accumulated delay value Dmax is not limited in any way, but can be calculated by, for example, Dmax = (M / 2) * (M / 2) * ΔT. When the modulation step width ΔT corresponds to the delay value by the C-stage basic delay cells connected in series (ΔT = C * D0), the cumulative delay maximum value calculation circuit 28 of the present embodiment is the maximum cumulative delay value Dmax. Is calculated by Q = (M / 2) * (M / 2) * C, which represents how many times the delay value D0 of the basic delay cell corresponds to.

  Here, a method of calculating the cumulative delay maximum value Dmax will be described.

  Table 3 shows the delay increase A (k) and the accumulated delay value B (k) (k is an integer of 1 ≦ k ≦ M) when the number of cycles M = 16 of the output clock CLKOUT and the modulation step width ΔT. It is a thing. In Table 3, the cumulative delay value B (16) = 64 * ΔT when the clock number k = 16 is the maximum cumulative delay value Dmax, and the value is the delay increase A ( 1) to A (16), and can be calculated by Q (16) = A (1) + A (2) +... + A (15) + A (16).

  Here, for the delay increases A (1) to A (16), A (1) + A (9), A (2) + A (10),... A (7) + A (15), A (8) + A Focusing on each group of (16), the value of each group is M / 2 * ΔT, and the number of groups is M / 2. Therefore, the cumulative delay maximum value Dmax can be calculated by multiplying M / 2 * ΔT and M / 2, that is, Dmax = (M / 2) * (M / 2) * ΔT.

Subsequently, the decimation timing signal generation circuit 30 operates in synchronization with the input clock CLKIN, and is calculated by the cycle number M of the output clock CLKOUT and the clock decimation number calculation unit 18 calculated based on the modulation pattern. Based on the thinning-out number U of the input clock CLKIN, a thinning-out timing signal GATE representing a period for thinning out the input clock CLKIN is generated.
In the case of the present embodiment, the thinning timing signal GATE is in the active state high level during the period of thinning the input clock CLKIN.

Subsequently, the input clock cycle calculation unit 16 calculates the cycle of the input clock CLKIN.
The input clock cycle calculation unit 16 of the present embodiment is generated by a ring oscillator configured by connecting the same basic delay cells as the basic delay cells constituting the delay line 12 in a ring shape for a period of one cycle of the input clock CLKIN. The number of cycles of the oscillation clock to be generated is up-counted by the counter, and based on the count value, the first period representing how many times the period of one cycle of the input clock CLKIN corresponds to the delay value D0 of the basic delay cell Multiple of P is calculated.

  When calculating the first multiple P, the input clock period calculation unit 16 counts up by a counter in a period that is an integral multiple of the delay value D0 of the basic delay cell in one period of the input clock CLKIN. The period during which the period is completed is set as the effective period, and the remaining period, that is, the period during which the up-counting cannot be performed is rounded down as the invalid period. By performing this truncation process, it is possible to prevent a fine output pulse from occurring in the output clock CLKOUT.

Subsequently, the clock thinning number calculation unit 18 operates in synchronization with the input clock CLKIN, and calculates the thinning number U of the input clock CLKIN based on the cycle of the input clock CLKIN and the accumulated delay maximum value Dmax in the delay line 12. Is.
Based on the first multiple P and the second multiple Q, the clock thinning number calculation unit 18 of the present embodiment calculates the thinning number U of the input clock CLKIN by U = Q / P.

When calculating the thinning number U, the clock thinning number calculation unit 18 rounds up the value after the decimal point of the thinning number U. By performing this rounding-up process, it is possible to prevent a fine output pulse from occurring in the output clock CLKOUT.
That is, the thinning-out number U represents how many times or less the period of the cumulative delay maximum value Dmax corresponds to the period of one cycle of the input clock CLKIN.

Finally, the clock decimation unit 20 decimates the input clock CLKIN during the period when the decimation timing signal GATE is asserted, and outputs it as a decimation output clock MCLKOUT.
When the decimation timing signal GATE is asserted, the clock decimation unit 20 of this embodiment decimates the input clock CLKIN during the period when the decimation timing signal GATE is in the active state, and outputs a low level as the decimation output clock MCLKOUT. .

Similarly, when the cycle Tin [ns] of the input clock CLKIN, the modulation cycle Tmod [ns] of the output clock CLKOUT, and the modulation factor R [%], in the SSCG 10, the number of cycles M of the output clock CLKOUT and the modulation step width ΔT are: Calculated by equation (4).
M = Tmod / Tin
ΔT = (Tin * R) / (M / 2) Equation (4)

In this case, a down spread modulation profile is realized in which the period Tout [ns] of the output clock CLKOUT varies within the range calculated by the equation (5) according to the modulation pattern.
Tout = Tin−ΔT * (M / 2) to Tin (5)

For example, when the cycle Tin = 10 ns of the input clock CLKIN, the modulation cycle Tmod = 440 ns of the output clock CLKOUT, and the modulation factor R = −22%, the number of cycles M of the output clock CLKOUT and the modulation step width ΔT are expressed by the equation (6). Street.
Number of cycles of output clock CLKOUT M = 440/10 = 44
Modulation step width ΔT = (10 * 0.22) / (44/2) = 0.1 ns (6)

  5A, 5B, and 5C are graphs showing examples of the output frequency, the output cycle, and the accumulated delay value of the output clock CLKOUT of the SSCG of this embodiment shown in FIG. 1, respectively. . These graphs represent the output frequency, output period, and accumulated delay value of the output clock CLKOUT in the case of the above numerical example, and the respective vertical axes represent the output frequency [MHz], the output period [ns], and the accumulated delay. The value [ΔT] is represented, and the horizontal axis represents time [t].

In the case of the above numerical example, the output frequency of the output clock CLKOUT changes (increases / decreases) every cycle within the range of the frequency of the input clock CLKIN = 100 MHz to about 82.0 MHz, as shown in the graph of FIG. .
That is, the frequency gradually decreases from 100 MHz, reaches a minimum value of about 82.0 MHz at a timing of 1/2 of one modulation period, increases gradually from the minimum value, and returns to 100 MHz at the timing of one modulation period.

On the other hand, the output cycle of the output clock CLKOUT changes (increases / decreases) every cycle in the range of the cycle of the input clock CLKIN = 10 ns to 12.2 ns, as shown in the graph of FIG.
In other words, it gradually increases from 10 ns, reaches the maximum value of 12.2 ns at half the timing of one modulation period, decreases gradually from the maximum value, and returns to 10 ns at the timing of one modulation period.

The accumulated delay value of the output clock CLKOUT changes (increases) every cycle from 0 * ΔT to 484 * ΔT, as shown in FIG.
That is, it increases sequentially from 0 * ΔT and reaches the maximum value of 484 * ΔT at the timing of one modulation period.

  Subsequently, Table 4 shows the time [ns], the cycle number [#] of the input clock CLKIN, the stage number difference [ΔT], the accumulated delay stage number [ΔT], and the delay stage number selection signal S [ n: 0].

  Looking at the difference in the number of stages, it can be seen that in SSCG 10, a modulation profile only for down spread is realized. Further, when looking at the accumulated delay stage number, it can be seen that in SSCG 10, the accumulated delay stage number increases from the minimum value 0 to the maximum value 484 in one modulation period of the output clock CLKOUT. Therefore, at the end of one modulation period, the input clock CLKIN is delayed by 484 delay cells 22.

  FIG. 5D is an example timing chart showing operations of the input clock CLKIN, the thinning timing signal GATE, the thinning output clock MCLKOUT, and the output clock CLKOUT of the SSCG of this embodiment shown in FIG.

When the down spread output clock CLKOUT is generated by modulating the frequency of the input clock CLKIN, the cycle of the input clock CLKIN included in one modulation period as shown in the timing chart of FIG. The number of cycles of the output clock CLKOUT included in one modulation period is 44 cycles from 0 to 43, whereas the number is 49 cycles from 0 to 48, and there are 5 cycles of the input clock CLKIN between them. Differences in minutes occur.
The number of cycles of the input clock CLKIN that is not output as the output clock CLKOUT, that is, 49-44 = 5 cycles in the above numerical example, is the thinning-out number U.

  The SSCG 10 asserts the thinning timing signal GATE, and inputs the thinned input clock CLKIN to the delay line 12 during the cycle of the input clock CLKIN corresponding to the thinning number U. Thus, after the input clock CLKIN corresponding to the last output clock CLKOUT included in one modulation period is input to the delay line 12, the input clock CLKIN corresponding to the first output clock CLKOUT included in the next one modulation period is changed. The input clock CLKIN is not input to the delay line 12 until it is input to the delay line 12 (in this embodiment, it is at a low level).

  Since the rounding-up process is performed when calculating the thinning number U, the cycle period of the input clock CLKIN corresponding to the thinning number U is equal to or longer than the cumulative delay maximum value Dmax. In other words, the input clock CLKIN corresponding to the last output clock CLKOUT included in one modulation period is input as the output clock CLKOUT during the period of the input clock CLKIN having the number of cycles corresponding to the thinning-out number U after being input to the delay line 12. Is output, and the accumulated delay in the delay line 12 becomes zero. Therefore, the SSCG 10 can continuously perform the down spread operation.

  Next, the operation of the SSCG 10 will be described with reference to the flowcharts of FIGS.

First, the first multiple P (truncated) is calculated by the input clock period calculation unit 16, the second multiple Q is calculated by the maximum accumulated delay value calculation circuit 28, and the thinning number U is calculated by the clock thinning number calculation unit 18. , U = Q / P (rounded up).
Further, the reset signal RESET becomes an active low level, the control counter 32 is initialized, and the count value CTRL_COUNT becomes 0 (step S1).

For example, as in the above numerical example, the cycle Tin of the input clock CLKIN is 10 ns, the modulation cycle Tmod of the output clock CLKOUT is 440 ns, the modulation degree R is −22%, and the modulation step width ΔT is C stages. When it corresponds to the delay value D0 of the delay cell 22 (ΔT = C * D0), when C = 4, the first multiple P is P = Tin / ΔT * C = 10 ns / 0.1 ns * 4 = 400 It becomes.
The second multiple Q is Q = (M / 2) * (M / 2) * C = (44/2) * (44/2) * 4 = 1936, and the thinning-out number U is U = Q Since /P=1936/400=4.84, U = 5.

  When the reset signal RESET becomes the inactive high level, the control counter 32 counts up the number of cycles of the input clock CLKIN, and sequentially outputs the count value CTRL_COUNT (step S2). That is, for each cycle of the input clock CLKIN, the count value CTRL_COUNT = CTRL_COUNT + 1.

Subsequently, the thinning timing signal generation circuit 30 determines whether or not the count value CTRL_COUNT is up-counted from 0 to (M−1) (step S3).
In the numerical example described above, (M−1) = (44-1) = 43.

  If the count value CTRL_COUNT is not (M−1) (N in step S3), the process returns to step S2, and the control counter 32 continues to count up the number of cycles of the input clock CLKIN.

  When the count value CTRL_COUNT has become (M−1) (Y in step S3), the input clock CLKIN of the cycle in which the count value CTRL_COUNT has been up-counted to (M−1) is input to the delay line 12, and then decimation is performed. The thinning timing signal GATE is asserted by the timing signal generation circuit 30 (step S4). That is, thinning of the input clock CLKIN by the clock thinning unit 20 is started.

  Subsequently, the control counter 32 continues to count up the number of cycles of the input clock CLKIN, and sequentially outputs the count value CTRL_COUNT (step S5).

Subsequently, the thinning timing signal generation circuit 30 determines whether or not the count value CTRL_COUNT is further counted up from (M−1) to (M−1) + U (step S6).
In the case of the above numerical example, (M-1) + U = (44-1) + 5 = 48.

  If the count value CTRL_COUNT is not (M−1) + U (N in step S6), the process returns to step S5, and the control counter 32 continues to count up the number of cycles of the input clock CLKIN.

  When the count value CTRL_COUNT becomes (M−1) + U (Y in step S6), the clock decimation unit 20 decimates the input clock CLKIN of the cycle in which the count value CTRL_COUNT is up-counted to (M−1) + U. After that, the thinning timing signal generation circuit 30 negates the thinning timing signal GATE (step S7). That is, the decimation of the input clock CLKIN by the clock decimation unit 20 is completed.

  That is, the count value CTRL_COUNT of the control counter 32 is asserted during the period from the number of cycles M to (M−1) + U, and the thinned input clock CLKIN is input to the delay line 12.

  Subsequently, the control counter 32 is initialized again in synchronization with the input clock CLKIN of the cycle next to the cycle in which the count value CTRL_COUNT is up-counted to (M−1) + U, and the count value CTRL_COUNT becomes 0 ( Step S8). That is, the control counter 32 is initialized with the first input clock CLKIN immediately after the decimation of the input clock CLKIN is completed. Subsequent operations are repeated as described above.

  On the other hand, in the delay stage number setting circuit 26, as described above, when the reset signal RESET becomes the active low level, the number of accumulated delay stages constituting the control counter 32, the stage number difference calculating circuit 34, and the accumulated delay stage number calculating circuit 36. The latch 40 is initialized, and the count value CTRL_COUNT of the control counter 32, the stage number difference calculated by the stage number difference calculating circuit 34, and the cumulative delay stage number calculated by the cumulative delay stage number calculating circuit 36 are all 0 (step) S9).

  When the reset signal RESET becomes high level in an inactive state, as described above, the control counter 32 counts up the number of cycles of the input clock CLKIN, and sequentially outputs the count value CTRL_COUNT (step S10).

  Subsequently, the stage number difference calculation circuit 34 calculates the stage number difference corresponding to the count value CTRL_COUNT for each cycle of the input clock CLKIN based on the modulation pattern (step S11).

  Subsequently, in the accumulated delay stage number calculation circuit 36, the adder 38 causes the stage number difference in the current cycle and the accumulated value of the stage number difference until the previous cycle held by the accumulated delay stage number latch 40, that is, one. The accumulated delay stage number in the previous cycle is added and held in the accumulated delay stage number latch 40 again in synchronization with the input clock CLKIN. Thereby, the stage number difference up to the current cycle is cumulatively added, and the cumulative number of delay stages in the current cycle is calculated (step S12).

  That is, the accumulated delay stage number calculating circuit 36 cumulatively adds the stage number differences of all the cycles of the output clock CLKOUT included in one modulation period for each cycle of the input clock CLKIN, and sequentially calculates the accumulated delay stage number in each cycle. Calculated.

  Then, the number of accumulated delay stages in each cycle is decoded by the decoder 42, and a delay stage number selection signal S [n: 0] corresponding to the accumulated delay stage number is sequentially generated and input to the delay line 12 (step S13). .

  In the case of the above numerical example, the stage number difference, the accumulated delay stage number, and the delay stage number selection signal S [n: 0] change as shown in Table 4.

Subsequently, the thinned output clock MCLKOUT is delayed by the delay line 12 in accordance with the delay stage number selection signal S [n: 0] and sequentially output as the output clock CLKOUT (step S14).
As a result, the output clock CLKOUT having the output frequency and output cycle shown in FIGS. 5 (A) and 5 (B) is output from the delay line 12.

Since the SSCG 10 realizes a down spread modulation profile with the digital SSCG, it is not necessary to increase the operating clock frequency as compared with the conventional SSCG 70 that implements the center spread modulation profile. Therefore, circuit design can be facilitated, an increase in circuit scale can be suppressed, and the diversion range of existing design circuits and existing LSIs can be expanded.
Further, the SSCG 10 has an advantage that the silicon area can be reduced and a dedicated pad and a dedicated pin are not required, as compared with an analog SSCG that realizes a down spread modulation profile.

  Next, a second embodiment of the SSCG of the present invention will be described.

FIG. 8 is a block diagram of the second embodiment showing the configuration of the SSCG of the present invention. The SSCG 50 shown in the figure further includes a pre-delay line 52 in the SSCG 10 shown in FIG. 1, and instead of the delay line control unit 14 and the clock thinning number calculation unit 18, a delay line control unit 14B and a clock thinning number calculation unit. 18B is provided.
That is, the SSCG 50 includes the delay line 12, the delay line control unit 14B, the input clock cycle calculation unit 16, the clock thinning number calculation unit 18B, the clock thinning unit 20, and the pre-delay line 52.

  In the following, the same components as those of the SSCG 10 are denoted by the same reference numerals, detailed description thereof is omitted, and the pre-delay line 52, the delay line control unit 14B, and the clock thinning number calculation unit 18B will be described.

The pre-delay line 52 delays the decimation output clock MCLKOUT as the input clock CLKIN to the pre-delay line 52 in accordance with the pre-delay stage number selection signal PS [m: 0] (m is an integer equal to or greater than 0). This is output as the output clock PCLKOUT. The pre-delay output clock PCLKOUT is input to the delay line 12 as an input clock CLKIN for the delay line 12.
As shown in FIG. 9, the pre-delay line 52 of the present embodiment includes (m + 1) basic delay cells 54 [m: 0] and basic delay cells 54 [m: 0] connected in series. It is configured by (m + 1) AND circuits 56 [m: 0] provided correspondingly.

  In the pre-delay line 52, instead of the delay cell 22 [i] and the AND circuit 24 [i] configured by a plurality of basic delay cells, the basic delay cell 54 [j] (j is an integer of 0 ≦ j ≦ m). ) And an AND circuit 56 [j], a pre-delay stage number selection signal PS [j] is input instead of the delay stage number selection signal S [i], and a pre-delay output clock PCLKOUT is used instead of the output clock CLKOUT. The output point is only different from the delay line 12 shown in FIG. 2, and the basic configuration and operation are the same, and thus detailed description thereof is omitted.

  The pre-delay stage number selection signal PS [m: 0] is, for example, a signal that is in an active state for each modulation period, or a signal that is in an active state at a high level in this embodiment. In the pre-delay line 52, the thinned output clock MCLKOUT is delayed by the number of basic delay cells 54 [j] corresponding to the pre-delay stage number selection signal PS [j], and is output as the pre-delay output clock PCLKOUT. Table 5 shows the relationship between the pre-delay stage number selection signal PS [j] and the delay value.

  Subsequently, the clock decimation number calculation unit 18B operates in synchronization with the input clock CLKIN, and sets the initial decimation number U0 of the input clock CLKIN based on the first multiple P and the second multiple Q to U0 = It is calculated by Q / P.

When calculating the initial value U0 of the thinned-out number, the clock thinned-out number calculating unit 18B truncates the value after the decimal point of the initial value U0 of the thinned-out number.
That is, the initial value U0 of the thinning-out number represents how many periods of one cycle of the input clock CLKIN are included in the period of the cumulative delay maximum value Dmax.
The initial value U0 of the thinning number is used as the initial value of the thinning number U by the thinning timing signal generation circuit 30B.

Subsequently, as shown in FIG. 10, the delay line control unit 14B is further provided with a pre-delay stage number setting circuit 58 in the delay line control unit 14 shown in FIG. A timing signal generation circuit 30B is provided.
That is, the delay line control unit 14B includes the delay stage number setting circuit 26, the pre-delay stage number setting circuit 58, the cumulative delay maximum value calculation circuit 28, and the thinning timing signal generation circuit 30B.

The pre-delay stage number setting circuit 58 sequentially changes the delay value of the input clock CLKIN in units of the delay value D0 of the basic delay cell 54 [j] for each modulation period. Is generated.
The pre-delay stage number setting circuit 58 includes a pre-delay basic stage number calculation circuit 60, a pre-delay stage number calculation circuit 62, and a decoder 64, as shown in FIG.

The pre-delay basic stage number calculating circuit 60 calculates the pre-delay basic stage number TRIM_BASE by TRIM_BASE = Q−P * U.
That is, the pre-delay basic stage number TRIM_BASE represents a remaining period excluding a period corresponding to the number of periods of one cycle of the input clock included in the accumulated delay maximum value Dmax among the accumulated delay maximum value Dmax.

  The pre-delay stage number calculation circuit 62 adds the pre-delay basic stage number TRIM_BASE and the pre-delay stage number in the current modulation period held by the pre-delay stage number latch for each modulation period, and pre-delays in the next modulation period The stage number TRIM is sequentially calculated.

  When the current pre-delay stage number TRIM is equal to or smaller than the first multiple P, the pre-delay stage number calculation circuit 62 according to the present embodiment calculates the pre-delay stage number TRIM in the next modulation period using TRIM = TRIM + TRIM_BASE. On the other hand, when the current pre-delay stage number TRIM is larger than the first multiple P, the pre-delay stage number TRIM in the next modulation period is calculated by TRIM = TRIM + TRIM_BASE-P.

  The decoder 64 decodes the pre-delay stage number TRIM in each modulation period, and sequentially generates a pre-delay stage number selection signal PS [m: 0] corresponding to the pre-delay stage number TRIM.

  Subsequently, the thinning timing signal generation circuit 30B of the delay line control unit 14B operates in synchronization with the input clock CLKIN, and calculates the cycle number M of the output clock CLKOUT and the clock thinning number calculated based on the modulation pattern. A decimation timing signal GATE representing a period of decimation of the input clock CLKIN is generated based on the decimation number U of the current modulation period calculated from the initial decimation number U0 of the input clock CLKIN calculated by the unit 18B. is there.

  Next, the operation of the SSCG 50 will be described with reference to the graph of FIG. 12A, the timing chart of FIG. 12B, and the flowcharts of FIGS.

  FIG. 12A is an example graph illustrating the output period of the output clock. This graph is the same as the graph of FIG. FIG. 7B is an example timing chart showing operations of the input clock CLKIN, the thinning timing signal GATE, the thinning output clock MCLKOUT, the pre-delay output clock PCLKOUT, and the output clock CLKOUT.

First, a first multiple P (truncated) is calculated by the input clock period calculation unit 16, a second multiple Q is calculated by the cumulative delay maximum value calculation circuit 28, and an initial decimation number is calculated by the clock decimation number calculation unit 18B. The value U0 is calculated by U0 = Q / P (truncated). Then, the thinning-out timing signal generation circuit 30B initializes the thinning-out number U to U = U0.
The pre-delay basic stage number calculation circuit 60 calculates the pre-delay basic stage number TRIM_BASE by TRIM_BASE = Q−P * U, and the pre-delay stage number calculation circuit 62 initializes the pre-delay stage number TRIM to 0.
Further, the reset signal RESET becomes an active low level, the control counter 32 is initialized, and the count value CTRL_COUNT becomes 0 (step S20).

For example, in the above numerical example, the first multiple P is P = Tin / ΔT * C = 10 ns / 0.1 ns * 4 = 400, and the second multiple Q is Q = (M / 2) * ( M / 2) * C = (44/2) * (44/2) * 4 = 1936, and the initial value U0 of the thinning-out number is U0 = 4 from U = Q / P = 1936/400 = 4.84. It becomes.
The number of pre-delay basic stages TRIM_BASE is TRIM_BASE = Q−P * U = 1936−400 * 4 = 336.

  The operation from step S21 to S25 is the same as the operation from step S2 to S6 shown in FIG.

When the count value CTRL_COUNT becomes (M−1) + U (Y in step S25), the pre-delay stage number calculation circuit 62 then causes the pre-delay stage number TRIM in the current modulation period to be larger than the first multiple P. Is determined (TRIM + TRIM_BASE> P) (step S26).
In the above numerical example, (M−1) + U = (44-1) + 4 = 47, and TRIM + TRIM_BASE = 0 + 336 = 336.

  Here, when the number of pre-delay stages TRIM in the current modulation period is equal to or smaller than the first multiple P (N in step S26), the clock decimation unit 20 causes the count value CTRL_COUNT to be changed from (M-1) to (M-1) + U. After the input clock CLKIN of the cycle counted up is thinned out, the thinning timing signal generation circuit 30B negates the thinning timing signal GATE (step S27). That is, the decimation of the input clock CLKIN by the clock decimation unit 20 is completed.

  That is, the count value CTRL_COUNT of the control counter 32 is asserted during the period from the number of cycles M to (M−1) + U, and the thinned output clock MCLKOUT is preliminarily used as the input clock CLKIN during that period. Input to the delay line 52.

  Subsequently, after the decimation timing signal GATE is negated by the decimation timing signal generation circuit 30B, the pre-delay stage number TRIM is updated to TRIM = TRIM + TRIM_BASE (step S28).

  Subsequently, the control counter 32 is initialized again in synchronization with the input clock CLKIN of the cycle next to the cycle in which the count value CTRL_COUNT is up-counted to (M−1) + U, and the count value CTRL_COUNT becomes 0 ( Step S29). That is, the control counter 32 is initialized with the first input clock CLKIN immediately after the decimation of the input clock CLKIN is completed. Subsequent operations are repeated as described above.

If the pre-delay stage number TRIM in the current modulation period is larger than the first multiple P in step S26 (Y in step S26), the thinning-out timing signal generation circuit 30B updates the thinning-out number U to U = U + 1. .
In the above numerical example, the thinning-out number U is U = U + 1 = 4 + 1 = 5.
Further, the control counter 32 continues to count up the number of cycles of the input clock CLKIN, and the count value CTRL_COUNT = CTRL_COUNT + 1 is obtained (step S30).

  Subsequently, after the input clock CLKIN of the cycle in which the count value CTRL_COUNT is up-counted from (M−1) to (M−1) + U is thinned by the clock thinning unit 20, the thinning timing signal generation circuit 30B The thinning timing signal GATE is negated (step S31). That is, the decimation of the input clock CLKIN by the clock decimation unit 20 is completed.

  Subsequently, after the decimation timing signal GATE is negated by the decimation timing signal generation circuit 30B, the pre-delay stage number TRIM is updated to TRIM = TRIM + TRIM_BASE-P, and the process proceeds to step S29. Subsequent operations are repeated as described above.

  On the other hand, in the pre-delay stage number setting circuit 58, the operation from step S33 to S37 is the same as the operation from step S9 to S13 shown in FIG.

  Subsequently, the decoder 64 generates a pre-delay stage number selection signal PS [m: 0] corresponding to the pre-delay stage number TRIM (step S38).

  Subsequently, the pre-delay line 52 delays the decimation output clock MCLKOUT in accordance with the pre-delay stage number selection signal PS [m: 0] and sequentially outputs it as the pre-delay output clock PCLKOUT (step S39).

In the above numerical example, when the thinning-out number U is U = 4 (the first modulation cycle), as shown in the center portion of the timing chart of FIG. 12B, (M−1) + U = (44-1) + 4 = 47, and the pre-delay stage number TRIM is TRIM = TRIM + TRIM_BASE = 0 + 336 = 336.
In the case of U = 5 (second modulation cycle), as shown in the right part of the timing chart of FIG. 5B, (M−1) + U = (44-1) + 5 = 48, and the number of pre-delay stages TRIM is , TRIM = TRIM + TRIM_BASE-P = 336 + 336-400 = 272.

Then, the thinned output clock MCLKOUT is delayed by the delay line 12 in accordance with the delay stage number selection signal S [n: 0], and sequentially output as the output clock CLKOUT (step S40).
As a result, the output clock CLKOUT having the output cycle shown in FIG.

  The SSCG 10 of the first embodiment delays the input clock CLKIN by the unit of the modulation step width ΔT by the delay cell 22 [i] of the delay line 12, but the SSCG 50 of the second embodiment The basic delay cell 54 [j] delays the input clock CLKIN in units of the delay value D0 by the basic delay cell 54 [j]. Therefore, the SSCG 50 can realize a modulation profile that can connect the current modulation period and the next modulation period more smoothly than the SSCG 10 with respect to the period of the output clock CLKOUT.

  In addition, the specific structure of each component which comprises SSCG of this invention is not limited at all, The thing of the various structures which can fulfill | perform the same function can be used.

The present invention is basically as described above.
Although the present invention has been described in detail above, the present invention is not limited to the above-described embodiment, and it is needless to say that various improvements and modifications may be made without departing from the gist of the present invention.

10, 50 SSCG
12 Delay line 14, 14B Delay line control unit 16 Input clock cycle calculation unit 18, 18B Clock decimation number calculation unit 20 Clock decimation unit 22 Delay cell 24, 56 AND circuit 26 Delay stage number setting circuit 28 Cumulative delay maximum value calculation circuit 30, 30B Thinning-out timing signal generation circuit 32 Control counter 34 Stage number difference calculation circuit 36 Cumulative delay stage number calculation circuit 38 Adder 40 Cumulative delay stage number latch 42, 64 Decoder 52 Pre delay line 54 Basic delay cell 58 Pre delay stage number setting circuit 60 Pre delay basic circuit Stage number calculation circuit 62 Pre-delay stage number calculation circuit

Claims (17)

A spread spectrum clock generator that modulates the frequency of the output clock at a constant modulation period by changing the delay value of the input clock for each cycle of the input clock,
A delay line that has a plurality of delay cells connected in series, delays the thinned output clock by the number of delay cells corresponding to the delay stage number selection signal that changes the delay value of the input clock, and outputs the delayed output clock as the output clock When,
The delay stage number selection signal is generated for each cycle of the input clock based on a modulation pattern that generates an output clock having a down spread output frequency that is preset according to the modulation period and modulation degree of the output clock. A delay stage number setting circuit that calculates a cumulative delay maximum value Dmax in the delay line based on the output clock cycle number M and a modulation step width ΔT calculated based on the modulation pattern And a delay line control unit having a decimation timing signal generation circuit that generates a decimation timing signal representing a period of decimation of the input clock based on the number M of cycles of the output clock and the decimation number U of the input clock;
An input clock period calculation unit for calculating the period of the input clock;
A clock decimation number calculation unit for calculating the decimation number U of the input clock based on the cycle of the input clock and the accumulated delay maximum value Dmax in the delay line;
A clock decimation unit that decimates the input clock during a period in which the decimation timing signal is asserted, and outputs the decimation output clock.
The delay cell is configured by connecting a plurality of basic delay cells in series, a delay value by the basic delay cell in one stage is D0, and a delay value by the delay cell in one stage is connected in series. A spread spectrum clock generator characterized in that the time is equal to a value obtained by multiplying the number of basic delay cells by the delay value D0 of the one-stage basic delay cell. The delay stage number setting circuit includes:
A control counter that outputs a count value obtained by counting up the number of cycles of the input clock;
A stage number difference calculation circuit for calculating the stage number difference of each cycle of the output clock included in one modulation period corresponding to the count value of the control counter based on the modulation pattern for each cycle of the input clock. When,
An accumulated delay stage number calculating circuit for accumulating and adding the stage number differences of all the cycles of the output clock included in one modulation period for each cycle of the input clock, and calculating the accumulated delay stage number in each cycle;
The spread spectrum clock generator according to claim 1, further comprising: a decoder that decodes the accumulated delay stage number in each cycle and generates the delay stage number selection signal corresponding to the accumulated delay stage number.   The input clock cycle calculation unit rounds out a period corresponding to an integral multiple of the delay value D0 of the basic delay cell in a period of one cycle of the input clock and discards the remaining period as an invalid period, 3. The spread spectrum clock generator according to claim 1, wherein a first multiple P representing how many times a period of one cycle of the input clock corresponds to a delay value D0 of the basic delay cell is calculated.   The cumulative delay maximum value calculation circuit calculates the cumulative delay maximum value Dmax by Dmax = (M / 2) * (M / 2) * ΔT. Spread spectrum clock generator.   When the modulation step width ΔT corresponds to the delay value C * D0 by the C-stage basic delay cells connected in series, the cumulative delay maximum value calculation circuit calculates the maximum delay value Dmax as the basic delay value. The spread spectrum according to claim 3, wherein a second multiple Q representing how many times the cell delay value D0 corresponds is calculated by Q = (M / 2) * (M / 2) * C. Clock generator.   6. The spread spectrum clock generator according to claim 5, wherein the clock thinning number calculation unit calculates the thinning number U by rounding up a value after the decimal point of U = Q / P. The decimation timing signal generation circuit asserts the decimation timing signal after an input clock of a cycle in which the count value of the control counter is counted up from 0 to (M−1) is input to the delay line, After the input clock of the cycle in which the count value of the control counter is up-counted from (M−1) to (M−1) + U is thinned, the thinning timing signal is negated.
3. The control counter according to claim 2, wherein the control counter is initialized to 0 in synchronization with an input clock of a cycle next to a cycle in which the count value of the control counter is up-counted to (M-1) + U. Spread spectrum clock generator. A spread spectrum clock generator that modulates the frequency of the output clock at a constant modulation period by changing the delay value of the input clock for each cycle of the input clock,
A plurality of basic delay cells connected in series, and the decimation output clock is delayed by the basic delay cells of the number of stages corresponding to the pre-delay stage number selection signal for changing the delay value of the input clock as a pre-delay output clock Output pre-delay line,
A delay line that has a plurality of delay cells connected in series, delays the thinned output clock by the number of delay cells corresponding to the delay stage number selection signal that changes the delay value of the input clock, and outputs the delayed output clock as the output clock When,
A pre-delay stage number setting circuit that generates the pre-delay stage number selection signal for each modulation period, and an output clock having an output frequency that is preset according to the modulation period and modulation degree of the output clock and having a down spread. A delay stage number setting circuit that generates the delay stage number selection signal for each cycle of the input clock based on a modulation pattern, and the pre-delay stage number selection signal for each modulation period based on the modulation pattern. Pre-delay stage number setting circuit, a maximum accumulated delay value calculation circuit for calculating a maximum accumulated delay value Dmax in the delay line based on the number M of output clock cycles and a modulation step width ΔT calculated based on the modulation pattern , And an initial value U0 of the number of cycles M of the output clock and the thinning-out number of the input clock. Is calculated, and the current based on the thinning-out number U of the modulation period, the delay line control unit having a thinning-out timing signal generating circuit for generating a thinned-out timing signal representative of the period for thinning out the input clock,
An input clock period calculation unit for calculating the period of the input clock;
A clock decimation number calculation unit for calculating an initial value U0 of the decimation number of the input clock based on the cycle of the input clock and the accumulated delay maximum value Dmax in the delay line;
A clock decimation unit that decimates the input clock during a period in which the decimation timing signal is asserted, and outputs the decimation output clock.
The delay cell is configured by connecting a plurality of basic delay cells in series, a delay value by the basic delay cell in one stage is D0, and a delay value by the delay cell in one stage is connected in series A spread-spectrum clock generator characterized in that the time is equal to a value obtained by multiplying the number of the basic delay cells and the delay value D0 of the one-stage basic delay cell.   9. The delay cell according to claim 8, wherein the delay cell is configured by connecting a plurality of the basic delay cells in series, and a delay value by the delay cell in one stage is set to a time equal to the modulation step width ΔT. Spread spectrum clock generator. The pre-delay stage number setting circuit includes:
Of the accumulated delay maximum value Dmax, the pre-delay basic stage number TRIM_BASE representing the remaining period excluding the period corresponding to the number of periods of one cycle of the input clock included in the accumulated delay maximum value Dmax is expressed as TRIM_BASE = Q− A pre-delay basic stage number calculation circuit calculated by P * U;
A pre-delay stage number calculating circuit that calculates the pre-delay stage number TRIM in the next modulation period by adding the pre-delay basic stage number TRIM_BASE and the pre-delay stage number in the current modulation period for each modulation period;
10. The spread spectrum clock according to claim 8, further comprising: a first decoder that decodes the pre-delay stage number TRIM in each modulation period and generates the pre-delay stage number selection signal corresponding to the pre-delay stage number TRIM. generator. The delay stage number setting circuit includes:
A control counter that outputs a count value obtained by counting up the number of cycles of the input clock;
A stage number difference calculation circuit for calculating the stage number difference of each cycle of the output clock included in one modulation period corresponding to the count value of the control counter based on the modulation pattern for each cycle of the input clock. When,
An accumulated delay stage number calculating circuit for accumulating and adding the stage number differences of all the cycles of the output clock included in one modulation period for each cycle of the input clock, and calculating the accumulated delay stage number in each cycle;
The spread spectrum clock generator according to claim 10, further comprising: a second decoder that decodes the accumulated delay stage number in each cycle and generates the delay stage number selection signal corresponding to the accumulated delay stage number.   The input clock cycle calculation unit sets a period corresponding to an integral multiple of the delay value D0 of the basic delay cell in a period of one cycle of the input clock as a valid period, and discards the remaining period as an invalid period. The first multiple P representing how many times the delay value D0 of the basic delay cell corresponds to a period of one cycle of the input clock is calculated according to any one of claims 8 to 11. Spread spectrum clock generator.   12. The cumulative delay maximum value calculation circuit calculates the cumulative delay maximum value Dmax by Dmax = (M / 2) * (M / 2) * ΔT. 12. Spread spectrum clock generator.   When the modulation step width ΔT corresponds to the delay value C * D0 by the C-stage basic delay cells connected in series, the cumulative delay maximum value calculation circuit calculates the maximum delay value Dmax as the basic delay value. 13. The spread spectrum according to claim 12, wherein a second multiple Q representing how many times the cell delay value D0 corresponds is calculated by Q = (M / 2) * (M / 2) * C. Clock generator.   The spread spectrum clock generator according to claim 14, wherein the clock decimation number calculation unit calculates the initial value U0 of the decimation number by rounding down a value after the decimal point of U0 = Q / P. The decimation timing signal generation circuit asserts the decimation timing signal after an input clock of a cycle in which the count value of the control counter is counted up from 0 to (M−1) is input to the delay line, When the pre-delay stage number TRIM in the current modulation period is less than or equal to the first multiple P, the input clock of the cycle in which the count value of the control counter is up-counted from (M−1) to (M−1) + U After the thinning, the thinning timing signal is negated,
The pre-delay stage number calculation circuit updates the pre-delay stage number TRIM to TRIM = TRIM + TRIM_BASE after the decimation timing signal is negated,
12. The control counter according to claim 11, wherein the control counter is initialized to 0 in synchronization with an input clock of a cycle next to a cycle in which the count value of the control counter is up-counted to (M−1) + U. Spread spectrum clock generator. The decimation timing signal generation circuit asserts the decimation timing signal after an input clock of a cycle in which the count value of the control counter is counted up from 0 to (M−1) is input to the delay line, When the pre-delay stage number TRIM in the current modulation period is larger than the first multiple P, the thinning-out number U is updated to U = U + 1, and the count value of the control counter is changed from (M−1) to (M−1) M-1) After the input clock of the cycle counted up to + U is thinned, the thinning timing signal is negated.
The pre-delay stage number calculation circuit updates the pre-delay stage number TRIM to TRIM = TRIM + TRIM_BASE-P after the decimation timing signal is negated,
12. The control counter according to claim 11, wherein the control counter is initialized to 0 in synchronization with an input clock of a cycle next to a cycle in which the count value of the control counter is up-counted to (M−1) + U. Spread spectrum clock generator.