JP2016119497A - Frequency synchronization device, radio base station, frequency synchronization program and frequency synchronization method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a novel frequency synchronization device that can establish frequency synchronization using an IP network.SOLUTION: A frequency synchronization device 10 for synchronizing a clock frequency between a master device 102 and a slave device 103 has a frequency offset calculator 12 for calculating a frequency offset O which is a deviation of the clock frequency of the slave device 103 from the clock frequency of the master device 102, and a synchronization calculator 14 for calculating an interval time T till execution of synchronization processing of synchronizing the clock frequency next time on the basis of a residual frequency offset Oremaining after the frequency offset O is multiplied by a convergence coefficient, and a minimum frequency unit adjustable in the slave device 103.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a frequency synchronization device, a frequency synchronization program, a frequency synchronization method, and a radio base station as a slave device that calculate an interval time of synchronization processing for synchronizing clock frequencies between a master device and a slave device. .

  2. Description of the Related Art Conventionally, broadcasting systems using unused channels in terrestrial digital broadcasting in VHF (Very-High Frequency) -low band and UHF band (Ultra-High Frequency), which are free radio bands of analog television, have been proposed. Such a broadcasting system is useful as a broadcasting system for disaster prevention and disaster, for example, and has already been verified in some areas.

  In such a broadcasting system, a wide area is covered by installing a plurality of radio base stations connected by an IP network and overlapping the cover areas. In this case, adopting a single frequency network (SFN) that uses the same frequency in a plurality of radio base stations is advantageous from the viewpoint of frequency utilization efficiency.

  SFN has been put into practical use in radio systems such as police radio. However, in a broadcasting system using OFDM (Orthogonal Frequency Division Multiplexing) modulation such as ISDB-T (Integrated Services Digital Broadcasting-Terrestrial), even if there is a slight shift in clock frequency, intersymbol interference occurs between subchannels. Therefore, precise frequency synchronization between radio base stations is required.

  As described above, in a broadcasting system in which a plurality of radio base stations connected by an IP network cover a wide band by SFN, one radio base station is used as a master device, and the other radio base station is used as a slave device. Synchronize the clock frequency of the station. As a method for establishing synchronization, there is a broadcast relay method, but this method requires a wraparound canceller, which increases costs. In addition, there is a system using GPS (Global Positioning System), but this system has a restriction that a radio base station must be installed in a place where GPS radio waves can be received.

  Therefore, it is desirable to realize synchronization between wireless base stations at low cost using an IP network. In synchronization establishment using an IP network, a synchronization packet is transmitted from the master device and received by the slave device, so that the slave device synchronizes the clock frequency with the master device.

  The establishment of such synchronization has a problem that the pull-in speed (the time required to establish synchronization) is slow. In particular, it takes time to establish synchronization when the apparatus is activated or when it recovers from a network disconnection. Therefore, when precise synchronization of the clock frequency is required as described above, it is necessary to shorten the time until synchronization is established by shortening the transmission interval of the synchronization packet and transmitting a large number of synchronization packets. There is. However, if a large number of synchronization packets are transmitted with the synchronization packet transmission interval shortened, the network bandwidth is compressed.

  A technique for precisely synchronizing the clock frequency by suppressing the number of synchronization packets has been proposed (for example, Patent Document 1). In this technique, the slave device regenerates the transmission source clock from the packet received from the master device, and after adjusting the time once, advances the time with the regenerated clock. As a result, the time is less likely to be shifted after the time is set, so the number of synchronization packets can be reduced. The clock frequency can also be synchronized by regenerating the transmission source clock.

International Publication No. 2012/118177

  However, in the technique of Patent Document 1, all the relay devices on the route must support clock synchronization, and therefore, existing relay devices cannot be used. Also, the slave device needs to have a configuration for clock recovery because of its hardware configuration, which increases the cost.

  The present invention has been made in view of the above problems, and an object thereof is to provide a novel frequency synchronization apparatus that realizes establishment of frequency synchronization using an IP network.

  The frequency synchronization device of the present invention is a frequency synchronization device that synchronizes a clock frequency between a master device and a slave device, and calculates a frequency offset that is a deviation of the clock frequency of the slave device with respect to the clock frequency of the master device. Synchronization for synchronizing the clock frequency next, based on a frequency offset calculation unit that performs, a residual frequency offset remaining after multiplying the frequency offset by a convergence coefficient, and a minimum frequency unit that can be adjusted in the slave device And a synchronization timing calculation unit that calculates an interval time until processing is performed.

  The radio base station of the present invention is a radio base station as a slave device that performs broadcasting by SFN together with the master device by being connected to a radio base station as a master device via an IP network, and the master device A frequency offset calculation unit that calculates a frequency offset with respect to the clock frequency of the radio base station, a conversion unit that converts a control voltage value based on the frequency offset into a control voltage and outputs the control voltage, and the slave device based on the control voltage Based on a frequency adjusting unit that adjusts the clock frequency of the radio base station, a residual frequency offset that remains after multiplying the frequency offset by a convergence coefficient, and a minimum frequency unit that can be adjusted in the slave device, Until the synchronization process is performed to synchronize the clock frequency. A synchronization timing calculation unit that calculates a interval time, has a configuration in which a communication unit that notifies the interval time to the radio base station as the master device.

  The frequency synchronization program according to the present invention provides a computer of a frequency synchronization device that calculates the timing of synchronization processing for synchronizing a clock frequency between a master device and a slave device, the clock of the slave device relative to the clock frequency of the master device. Based on a frequency offset calculation unit that calculates a frequency offset that is a frequency shift, a residual frequency offset that remains after multiplying the frequency offset by a convergence coefficient, and a minimum frequency unit that can be adjusted in the slave device, It functions as a synchronization timing calculation unit that calculates an interval time until the synchronization process for synchronizing the clock frequency is performed.

  The frequency synchronization method of the present invention is a frequency synchronization method for calculating a timing of a synchronization process for synchronizing a clock frequency between a master device and a slave device, the clock of the slave device with respect to the clock frequency of the master device. Based on a frequency offset calculating step for calculating a frequency offset that is a frequency shift, a residual frequency offset remaining after multiplying the frequency offset by a convergence coefficient, and a minimum frequency unit that can be adjusted in the slave device, A synchronization timing calculation step of calculating an interval time until synchronization processing for synchronizing the clock frequency is performed.

  According to the present invention, since the interval time of the synchronization processing is calculated based on the minimum frequency unit that can be adjusted in the slave device, wasteful synchronization processing is performed when the clock frequency cannot be adjusted in the slave device. Thus, it is possible to reduce the load on the network bandwidth, and it is also possible to prevent the pull-in speed from becoming slow due to the interval time of the synchronization process becoming too long.

The block diagram which shows the structure of the frequency synchronizer in the 1st Embodiment of this invention The block diagram of the broadcasting system in the 1st Embodiment of this invention The block diagram which shows the structure for adjusting a clock frequency in the slave apparatus in the 1st Embodiment of this invention The figure explaining the tuning process between the master apparatus and slave apparatus in the 1st Embodiment of this invention The figure explaining the tuning process between the master apparatus and slave apparatus in the 1st Embodiment of this invention Flow chart of operation of tuning process by master device and slave device in the first embodiment of the present invention The block diagram which shows the structure of the frequency synchronization apparatus in the 2nd Embodiment of this invention. The figure explaining the tuning process between the master apparatus and slave apparatus in the 2nd Embodiment of this invention Flow chart of operation of tuning process by master device and slave device in the second embodiment of the present invention

  Hereinafter, a frequency synchronization apparatus according to an embodiment of the present invention will be described. The embodiment described below shows an example when the present invention is implemented, and the present invention is not limited to the specific configuration described below. In carrying out the present invention, a specific configuration according to the embodiment may be adopted as appropriate.

  The frequency synchronization device according to the embodiment is a frequency synchronization device that synchronizes the clock frequency between the master device and the slave device, and calculates a frequency offset that is a deviation of the clock frequency of the slave device from the clock frequency of the master device. Next, based on the frequency offset calculation unit, the remaining frequency offset remaining after the frequency offset is multiplied by the convergence coefficient, and the minimum frequency unit that can be adjusted in the slave device, a synchronization process for synchronizing the clock frequency is performed. And a synchronization timing calculation unit for calculating the interval time until.

  With this configuration, since the interval time of the synchronization process is calculated based on the minimum frequency unit that can be adjusted in the slave device, it is possible to avoid performing unnecessary synchronization processing when the clock frequency cannot be adjusted in the slave device. Thus, it is possible to reduce the load on the network bandwidth, and it is also possible to prevent the pull-in speed from becoming slow because the interval time of the synchronization processing becomes too long.

  The slave device may include a conversion unit that converts the control voltage value based on the frequency offset into a control voltage and outputs the control voltage, and a frequency adjustment unit that adjusts the clock frequency of the slave device based on the control voltage. The minimum frequency unit may be the resolution of conversion in the conversion unit.

  With this configuration, the interval time can be calculated according to the resolution of the conversion unit of the slave device.

  The slave device may include a conversion unit that converts the control voltage value based on the frequency offset into a control voltage and outputs the control voltage, and a frequency adjustment unit that adjusts the clock frequency of the slave device based on the control voltage. The minimum frequency unit may be a minimum frequency unit that can be adjusted by the frequency adjustment unit.

  Also with this configuration, the interval time can be calculated according to the minimum frequency unit that can be adjusted by the frequency adjusting unit.

  The synchronization timing calculation unit may calculate the interval time until the remaining frequency offset accumulates and becomes the minimum frequency unit that can be adjusted, as the interval time.

  With this configuration, the shortest interval in which the clock frequency can be adjusted in the slave device can be calculated.

  The frequency synchronization device may further include a correction time adjustment unit that adjusts a correction time for correcting the interval time, and the frequency offset calculation unit sequentially calculates a plurality of frequency offsets for each interval time. The correction time adjustment unit may adjust the correction time based on which of the plurality of sequentially calculated frequency offsets is the smallest frequency unit that can be adjusted in the slave device. The interval time may be corrected using the correction time.

  With this configuration, it is possible to calculate an interval time by correcting an error based on an individual difference in the configuration for adjusting the clock frequency in the slave device and an error due to fluctuations in network delay.

  The correction time adjustment unit may adjust the correction time so as to shorten the interval time when the first frequency offset of the plurality of frequency offsets is equal to or greater than the minimum frequency unit that can be adjusted in the slave device. .

  With this configuration, if the interval time is too long, it can be adjusted to shorten it.

  The correction time adjustment unit sets the correction time to (N−) when the frequency unit after the Nth (N is a natural number of 2 or more) frequency offsets of a plurality of frequency offsets becomes the minimum frequency unit that can be adjusted in the slave device. 1) x The correction time may be adjusted so as to be shortened by a predetermined time.

  With this configuration, when the interval time is short, it can be corrected to increase it.

  The correction time adjustment unit may continuously execute the frequency offset calculation in the slave device when the minimum frequency unit that can be adjusted in the slave device is not obtained for the plurality of frequency offsets.

  With this configuration, when the interval time is short, it can be corrected to increase it.

  The radio base station according to the embodiment is a radio base station as a slave device that performs broadcasting by SFN together with a radio base station as a master device by being connected to a radio base station as a master device via an IP network. A frequency offset calculation unit that calculates a frequency offset with respect to the clock frequency of the radio base station as a master device, a conversion unit that converts a control voltage value based on the frequency offset into a control voltage, and a slave based on the control voltage Based on the frequency adjustment unit that adjusts the clock frequency of the radio base station as a device, the residual frequency offset that remains after multiplying the frequency offset by the convergence coefficient, and the minimum frequency unit that can be adjusted in the slave device, The interface until synchronization is performed to synchronize the clock frequency. It has a synchronization timing calculation unit that calculates a Le time, a configuration in which a communication unit that notifies the interval time to the radio base station as the master device.

  Even with this configuration, since the interval time of the synchronization process is calculated based on the minimum frequency unit that can be adjusted in the radio base station as the slave device, the clock frequency cannot be adjusted in the radio base station as the slave device. It is possible to avoid the unnecessary synchronization processing from being performed, thereby reducing the load applied to the network bandwidth, and it is also possible to prevent the pull-in speed from being slowed because the interval time of the synchronization processing becomes too long.

  The frequency synchronization program according to the embodiment is configured to calculate a computer of a frequency synchronization device that calculates a timing of synchronization processing for synchronizing a clock frequency between a master device and a slave device, and a clock of the slave device with respect to the clock frequency of the master device. Next, a frequency offset calculation unit that calculates a frequency offset that is a frequency shift, and a remaining frequency offset remaining after multiplying the frequency offset by a convergence coefficient and a minimum frequency unit that can be adjusted in the slave device are clocked next. It is made to function as a synchronization timing calculation part which calculates the interval time until the synchronous process for synchronizing a frequency is performed.

  Even with this configuration, since the interval time of the synchronization processing is calculated based on the minimum frequency unit that can be adjusted in the slave device, it is possible to perform useless synchronization processing when the clock frequency cannot be adjusted in the slave device. Therefore, it is possible to reduce the load on the network bandwidth, and it is also possible to prevent the pull-in speed from becoming slow because the interval time of the synchronization processing becomes too long.

  The frequency synchronization method of the embodiment is a frequency synchronization method for calculating the timing of synchronization processing for synchronizing the clock frequency between the master device and the slave device, and the clock frequency of the slave device with respect to the clock frequency of the master device Next, the clock frequency is calculated based on the frequency offset calculating step for calculating the frequency offset, which is a deviation, the remaining frequency offset remaining after the frequency offset is multiplied by the convergence coefficient, and the minimum frequency unit that can be adjusted in the slave device. A synchronization timing calculation step of calculating an interval time until the synchronization processing for synchronizing is performed.

  Even with this configuration, since the interval time of the synchronization processing is calculated based on the minimum frequency unit that can be adjusted in the slave device, it is possible to perform useless synchronization processing when the clock frequency cannot be adjusted in the slave device. Therefore, it is possible to reduce the load on the network bandwidth, and it is also possible to prevent the pull-in speed from becoming slow because the interval time of the synchronization processing becomes too long.

  Embodiments of the present invention will be described below with reference to the drawings.

(First embodiment)
FIG. 2 is a configuration diagram of the broadcasting system according to the first embodiment of the present invention. In the broadcasting system 100, a plurality of radio base stations 102, 103, and 103 are connected to each other via an IP network 101 so as to communicate with each other. In the example of FIG. 2, only three radio base stations are shown, but the broadcasting system 100 may include more radio base stations. Broadcast signals (content signals, control signals, etc.) are transmitted to the respective radio base stations 102, 103, 103 via the IP network 101. Each of the wireless base stations 102, 103, and 103 wirelessly transmits a broadcast signal as a transmission device. A broadcast receiving terminal (not shown) receives broadcast signals from nearby radio base stations and reproduces broadcast content.

  Each radio base station 102, 103, 103 has a cover area that overlaps each other. In addition, each of the radio base stations 102, 103, 103 performs broadcasting by SFN using the same frequency f1. Among the plurality of radio base stations 102, 103, 103, one radio base station 102 becomes a master device in establishing synchronization, and the other radio base station 103 becomes a slave device in establishing synchronization. Each slave device 103 synchronizes (tunes) with the master device 102, thereby realizing synchronization of the entire broadcasting system 100.

  FIG. 3 is a block diagram showing a configuration for adjusting the frequency of the operation clock (hereinafter referred to as “clock frequency”) in the slave device 103. The slave device 103 includes a CPU (Central Processing Unit) 31, a DAC (Digital-to-Analog Converter) 32, and a VCXO (Voltage-Controlled Crystal Oscillator) 33 as a configuration for adjusting the clock frequency. It has.

  In order to synchronize the clock frequency, the CPU 31 calculates a shift in the clock frequency based on the synchronization packet, calculates a control voltage value for adjusting the clock frequency, and outputs the control voltage value to the DAC 32. The DAC 32 converts the control voltage value into a control voltage and outputs it to the VCXO 33. The VCXO 33 supplies the CPU 31 with an operation clock adjusted according to the control voltage. The DAC 32 corresponds to a conversion unit, and the VCXO 33 corresponds to a frequency adjustment unit.

  FIG. 1 is a block diagram showing the configuration of the frequency synchronization apparatus according to the first embodiment of the present invention. The frequency synchronization apparatus 10 is provided in the slave apparatus 103 and establishes synchronization with the master apparatus 102 connected via the IP network 101 while controlling the transmission interval of the synchronization packet. The frequency synchronization apparatus 10 includes a synchronization processing execution unit 11, a frequency offset calculation unit 12, a frequency correction unit 13, and a synchronization timing calculation unit 14. The frequency synchronization apparatus 10 may be realized by the CPU 31 executing a program.

Before explaining the process (tuning process) for establishing frequency synchronization by the frequency synchronizer 10, a general tuning process will be explained. FIG. 4 is a diagram illustrating a tuning process between the master device 102 and the slave device 103. First, the master device 102 transmits a synchronization message to the slave device 103 (S41). Subsequently, the master device 102 transmits the synchronization message transmission time t _m ⁽¹⁾ measured with the clock of the master device 102 as a follow-up message (S42). These synchronization messages and follow-up messages are called “synchronization packets”.

The slave device 103 receives the synchronization message, and records the synchronization message reception time t _s ⁽¹⁾ measured with the clock of the slave device 103. Further, the slave device 103 receives the follow-up message, thereby knowing and recording the synchronization message transmission time t _m ⁽¹⁾ in the master device 102.

At the next synchronization timing, the master device 102 and the slave device 103 perform the same processing as described above. That is, the master device 102 transmits a synchronization message (S43), and notifies the slave device 103 of the synchronization message transmission time t _m ⁽²⁾ (S44). The slave device 103 records the time t _s ^{(2) at} which the synchronization message is received, and also records the synchronization message transmission time t ₁ ′ notified from the master device 102.

The slave device 103 uses the recorded synchronization message transmission times t _m ⁽¹⁾ and t _m ⁽²⁾ and the synchronization message reception times t _s ⁽¹⁾ and t _s ⁽²⁾ to generate t _m ⁽²⁾ − The clock frequency is adjusted so that t _m ⁽¹⁾ = t _s ⁽²⁾ −t _s ⁽¹⁾ . The frequency synchronization apparatus 10 of the present embodiment synchronizes the clock frequency of the slave apparatus 103 with the clock frequency of the master apparatus 102 using the principle of establishment of frequency synchronization as described above while controlling the synchronization timing. Hereinafter, with reference to FIG.1 and FIG.5, operation | movement of each structure of the frequency synchronizer 10 of this Embodiment is demonstrated.

The synchronization processing execution unit 11 executes processing for establishing frequency synchronization with the master device 102. As shown in FIG. 5, the synchronization processing execution unit 11 performs a plurality of synchronization processes, that is, transmission of a synchronization message and a follow-up message in each synchronization period. In FIG. 5, one arrow represents one synchronization message transmission and the corresponding follow-up message transmission. In the example of FIG. 5, in each synchronization period S _n, transmission and reception s ₁ of four sync messages and follow-up message ⁽ⁿ⁾ ~s ₄ ⁽ⁿ⁾ is performed.

The frequency offset calculation unit 12 performs the synchronization message transmission time t _mk ^{(n) of} each time, the synchronization message transmission time t _mk ⁽ⁿ⁻¹⁾ and the synchronization message reception time t _sk ^{(n) of} the previous synchronization period, and Based on the synchronization message reception time t _sk ⁽ⁿ⁻¹⁾ in the corresponding previous synchronization period, the frequency offset (clock frequency deviation) O _k ⁽ⁿ⁾ is calculated. Here, k is the number of synchronization processes in each synchronization period, and k = 1, 2, 3, 4 in the example of FIG. Specifically, the frequency offset _Ok is calculated using the following equation (1).
^{_{O k = (t mk (n}} ) -t mk (n-1)) - (t sk (n) -t sk (n-1)) ··· (1)
The frequency offset calculation unit 12 calculates the average frequency offset O _avg ⁽ⁿ⁾ by taking the average of the frequency offsets O _k ⁽ⁿ⁾ and outputs the average frequency offset O _avg ⁽ⁿ⁾ to the frequency correction unit 13.

The frequency correction unit 13 calculates and outputs a control voltage value for correcting the clock frequency based on the average frequency offset O _avg ⁽ⁿ⁾ . This control voltage value corresponds to the control voltage value output from the CPU 31 described with reference to FIG. The frequency correction unit 13 calculates a control voltage value that reduces the average frequency offset O _avg ⁽ⁿ⁾ . Specifically, the frequency correction unit 13 does not calculate a control voltage value that completely sets the average frequency offset O _avg ⁽ⁿ⁾ to zero, but converges to the average frequency offset O _avg ⁽ⁿ⁾ so as not to oscillate. A control voltage value is calculated by multiplying by a coefficient α (0 <α <1). In this embodiment, α = 0.9.

The synchronization timing calculation unit 14 calculates an interval time T ⁽ⁿ⁾ until the next synchronization period S _{n + 1} . Specifically, the synchronization timing calculation unit 14 accumulates the residual frequency offset O _res ^{(n) obtained} by multiplying the average frequency offset O _avg ⁽ⁿ⁾ by (1−α) to obtain the resolution of the DAC 32 (see FIG. 3). The time to reach is calculated as an interval time T ⁽ⁿ⁾ until the next synchronization period. The reason for calculating the interval time T ⁽ⁿ⁾ in this way will be described.

As described above, the control voltage value is calculated by multiplying the average frequency offset O _avg ⁽ⁿ⁾ by the convergence coefficient α. Therefore, even if the operation clock is adjusted according to this control voltage value, the average frequency offset O _avg A clock frequency shift corresponding to ⁽ⁿ⁾ × (1−α) remains (residual frequency offset O _res ⁽ⁿ⁾ ). However, if the average frequency offset is calculated by performing the synchronization process in the next synchronization period, it becomes as large as the residual frequency offset. Therefore, even if a control voltage value corresponding to such an average frequency offset is given to the DAC 32, it is a minimum frequency unit that can be adjusted when adjusting the clock frequency of the DAC 32, that is, a value smaller than the resolution of the DAC 32. In some cases, the DAC 32 cannot output a significant control voltage that can adjust the operation clock of the VCXO 33. As a result, the VCXO 33 cannot adjust the clock.

That is, even if the processing of the next synchronization period is performed before the time (hereinafter also referred to as “significant time difference” ^{) in} which the residual frequency offset O _res ⁽ⁿ⁾ accumulates and reaches the resolution of the DAC 32 elapses, Therefore, the operation clock for frequency synchronization is not adjusted, and a synchronization packet transmitted and received during such a synchronization period is wasted. Therefore, the synchronization timing calculation unit 14 calculates the interval time T until the next synchronization period as described above as a significant time difference in order to avoid such unnecessary transmission / reception of synchronization packets.

The calculated interval time T ⁽ⁿ⁾ is transmitted as a predicted time response from the synchronization processing execution unit 11 to the master device 102, and the master device 102 receives the next synchronization period S _{n +} after the interval time T ⁽ⁿ⁾ has elapsed. Start synchronization process ₁ (send synchronization message). That is, the synchronization processing execution unit 11 corresponds to a communication unit that notifies the master device 102 of the interval time T ⁽ⁿ⁾ .

  FIG. 6 is a flowchart of the tuning process performed by the master device 102 and the slave device 103. First, the master device 102 and the slave device 103 perform transmission / reception of a synchronization message and a follow-up message a plurality of times (step S61). The frequency offset calculation unit 12 calculates the average frequency offset based on the transmission time and reception time of the plurality of synchronization messages and the previous transmission time and reception time of the plurality of corresponding synchronization messages (step S62).

Next, the slave device 103 adjusts the clock frequency based on the average frequency offset O _avg ⁽ⁿ⁾ (step S63). Specifically, the frequency correction unit 13 calculates a control voltage value based on the average frequency offset O _avg ⁽ⁿ⁾ , the DAC 32 converts this into a control voltage and outputs it to the VCXO 33, and the VCXO 33 operates according to the control voltage. The clock is adjusted and output to the CPU 31.

The synchronization timing calculation unit 14 calculates a time T ⁽ⁿ⁾ until the next synchronization period based on the resolution of the DAC 32 and the remaining frequency offset O _res ⁽ⁿ⁾ (step S64), and the synchronization processing execution unit 11 determines this interval. The master device 102 is notified of the time T ⁽ⁿ⁾ as a predicted time response. The master device 102 waits for the this interval time T ⁽ⁿ⁾ has elapsed (step S65), the interval time when T ⁽ⁿ⁾ has passed (YES at step S65), returns to step S61, the next synchronization The process for the period S _{n + 1} is started.

  As described above, according to the frequency synchronization apparatus 10 of the present embodiment, since the frequency offset is less than the resolution of the DAC 32, transmission / reception of the synchronization packet at a timing at which the operation clock cannot be adjusted is avoided. The load on the band is reduced. Further, since the synchronization process is started at a timing at which the frequency offset becomes equal to or higher than the resolution of the DAC 32 and the operation clock can be adjusted, it is possible to avoid the interval of the synchronization period from becoming too long. That is, according to the frequency synchronization apparatus 10 of the present embodiment, the pull-in speed can be increased while reducing the load on the network band.

In the frequency synchronization apparatus 10 described above, the synchronization message is transmitted a plurality of times in each synchronization period, and the average frequency offset O _avg is obtained as the frequency offset. However, as described with reference to FIG. The synchronization message may be transmitted only once in the period.

  Further, the frequency synchronization apparatus 10 is described as being provided in the slave apparatus 103 and realized by the CPU 31 executing a program. However, the frequency synchronization apparatus 10 is configured as a separate apparatus from the slave apparatus 103. May be.

  Further, in the frequency synchronization device 10 described above, the synchronization timing calculation unit 14 pays attention to a significant time difference corresponding to the resolution of the DAC 32 as a minimum adjustable frequency unit when adjusting the clock frequency, and the resolution of the DAC 32 Based on the above, the interval time T until the start of the next synchronization period is calculated. In addition, in consideration of the minimum frequency unit that can be adjusted when the clock frequency is adjusted by the VCXO 33, either the DAC 32 or the VCXO 33 is used. Alternatively, the time difference that is significant may be used as the interval time T until the start of the synchronization process in the next synchronization period.

  Further, when the minimum adjustable frequency unit in the VCXO 33 is larger than the resolution of the DAC 32, the interval time T may be determined in consideration of only the minimum adjustable frequency unit of the VCXO 33. That is, the synchronization timing calculation unit 14 sets the time until the minimum frequency unit that can be adjusted in the entire slave device 103 including the DAC 32 and the VCXO 33 as a significant time difference, and the interval until the start of the synchronization process in the next synchronization period. The time T may be calculated.

(Second Embodiment)
Next, the frequency synchronization apparatus 10 ′ of the second embodiment will be described. The frequency synchronization apparatus 10 ′ of the present embodiment is an improvement of the frequency synchronization apparatus 10 of the first embodiment. In the first embodiment, a significant time difference is predicted and set as an interval time T, and the processing of the next synchronization period is started after the interval time T has elapsed. There is a possibility that a frequency offset greater than a significant time difference has not occurred, and conversely, there is a possibility that a significant time difference has already passed. This is due to the following reason.

  First, the output voltage of the DAC 32 for controlling the VCXO 33 varies due to individual differences of the DAC 32. Further, the output frequency with respect to the control voltage of the VCXO 33 also varies due to individual differences of the VCXO 33. Further, the IP network 101 also has a network delay fluctuation. For these reasons, it is conceivable that the interval time T calculated by the first embodiment is not necessarily the minimum synchronization interval for significant frequency synchronization. Therefore, in the frequency synchronization apparatus 10 ′ of the present embodiment, control for improving the accuracy of frequency synchronization is performed by correcting the error of the interval time T.

  FIG. 7 is a block diagram illustrating a configuration of a frequency synchronization apparatus 10 ′ according to the second embodiment. In the frequency synchronization apparatus 10 ′ of FIG. 7, the same components as those of the frequency synchronization apparatus 10 of the first embodiment are denoted by the same reference numerals, and the description thereof is omitted as appropriate. The frequency synchronization apparatus 10 ′ includes a correction time adjustment unit 15 in addition to the synchronization processing execution unit 11, the frequency offset calculation unit 12, the frequency correction unit 13, and the synchronization timing calculation unit 14. Hereinafter, the operation of the frequency synchronization apparatus 10 ′ of the present embodiment will be described with reference to FIGS.

The synchronization timing calculation unit 14 obtains the interval time T ^(n-1) as in the first embodiment. The correction time adjustment unit 15 gives the correction time Δt ⁽ⁿ⁻¹⁾ to the synchronization timing calculation unit 14. The correction time adjustment unit 15 first provides the specified value to the synchronization timing calculation unit 14 as the correction time Δt ⁽¹⁾ . The synchronization timing calculation unit 14 uses the correction time Δt ⁽ⁿ⁻¹⁾ obtained from the correction time adjustment unit 15 to calculate the correction interval time T ⁽ⁿ⁻¹⁾ −Δt ⁽ⁿ⁻¹⁾ as the next synchronization period S _n. Is output to the synchronization processing execution unit 11, and the synchronization processing execution unit 11 transmits the correction interval time T ⁽ⁿ⁻¹⁾ −Δt ⁽ⁿ⁻¹⁾ to the master device 102 as a predicted time response.

The master device 102, the correction interval time T ^(n-1) when -Δt ^(n-1) has elapsed to begin the synchronization process of the next synchronization period S _n. In the present embodiment, as in the first embodiment, a plurality of synchronization messages s _k ⁽ⁿ⁾ are transmitted in one synchronization period to calculate a plurality of frequency offsets O _k ⁽ⁿ⁾ . . That is, the frequency offset calculation unit 12 calculates a frequency offset every time a synchronization message is received. The correction time adjustment unit 15 determines whether or not a significant time difference occurs every time the frequency offset calculation unit 14 calculates the frequency offset O _k ⁽ⁿ⁾ .

When a significant time difference has already occurred in the first frequency offset O ₁ ⁽ⁿ⁾ , the correction time adjustment unit 15 increases the correction time Δt ⁽ⁿ⁻¹⁾ by a predetermined step width and performs the next correction. It is assumed that time Δt ⁽ⁿ⁾ . When there is a significant time difference in the middle of the plurality of frequency offsets O _k ⁽ⁿ⁾ sequentially calculated by the frequency offset calculation unit 14, the correction time adjustment unit 15 does not have such a significant time difference. The correction time Δt ⁽ⁿ⁻¹⁾ is shortened to the next correction time Δt ⁽ⁿ⁾ according to the time required (the number of received synchronization messages ⁾ .

Specifically, when there is a significant time difference in the frequency offset O _k ⁽ⁿ⁾ (k ≧ 2) calculated based on the second and subsequent synchronization messages, the correction time adjustment unit 15 The correction time Δt ^{(n−1 )} with a predetermined step width so that the correction time Δt ⁽ⁿ⁾ becomes a negative value according to the time ⁽ number of received synchronization messages) required until such a significant time difference occurs. ⁾ Is reduced (the time until the next synchronization period _{Sn + 1} is started is increased).

  In addition, the correction time adjustment unit 15 does not generate a significant time difference in the frequency offset calculated by the frequency offset calculation unit 14 even when the synchronization message is received a predetermined number of times (four times in the example of FIG. 8). The synchronization processing execution unit 11 is instructed to transmit a message requesting to continuously transmit a synchronization message to the master device 102, and the synchronization processing execution unit 11 transmits a request to the master device 102 according to this instruction. To do.

In this way, when the transmission of the synchronization message is continued and a significant time difference occurs in the frequency offset, the correction time adjustment unit 15 determines the time required until such a frequency offset is obtained (the received synchronization message The correction time Δt ⁽ⁿ⁻¹⁾ is reduced in accordance with the number of corrections Δt ⁽ⁿ⁾ .

The correction time adjustment unit 15 does not output Δt ⁽ⁿ⁾ to the synchronization timing calculation unit 14 when there is no significant time difference in the frequency offset calculated by receiving the synchronization message a predetermined number of times. Therefore, the synchronization timing calculation unit 14 also does not output the correction interval time T ⁽ⁿ⁾ −Δt ⁽ⁿ⁾ as the predicted time response to the synchronization process execution unit 11, and the synchronization process execution unit 11 sends the predicted time response to the master device 102. Do not send to. Therefore, instead of transmitting the request for transmitting the synchronization message from the slave device 103 to the master device 102 as described above, the master device 102 continuously transmits the synchronization message until receiving the response of the predicted time from the slave device 103. It may be.

Further, the correction time Δt ⁽ⁿ⁾ may be gradually changed by taking a moving average or the like. For example, to start the synchronization period S _n-2 obtained in synchronization period S _n-1 to start correction time to Δt ^(n-2), the synchronization period S _n obtained in synchronization period S _n-1 taking the correction time for Δt ^(n-1), the average of the correction time Delta] t for starting the synchronization period S _{n + 1} obtained by the synchronization period S ^{_{n (n),}} the synchronization period S _{n + 1} The correction time Δt ⁽ⁿ⁾ subtracted from the interval time T ⁽ⁿ⁾ for starting the process may be obtained.

FIG. 9 is a flowchart of the operation of the tuning process performed by the master device 102 and the slave device 103. First, the master device 102 and the slave device 103 transmit / receive a synchronization message and a follow-up message (step S91). Frequency offset calculator 12 calculates the frequency offset O _k based on the transmission time and reception time of transmission time and reception time and the previous corresponding synchronization message the synchronization message, the frequency offset O _k becomes significant time difference Is determined (step S92). Until the frequency offset _Ok becomes a significant time difference (NO in step S92), the process returns to step S91 to repeat reception of the synchronization message and the follow-up message.

When the frequency offset O _k is a significant time difference (YES at step S92), the slave device 103, based on the frequency offset O _k at that time, to adjust the frequency of the operation clock (step S93). Then, the correction time adjustment unit 15 increases or decreases the correction time Δt ⁽ⁿ⁻¹⁾ based on the time taken for the frequency offset to become a significant time difference (the number of received synchronization messages), thereby adjusting the correction time. It is updated to the correction time Δt ⁽ⁿ⁾ (step S94).

Based on the remaining frequency offset O _res ⁽ⁿ⁻¹⁾ , the synchronization timing calculation unit 14 calculates an interval time T ⁽ⁿ⁾ until the next synchronization period in the same manner as in step S64 of the first embodiment. Further, a correction interval time T ⁽ⁿ⁾ −Δt ⁽ⁿ⁾ is calculated using the correction time Δt ⁽ⁿ⁾ (step S95). The synchronization processing execution unit 11 notifies the master device 102 of this correction interval time T ⁽ⁿ⁾ −Δt ⁽ⁿ⁾ as a predicted time response. The master device 102, in waiting for the correction interval time T ⁽ⁿ⁾ -Δt ⁽ⁿ⁾ has elapsed (step S96), the correction interval time T ⁽ⁿ⁾ -Δt ⁽ⁿ⁾ has elapsed (step S96 YES), returning to step S91, the processing of the next synchronization period S _{n + 1} is started.

  Thus, according to the frequency synchronization apparatus 10 ′ of the present embodiment, similarly to the frequency agreement apparatus 10 of the first embodiment, the load on the network band can be determined by appropriately determining the timing of frequency synchronization. The pull-in speed can be increased while reducing the error, and further, the frequency synchronization timing can be determined more accurately by correcting the error due to individual differences of the DAC 32 and the VCXO 33 and the error of the interval time T due to the fluctuation of the network delay. it can.

  As described above, according to the present invention, since the interval time of the synchronization process is calculated based on the minimum frequency unit that can be adjusted in the slave device, useless synchronization when the clock frequency cannot be adjusted in the slave device. It is possible to avoid the processing being performed, thereby reducing the load on the network bandwidth, and also having the effect that the synchronization processing interval time becomes too long and the pulling-in speed can be avoided, This is useful as a frequency synchronization device for calculating the interval time of synchronization processing for synchronizing the clock frequency with the slave device.

DESCRIPTION OF SYMBOLS 10 Frequency synchronization apparatus 11 Synchronization process execution part 12 Frequency offset calculation part 13 Frequency correction part 14 Synchronization timing calculation part 15 Correction time adjustment part 100 Broadcast system 101 IP network 102 Wireless base station (master apparatus)
103 wireless base station (slave device)
31 CPU
32 DAC
33 VCXO

Claims (11)

A frequency synchronization device that synchronizes a clock frequency between a master device and a slave device,
A frequency offset calculating unit that calculates a frequency offset that is a deviation of the clock frequency of the slave device with respect to the clock frequency of the master device;
Interval time until the next synchronization processing for synchronizing the clock frequency based on the residual frequency offset remaining after multiplying the frequency offset by the convergence coefficient and the minimum frequency unit that can be adjusted in the slave device A synchronization timing calculation unit for calculating
A frequency synchronization device comprising: The slave device includes a conversion unit that converts a control voltage value based on the frequency offset into a control voltage and outputs the control voltage, and a frequency adjustment unit that adjusts a clock frequency of the slave device based on the control voltage,
The frequency synchronization apparatus according to claim 1, wherein the minimum frequency unit that can be adjusted is a resolution of conversion in the conversion unit. The slave device includes a conversion unit that converts a control voltage value based on the frequency offset into a control voltage and outputs the control voltage, and a frequency adjustment unit that adjusts a clock frequency of the slave device based on the control voltage,
The frequency synchronization apparatus according to claim 1, wherein the minimum frequency unit that can be adjusted is a minimum frequency unit that can be adjusted by the frequency adjustment unit.   4. The synchronization timing calculating unit according to claim 1, wherein the time until the remaining frequency offset accumulates and becomes the minimum frequency unit that can be adjusted is calculated as the interval time. The frequency synchronizer of description. A correction time adjustment unit for adjusting a correction time for correcting the interval time;
The frequency offset calculation unit sequentially calculates a plurality of frequency offsets for each interval time,
The correction time adjustment unit adjusts the correction time based on which of the plurality of frequency offsets sequentially calculated has become the minimum frequency unit that can be adjusted in the slave device,
The frequency synchronization apparatus according to claim 1, wherein the synchronization timing calculation unit corrects the interval time using the correction time.   When the first frequency offset of the plurality of frequency offsets is equal to or greater than a minimum frequency unit that can be adjusted in the slave device, the correction time adjustment unit adjusts the correction time so that the interval time is shortened. The frequency synchronization device according to claim 5, wherein the frequency synchronization device is adjusted.   The correction time adjustment unit is configured to perform the correction time when the frequency unit is the smallest frequency unit that can be adjusted in the slave device in the N (N is a natural number of 2 or more) frequency offsets of the plurality of frequency offsets. The frequency synchronization apparatus according to claim 5, wherein the correction time is adjusted such that (N−1) × predetermined time is shortened.   The correction time adjustment unit continuously executes frequency offset calculation in the slave device when the plurality of frequency offsets are not the minimum frequency unit that can be adjusted in the slave device. The frequency synchronizer according to claim 5. A wireless base station as a slave device that performs broadcasting by SFN together with a wireless base station as a master device by being connected to a wireless base station as a master device via an IP network,
A frequency offset calculating unit that calculates a frequency offset with respect to the clock frequency of the radio base station as the master device;
A converter that converts the control voltage value based on the frequency offset into a control voltage and outputs the control voltage;
A frequency adjusting unit that adjusts the clock frequency of the radio base station as the slave device based on the control voltage;
Interval time until the next synchronization processing for synchronizing the clock frequency based on the residual frequency offset remaining after multiplying the frequency offset by the convergence coefficient and the minimum frequency unit that can be adjusted in the slave device A synchronization timing calculation unit for calculating
A communication unit that notifies the radio base station as the master device of the interval time;
A radio base station as a slave device comprising: A computer of the frequency synchronization device that calculates the timing of the synchronization processing for synchronizing the clock frequency between the master device and the slave device,
A frequency offset calculation unit that calculates a frequency offset that is a shift of the clock frequency of the slave device with respect to a clock frequency of the master device, and a residual frequency offset that remains after the frequency offset is multiplied by a convergence coefficient, and is adjusted in the slave device A synchronization timing calculation unit for calculating an interval time until the next synchronization processing for synchronizing the clock frequency based on the smallest possible frequency unit;
Frequency synchronization program to function as. A frequency synchronization method for calculating a timing of a synchronization process for synchronizing a clock frequency between a master device and a slave device,
A frequency offset calculating step of calculating a frequency offset which is a deviation of the clock frequency of the slave device with respect to the clock frequency of the master device;
Interval time until the next synchronization processing for synchronizing the clock frequency based on the residual frequency offset remaining after multiplying the frequency offset by the convergence coefficient and the minimum frequency unit that can be adjusted in the slave device A synchronization timing calculating step for calculating
A frequency synchronization method comprising:

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