JP2016116319A - Insulation type dc power supply unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a component from being damaged by sampling a voltage as output voltage control information in optimum timing.SOLUTION: In an insulation type DC power supply unit comprising a primary-side control circuit which outputs a driving pulse for ON/OFF control over a switching element connected to primary winding of a transformer, the primary-side control circuit is provided with a sample holding circuit receiving a voltage induced across the auxiliary winding or a voltage at a terminal applied with a voltage proportional to the voltage in predetermined timing, a detection circuit giving a timing of turning OFF the switching element based upon the voltage received by the sample holding circuit and a voltage proportional to a current flowing to the primary winding, and a timer circuit which imparts the timing of turning ON the switching element. The sample holding circuit is configured to perform sampling at or before the timing when a current of secondary winding becomes zero after the switching element turns OFF.SELECTED DRAWING: Figure 2

Description

  The present invention relates to an insulation type DC power supply device including a voltage conversion transformer, and more particularly, a so-called Primary Side Regulation (hereinafter referred to as PSR) type insulation DC that controls a secondary side output voltage only by information acquired on the primary side. The present invention relates to a technique that is effective when used for a primary side control circuit in a DC converter.

In DC power supply devices, the switching element connected in series with the primary winding of the voltage conversion transformer is turned on and off to control the current flowing in the primary winding and the voltage induced in the secondary winding. There is known an insulation type DC-DC converter of a switching control system configured as described above.
One of the switching control type isolated DC-DC converters is a current mode control flyback converter.
In this current mode converter, the output voltage or output current is controlled by detecting the output voltage or output current on the secondary side, feeding back to the primary side, and controlling the current peak of the switching element.

  On the other hand, there is a PSR type isolated DC-DC converter that controls the output voltage on the secondary side only by the information acquired on the primary side without applying feedback from the secondary side to the primary side. This PSR converter has a simple secondary circuit and a large part of the primary control circuit can be configured by a semiconductor integrated circuit, so that it can realize a low-cost converter with a small number of components. There are advantages. For example, Patent Document 1 discloses an invention relating to switching control in the PSR type isolated DC-DC converter.

US Pat. No. 7,349,229

  FIG. 8 shows a timing chart of switching control in the PSR type isolated DC-DC converter disclosed in Patent Document 1. In the converter described in Patent Document 1, a period T2 from the demagnetization start timing t1 of the transformer to a period immediately after demagnetization is completed and LC resonance is entered is detected every period, and the detection period T2 is detected in the next period. The voltage Vs obtained by dividing the induced voltage of the auxiliary winding of the transformer is sampled at the time T1 obtained by subtracting the fixed time ΔT from the output voltage control information. In FIG. 8, Sw is a switching element on / off control signal, and Sp is a pulse that gives sampling timing.

  In the insulated DC-DC converter disclosed in Patent Document 1, if there is no information on the detection period T2 of the previous cycle, the voltage Vs cannot be sampled in the next cycle. It is necessary to generate time T1. In addition, when the demagnetization period of the next cycle significantly changes compared to the previous cycle, the voltage Vs cannot be sampled at an appropriate timing. Particularly when the demagnetization period is shorter than the previous period, sampling is performed in the LC resonance period, and a voltage lower than the demagnetization period is sampled. There is a problem in that components such as transformers and diodes may be damaged or destroyed due to excessive breakdown voltage.

  An object of the present invention is to provide an output voltage control at an optimal timing on the primary side in a PSR type isolated DC power supply device that includes a voltage conversion transformer and controls the output by turning on and off the current flowing in the primary winding. It is an object of the present invention to provide a technique capable of sampling information voltage and preventing damage to components such as switching elements, transformers, and diodes.

In order to achieve the above object, the present invention
A transformer for voltage conversion having a primary winding, a secondary winding, and an auxiliary winding, a switching element for intermittently passing a current through the primary winding of the transformer, and a current flowing through the primary winding of the transformer Insulation having a primary side control circuit that generates and outputs a drive pulse for controlling on and off of the switching element by inputting a proportional voltage and a voltage proportional to a voltage induced in the auxiliary winding of the transformer Type DC power supply,
The primary side control circuit includes:
A sample-and-hold circuit that captures and holds a voltage induced at the auxiliary winding of the transformer or a voltage of a terminal to which a voltage proportional to the voltage is applied at a predetermined timing;
A detection circuit for providing a timing for turning off the switching element based on a voltage taken in by the sample-and-hold circuit and a voltage proportional to a current flowing in the primary winding of the transformer;
A timer circuit for providing a timing for turning on the switching element;
The sample-and-hold circuit holds the captured voltage at a timing when the current discharged from the secondary winding decreases to near zero after the switching element is turned off and the voltage at the terminal starts to fall rapidly. Configured to do.

  According to the above-described means, it is possible to determine the optimum sampling timing by the sample hold circuit that takes in the voltage induced in the auxiliary winding or the voltage of the terminal to which the voltage proportional to the voltage is applied with the information within one period. In the case where the demagnetization period is shorter than the previous period, it is possible to avoid sampling in the LC resonance period. As a result, control that increases the output voltage by sampling a lower voltage than during the demagnetization period is prevented, and components such as switching elements, transformers, and diodes are prevented from being damaged or destroyed due to overvoltage. be able to.

Preferably, the delay means for delaying the voltage of the terminal, the offset adding means for giving an offset to the voltage delayed by the delay means, the voltage to which the offset is added by the offset adding means, and the voltage of the terminal And the sample hold circuit is configured to hold the voltage delayed by the delay means at the timing when the voltage comparison circuit detects the coincidence of the input voltages.
As a result, it is possible to determine the optimum sampling timing only by providing a simple circuit. Instead of holding the voltage delayed by the delay means, the voltage (Vs) of the terminal (VS) may be held at the timing.

Preferably, the timer circuit is configured to start measuring the next switching cycle at a timing when the switching element is turned on.
Thereby, the switching cycle on the primary side can be determined by the timer circuit.

Preferably, the timer circuit is configured such that the time to be measured is variable according to the voltage taken in by the sample and hold circuit.
As a result, the primary-side switching cycle can be changed in accordance with the voltage induced in the auxiliary winding, thereby enabling control to easily maintain the secondary-side output voltage constant.

Further preferably, the sample and hold circuit includes a first switch for sampling and a first capacitance element connected to the terminal via the first switch, and the connection between the first switch and the first capacitance element. The voltage taken in the first capacitor element is transmitted to the detection circuit via a first buffer having an input terminal connected to the node.
Thus, when the input impedance of the subsequent circuit is low, it is possible to avoid the sampled voltage from fluctuating due to the influence of the subsequent circuit.

Preferably, the sample and hold circuit includes a second switch for sampling and a second capacitor element that captures and holds the output voltage of the first buffer, and the voltage captured by the second capacitor element is supplied to the second capacitor element. The signal is transmitted to the detection circuit via two buffers.
As a result, when an enhancement type N-channel MOS transistor is used as the first switch, when the gate potential is zero and the potential of the sampling target terminal (VS) becomes negative, the switch is turned on and the first capacitor element is turned on. In addition to avoiding the loss of charge and the inability to hold the sampled voltage, when the input impedance of the subsequent circuit is low, the sampled voltage fluctuates due to the influence of the subsequent circuit. Can be avoided.

  According to the present invention, an output voltage control is performed at an optimal timing on the primary side in a PSR type isolated DC power supply device that includes a voltage conversion transformer and controls the output by turning on and off the current flowing in the primary winding. The information voltage can be sampled to prevent the components such as the switching element, the transformer, and the diode from being damaged.

It is a circuit block diagram which shows one Embodiment of the insulation type DC-DC converter as an insulation type DC power supply device which concerns on this invention. FIG. 2 is a block diagram illustrating a configuration example of a primary side control circuit (primary side control IC) of a transformer in the insulated DC-DC converter of FIG. 1. It is a circuit block diagram which shows the structural example of the sample hold circuit which comprises the primary side control IC of an Example. FIG. 4 is a circuit configuration diagram showing a configuration example of a switch control circuit constituting the sample hold circuit of the embodiment of FIG. 3. It is a timing chart which shows the mode of the change of the various signals in the IC for primary side control of an Example. It is a circuit block diagram which shows the 1st modification of the sample hold circuit which comprises IC for primary side control. FIG. 10 is a circuit configuration diagram showing a second modification of the sample and hold circuit constituting the primary side control IC. 6 is a timing chart showing the timing of switching control in the PSR type isolated DC-DC converter disclosed in Patent Document 1.

DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described with reference to the drawings.
FIG. 1 shows a so-called Primary Side Regulation (hereinafter referred to as PSR) system in which the present invention controls the output voltage on the secondary side only by the information acquired on the primary side without applying feedback from the secondary side to the primary side as an example. It is a circuit block diagram which shows one Embodiment at the time of applying to the insulation type DC-DC converter of this.

  The DC-DC converter of this embodiment is connected in series with a voltage conversion transformer TR1 having a primary winding Np, a secondary winding Ns and an auxiliary winding Na, and a primary winding Np of the transformer TR1. It has a switching transistor SW as a switching element made of an N-channel MOSFET, and a power supply control circuit 10 that drives the switching transistor SW. Although not particularly limited, in this embodiment, the power supply control circuit 10 is formed as a semiconductor integrated circuit (hereinafter referred to as a primary side control IC) on one semiconductor chip such as single crystal silicon. ing.

Further, the DC-DC converter of FIG. 1 does not have an oscillation circuit for the primary-side control IC 10 to turn on and off the switching transistor SW, performs switching control in a self-excited manner, and serves as a transformer TR1 as a secondary winding Ns. Is used as a quasi-resonant flyback converter by controlling the output voltage by controlling the current peak of the switching element.
The DC-DC converter shown in FIG. 1 includes a noise blocking filter, a diode bridge circuit that rectifies AC voltage (AC) and converts it into DC voltage, and a smoothing capacitor that smoothes the rectified voltage. It may be provided and configured as an AC-DC converter (so-called AC adapter).

The secondary side of the transformer TR1 is connected between the rectifying diode D2 connected in series with the secondary winding Ns, and the cathode terminal of the diode D2 and the other terminal of the secondary winding Ns. A smoothing capacitor C2 is provided.
The primary side of the DC-DC converter of this embodiment is connected between the rectifying diode D1 connected in series with the auxiliary winding Na, and between the cathode terminal of the diode D1 and the ground point GND. A rectifying / smoothing circuit including a smoothing capacitor C1 is provided, and a voltage rectified and smoothed by the rectifying / smoothing circuit is applied to the power supply voltage terminal VDD of the primary side control IC 10. The input voltage Vin of the primary winding may be applied to the power supply terminal of the primary side control IC 10 directly or via a diode or resistor, and the internal circuit may be operated by the voltage.

  Further, in the present embodiment, a current detection resistor Rs for converting a current flowing through the switching transistor SW into a voltage is connected between the source terminal of the switching transistor SW and the ground point GND, and the current detection resistor Rs. The voltage Vcs of the node N0 converted by the above is input to the current detection terminal CS of the primary side control IC 10. At the same time, voltage dividing resistors R1 and R2 for dividing the induced voltage of the auxiliary winding Na between the anode terminal of the rectifying diode D1 connected in series with the auxiliary winding Na and the ground point GND are connected in series. The potential Vs of the connection node N1 of the resistors R1 and R2 is input to the voltage detection terminal VS of the primary side control IC 10. Here, since the potential Vs of the terminal VS is proportional to the output voltage Vout on the secondary side, the primary side control IC 10 controls the output voltage Vout to a predetermined voltage by controlling the potential of the terminal VS to be constant. Configured to maintain.

A voltage proportional to the voltage induced in the secondary winding Ns is induced in the auxiliary winding Na. Therefore, the potential of the terminal VS is defined as Na / N2 as the turns ratio of the auxiliary winding and the secondary winding, V2 as the voltage between the terminals of the secondary winding, and VF as the forward voltage of the diode D2 on the secondary side. The following formula (1)
It is represented by As can be seen from the above equation (1), the potential of the terminal VS is proportional to the inter-terminal voltage V2 (= Vout + VF) of the secondary winding. That is, the output voltage Vout controlled according to the potential Vs depends on VF.

However, since the forward voltage VF of the secondary-side diode D2 changes according to the current value of the secondary-side discharge current, VF is always constant regardless of the load connected to the output terminal and the switching cycle. It is necessary to sample the voltage of the terminal VS at a timing when the secondary side current is constant, and to perform switching control based on the voltage. For this purpose, the secondary side current (current of the secondary winding) is zero or zero. It is desirable to sample the voltage at the terminal VS at a slightly higher timing than that. As shown in FIG. 5E, the induced voltage of the secondary winding and the auxiliary winding, that is, the voltage at the terminal VS, starts to fall rapidly immediately after the secondary side current becomes zero. It is desirable to sample the voltage at the timing when the voltage starts falling.
Therefore, in the embodiment described below, the circuit is configured to start sampling the voltage at the terminal VS at a timing before the secondary current becomes zero and hold it at a timing at which the voltage starts to fall.

Next, a specific configuration example of the primary side control IC 10 will be described with reference to FIGS. 2 to 4, FIG. 2 is a block diagram illustrating an embodiment of the primary side control IC 10, FIG. 3 is a circuit configuration diagram illustrating a configuration example of a sample hold circuit in the primary side control IC 10, and FIG. 4 is a sample. It is a circuit block diagram which shows the structural example of the switch control circuit in a hold circuit.
The primary side control IC 10 of this embodiment determines the off timing of the switching transistor SW based on the current detection voltage Vcs to control the peak current of the primary winding, and the timing near the secondary side current becomes zero. In this case, the voltage of the terminal VS is sampled, and the switching cycle is controlled according to the sampled voltage VSH to determine the ON timing of the switching transistor SW.

  In order to realize the off-timing determination function, the primary side control IC 10 of this embodiment has a desired voltage Vs obtained by dividing the induced voltage of the auxiliary winding input to the terminal VS as shown in FIG. A sample hold circuit 11 that performs sampling at timing, an error amplifier circuit (hereinafter referred to as an error amplifier) 12 that generates a voltage corresponding to a potential difference between VSH obtained by sampling the voltage Vs and a predetermined voltage Vref1, and is input to a terminal CS. A comparator 13 for comparing the detected current detection voltage Vcs and the output voltage Vcont of the error amplifier 12, and the output of the comparator 13 is input to the reset terminal R of the RS flip-flop 14.

  The output of the flip-flop 14 is supplied to a drive circuit (driver) 15, and the output from the drive circuit 15 becomes a drive pulse DRV that drives the switching transistor SW on and off. In this embodiment, when the current detection voltage Vcs exceeds the output voltage Vcont of the error amplifier 12, the output of the comparator 13 changes to a high level, the RS flip-flop 14 is reset, and the output changes to a low level. The drive pulse DRV output from 15 is changed to a low level and the switching transistor SW is turned off.

In order to realize the on-timing determination function, the primary control IC 10 includes a timer circuit 16 activated by the output of the flip-flop 14, and when the timer circuit 16 times a predetermined time, the flip-flop 14 The drive pulse DRV output from the drive circuit 15 is set to a high level and the switching transistor SW is turned on.
In addition, the timer circuit 16 changes the time to be measured in accordance with the output voltage Vcont of the error amplifier 12, thereby changing the switching period. Specifically, unless the peak current control of the primary winding described above is considered, when the output voltage Vcont of the error amplifier 12 becomes high, the time that the timer circuit 16 measures becomes short and the switching cycle becomes short. When the output voltage Vcont of 12 is lowered, the time taken by the timer circuit 16 becomes longer and the switching cycle becomes longer. Thereby, the switching cycle on the primary side can be changed according to the voltage induced in the auxiliary winding.

More precisely, in the case of the present embodiment, the control for maintaining the output voltage on the secondary side constant by combining the control of the switching cycle as described above and the peak current control of the primary winding described above. Therefore, even if the voltage Vcont increases, the switching period may not change or may decrease.
Note that, as described above, the timer circuit with a variable timing time compares, for example, a variable current source, a capacitor charged by a current from the variable current source, and a charging voltage of the capacitor with a predetermined reference voltage. This can be realized by providing a comparator and increasing or decreasing the current flowing from the variable current source in proportion to the output voltage Vcont of the error amplifier 12.

FIG. 3 shows a configuration example of the sample and hold circuit 11 constituting the primary side control IC 10.
3 includes a switch SW1 and a capacitor C3 connected in series between a terminal VS to which a voltage Vs obtained by dividing the induced voltage of the auxiliary winding is input and a ground point, and a terminal VS and a switch. An offset circuit comprising a switch SW2 and a resistor R3 connected in series between SW1 and a connection node N2 of the capacitor C3, and an operational amplifier circuit for applying a negative voltage offset VSHoff (for example, −100 mV) to the potential of the connection node N2. 18 and a comparator 19 that compares the output of the offset circuit 18 with a voltage Vs obtained by dividing the induced voltage of the auxiliary winding input to the terminal VS. The offset circuit 18 can also be composed of a level shift circuit.

3 has an output voltage Vcont of the error amplifier 12, an output signal S of the flip-flop 14, and a voltage Vs obtained by dividing the induced voltage of the auxiliary winding input to the terminal VS. The switch control circuit 20 is provided with the output signal SK of the comparator 19 as an input.
FIG. 4 shows a configuration example of the switch control circuit 20 constituting the sample hold circuit 11. The switch control circuit 20 shown in FIG. 4 includes a comparator CMP1, an AND gate G1, a flip-flop FF1, and the like. A start point detection circuit 21 is provided.

  The switch control circuit 20 rises at the start of degaussing and generates a pulse signal S1 having a width controlled by the output voltage Vcont of the error amplifier 12, and the output voltage Vcont of the error amplifier 12 And a second pulse generation circuit 23 including a flip-flop FF3 that generates a pulse signal S2 having a width from the falling edge of the pulse signal S1 to the completion of demagnetization. The first pulse generation circuit 22 includes a timer that measures a time proportional to the output voltage Vcont of the error amplifier 12, and generates a pulse signal S1 having a pulse width corresponding to the time measured by the timer.

In the demagnetization start point detection circuit 21, the input signal at the terminal S (output signal from the flip-flop 14) is at low level, the voltage Vs at the terminal VS is higher than the reference voltage Vref1, and the output of the comparator CMP1 is at high level. Is changed to, the output of the AND gate G1 becomes high level, the flip-flop FF1 is set, and its output Q changes to high level. When the input signal at the terminal S changes to a high level, the flip-flop FF1 is reset and its output Q changes to a low level and / Q changes to a high level.
The first pulse generation circuit 22 includes, for example, a constant current source CI, a capacitor C5 that is charged by a constant current from the constant current source CI, a switch SW3 that discharges the charge of the capacitor C5, a charging voltage of the capacitor C5, and an error amplifier. A timer circuit constituted by a comparator CMP2 that compares the output voltage Vcont of 12 and a flip-flop FF2 and the like are provided, and a pulse signal S1 having a pulse width corresponding to the time measured by the timer circuit is generated. Note that the circuit shown in FIG. 4 is an example, and the present invention is not limited to such a configuration.

The timer circuit (CI, C5, SW3) in the first pulse generation circuit 22 changes the time to be measured according to the output voltage Vcont of the error amplifier 12. Specifically, a time that is proportional to the output voltage Vcont of the error amplifier 12 and is slightly shorter than a period T2 (see FIG. 5) from when the current starts to flow to the secondary winding until it becomes zero, is measured. The period T4 shown in FIG. 5 is configured to be as short as possible.
As will be described in detail later, since the voltage VSH is delayed with respect to the voltage VS in the period from the timing t3 to the timing t4 in FIG. 5, when T4 is longer than T3, the deviation of VSH from the VS increases, Since the accuracy is lowered, the period T4 should be as short as possible.

  Therefore, in this embodiment, as means for shortening the period T4 as much as possible, the fact that the output voltage Vcont of the error amplifier 12 and the period during which current flows through the secondary winding (demagnetization period) T2 is proportionally utilized. In addition, timers (CI, C5, SW3) that obtain a time T3 that is proportional to Vcont and shorter than T2 are provided, and the pulse width of the pulse signal S1 is determined by this timer. As a result, even when the current demagnetization period is significantly shorter than the previous period, it is possible to avoid erroneous sampling during the LC resonance period.

Note that the proportional relationship between the output voltage Vcont of the error amplifier 12 and the demagnetization period T2 can be derived from the following equation. That is, the inductance of the primary winding of the transformer is L1, the inductance of the secondary winding is L2, the number of turns of the primary winding is Np, the number of turns of the secondary winding is Ns, the current peak on the primary side is I1pk, When the current peak is I2pk and the forward voltage of the secondary side rectifier diode D2 is VF, first, the demagnetization period T2 is expressed by the following equation.
It is represented by Where L2, I1pk and I2pk are respectively
It is represented by Rs is a resistance value of a sense resistor for current detection (see FIG. 1). And by substituting equation (3) into equation (2) and rearranging,
Is obtained. From equation (4), it can be seen that Vcont and T2 are in a proportional relationship.

Next, the function and operation of each circuit constituting the primary side control IC 10 will be described with reference to the timing chart of FIG. 5 (F) and 5 (G) show the timings of the pulse signals S1 and S2 generated by the first pulse generation circuit 22 and the second pulse generation circuit 23, and FIG. The timing of the output signal SK is shown.
In the primary-side control IC 10, when the flip-flop 14 is set by the timer circuit 16 being timed up, the output signal DRV of the drive circuit 15 is changed from the low level to the high level as shown in FIG. It rises (timing t1). Then, the switching transistor SW is turned on, and as shown in FIG. 5B, the current I1 starts to flow through the primary winding and then gradually increases (period T1).

  Then, as shown in FIG. 5C, when the detection voltage Vcs of the sense resistor Rs for detecting the current I1 reaches the output voltage Vcont of the error amplifier 12 (or a voltage proportional to Vcont), the output of the comparator 13 becomes high. The flip-flop 14 is reset, the drive pulse DRV output from the drive circuit 15 changes to a low level, and the switching transistor SW is turned off (timing t2). As a result, as shown in FIG. 5D, the current I2 starts to flow through the secondary winding of the transformer, and the demagnetization of the transformer, that is, the discharge to the secondary side is started. At this time, in the sample hold circuit 11 of FIG. 3, as shown in FIG. 5F, the pulse signal S1 output from the switch control circuit 20 (first pulse generation circuit 22) changes to a high level. The switch SW1 is turned on. Then, a charge corresponding to the voltage Vs of the terminal VS at that time is charged in the capacitor C3.

  Thereafter, when the timer in the first pulse generation circuit 22 that measures the time proportional to the output voltage Vcont of the error amplifier 12 has expired, the pulse signal S1 changes to low level and the switch SW1 is turned off (timing t3 ). Then, a charge corresponding to the voltage Vs of the immediately preceding terminal VS is held in the capacitor C3. At the same time, the pulse signal S2 output from the switch control circuit 20 (second pulse generation circuit 23) changes to a high level and the switch SW2 is turned on. Then, as shown by a broken line in FIG. 5E, the voltage VSH obtained by delaying the voltage Vs of the terminal VS by a delay time corresponding to the time constant of the resistor R3 and the capacitor C3 connected in series with the switch SW2 is Appears at node N2.

  Thereafter, at timing t5 when the voltage VSHoff obtained by adding the negative voltage offset ΔVoff to the voltage VSH of the node N2 intersects the voltage Vs of the terminal VS, the pulse signal S2 changes to the low level and the switch SW2 is turned off. Then, the potential VSH of the node N2 at that time is held in the capacitor C3. Then, the potential is supplied to the error amplifier 12 (see FIG. 2), and an output voltage Vcont corresponding to the potential difference from the reference voltage Vref1 is generated. Note that, at the timing t5, instead of holding the voltage delayed by the time constant of the resistor R3 and the capacitor C3, the voltage Vs of the terminal VS may be held.

Then, when the timer circuit 16 receiving the output voltage Vcont times the time according to Vcont, the flip-flop 14 is set, the drive pulse DRV output from the drive circuit 15 changes to high level, and the switching transistor SW is turned on. Turned on (timing t6). At this time, the timer circuit 16 starts measuring the next cycle from the time when the drive pulse DRV changes to the high level. That is, the timer circuit 16 determines the switching cycle, and the switching cycle is a cycle corresponding to the output voltage Vcont of the error amplifier 12.
Note that the potential VSH of the node N2 supplied to the error amplifier 12 becomes a voltage smaller than ideal due to the delay of the comparator 19, but the slope is reduced by the filter composed of the resistor R3 and the capacitor C3, so that it is close to ideal. The voltage can be sampled.

(Modification)
Next, a modification of the primary control IC 10 of the above embodiment will be described with reference to FIGS. 6 and 7.
In the modification shown in FIG. 6, the potential VSH of the connection node N2 is applied to the input terminal between the connection node N2 between the resistor R3 and the capacitor C3 and the offset circuit 18 in the sample and hold circuit 11 of FIG. A functioning voltage follower 17A is added. The voltage follower 17A is provided because the potential of the connection node N3 may vary due to the influence of the error amplifier 12 when the input impedance of the subsequent error amplifier 12 to which the potential of the connection node N3 is supplied is low. This is to avoid this.

  In the modification shown in FIG. 7, the potential of the sample hold circuit including the switch SW3 and the capacitor C4, and the connection node N4 of the switch SW3 and the capacitor C4 are set in the subsequent stage of the voltage follower 17A with respect to the sample hold circuit 11 of FIG. A voltage follower 17B that is applied to the input terminal and functions as a buffer is added. FIG. 5I shows the timing of the control signal S3 for controlling the switch SW3 to be turned on / off. This control signal S3 is, for example, a D flip-flop that uses the output Q of the flip-flop FF1 (see FIG. 4) as a latch signal and an inverted signal of the signal SK as a reset signal, or an OR gate that takes the logical sum of the control signals S1 and S2. It can be generated by providing.

  The sample and hold circuit comprising the switch SW3 and the capacitor C4 is provided when the enhancement type N-channel MOS transistor is used as the switches SW1 and SW2, the gate potential is zero, and the potential of the sampling target terminal (VS) is negative. Then, it is possible to avoid that the switches SW1 and SW2 are turned on and the charge of the capacitor C4 is lost and the sampled voltage cannot be held. The voltage follower 17B is provided because the potential of the connection node N4 fluctuates due to the influence of the error amplifier 12 when the input impedance of the subsequent error amplifier 12 to which the potential of the connection node N4 is supplied is low. This is to avoid this because there is a fear. In FIG. 7, a configuration in which the voltage follower 17A, the switch SW3, and the capacitor C4 are omitted is also possible.

  Although the invention made by the present inventor has been specifically described based on the embodiment, the present invention is not limited to the embodiment. For example, in the embodiment (FIG. 1), the resistors R1 and R2 for voltage division for dividing the induced voltage of the auxiliary winding Na are provided on the primary side, and the voltage divided by the resistors is used as the voltage of the primary control IC 10. Although applied to the detection terminal VS, the induced voltage of the auxiliary winding Na may be directly applied to the voltage detection terminal VS of the primary side control IC 10.

  Further, in the DC-DC converter shown in FIG. 1, the simplest configuration in which a rectifying diode D2 and a smoothing capacitor C2 are provided as a secondary side circuit is shown as an example. A MOS transistor is connected instead of a diode, and a control circuit that generates an on / off control signal by monitoring the source voltage and drain voltage of the transistor is provided, and the rectifying MOS transistor is turned on when current flows through the diode. The present invention can also be applied to a synchronous rectification type DC-DC converter.

10 Primary side control circuit (Primary side control IC)
11 Sample hold circuit 12 Error amplification circuit (error amplifier)
13 Comparator (current detection circuit)
14 RS flip-flop 15 Drive circuit (driver)
16 Timer circuit 17 Voltage follower (buffer)
18 Offset circuit 19 Comparator (voltage detection circuit)
20 Switch control circuit 21 Demagnetization start point detection circuit 22, 23 Pulse generation circuit

Claims (7)

A transformer for voltage conversion having a primary winding, a secondary winding, and an auxiliary winding, a switching element for intermittently passing a current through the primary winding of the transformer, and a current flowing through the primary winding of the transformer Insulation having a primary side control circuit that generates and outputs a drive pulse for controlling on and off of the switching element by inputting a proportional voltage and a voltage proportional to a voltage induced in the auxiliary winding of the transformer Type DC power supply,
The primary side control circuit includes:
A sample-and-hold circuit that captures and holds a voltage induced at the auxiliary winding of the transformer or a voltage of a terminal to which a voltage proportional to the voltage is applied at a predetermined timing;
A detection circuit for providing a timing for turning off the switching element based on a voltage taken in by the sample-and-hold circuit and a voltage proportional to a current flowing in the primary winding of the transformer;
A timer circuit for providing a timing for turning on the switching element;
The sample-and-hold circuit captures at a timing when the current discharged from the secondary winding of the transformer decreases to near zero after the switching element is turned off and the voltage at the terminal starts to fall rapidly. An insulated DC power supply device configured to hold a voltage. Delay means for delaying the voltage of the terminal, offset adding means for giving an offset to the voltage delayed by the delay means, and voltage comparison for comparing the voltage to which the offset is added by the offset adding means with the voltage of the terminal With circuit,
2. The insulation according to claim 1, wherein the sample hold circuit is configured to hold the voltage delayed by the delay means at a timing when the voltage comparison circuit detects coincidence of input voltages. Type DC power supply. Delay means for delaying the voltage of the terminal, offset adding means for giving an offset to the voltage delayed by the delay means, and voltage comparison for comparing the voltage to which the offset is added by the offset adding means with the voltage of the terminal With circuit,
2. The isolated DC power supply device according to claim 1, wherein the sample hold circuit is configured to hold the voltage of the terminal at a timing when the voltage comparison circuit detects coincidence of input voltages. .   4. The insulated DC power supply device according to claim 2, wherein the timer circuit is configured to start measuring a next switching cycle at a timing when the switching element is turned on.   5. The insulated DC power supply device according to claim 4, wherein the timer circuit is configured to be variable in time to be measured according to the voltage taken in by the sample and hold circuit.   The sample hold circuit includes a first switch for sampling and a first capacitor element connected to the terminal via the first switch, and an input terminal is connected to a connection node between the first switch and the first capacitor element. The insulation type according to any one of claims 2 to 5, wherein a voltage taken in the first capacitance element is transmitted to the detection circuit via a connected first buffer. DC power supply.   The sample hold circuit includes a second switch for sampling that captures and holds the output voltage of the first buffer and a second capacitive element, and the voltage captured by the second capacitive element is passed through the second buffer. The insulated DC power supply device according to claim 6, wherein the insulated DC power supply device is configured to be transmitted to the detection circuit.