JP2016115385A - Semiconductor device, storage device, and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a novel semiconductor device, provide a semiconductor device capable of storing multivalued information, provide a semiconductor device with high reliability, or provide a semiconductor with low power consumption.SOLUTION: A memory cell has a first holding part and a second holding part. The first holding part is connected with wiring WLa and wiring BLa; and the second holding part is connected with wiring WLb and wiring BLb. When a selection signal is supplied to the wiring WLa, the writing potential of the wiring BLa is supplied to the first holding part and held. In addition, when a selection signal is supplied to the second holding part, the writing potential of the wiring BLb is supplied to the holding part 21b and held. This enables data of 2 bits or more to be stored in the memory cell.SELECTED DRAWING: Figure 1

Description

One embodiment of the present invention relates to a semiconductor device, a memory device, and an electronic device.

Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter). One embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an imaging device, a driving method thereof, or a manufacturing method thereof.

Patent Document 1 describes a memory device including a transistor using an oxide semiconductor and a transistor using single crystal silicon. Further, it is described that a transistor including an oxide semiconductor has extremely small off-state current.

JP 2012-256400 A

An object of one embodiment of the present invention is to provide a novel semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device capable of storing multilevel information. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.

Note that one embodiment of the present invention does not necessarily have to solve all of the problems described above, and may be one that can solve at least one problem. Further, the description of the above problem does not disturb the existence of other problems. Issues other than these will be apparent from the description of the specification, drawings, claims, etc., and it is possible to extract other issues from the description of the specification, drawings, claims, etc. .

A semiconductor device according to one embodiment of the present invention includes a memory cell, and the memory cell includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor. , The first capacitor element, and the second capacitor element. The gate of the first transistor is electrically connected to the first wiring, and one of the source and the drain of the first transistor is The gate of the second transistor and the first capacitor are electrically connected, and the other of the source and the drain of the first transistor is electrically connected to the second wiring and the source or the drain of the second transistor Is electrically connected to one of the source and the drain of the fourth transistor, and the other of the source and the drain of the second transistor is connected to the source of the fifth transistor. One of the gate and the drain of the third transistor is electrically connected to the third wiring, and one of the source and the drain of the third transistor is connected to the gate of the fourth transistor and The other of the source and the drain of the third transistor is electrically connected to the fourth wiring, and the other of the source and the drain of the fourth transistor is electrically connected to the fifth capacitor. The gate of the fifth transistor is electrically connected to the sixth wiring, and the other of the source and the drain of the fifth transistor is electrically connected to the seventh wiring. It is a semiconductor device.

Further, the semiconductor device according to one embodiment of the present invention has a function of supplying the first potential corresponding to the potential of the gate of the second transistor to the fifth wiring and the potential of the gate of the fourth transistor. And a function of supplying the second potential to the fifth wiring.

Furthermore, in the semiconductor device according to one embodiment of the present invention, the first potential is supplied to the fifth wiring when the fourth transistor and the fifth transistor are in the on state. The supply to the fifth wiring may be performed when the second transistor and the fifth transistor are on.

Further, in the semiconductor device according to one embodiment of the present invention, the first transistor and the third transistor may include an oxide semiconductor in a channel formation region.

Further, in the semiconductor device according to one embodiment of the present invention, the first transistor and the second transistor are provided over the fifth transistor, and the third transistor and the fourth transistor are the first transistor and the second transistor. It may be provided on the second transistor.

A memory device according to one embodiment of the present invention includes the above semiconductor device and a driver circuit.

An electronic device according to one embodiment of the present invention includes the semiconductor device or the memory device, and a display portion, a microphone, a speaker, or an operation key.

According to one embodiment of the present invention, a novel semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device capable of storing multi-value information can be provided. Alternatively, according to one embodiment of the present invention, a highly reliable semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low power consumption can be provided.

Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. It should be noted that the effects other than these are naturally obvious from the description of the specification, drawings, claims, etc., and it is possible to extract the other effects from the descriptions of the specification, drawings, claims, etc. It is.

FIG. 6 illustrates one embodiment of the present invention. FIG. 10 is a circuit diagram illustrating one embodiment of the present invention. Timing chart. FIG. 6 illustrates a potential distribution. FIG. 10 is a circuit diagram illustrating one embodiment of the present invention. FIG. 10 is a circuit diagram illustrating one embodiment of the present invention. FIG. 6 illustrates one embodiment of the present invention. FIG. 6 illustrates one embodiment of the present invention. FIG. 6 illustrates one embodiment of the present invention. FIG. 6 illustrates one embodiment of the present invention. FIG. 6 illustrates one embodiment of the present invention. FIG. 6 illustrates one embodiment of the present invention. FIG. 6 illustrates one embodiment of the present invention. 6A and 6B illustrate an example of a structure of a transistor. 6A and 6B illustrate an example of a structure of a transistor. 6A and 6B illustrate an example of a structure of a transistor. 10 is a flowchart illustrating an example of a method for manufacturing an electronic component. 10A and 10B each illustrate an electronic device. 10A and 10B illustrate characteristics of a transistor. 10A and 10B illustrate characteristics of a transistor. 10A and 10B illustrate characteristics of a transistor. FIG. 10 is a circuit diagram illustrating one embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the description in the following embodiments, and those skilled in the art can easily understand that the forms and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention should not be construed as being limited to the description of the following embodiments.

One embodiment of the present invention includes, in addition to a memory device, any device including an RF (Radio Frequency) tag, a display device, an imaging device, and an integrated circuit. In addition, the display device includes a liquid crystal display device, a light-emitting device including a light-emitting element typified by an organic light-emitting element in each pixel, electronic paper, DMD (Digital Micromirror Device), PDP (Plasma Display Panel), FED (Field Emission). Display) including an integrated circuit such as Display) is included in the category.

Note that in describing the structure of the invention with reference to the drawings, the same reference numerals may be used in common in different drawings.

In addition, in this specification and the like, when it is explicitly described that X and Y are connected, X and Y are electrically connected, and X and Y function. And the case where X and Y are directly connected are disclosed in this specification and the like. Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or text, and things other than the connection relation shown in the figure or text are also described in the figure or text. Here, X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

As an example of the case where X and Y are directly connected, an element that enables electrical connection between X and Y (for example, a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display, etc.) Element, light emitting element, load, etc.) are not connected between X and Y, and elements (for example, switches, transistors, capacitive elements, inductors) that enable electrical connection between X and Y X and Y are not connected via a resistor element, a diode, a display element, a light emitting element, a load, or the like.

As an example of the case where X and Y are electrically connected, an element (for example, a switch, a transistor, a capacitive element, an inductor, a resistance element, a diode, a display, etc.) that enables electrical connection between X and Y is shown. More than one element, light emitting element, load, etc.) can be connected between X and Y. Note that the switch has a function of controlling on / off. That is, the switch is in a conductive state (on state) or a non-conductive state (off state), and has a function of controlling whether or not to pass a current. Alternatively, the switch has a function of selecting and switching a current flow path. Note that the case where X and Y are electrically connected includes the case where X and Y are directly connected.

As an example of the case where X and Y are functionally connected, a circuit (for example, a logic circuit (an inverter, a NAND circuit, a NOR circuit, etc.) that enables a functional connection between X and Y, signal conversion, etc. Circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, step-down circuit, etc.), level shifter circuit that changes signal potential level, etc.), voltage source, current source, switching Circuit, amplifier circuit (circuit that can increase signal amplitude or current amount, operational amplifier, differential amplifier circuit, source follower circuit, buffer circuit, etc.), signal generation circuit, memory circuit, control circuit, etc.) One or more can be connected between them. As an example, even if another circuit is interposed between X and Y, if the signal output from X is transmitted to Y, X and Y are functionally connected. To do. Note that the case where X and Y are functionally connected includes the case where X and Y are directly connected and the case where X and Y are electrically connected.

In addition, when it is explicitly described that X and Y are electrically connected, a case where X and Y are electrically connected (that is, there is a separate connection between X and Y). And X and Y are functionally connected (that is, they are functionally connected with another circuit between X and Y). And the case where X and Y are directly connected (that is, the case where another element or another circuit is not connected between X and Y). It shall be disclosed in the document. In other words, when it is explicitly described that it is electrically connected, the same contents as when it is explicitly described only that it is connected are disclosed in this specification and the like. It is assumed that

In addition, even in the case where the components shown in the drawing are shown as being electrically connected to each other, one component may have the functions of a plurality of components. is there. For example, in the case where a part of the wiring also functions as an electrode, one conductive film has both the functions of the constituent elements of the wiring function and the electrode function. Therefore, the term “electrically connected” in this specification includes in its category such a case where one conductive film has functions of a plurality of components.

(Embodiment 1)
In this embodiment, a structural example of a semiconductor device according to one embodiment of the present invention will be described.

<Configuration example of semiconductor device>
FIG. 1A illustrates a configuration example of a semiconductor device 10 according to one embodiment of the present invention. The semiconductor device 10 includes a plurality of memory cells 20 and can be used as a memory device. Here, a configuration in which the semiconductor device 10 includes memory cells 20 (memory cells 20 [1, 1] to [n, m]) in n rows and m columns (n and m are natural numbers) will be described.

The memory cell 20 has a function of storing data. In particular, in one embodiment of the present invention, data of 2 bits or more (multi-value data) can be stored in the memory cell 20. Thereby, the area of the semiconductor device 10 per bit can be reduced.

The memory cell 20 is connected to the wiring WL, the wiring BL, and the wiring SL. The wiring WL has a function of transmitting a signal for selecting the memory cells 20 in a predetermined row (hereinafter also referred to as a selection signal). The wiring BL has a function of transmitting a potential corresponding to data to be written to the selected memory cell 20 (hereinafter also referred to as a write potential). The wiring SL has a function of transmitting a potential corresponding to data stored in the memory cell 20 (hereinafter also referred to as a read potential).

Here, the memory cell 20 is connected to a plurality of WLs and a plurality of BLs. In FIG. 1A, the memory cell 20 is connected to two wirings WL (wirings WLa and WLb) and two wirings BL (wirings BLa and BLb). Thereby, data of 2 bits or more can be written in each memory cell 20.

Specifically, as illustrated in FIG. 1B, the memory cell 20 includes a plurality of holding portions 21. The holding unit 21 is a circuit having a function of holding a predetermined potential. Here, a configuration in which the memory cell 20 includes two holding units 21 (holding units 21a and 21b) is shown. The holding portion 21a is connected to the wiring WLa and the wiring BLa, and the holding portion 21b is connected to the wiring WLb and the wiring BLb.

When the selection signal is supplied to the wiring WLa, the writing potential of the wiring BLa is supplied to and held in the holding portion 21a. Further, when a selection signal is supplied to the wiring WLb, the writing potential of the wiring BLb is supplied to and held in the holding portion 21b. Therefore, data of 2 bits or more can be stored in the memory cell 20.

The holding unit 21a can hold a potential of i value (i is a natural number), and the holding unit 21b can hold a potential of j value (j is a natural number). Note that the values of i and j can be set freely. For example, the potentials held in the holding units 21a and 21b may be binary potentials of high level and low level (i = 2, j = 2), respectively, or any potential of three or more values (i is 3 or more, j may be 3 or more). Further, the values of i and j may be the same or different.

Data is read from the memory cell 20 by supplying a potential corresponding to the potential held in the holding portion 21a and a potential corresponding to the potential held in the holding portion 21b to the wiring SL. Here, when the potential held in the holding unit 21 a is the i value and the potential held in the holding unit 21 b is the j value, the data of the i × j value can be read from the memory cell 20. That is, when a-bit (a is a natural number) data is stored in the holding unit 21a and b-bit (b is a natural number) data is stored in the holding unit 21b, a + b-bit data can be read.

Here, a transistor including an oxide semiconductor in a channel formation region (hereinafter also referred to as an OS transistor) is preferably used for the holding portion 21. An oxide semiconductor has a wider band gap and a lower carrier density than other semiconductors such as silicon. Therefore, the off-state current of the OS transistor is extremely small. Therefore, by using an OS transistor for the holding unit 21, the potential held in the holding unit 21 can be held for a long period of time.

A configuration example of the holding unit 21 is illustrated in FIG. The holding unit 21 includes a transistor 22 and a capacitor 23. Note that the transistor 22 is an OS transistor. One of the source and the drain of the transistor 22 is connected to the capacitor 23. Here, a node connected to one of the source and the drain of the transistor 22 and the capacitor 23 is a node FN.

The potential held in the holding portion 21 is supplied to the node FN from the wiring BL or the like through the transistor 22. When the transistor 22 is turned off, the node FN is in a floating state, and the potential of the node FN is held. Here, since the off-state current of the transistor 22 which is an OS transistor is extremely small, the potential of the node FN can be held for a long time.

The potential held in the node FN may be a binary (high level and low level) potential, or may be a potential of three or more values. In particular, when the potential held at the node FN is three or more, the interval between the held potentials is narrowed, so that a minute charge leak can cause data fluctuation. However, since the off-state current of the OS transistor is extremely small, leakage of charge from the node FN can be extremely small. Therefore, in the case where a potential of three values or more is held in the node FN, the transistor 22 is particularly preferably an OS transistor.

An OS transistor has higher withstand voltage than a transistor having silicon in a channel formation region (hereinafter also referred to as Si transistor). Therefore, when the transistor 22 is an OS transistor, the potential range held at the node FN can be widened. Accordingly, the number of data held in the holding unit 21 can be increased.

For example, a 16-value potential can be held in the node FN. When 16-value potentials are held in the holding units 21a and 21b (i = 16, j = 16), 4-bit data can be stored in the holding units 21a and 21b, respectively (a = 4, b = 4). The memory cell 20 can read i × j = 16 × 16 = 256 values, that is, 8-bit data. For example, when 4 bits of data are stored in the holding unit 21a and 5 bits of data are stored in the holding unit 21b, 9 bits of data can be read from the memory cell 20.

As described above, by providing a plurality of holding portions 21 in the memory cell 20, a semiconductor device capable of storing multi-value data can be provided. In addition, by using an OS transistor for the holding portion 21, charges accumulated in the holding portion 21 can be held for a long time, and a highly reliable semiconductor device can be provided. Hereinafter, a specific configuration example of the memory cell 20 will be described.

<Configuration example of memory cell>
FIG. 2A shows a specific configuration example of the memory cell 20. The memory cell 20 includes a circuit 30a, a circuit 30b, and a circuit 40. The circuit 30a includes a transistor 31a, a transistor 32a, and a capacitor 33a. The circuit 30b includes a transistor 31b, a transistor 32b, and a capacitor 33b. The circuit 40 includes a transistor 41. Note that the circuits 30a and 30b correspond to the holding portions 21a and 21b in FIG. The circuit 40 has a function of controlling reading of data stored in the memory cell 20.

The gate of the transistor 31a is connected to the wiring WLa, one of the source and the drain is connected to the gate of the transistor 32a and one electrode of the capacitor 33a, and the other of the source or the drain is connected to the wiring BLa. One of the source and the drain of the transistor 32 a is connected to one of the source and the drain of the transistor 32 b, and the other of the source and the drain is connected to one of the source and the drain of the transistor 41. The other electrode of the capacitive element 33a is connected to the wiring CNODEa. Here, a node connected to one of the source and the drain of the transistor 31a, the gate of the transistor 32a, and one electrode of the capacitor 33a is a node FNa.

The gate of the transistor 31b is connected to the wiring WLb, one of the source and the drain is connected to the gate of the transistor 32b and one electrode of the capacitor 33b, and the other of the source and the drain is connected to the wiring BLb. The other of the source and the drain of the transistor 32b is connected to the wiring SL. The other electrode of the capacitor 33b is connected to the wiring CNODEb. Here, a node connected to one of the source and the drain of the transistor 31b, the gate of the transistor 32b, and one electrode of the capacitor 33b is a node FNb.

The gate of the transistor 41 is connected to the wiring SW, and the other of the source and the drain is connected to the wiring VL.

The wiring CNODE is a wiring having a function of transmitting a signal for controlling the potential of the node FN (hereinafter also referred to as a read signal). The wiring SW is a wiring having a function of transmitting a signal for controlling the conduction state of the transistor 41. The wiring VL is a wiring having a function of transmitting a power supply potential. Note that a high power supply potential VDD may be supplied to the wiring VL, or a low power supply potential VSS (such as a ground potential) may be supplied.

Here, the transistors 31a and 31b are OS transistors. Thus, when the transistors 31a and 31b are in the off state, the charge accumulated in the nodes FNa and FNb can be held for a long period. Accordingly, it is possible to accurately hold a potential of three or more values at the nodes FNa and FNb. Note that the nodes FNa and FNb correspond to the node FN in FIG.

The types of the transistors 32a and 32b are not particularly limited. For example, an OS transistor may be used, or a transistor whose channel formation region is formed over part of a substrate including a single crystal semiconductor (hereinafter also referred to as a single crystal transistor) may be used. Examples of the substrate having a single crystal semiconductor include a single crystal silicon substrate and a single crystal germanium substrate.

As the transistors 32a and 32b, a transistor in which a channel formation region is formed in a film containing a semiconductor material other than an oxide semiconductor can be used. For example, a transistor including a non-single-crystal semiconductor other than an oxide semiconductor in a channel formation region can be used. Examples of such non-single-crystal semiconductors include non-single-crystal silicon such as amorphous silicon, microcrystalline silicon, and polycrystalline silicon, and non-single-crystal germanium such as amorphous germanium, microcrystalline germanium, and polycrystalline germanium. Can be mentioned.

As the transistor 41, a transistor similar to the transistors 32a and 32b can be used. As the transistors 31a and 31b, a single crystal transistor or a transistor in which a channel formation region is formed in a film containing a semiconductor material other than an oxide semiconductor can be used.

Next, the operation of the memory cell 20 will be described.

First, the potential of the wiring WLa is set to a potential at which the transistor 31a is turned on, so that the transistor 31a is turned on. Accordingly, the potential of the wiring BLa is supplied to the node FNa (data writing). Next, the potential of the wiring WLa is set to a potential at which the transistor 31a is turned off, so that the transistor 31a is turned off. As a result, the node FNa enters a floating state, and the potential of the node FNa is retained (data retention). With such an operation, data is written and held in the circuit 30a.

In the circuit 30b, data can be written and held by the same operation as described above. Note that data writing and holding in the circuit 30b may be performed simultaneously with the circuit 30a or may be performed at different timings.

Note that the potentials written and held in the nodes FNa and FNb may be binary potentials of high level and low level (i = 2, j = 2), or potentials of three or more values (i 3 or more and j is 3 or more). Further, the values of i and j may be the same or different.

Here, let us consider a case where 1-bit data is held in the nodes FNa and FNb for 10 years. If the power supply voltage is 2 V or more and 3.5 V or less, the holding capacity of the nodes FNa and FNb is 21 fF, and the allowable fluctuation amount of the holding potential is less than 0.5 V, the holding potential is less than the allowable fluctuation amount at 85 ° C. for 10 years. In order to achieve this, the leakage current from the nodes FNa and FNb needs to be less than 33 × 10 ⁻²⁴ A. When leakage from other sources is even smaller and the leak location is almost an OS transistor, the leakage current per unit area of the OS transistor should be less than 93 × 10 ⁻²⁴ A / μm when the channel width of the OS transistor is 350 nm. Is preferred. By configuring the memory cell 20 as described above, the memory cell 20 can hold data for 10 years at 85 ° C.

Also, consider a case where 4-bit data is held in the nodes FNa and FNb for 10 years. When the power supply voltage is 2 V or more, 3.5 V or less, the holding capacity is 0.1 fF, the holding potential distribution width is less than 30 mV, and the allowable variation in holding potential is less than 80 mV, the holding potential is allowed at 85 ° C. for 10 years. In order to make it less than the fluctuation amount, the leakage current from the nodes FNa and FNb needs to be less than 0.025 × 10 ⁻²⁴ A. In the case where the leak from the other is smaller and the leak portion is almost an OS transistor, the leak current per unit area of the OS transistor is less than 0.423 × 10 ⁻²⁴ A / μm when the channel width of the OS transistor is 60 nm. It is preferable to do. By configuring the memory cell 20 as described above, the memory cell 20 can hold data for 10 years at 85 ° C.

Consider a case in which 8-bit data is held in the nodes FNa and FNb for 10 years. When the power supply voltage is 2 V or more, 3.5 V or less, the holding capacitor is 0.1 fF, the holding potential distribution width is less than 2 mV, and the allowable fluctuation amount of the holding potential is less than 5 mV, the holding potential is 85 ° C. for 10 years. In order to make it less than the allowable fluctuation amount, the leakage current from the nodes FNa and FNb needs to be less than 0.0016 × 10 ⁻²⁴ A. In the case where the leak from the other is further small and the leak location is almost an OS transistor, the leak current per unit area of the OS transistor is less than 0.026 × 10 ⁻²⁴ A / μm when the channel width of the OS transistor is 60 nm. It is preferable to do. By configuring the memory cell 20 as described above, the memory cell 20 can hold data for 10 years at 85 ° C.

Next, data is read from the circuit 30a. First, by supplying a predetermined potential to the wiring CNODEb, the transistor 32b is turned on regardless of the potential written to the node FNb. Specifically, when the transistor 32b is an n-channel type, the potential of the wiring CNODEb is raised to a high level. At this time, the potential of the node FNb also rises due to capacitive coupling of the capacitive element 33b. Accordingly, the transistor 32b can be turned on regardless of the potential written to the node FNb. The potential of the node FNb may be set so that the voltage between the gate and the source of the transistor 32b becomes equal to or higher than the threshold voltage. In addition, the wiring SL is precharged to a predetermined potential (here, low level).

After that, the potential of the wiring SW is set to a potential at which the transistor 41 is turned on, so that the transistor 41 is turned on. Thus, a predetermined potential (here, high level) is supplied from the wiring VL to the wiring SL in accordance with the potential of the node FNa. Specifically, when the voltage between the node FNa and the wiring SL is equal to or lower than the threshold voltage of the transistor 32a, the transistor 32a is turned off and the potential of the wiring SL is determined. That is, the potential of the wiring SL varies depending on the potential of the node FNa. Therefore, the potential of the node FNa can be determined by reading the potential of the wiring SL.

Next, data is read from the circuit 30b by performing the same operation as described above. Specifically, when the transistor 32a is an n-channel type, the potential of the wiring CNODEa is set to a high level, and the potential of the node FNa is increased. Accordingly, the transistor 32a is turned on regardless of the potential written to the node FNa. In addition, the wiring SL is precharged to a predetermined potential (here, low level). After that, the potential of the wiring SW is set to a potential at which the transistor 41 is turned on, so that the transistor 41 is turned on. Accordingly, the potential of the wiring SL becomes a potential corresponding to the potential of the node FNb.

By the operation as described above, writing and reading of multi-value data from the memory cell 20 can be performed. Specifically, in the case where an i-value potential is written in the node FNa and a j-value potential is written in the node FNb, the i-value potential and the j-value potential output to the wiring SL are read. Data of i × j value can be read out.

Further, data can be read from the circuits 30a and 30b while the potentials of the nodes FNa and FNb are held. That is, reading can be performed without destroying data stored in the circuits 30a and 30b. Therefore, it is not necessary to rewrite data stored in the circuits 30a and 30b at the time of reading, and power consumption can be reduced.

In addition, the data in the circuits 30a and 30b can be rewritten by the same operation as the above data writing and holding.

Note that FIG. 2A illustrates an example in which the transistors 31a, 31b, 32a, 32b, and 41 are n-channel transistors, but the transistors 31a, 31b, 32a, 32b, and 41 are n-channel transistors, respectively. May also be a p-channel type. FIG. 2B illustrates a configuration example in which the transistors 32b, 32b, and 41 are p-channel transistors.

In the memory cell 20 illustrated in FIG. 2B, the transistors 32a and 32b can be turned on by setting the potentials of the wirings CNODEa and CNODEb to a low level and decreasing the potentials of the nodes FNa and FNb. Further, it is preferable that the potential of the wiring VL be a low level and the wiring SL be precharged to a high level. Thus, the memory cell 20 can be operated by the same operation as that of the memory cell 20 illustrated in FIG.

<Operation example of memory cell>
Next, an operation example of the memory cell 20 will be described. FIG. 3 is a timing chart for explaining the operation of the memory cell 20 shown in FIG. Note that the period T11 to the period T12 are periods in which data is written to the memory cell 20, and the periods T21 to T25 are periods in which data is read from the memory cells 20.

First, in a period T11, a writing potential is supplied to the wirings BLa and BLb. Note that three or more potentials can be selectively supplied to the wirings BLa and BLb. Here, an example in which 16-level potentials are supplied to the wirings BLa and BLb (i = 16, j = 16) will be described below. In this case, 4-bit data is written to each of the circuits 30a and 30b.

In addition, the potentials of the wirings WLa and WLb are set high, so that the transistors 31a and 31b are turned on. Accordingly, the potential of the wiring BLa is supplied to the node FNa, and the potential of the wiring BLb is supplied to the node FNb. That is, data is written in the circuits 30a and 30b.

Next, in the period T12, the wirings WLa and WLb are set to a low level, and the transistors 31a and 31b are turned off. Accordingly, the nodes FNa and FNb are in a floating state, and the potentials of the nodes FNa and FNb are held even if the potentials of the wirings BLa and BLb are changed.

Next, in a period T21, the potential of CNODEb is set to a high level. Accordingly, the potential of the node FNb is increased, and the transistor 32b is turned on regardless of the potential supplied to the node FNb in the period T11. Further, after the potential of the wiring SL is precharged to a low level, the potential of the wiring SL is set in a floating state.

Next, in the period T22, the potential of the wiring SW is set high and the transistor 41 is turned on. Accordingly, the transistor 32a and the wiring VL are brought into conduction. The wiring VL is supplied with a high-level potential as a power supply potential. A 16-value potential corresponding to the potential of the node FNa is supplied to the wiring SL as a read potential. Thereby, 16-value data can be read from the circuit 30a.

Next, in a period T23, the potential of CNODEb is set to a low level. Accordingly, the potential of the node FNb is decreased to the potential supplied to the node FNb in the period T11. Further, the potential of CNODEa is set to a high level. Accordingly, the potential of the node FNa is increased, and the transistor 32a is turned on regardless of the potential supplied to the node FNa in the period T11. Further, the potential of the wiring SW is set to a low level. Further, after the potential of the wiring SL is precharged to a low level, the potential of the wiring SL is set in a floating state.

Next, in the period T24, the potential of the wiring SW is set high and the transistor 41 is turned on. Accordingly, the transistor 32b and the wiring VL are brought into conduction. The wiring VL is supplied with a high-level potential as a power supply potential. Here, a 16-value potential corresponding to the potential of the node FNb is supplied to the wiring SL as a read potential. Thereby, 16-value data can be read from the circuit 30b.

Next, in the period T25, the wiring SW and the wiring CNODEa are set to a low level. Accordingly, the potential of the node FNa is lowered to the potential supplied to the node FNa in the period T11, and the memory cell 20 is set to a state in the period T12 immediately after writing is performed.

Through the above operation, the multi-value data stored in the memory cell 20 can be written and read.

Note that when a 16-value potential is written to the nodes FNa and FNb, the potential V_SL read out to the wiring SL forms a distribution corresponding to 16-value data as illustrated in FIG. Each of the 16 distributions can correspond to data 0000 to 1111. Accordingly, 4-bit data can be read from the circuits 30a and 30b, respectively.

In addition, when OS transistors are used as the transistors 31a and 31b, leakage of charges at the nodes FNa and FNb can be suppressed. Therefore, the value of V_SL having a narrow distribution and a sharp peak can be obtained. Therefore, the interval between the multi-value data stored in the circuits 30a and 30b can be narrowed, and the number of stored data can be increased.

In addition, the OS transistor has higher withstand voltage than the Si transistor. Therefore, the range of potentials held at the nodes FNa and FNb can be expanded. Therefore, the number of data stored in the circuits 30a and 30b can be increased.

In FIG. 2, when OS transistors are used as the transistors 31a, 31b, 32a, and 32b, the channel width W / channel length L of the transistors 32a and 32b is preferably larger than the W / L of the transistors 31a and 31b. . Thus, high-speed reading can be performed by improving the current supply capability of the transistors 32a and 32b while suppressing the off-state current of the transistors 31a and 31b to be small.

In addition, the potential corresponding to the node FNa is read to the wiring SL through the transistor 32b. Therefore, the W / L of the transistor 32b is preferably larger than the W / L of the transistor 32a. As a result, the potential corresponding to the node FNa can be read to the wiring SL at high speed.

The gate insulating layers of the transistors 32a and 32b are preferably thicker than the gate insulating layers of the transistors 31a and 31b. Accordingly, the withstand voltage of the transistors 32a and 32b can be improved, and the range of potentials held at the nodes FNa and FNb can be widened.

As described above, by providing a plurality of holding portions 21 in the memory cell 20, a semiconductor device capable of storing multi-value data can be provided. In addition, by using an OS transistor for the holding portion 21, a charge stored in the holding portion 21 can be held for a long time, and a semiconductor device with high reliability and low power consumption can be provided.

Note that one embodiment of the present invention is not limited to the above structure. That is, since various aspects of the present invention are described in this embodiment, one aspect of the present invention is not limited to a specific aspect. For example, as an embodiment of the present invention, an example of a semiconductor device in which the memory cell 20 is provided with a plurality of holding portions 21 has been described. However, according to circumstances or circumstances, an embodiment of the present invention The cell 20 may have a configuration in which one holding unit 21 is provided. Although an example in which multivalued data is stored in the memory cell 20 is described as one embodiment of the present invention, depending on circumstances or circumstances, one embodiment of the present invention may include two memory cells 20. The configuration may be such that value data is stored. Although an example in which the present invention is applied to a memory cell is shown as one embodiment of the present invention, one embodiment of the present invention is not limited thereto. For example, depending on circumstances or circumstances, one embodiment of the present invention may be applied to a circuit having another function. Alternatively, for example, depending on circumstances or circumstances, one embodiment of the present invention may not be applied to a memory cell. Further, as one embodiment of the present invention, in the transistor and the like in the holding portion 21, an example in which the channel formation region, the source / drain region, and the like of the transistor include an oxide semiconductor has been described. It is not limited to this. In some cases or depending on circumstances, various transistors in one embodiment of the present invention, a channel formation region of the transistor, a source / drain region of the transistor, or the like may include various semiconductors. Depending on circumstances or circumstances, various transistors in one embodiment of the present invention, a channel formation region of the transistor, a source / drain region of the transistor, and the like can be formed using, for example, silicon, germanium, silicon germanium, silicon carbide, or gallium. At least one of arsenic, aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor may be included. Alternatively, for example, depending on circumstances or conditions, various transistors in one embodiment of the present invention, the channel formation region of the transistor, the source / drain region of the transistor, and the like do not include an oxide semiconductor. Also good.

This embodiment can be combined with any of the other embodiments as appropriate. Therefore, the content (may be a part of content) described in this embodiment is different from the content (may be a part of content) described in the embodiment and / or one or more other Application, combination, replacement, or the like can be performed on the contents described in the embodiment (may be part of the contents). Note that the contents described in the embodiments are the contents described using various drawings or the contents described in the specification in each embodiment. In addition, a drawing (or a part) described in one embodiment may include another part of the drawing, another drawing (may be a part) described in the embodiment, and / or one or more. More diagrams can be formed by combining the diagrams (may be a part) described in another embodiment. The same applies to the following embodiments.

(Embodiment 2)
In this embodiment, a modification of the memory cell 20 according to one embodiment of the present invention will be described.

<Modification Example 1 of Memory Cell>
FIG. 5 shows a modification of the memory cell 20. The memory cell 20 illustrated in FIG. 5A is different from FIG. 2A in that one of the source and the drain of the transistor 31a and one of the source and the drain of the transistor 31b are connected to the same wiring BL. Different. That is, the wiring BL is shared by the circuit 30a and the circuit 30b. Thereby, the number of wirings can be reduced and the area of the memory cell 20 can be reduced.

Note that in the memory cell 20 illustrated in FIG. 5A, writing to the node FNa and writing to the node FNb are performed in different periods. That is, the potential of the wiring BL is a potential supplied to the node FNa in a period in which the transistor 31a is on and the transistor 31b is off, the transistor 31a is off, and the transistor 31b is on. In the period, the potential is supplied to the node FNb.

A memory cell 20 illustrated in FIG. 5B is different from FIG. 2A in that the gate of the transistor 31a and the gate of the transistor 31b are connected to the same wiring WL. That is, the wiring WL is shared by the circuit 30a and the circuit 30b. Thereby, the number of wirings can be reduced and the area of the memory cell 20 can be reduced.

Note that in the memory cell 20 illustrated in FIG. 5B, writing to the node FNa and writing to the node FNb are performed at the same time as illustrated in a period T11 in FIG.

2A illustrates the configuration example in which the two circuits 30 (circuits 30a and 30b) are provided, the number of the circuits 30 may be an arbitrary number of 3 or more. For example, as shown in FIG. 5C, the memory cell 20 may be provided with three circuits 30 (circuits 30a, 30b, and 30c). Thereby, the amount of data that can be stored in the memory cell 20 can be further increased. In FIG. 5C, if the potentials stored in the circuits 30a, 30b, and 30c are respectively i value, j value, and k value (k is a natural number), the memory cell 20 has data of i × j × k value. Can be remembered. That is, when data of a bits, b bits, and c bits (c is a natural number) are stored in the circuits 30a, 30b, and 30c, respectively, data of a + b + c bits can be read.

<Modification Example 2 of Memory Cell>
FIG. 6 shows another modification of the memory cell 20. The memory cell 20 illustrated in FIG. 6 is different from FIG. 2A in that the transistors 31a, 31b, 32a, and 32b which are OS transistors have a pair of gates. That is, the transistors 31a, 31b, 32a, and 32b have back gates.

6A, the back gate of the transistor 31a is connected to the gate of the transistor 31a, the back gate of the transistor 31b is connected to the gate of the transistor 31b, and the back gate of the transistor 32a is connected to the gate of the transistor 32a. The back gate of the transistor 32b is connected to the gate of the transistor 32b. In the memory cell 20 illustrated in FIG. 6B, the back gates of the transistors 31a, 31b, 32a, and 32b are connected to the wiring BG. Note that a fixed potential is supplied to the wiring BG.

Here, as in the transistors 31a, 31b, 32a, and 32b, when a certain transistor T has a pair of gates with a semiconductor film interposed therebetween, a signal A is transmitted to one gate and the other is A fixed potential Vb may be applied to the gate.

The signal A is a signal for controlling a conduction state or a non-conduction state, for example. The signal A may be a digital signal that takes two kinds of potentials, that is, the potential V1 or the potential V2 (V1> V2). For example, the potential V1 can be a high power supply potential and the potential V2 can be a low power supply potential (such as a ground potential). The signal A may be an analog signal.

The fixed potential Vb is a potential for controlling the threshold voltage VthA of the transistor T, for example. The fixed potential Vb may be the potential V1 or the potential V2. In this case, it is preferable that a potential generating circuit for generating the fixed potential Vb need not be provided separately. The fixed potential Vb may be a potential different from the potential V1 or the potential V2. In some cases, the threshold voltage VthA can be increased by lowering the fixed potential Vb. As a result, the drain current when the gate-source voltage Vgs is 0 V can be reduced, and the leakage current of the circuit including the transistor T can be reduced in some cases. For example, the fixed potential Vb may be set lower than the low power supply potential. In some cases, the threshold voltage VthA can be lowered by increasing the fixed potential Vb. As a result, the drain current when the gate-source voltage Vgs is VDD may be improved, and the operation speed of the circuit including the transistor T may be improved. For example, the fixed potential Vb may be higher than the low power supply potential.

Further, the signal A may be supplied to one gate of the transistor T, and the signal B may be supplied to the other gate. The signal B is a signal for controlling the conduction state or non-conduction state of the transistor T, for example. The signal B may be a digital signal that takes two kinds of potentials, that is, the potential V3 or the potential V4 (V3> V4). For example, the potential V3 can be a high power supply potential and the potential V4 can be a low power supply potential. The signal B may be an analog signal.

When both the signal A and the signal B are digital signals, the signal B may be a signal having the same digital value as the signal A. In this case, the on-state current of the transistor T may be improved and the operation speed of the circuit including the transistor T may be improved. At this time, the potential V1 of the signal A may be different from the potential V3 of the signal B. Further, the potential V2 of the signal A may be different from the potential V4 of the signal B. For example, when the gate insulating layer corresponding to the gate to which the signal B is input is thicker than the gate insulating layer corresponding to the gate to which the signal A is input, the potential amplitude (V3 to V4) of the signal B is It may be larger than the potential amplitude (V1-V2). By doing so, the influence of the signal A and the influence of the signal B on the conduction state or non-conduction state of the transistor T may be almost the same.

When both the signal A and the signal B are digital signals, the signal B may be a signal having a digital value different from that of the signal A. In this case, the transistor T can be controlled separately by the signal A and the signal B, and a higher function may be realized. For example, when the transistor T is an n-channel transistor, the transistor A is in a conductive state only when the signal A is the potential V1 and the signal B is the potential V3, or the signal A is the potential V2 and the signal B In the case where the transistor is non-conductive only when the potential is V4, the function of a NAND circuit, a NOR circuit, or the like may be realized with one transistor. The signal B may be a signal for controlling the threshold voltage VthA. For example, the signal B may be a signal having a different potential between a period in which a circuit including the transistor T is operating and a period in which the circuit is not operating. The signal B may be a signal having a different potential according to the operation mode of the circuit. In this case, the potential of the signal B may not be switched as frequently as the signal A.

When both the signal A and the signal B are analog signals, the signal B is an analog signal having the same potential as the signal A, an analog signal obtained by multiplying the potential of the signal A by a constant, or the potential of the signal A is added or subtracted by a constant. An analog signal or the like may be used. In this case, the on-state current of the transistor T may be improved and the operation speed of the circuit including the transistor T may be improved. The signal B may be an analog signal different from the signal A. In this case, the transistor T can be controlled separately by the signal A and the signal B, and a higher function may be realized.

The signal A may be a digital signal and the signal B may be an analog signal. The signal A may be an analog signal and the signal B may be a digital signal.

Further, the fixed potential Va may be applied to one gate of the transistor T, and the fixed potential Vb may be applied to the other gate. When a fixed potential is applied to both gates of the transistor T, the transistor T may function as an element equivalent to a resistance element. For example, in the case where the transistor T is an n-channel transistor, the effective resistance of the transistor may be decreased (increased) by increasing (decreasing) the fixed potential Va or the fixed potential Vb. By making both the fixed potential Va and the fixed potential Vb higher (lower), an effective resistance lower (higher) than that obtained by a transistor having only one gate may be obtained.

Note that the transistor 41 may include a pair of gates.

<Modification Example 3 of Memory Cell>
In FIG. 2A, the example in which the transistor 41 is provided between the transistor 32a and the wiring VL is shown; however, the position where the transistor 41 is provided is not limited thereto. It is only necessary that the transistor 41 is connected in series with the transistors 32a and 32b.

For example, as illustrated in FIG. 22A, the transistor 41 may be provided between the transistor 32b and the wiring SL. 22A, the gate of the transistor 41 is connected to the wiring SW, one of the source and the drain is connected to one of the source and the drain of the transistor 32b, and the other of the source and the drain is connected to the wiring SL.

For example, as illustrated in FIG. 22B, the transistor 41 may be provided between the transistor 32a and the transistor 32b. 22B, the gate of the transistor 41 is connected to the wiring SW, one of the source and the drain is connected to one of the source and the drain of the transistor 32a, and the other of the source and the drain is one of the source and the drain of the transistor 32b. Connected with.

2A illustrates a configuration example in which one circuit 40 is provided in the memory cell 20, a plurality of circuits 40 may be provided.

For example, as illustrated in FIG. 22C, the circuit 40 may be provided between the circuit 30a and the wiring VL and between the circuit 30b and the wiring SL. The gate of the transistor 41a included in the circuit 40a is connected to the wiring SWa, one of the source and the drain is connected to one of the source and the drain of the transistor 32a, and the other of the source and the drain is connected to the wiring VL. The gate of the transistor 41b included in the circuit 40b is connected to the wiring SWb, one of the source and the drain is connected to one of the source and the drain of the transistor 32b, and the other of the source and the drain is connected to the wiring SL.

Note that in FIG. 22C, the gate of the transistor 41a is connected to the wiring SWa, and the gate of the transistor 41b is connected to the wiring SWb. However, the gate of the transistor 41a and the gate of the transistor 41b are connected to the same wiring. May be. The wiring SWb may be supplied with a signal corresponding to a signal supplied to the wiring SWa (the same signal as that supplied to the wiring SWa, an inverted signal of the signal supplied to the wiring SWa, or the like). A signal independent of the signal supplied to the wiring SWa may be supplied.

In FIG. 22C, a transistor 41 (see FIG. 22B) provided between the transistor 32a and the transistor 32b can be further added.

This embodiment can be combined with any of the other embodiments as appropriate.

(Embodiment 3)
In this embodiment, an example of a stacked structure of a semiconductor device according to one embodiment of the present invention will be described.

In the above embodiment, a layer including an OS transistor and a layer including a transistor other than the OS transistor can be stacked. In addition, a plurality of layers including OS transistors can be stacked. Specifically, the circuit 30a, the circuit 30b, and the circuit 40 can be stacked in the memory cell 20 of FIGS. For example, the circuit 30a can be stacked on the circuit 40, and the circuit 30b can be stacked on the circuit 30a. Thereby, the area of the memory cell can be reduced.

A structure in which the circuit 30a, the circuit 30b, and the circuit 40 are stacked will be described with reference to FIGS.

<Plan view>
FIG. 7 is a plan view of the memory cell 20 when the circuit 40, the circuit 30a, and the circuit 30b are sequentially stacked.

The layer of the circuit 40 includes a transistor 41. Specifically, the layer of the circuit 40 includes impurity regions 101a and 101b, a conductive layer 103, and a conductive layer 111. The impurity regions 101a and 101b function as a source region or a drain region of the transistor 41. The conductive layer 103 functions as a gate electrode of the transistor 41. The conductive layer 111 functions as the wiring BLa. In addition, the impurity region 101a functions as the wiring VL.

The conductive layer 111 is connected to the conductive layer 133a of the circuit 30a through the connection portion 251. The impurity region 101b is connected to the conductive layer 134b of the circuit 30a through the connection portion 252.

The layer of the circuit 30a includes transistors 31a and 32a. Specifically, the layers of the circuit 30a include semiconductor layers 131 and 132, conductive layers 133a and 133b, conductive layers 134a and 134b, and conductive layers 137 and 138.

The semiconductor layer 131 has a function as an active layer of the transistor 31a, and the semiconductor layer 132 has a function as an active layer of the transistor 32a. The conductive layers 133a and 133b function as a source electrode or a drain electrode of the transistor 31a, and the conductive layers 134a and 134b function as a source electrode or a drain electrode of the transistor 32a. The conductive layer 137 functions as the gate electrode of the transistor 31a, and the conductive layer 138 functions as the gate electrode of the transistor 32a.

The conductive layers 133 a and 133 b are connected to the semiconductor layer 131, and the conductive layers 134 a and 134 b are connected to the semiconductor layer 132. The conductive layer 133 a is connected to the conductive layer 111 of the layer of the circuit 40 through the connection portion 261. The conductive layer 133b is connected to the capacitor 33a (not shown) through the connection portion 262. In addition, the conductive layer 133 b is connected to the conductive layer 138 through the connection portion 263. That is, one of the source and the drain of the transistor 31a is connected to the gate of the transistor 32a. The conductive layer 134a is connected to the conductive layer 184a of the layer of the circuit 30b through the connection portion 265. In other words, one of the source and the drain of the transistor 32a is connected to one of the source and the drain of the transistor 32b. The conductive layer 134b is connected to the impurity region 101b through the connection portion 264. In other words, one of the source and the drain of the transistor 32a is connected to one of the source and the drain of the transistor 41.

The layer of the circuit 30b includes transistors 31b and 32b. Specifically, the layer of the circuit 30b includes semiconductor layers 181 and 182, conductive layers 183a and 183b, conductive layers 184a and 184b, and conductive layers 187 and 188.

The semiconductor layer 181 functions as an active layer of the transistor 31b, and the semiconductor layer 182 functions as an active layer of the transistor 32b. The conductive layers 183a and 183b function as a source electrode or a drain electrode of the transistor 31b, and the conductive layers 184a and 184b function as a source electrode or a drain electrode of the transistor 32b. The conductive layer 187 functions as a gate electrode of the transistor 31b, and the conductive layer 188 functions as a gate electrode of the transistor 32b.

The conductive layers 183 a and 183 b are connected to the semiconductor layer 181, and the conductive layers 184 a and 184 b are connected to the semiconductor layer 182. The conductive layer 183a is connected to a conductive layer (not shown) having a function as the wiring BLb through the connection portion 271. The conductive layer 183b is connected to the capacitor 33b (not shown) through the connection portion 272. Further, the conductive layer 183b is connected to the conductive layer 188 through the connection portion 273. That is, one of the source and the drain of the transistor 31b is connected to the gate of the transistor 32b. The conductive layer 184 a is connected to the conductive layer 134 a of the circuit 30 a through the connection portion 275. That is, one of the source and the drain of the transistor 32b is connected to one of the source and the drain of the transistor 32a. The conductive layer 184b is connected to a conductive layer (not shown) having a function as the wiring SL through the connection portion 274.

As described above, the memory cell 20 can have a structure in which the transistor 41, the transistors 31a and 32a, and the transistors 31b and 32b are sequentially stacked. Thereby, the area of the memory cell 20 can be reduced.

Note that oxide semiconductor layers can be used for the semiconductor layers 131 and 132 and the semiconductor layers 181 and 182. In this case, the transistors 31a and 32a and the transistors 31b and 32b are OS transistors.

<Cross section>
FIG. 8 is a cross-sectional view of the memory cell 20 when the circuit 40, the circuit 30a, and the circuit 30b are sequentially stacked. Here, a cross-sectional view taken along line X1-X2 in FIG. 7 and a cross-sectional view taken along line X3-X4 are shown.

In FIG. 8, a circuit 40, a circuit 30a, and a circuit 30b are sequentially stacked. The circuit 40 includes a transistor 41, the circuit 30a includes transistors 31a and 32a and a capacitor 33a, and the circuit 30b includes transistors 31b and 32b and a capacitor 33b.

The transistor 41 can be a transistor having a channel formation region in a semiconductor film or a semiconductor substrate of silicon, germanium, or the like that is amorphous, microcrystalline, polycrystalline, or single crystal. FIG. 8 illustrates a structure in which the transistor 41 includes a channel formation region in a single crystal semiconductor substrate 100. Note that in the case where the transistor 41 is formed using a silicon thin film, amorphous silicon formed by a vapor deposition method such as a plasma CVD method or a sputtering method, laser irradiation of amorphous silicon, or the like is used for the thin film. Polycrystalline silicon crystallized by the above process, single crystal silicon in which hydrogen ions or the like are implanted into a single crystal silicon wafer and the surface layer portion is peeled off can be used.

As the semiconductor substrate 100 on which the transistor 41 is formed, for example, a silicon substrate, a germanium substrate, a silicon germanium substrate, or the like can be used. Here, as an example, a case where a single crystal silicon substrate is used as the semiconductor substrate 100 will be described.

The transistor 41 may be electrically isolated from other transistors by an element isolation method. As an element isolation method, a selective oxidation method (LOCOS method: Local Oxidation of Silicon method), a trench isolation method (STI method: Shallow Trench Isolation), or the like can be used. Specifically, after forming a trench in the semiconductor substrate 100 by etching or the like, an element isolation region can be provided by embedding an insulator containing silicon oxide or the like in the trench.

The transistor 41 includes impurity regions 101a and 101b, an insulating layer 102 functioning as a gate insulating layer, and a conductive layer 103. Note that a sidewall insulating layer may be provided on a side surface of the conductive layer 103.

An insulating layer 104 is provided over the transistor 41, and an opening is provided in the insulating layer 104. In the opening portion of the insulating layer 104, a conductive layer 105 connected to the conductive layer 103 and a conductive layer 106 connected to the impurity region 101b are provided. The conductive layer 105 is connected to a conductive layer 112 provided over the insulating layer 104, and the conductive layer 106 is connected to a conductive layer 113 provided over the insulating layer 104. In addition, a conductive layer 111 is provided over the insulating layer 104. Note that the conductive layer 112 functions as the wiring SW. Alternatively, the conductive layer 112 is connected to the wiring SW.

An insulating layer 114 and an insulating layer 123 are provided over the conductive layers 111, 112, and 113, and an opening is provided in the insulating layer 114 and the insulating layer 123. A conductive layer 115 connected to the conductive layer 111 and a conductive layer 116 connected to the conductive layer 113 are formed in the openings of the insulating layer 114 and the insulating layer 123.

Note that conductive layers 121 and 122 may be provided over the insulating layer 114. The conductive layer 121 has a region overlapping with the semiconductor layer 131 and functions as a gate electrode of the transistor 31a. The conductive layer 122 has a region overlapping with the semiconductor layer 132 and functions as a gate electrode of the transistor 32a. As described above, the transistors 31a and 32a may include a pair of gate electrodes present with the semiconductor layer interposed therebetween. In this case, the insulating layer 123 functions as a gate insulating layer of the transistors 31a and 32a.

Over the insulating layer 123, semiconductor layers 131 and 132, conductive layers 133 a and 133 b having regions in contact with the semiconductor layer 131, and conductive layers 134 a and 134 b having regions in contact with the semiconductor layer 132 are provided. The conductive layer 133 a is connected to the conductive layer 111 through the conductive layer 115, and the conductive layer 134 b is connected to the conductive layer 113 through the conductive layer 116. Note that the semiconductor layers 131 and 132 can have a structure in which oxide semiconductor layers are stacked. Here, a structure in which the semiconductor layers 131 and 132 include three stacked oxide semiconductor layers is shown.

An insulating layer 135 is provided over the semiconductor layers 131 and 132, the conductive layers 133a and 133b, and the conductive layers 134a and 134b. The insulating layer 135 functions as a gate insulating layer of the transistors 31a and 32a. In addition, conductive layers 137 and 138 are provided over the insulating layer 135. The conductive layer 137 has a region overlapping with the semiconductor layer 131, and the conductive layer 138 has a region overlapping with the semiconductor layer 132. Note that the conductive layer 137 functions as the wiring WLa. Alternatively, the conductive layer 137 is connected to the wiring WLa.

Here, the conductive layer 133 b is connected to the conductive layer 138 through the conductive layer 136. That is, one of the source and the drain of the transistor 31a is connected to the gate of the transistor 32a. Note that the conductive layer 133b may be in direct contact with the conductive layer 138 without the conductive layer 136 interposed therebetween. A node where the conductive layer 133b and the conductive layer 138 are connected corresponds to a node FNa (see FIG. 2 and the like).

An insulating layer 139 is provided over the conductive layers 137 and 138, and an opening is provided in the insulating layer 139. In the opening portion of the insulating layer 139, a conductive layer 140 connected to the conductive layer 133b and a conductive layer 141 connected to the conductive layer 134a are provided. The conductive layer 140 is connected to a conductive layer 151 provided over the insulating layer 139, and the conductive layer 141 is connected to a conductive layer 152 provided over the insulating layer 139.

An insulating layer 153 is provided over the conductive layers 151 and 152. In addition, a conductive layer 161 is provided over the insulating layer 153.

The conductive element 151, the insulating layer 153, and the conductive layer 161 constitute a capacitor element 33 a. The conductive layer 151 functions as one electrode of the capacitor 33a, the insulating layer 153 functions as a dielectric of the capacitor 33a, and the conductive layer 161 functions as the other electrode of the capacitor 33a. Have. Accordingly, one of the source and the drain of the transistor 31a is connected to one electrode of the capacitor 33a through the conductive layer 140. Note that the conductive layer 161 has a function as the wiring CNODEa. Alternatively, the conductive layer 161 is connected to the wiring CNODEa.

An insulating layer 162 and an insulating layer 173 are provided over the conductive layer 161, and openings are provided in the insulating layer 162 and the insulating layer 173. The insulating layer 153 is also provided with an opening. A conductive layer 163 connected to the conductive layer 152 is provided in openings of the insulating layer 153, the insulating layer 162, and the insulating layer 173.

Note that conductive layers 171 and 172 may be provided over the insulating layer 162. The conductive layer 171 has a region overlapping with the semiconductor layer 181 and functions as a gate electrode of the transistor 31b. The conductive layer 172 has a region overlapping with the semiconductor layer 182 and functions as a gate electrode of the transistor 32b. As described above, the transistors 31b and 32b may include a pair of gate electrodes that are provided with a semiconductor layer interposed therebetween. In this case, the insulating layer 173 functions as a gate insulating layer of the transistors 31b and 32b.

Over the insulating layer 173, semiconductor layers 181 and 182, conductive layers 183 a and 183 b having regions in contact with the semiconductor layer 181, and conductive layers 184 a and 184 b having regions in contact with the semiconductor layer 182 are provided. The conductive layer 184 a is connected to the conductive layer 152 through the conductive layer 163. That is, one of the source and the drain of the transistor 32b is connected to one of the source and the drain of the transistor 32a.

An insulating layer 185 is provided over the semiconductor layers 181 and 182, the conductive layers 183a and 183b, and the conductive layers 184a and 184b. The insulating layer 185 functions as a gate insulating layer of the transistors 31b and 32b. In addition, conductive layers 187 and 188 are provided over the insulating layer 185. The conductive layer 187 has a region overlapping with the semiconductor layer 181, and the conductive layer 188 has a region overlapping with the semiconductor layer 182. Note that the semiconductor layers 181 and 182 can have a structure in which oxide semiconductor layers are stacked. Here, a structure in which the semiconductor layers 181 and 182 each include three stacked oxide semiconductor layers is shown.

Here, the conductive layer 183 b is connected to the conductive layer 188 through the conductive layer 186. That is, one of the source and the drain of the transistor 31b is connected to the gate of the transistor 32b. Note that the conductive layer 183b may be in direct contact with the conductive layer 188 without the conductive layer 186 interposed therebetween. A node to which the conductive layer 183b and the conductive layer 188 are connected corresponds to the node FNb (see FIG. 2 and the like). Note that the conductive layer 187 functions as the wiring WLb. Alternatively, the conductive layer 187 is connected to the wiring WLb.

An insulating layer 189 is provided over the conductive layers 187 and 188, and an opening is provided in the insulating layer 189. In the opening portion of the insulating layer 189, a conductive layer 190 connected to the conductive layer 183a, a conductive layer 191 connected to the conductive layer 183b, and a conductive layer 192 connected to the conductive layer 184b are provided. In addition, the conductive layer 190 is connected to the conductive layer 201 provided over the insulating layer 189, the conductive layer 191 is connected to the conductive layer 202 provided over the insulating layer 189, and the conductive layer 192 is insulated. The conductive layer 203 provided over the layer 189 is connected.

An insulating layer 204 is provided over the conductive layers 201, 202, and 203. In addition, a conductive layer 211 is provided over the insulating layer 204.

The conductive layer 202, the insulating layer 204, and the conductive layer 211 constitute a capacitor element 33b. The conductive layer 202 functions as one electrode of the capacitor 33b, the insulating layer 204 functions as a dielectric of the capacitor 33b, and the conductive layer 211 functions as the other electrode of the capacitor 33b. Have. Accordingly, one of the source and the drain of the transistor 31b is connected to one electrode of the capacitor 33b through the conductive layer 191. Note that the conductive layer 211 has a function as the wiring CNODEb. Alternatively, the conductive layer 211 is connected to the wiring CNODEb.

An insulating layer 212 is provided over the conductive layer 211, and an opening is provided in the insulating layer 212. The insulating layer 204 is also provided with an opening. A conductive layer 205 connected to the conductive layer 201 and a conductive layer 206 connected to the conductive layer 203 are provided in openings of the insulating layer 204 and the insulating layer 212.

Conductive layers 221 and 222 are provided over the insulating layer 212. The conductive layer 221 has a function as the wiring BLb, and the conductive layer 222 has a function as the wiring SL.

The conductive layer 221 is connected to the conductive layer 205, and the conductive layer 222 is connected to the conductive layer 206. Thus, the conductive layer 221 is connected to the conductive layer 183a, and the conductive layer 222 is connected to the conductive layer 184b.

As described above, the area of the memory cell 20 can be reduced by stacking the circuit 40, the circuit 30a, and the circuit 30b.

8 shows a configuration in which two layers of circuits 30 (circuits 30a and 30b) are stacked on the circuit 40, three or more layers of circuits 30 may be stacked. Thus, three or more circuits 30 can be mounted on the memory cell 20 as shown in FIG. 5C while suppressing an increase in the area of the memory cell 20. Therefore, the amount of data that can be stored in the memory cell 20 can be increased.

7 and 8 show the configuration in which the circuit 30a and the circuit 30b are formed in different layers, the circuit 30a and the circuit 30b may be formed in the same layer on the circuit 40. That is, the transistors 31b and 32b may be formed in the same layer as the transistors 31a and 32a, and the capacitor 33b may be formed in the same layer as the capacitor 33a.

As described above, the area of the memory cell 20 can be reduced by stacking the transistors included in the memory cell 20.

The structures and methods described in this embodiment can be combined as appropriate with any of the structures and methods described in the other embodiments.

(Embodiment 4)
In this embodiment, a memory device and a computer including the semiconductor device according to one embodiment of the present invention will be described.

<Configuration example of storage device>
FIG. 9 is a block diagram illustrating a configuration example of a memory device including the semiconductor device 10 described in the above embodiment.

A memory device 300 illustrated in FIG. 9 includes a memory cell array 310 provided with a plurality of memory cells 20 described in the above embodiment, a row selection driver 320, a column selection driver 330, and an A / D converter 340. Note that the memory device 300 includes memory cells 20 provided in a matrix of n rows and m columns. In FIG. 9, as the wirings WLa and WLb, the wirings CNODEa and CNODEb, the wiring BL, and the wiring SL, the wirings WLa [1] and WLb [1] in the first row, the wirings CNODEa [1], CNODEb [1], and 2 Lines WLa [2], WLb [2], lines CNODEa [2], CNODEb [2], lines BLa [1], BLb [1] in the first column, lines BLa [2] in the second column, BLb [2], the first row wiring SL [1], and the second row wiring SL [2] are shown.

A memory cell array 310 illustrated in FIG. 9 includes the memory cells 20 described in the above embodiment in a matrix. In addition, description of each structure which the memory cell 20 has is the same as that of FIG. 2, and description is abbreviate | omitted as what uses description in FIG.

The row selection driver 320 is a drive circuit having a function of selectively turning on the transistors 31 of the memory cells 20 in each row and a function of selectively changing the potential of the node FN of the memory cells 20 in each row. . Specifically, it is a circuit that applies selection signals to the wirings WLa and WLb and applies read signals to the wirings CNODEa and CNODEb. With the row selection driver 320, the storage device 300 can select and write data to and from the memory cell 20 for each row.

The column selection driver 330 has a function of selectively writing data to the node FN of the memory cell 20 in each column, a function of precharging the potential of the wiring BL, a function of initializing the potential of the wiring BL, and electrically connecting the wiring BL. This is a drive circuit having a function of bringing it into a floating state. Specifically, this is a circuit having a function of _supplying a write potential corresponding to multi-value data, a precharge voltage V _precharge , an initialization voltage V _{initial, and the} like to the wiring BL through a switch. By including the column selection driver 330, the storage device 300 can select and write data to and from the memory cell 20 for each column. Note that the column selection driver 330 does not have to have all the above functions, and can be omitted as appropriate in accordance with the operation of the memory cell 20.

The A / D converter 340 is a circuit having a function of converting the potential of the wiring BL, which is an analog value, into a digital value and outputting the digital value to the outside. Specifically, it is a circuit having a flash A / D converter. By including the A / D converter 340, the memory device 300 can output the potential of the wiring SL corresponding to the data read from the memory cell 20 to the outside.

Although the A / D converter 340 is described as a flash A / D converter, a successive approximation type, a multi-slope type, or a delta sigma type A / D converter may be used.

[Configuration example of row selection driver]
FIG. 10 is a block diagram illustrating a configuration example of the row selection driver 320 described in FIG.

A row selection driver 320 illustrated in FIG. 10 includes a decoder 321 and a control circuit 322. The control circuit 322 is provided for each row of the wirings WLa and WLb and the wirings CNODEa and CNODEb. The control circuit 322 in each row is connected to the wiring WLa and the wiring CNODEa, or the wiring WLb and the wiring CNODEb.

The decoder 321 is a circuit having a function of outputting a signal for selecting a row in which the wirings WLa and WLb and the wirings CNODEa and CNODEb are provided. Specifically, this is a circuit that receives an address signal Address and selects a control circuit 322 in a predetermined row in accordance with the address signal Address. By including the decoder 321, the row selection driver 320 can select an arbitrary row and write or read data. Note that the decoder 321 may have a function of selecting any one of the plurality of control circuits 322, or may have a function of selecting two or more.

The control circuit 322 is a circuit having a function of outputting a selection signal and a function of selectively outputting a read signal of a row having the wirings WLa and WLb and the wirings CNODEa and CNODEb selected by the decoder 321. Specifically, the control circuit 322 is a circuit that receives a write control signal Write_CONT and a read control signal Read_CONT and selectively outputs a selection signal or a read signal in accordance with the signals. By providing the control circuit 322, the row selection driver 320 can select and output a selection signal or a read signal in the row selected by the decoder 321.

[Example of column selection driver configuration]
FIG. 11 is a block diagram illustrating a configuration example of the column selection driver 330 described in FIG.

The column selection driver 330 illustrated in FIG. 11 includes a decoder 331, a latch circuit 332, a D / A converter 333, a switch circuit 334, a transistor 335, and a transistor 336. The latch circuit 332, the D / A converter 333, the switch circuit 334, the transistor 335, and the transistor 336 are provided for each column. In addition, the switch circuit 334 and the transistor 335 in each column are connected to the wiring BL. In addition, the transistor 336 is connected to the wiring SL.

The decoder 331 is a circuit having a function of selecting a column in which the wiring BL is provided, and sorting and outputting input data. Specifically, the address signal Address and the data Data are input, and the data Data is output to the latch circuit 332 in any row in accordance with the address signal Address. By providing the decoder 331, the column selection driver 330 can select an arbitrary column and write data.

The data Data input to the decoder 331 is a-bit digital data. The a-bit digital data is a signal represented by binary data of 1 or 0 for each bit. For example, in the case of 2-bit digital data, the data is represented by 00, 01, 10, and 11.

The latch circuit 332 is a circuit having a function of temporarily storing input data Data. Specifically, it is a flip-flop circuit that receives a latch signal W_LAT and outputs data Data stored in accordance with the latch signal W_LAT to the D / A converter 333. With the latch circuit 332, the column selection driver 330 can write data at an arbitrary timing.

The D / A converter 333 is a circuit having a function of converting input digital value data Data into analog value data V _data . Specifically, if the number of bits of data Data is 4, the D / A converter 333 is a circuit that converts the data into any one of a plurality of potentials V0 to V15 and outputs it to the switch circuit 334. . By providing the D / A converter 333, the column selection driver 330 can set the data written to the memory cell 20 to a potential corresponding to multi-value data.

Note that V _data output from the D / A converter 333 is data represented by different voltage values. For example, in the case of 2-bit data, it becomes four-value data of 0.5 V, 1.0 V, 1.5 V, and 2.0 V, and can be said to be data represented by any voltage value.

The switch circuit 334 is a circuit having a function of _supplying input data V _data to the wiring BL and a function of electrically floating the wiring BL. Specifically, this is a circuit that includes an analog switch and an inverter and applies the data V _data to the wiring BL under control by the switch control signal Write_SW, and then turns off the analog switch so that the wiring BL is in an electrically floating state. is there. With the switch circuit 334, the column selection driver 330 can hold the wiring BL in an electrically floating state after _supplying the data V _data to the wiring BL.

The transistor 335 is a circuit having a function of applying the initialization voltage V _initial to the wiring BL and a function of electrically floating the wiring BL. Specifically, the switch is a switch that applies the initialization voltage V _initial to the wiring BL under the control of the initialization control signal Init_EN, and then causes the wiring BL to be in an electrically floating state. With the transistor 335, the column selection driver 330 can hold the wiring BL in an electrically floating state after applying the initialization voltage V _initial to the wiring BL.

The transistor 336 is a circuit having a function of applying the precharge voltage V _precharge to the wiring SL and a function of electrically floating the wiring SL. Specifically, the switch is a switch that _{applies the} precharge voltage V _precharge to the wiring SL under the control of the precharge control signal Pre_EN, and then causes the wiring SL to be in an electrically floating state. By including the transistor 336, the column selection driver 330 can hold the wiring SL in an electrically floating state after _{applying the} precharge voltage V _precharge to the wiring SL.

[Configuration example of A / D converter]
FIG. 12 is a block diagram illustrating a configuration example of the A / D converter 340 described with reference to FIG.

An A / D converter 340 illustrated in FIG. 12 includes a comparator 341, an encoder 342, a latch circuit 343, and a buffer 344. The comparator 341, the encoder 342, the latch circuit 343, and the buffer 344 are provided for each column. The buffer 344 in each column outputs data Dout.

The comparator 341 has a function of comparing the potential of the wiring SL and the potentials of the reference voltages Vref0 to Vref14 and determining whether the potential of the wiring SL is a potential corresponding to any of multi-value data. Circuit. Specifically, a plurality of comparators 341 are provided, and each of the comparators 341 is supplied with a potential of the wiring SL and different reference voltages Vref0 to Vref14 to determine whether the potential of the wiring SL is between any potentials. Circuit. By including the comparator 341, the A / D converter 340 can determine whether the potential of the wiring SL corresponds to any of multi-value data.

As an example, the reference voltages Vref0 to Vref14 shown in FIG. 12 are potentials applied when multi-value data is 4-bit, that is, 16-value data.

The encoder 342 is a circuit having a function of generating a multi-bit digital signal based on a signal for determining the potential of the wiring SL output from the comparator 341. Specifically, it is a circuit that performs encoding based on high-level or low-level signals output from a plurality of comparators 341 to generate a digital signal. By providing the encoder 342, the A / D converter 340 can convert the data read from the memory cell 20 into digital value data.

The latch circuit 343 is a circuit having a function of temporarily storing input digital value data. Specifically, it is a flip-flop circuit that receives a latch signal LAT and outputs data stored in accordance with the latch signal LAT to a buffer 344. By including the latch circuit 343, the A / D converter 340 can output data at an arbitrary timing. Note that the latch circuit 343 can be omitted.

The buffer 344 is a circuit having a function of amplifying the data output from the latch circuit 343 and outputting it as an output signal Dout. Specifically, the circuit includes an even number of inverter circuits. By including the buffer 344, the A / D converter 340 can reduce noise with respect to the digital signal. Note that the buffer 344 can be omitted.
<Computer configuration example>
FIG. 13 is a block diagram illustrating a configuration example of a computer having the above storage device.

The computer 400 includes an input device 410, an output device 420, a central processing unit 430, and a storage device (main memory) 440.

The central processing unit 430 includes a control circuit 431, an arithmetic circuit 432, a storage circuit (register) 433, and a storage circuit (cache memory) 434.

The input device 410 has a function of inputting data to the computer 400 from the outside.

The output device 420 has a function of outputting data from the computer 400 to the outside.

The control circuit 431 has a function of outputting a control signal for controlling these devices to the input device 410, the output device 420, and the storage device (main memory) 440.

The arithmetic circuit 432 has a function of performing arithmetic on input data.

The storage device (register) 433 is used to hold data used by the arithmetic circuit 432 for calculation or the like.

The storage device (cache memory) 434 is used for copying frequently used information in the storage device (main memory) 440.

Since the storage device (cache memory) 434 can be accessed faster than the storage device (main memory) 440, the processing speed of the central processing unit 430 is improved. Note that the capacity of the main memory is larger than the capacity of the cache memory, and the capacity of the cache memory is larger than the capacity of the register. In addition, the cache memory and the register operate faster than the main memory. The storage device 300 in FIG. 9 can be used for any of the storage circuit (register) 433, the storage circuit (cache memory) 434, and the storage device (main memory) 440.

The structures and methods described in this embodiment can be combined as appropriate with any of the structures and methods described in the other embodiments.

(Embodiment 5)
In this embodiment, structural examples of OS transistors that can be used for one embodiment of the present invention will be described.

<Configuration example 1>
FIG. 14 shows an example of the structure of the OS transistor. FIG. 14A is a top view illustrating an example of a structure of the OS transistor. 14B is a cross-sectional view taken along the line y1-y2, FIG. 14C is a cross-sectional view taken along the line x1-x2, and FIG. 14D is a cross-sectional view taken along the line x3-x4. Here, the y1-y2 line direction may be referred to as a channel length direction, and the x1-x2 line direction may be referred to as a channel width direction. 14B is a diagram illustrating a cross-sectional structure of the OS transistor in the channel length direction, and FIGS. 14C and 14D are diagrams illustrating a cross-sectional structure of the OS transistor in the channel width direction. is there. Note that some components are omitted in FIG. 14A in order to clarify the device structure.

A transistor 581 which is an OS transistor is formed over an insulating surface. Here, the insulating layer 511 is formed. The insulating layer 511 is formed on the surface of the substrate 510. The transistor 581 is covered with an insulating layer 516. Note that the insulating layer 516 can also be regarded as a component of the transistor 581. The transistor 581 includes an insulating layer 512, an insulating layer 513, an insulating layer 514, an insulating layer 515, semiconductor layers 521 to 523, a conductive layer 530, a conductive layer 531, a conductive layer 532, and a conductive layer 533. Here, the semiconductor layers 521 to 523 are collectively referred to as a semiconductor region 520.

The conductive layer 530 functions as a gate electrode, and the conductive layer 533 functions as a back gate electrode. The conductive layers 531 and 532 function as a source electrode or a drain electrode, respectively. The insulating layer 511 has a function of electrically separating the substrate 510 and the conductive layer 533. The insulating layer 515 constitutes a gate insulating layer, and the insulating layers 513 and 514 constitute a gate insulating layer on the back channel side.

Note that the channel length means, for example, in a top view of a transistor, a region where a semiconductor (or a portion where current flows in the semiconductor when the transistor is on) and a gate electrode overlap, or a region where a channel is formed , The distance between the source (source region or source electrode) and the drain (drain region or drain electrode). Note that in one transistor, the channel length is not necessarily the same in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in this specification and the like, the channel length is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

The channel width is, for example, that a source and a drain face each other in a region where a semiconductor (or a portion where a current flows in the semiconductor when the transistor is on) and a gate electrode overlap, or a region where a channel is formed. The length of the part. Note that in one transistor, the channel width is not necessarily the same in all regions. That is, the channel width of one transistor may not be fixed to one value. Therefore, in this specification, the channel width is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

Note that depending on the structure of the transistor, the channel width in a region where a channel is actually formed (hereinafter referred to as an effective channel width) and the channel width shown in a top view of the transistor (hereinafter, apparent channel width). May be different). For example, in a transistor having a three-dimensional structure, the effective channel width is larger than the apparent channel width shown in the top view of the transistor, and the influence may not be negligible. For example, in a transistor having a fine and three-dimensional structure, the ratio of the channel region formed on the side surface of the semiconductor may be large. In that case, the effective channel width in which the channel is actually formed is larger than the apparent channel width shown in the top view.

By the way, in a transistor having a three-dimensional structure, it may be difficult to estimate an effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, it is difficult to accurately measure the effective channel width when the shape of the semiconductor is not accurately known.

Therefore, in this specification, in the top view of a transistor, an apparent channel width which is a length of a portion where a source and a drain face each other in a region where a semiconductor and a gate electrode overlap with each other is referred to as an “enclosed channel width (SCW : Surrounded Channel Width) ”. In this specification, in the case where the term “channel width” is simply used, it may denote an enclosed channel width or an apparent channel width. Alternatively, in this specification, in the case where the term “channel width” is simply used, it may denote an effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, enclosed channel width, and the like can be determined by obtaining a cross-sectional TEM image and analyzing the image. it can.

Note that in the case where the field-effect mobility of a transistor, the current value per channel width, and the like are calculated and calculated, the calculation may be performed using the enclosed channel width. In that case, the value may be different from that calculated using the effective channel width.

As shown in FIGS. 14B and 14C, the semiconductor region 520 includes a portion in which a semiconductor layer 521, a semiconductor layer 522, and a semiconductor layer 523 are stacked in this order. An insulating layer 515 covers this stacked portion. The conductive layer 530 overlaps with the stacked portion with the insulating layer 513 provided therebetween. The conductive layer 531 and the conductive layer 532 are provided over a stack including the semiconductor layer 521 and the semiconductor layer 523, and are in contact with the upper surface of the stack and the side surface in the channel length direction. The stacked layers of the semiconductor layers 521 and 522 and the conductive layers 531 and 532 are formed through an etching process using the same mask.

The semiconductor layer 523 is formed so as to cover the semiconductor layers 521 and 522 and the conductive layers 531 and 532. The insulating layer 515 covers the semiconductor layer 523. Here, the semiconductor layer 523 and the insulating layer 515 are etched using the same mask.

A conductive layer 530 is formed so as to surround the channel width direction of the stacked portion of the semiconductor layers 521 to 523 with the insulating layer 515 provided therebetween (see FIG. 14C). For this reason, a gate electric field from the vertical direction and a gate electric field from the side surface direction are also applied to the stacked portion. In the transistor 581, a gate electric field refers to an electric field formed by voltage applied to the conductive layer 530 (gate electrode layer). Since the entire stacked portion of the semiconductor layers 521 to 523 can be electrically surrounded by the gate electric field, a channel may be formed (bulk) in the entire semiconductor layer 522. Therefore, the transistor 581 can have a high on-state current. In addition, with the s-channel structure, the high-frequency characteristics of the transistor 581 can be improved. Specifically, the cutoff frequency can be improved.

The s-channel structure can be said to be a structure suitable for a semiconductor device that requires a miniaturized transistor such as an LSI (Large Scale Integration) because a high on-state current can be obtained. The s-channel structure can be said to be a structure suitable for a transistor that requires high-frequency operation because a high on-state current can be obtained. The semiconductor device including the transistor can be a semiconductor device that can operate at high frequency.

By miniaturization of the OS transistor, a highly integrated or small semiconductor device can be provided. For example, the OS transistor preferably has a channel length of 10 nm or more and less than 1 μm, more preferably 10 nm or more and less than 100 nm, more preferably 10 nm or more and less than 70 nm, more preferably 10 nm or more, less than 60 nm, more preferably 10 nm or more, It has a region less than 30 nm. For example, the transistor preferably has a channel width of 10 nm or more and less than 1 μm, more preferably 10 nm or more and less than 100 nm, more preferably 10 nm or more and less than 70 nm, more preferably 10 nm or more and less than 60 nm, more preferably 10 nm or more and 30 nm. With less than.

Note that an oxide semiconductor such as an In—Ga—Zn oxide has lower thermal conductivity than silicon. Therefore, when an oxide semiconductor is used for the semiconductor layer 522, heat is likely to be generated particularly in an end portion on the drain side of the channel formation region of the semiconductor layer 522 or the like. However, since the transistor 581 illustrated in FIG. 14B includes a region where the conductive layers 531 and 532 overlap with the conductive layer 530, the conductive layers 531 and 532 are provided in the vicinity of the channel formation region of the semiconductor layer 522. Accordingly, heat generated in the channel formation region of the semiconductor layer 522 is conducted to the conductive layers 531 and 532. In other words, the channel formation region can be radiated using the conductive layers 531 and 532.

Next, details of each layer shown in FIG. 14 will be described.

[substrate]
As the substrate 510, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria stabilized zirconia substrate), and a resin substrate. The semiconductor substrate is, for example, a single semiconductor substrate such as silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. The semiconductor substrate may be a bulk type, or an SOI (Silicon On Insulator) type in which a semiconductor layer is provided on the semiconductor substrate through an insulating region. The conductor substrate is a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, or the like. Alternatively, there are a substrate having a metal nitride, a substrate having a metal oxide, and the like. Further, a substrate in which an insulator or a semiconductor is provided on an insulator substrate, a substrate in which a conductor or an insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided on a conductor substrate, or the like. Alternatively, a substrate provided with an element may be used. Elements provided on the substrate are a capacitor element, a resistor element, a switch element, a light emitting element, a memory element, and the like.

The substrate 510 may be a flexible substrate. As a method for providing a transistor over a flexible substrate, a transistor is manufactured over a non-flexible substrate (for example, a semiconductor substrate), and then the transistor is peeled and transferred to the substrate 510 which is a flexible substrate. There is also. In that case, a separation layer is preferably provided between the non-flexible substrate and the transistor. Note that a sheet woven with fibers, a film, a foil, or the like may be used as the substrate 510. Further, the substrate 510 may have elasticity. Further, the substrate 510 may have a property of returning to its original shape when bending or pulling is stopped. Or you may have a property which does not return to an original shape. The thickness of the substrate 510 is, for example, 5 μm to 700 μm, preferably 10 μm to 500 μm, and more preferably 15 μm to 300 μm. When the substrate 510 is thinned, the weight of the semiconductor device can be reduced. Further, by reducing the thickness of the substrate 510, it may be stretchable even when glass or the like is used, or may have a property of returning to its original shape when bending or pulling is stopped. Therefore, an impact applied to the semiconductor device on the substrate 510 due to a drop or the like can be reduced. That is, a durable semiconductor device can be provided.

The substrate 510 which is a flexible substrate is, for example, a metal, an alloy, a resin or glass, or a fiber thereof. The flexible substrate is preferably as the linear expansion coefficient is lower because deformation due to the environment is suppressed. For example, a material having a linear expansion coefficient of 1 × 10 ⁻³ / K or less, 5 × 10 ⁻⁵ / K or less, or 1 × 10 ⁻⁵ / K or less may be used for the flexible substrate. Examples of the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, acrylic, and polytetrafluoroethylene (PTFE). In particular, aramid is suitable as a flexible substrate material because of its low linear expansion coefficient.

[Insulation layer]
The insulating layers 511 to 516 are formed of an insulating layer having a single layer structure or a stacked structure. Examples of the material constituting the insulating layer include aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and oxide. There are hafnium and tantalum oxide.

Note that in this specification, an oxynitride refers to a compound having a higher oxygen content than nitrogen, and a nitride oxide refers to a compound having a higher nitrogen content than oxygen. In this specification and the like, oxides used for insulating materials include those having a nitrogen concentration of less than 1 atomic%.

Since the insulating layers 514 and 515 are in contact with the semiconductor region 520, the insulating layers 514 and 515 preferably include an oxide, and particularly preferably include an oxide material from which part of oxygen is released by heating. It is preferable to use an oxide containing oxygen in excess of that in the stoichiometric composition. Part of oxygen is released by heating from the oxide film containing oxygen in excess of the stoichiometric composition. Oxygen released from the insulating layers 514 and 515 is supplied to the semiconductor region 520 that is an oxide semiconductor, so that oxygen vacancies in the oxide semiconductor can be reduced. As a result, variation in electrical characteristics of the transistor can be suppressed and reliability can be improved.

An oxide film containing more oxygen than that in the stoichiometric composition is converted into oxygen atoms at a surface temperature of 100 ° C. or more and 700 ° C. or less by, for example, TDS (Thermal Desorption Spectroscopy) analysis. The oxide film has an oxygen desorption amount of 1.0 × 10 ¹⁸ atoms / cm ³ or more, preferably 3.0 × 10 ²⁰ atoms / cm ³ or more. Note that the surface of the film during the TDS analysis is preferably in the range of 100 ° C. to 700 ° C., or 100 ° C. to 500 ° C.

The insulating layer 513 has a passivation function of preventing oxygen contained in the insulating layer 514 from being combined with a metal contained in the conductive layer 533 and reducing oxygen contained in the insulating layer 514. The insulating layer 516 has a passivation function for preventing oxygen contained in the insulating layer 514 from decreasing.

The insulating layers 511, 513, and 516 preferably have a function of blocking oxygen, hydrogen, water, alkali metal, alkaline earth metal, and the like. By providing the insulating layers 511, 513, and 516, diffusion of oxygen from the semiconductor region 520 to the outside and entry of hydrogen, water, and the like from the outside to the semiconductor region 520 can be prevented. In order to provide such a function, the insulating layers 511, 513, and 516 include, for example, silicon nitride, silicon nitride oxide, aluminum nitride, aluminum nitride oxide, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, and oxide. At least one insulating layer formed of yttrium, yttrium oxynitride, hafnium oxide, hafnium oxynitride, or the like may be provided.

Note that the insulating layer 511 corresponds to the insulating layer 114, the insulating layer 162, or the like in FIG.

[Conductive layer]
The conductive layers 531 and 532 are formed of copper (Cu), tungsten (W), molybdenum (Mo), gold (Au), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), nickel Low (Ni), chromium (Cr), lead (Pb), tin (Sn), iron (Fe), cobalt (Co), ruthenium (Ru), platinum (Pt), iridium (Ir), strontium (Sr) It is preferable to form a single layer or a stacked layer of a conductive film containing a simple substance made of a resistive material, an alloy, or a compound containing these as a main component. In particular, it is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity. Moreover, it is preferable to form with low resistance conductive materials, such as aluminum and copper. Further, it is preferable to use a Cu—Mn alloy because manganese oxide is formed at the interface with the oxygen-containing insulator, and the manganese oxide has a function of suppressing Cu diffusion.

The conductive layer 531 and the conductive layer 532 are manufactured using a hard mask used for forming a stack of the semiconductor layer 521 and the semiconductor layer 522. Therefore, the conductive layer 531 and the conductive layer 532 do not have a region in contact with the side surfaces of the semiconductor layer 521 and the semiconductor layer 522. For example, the semiconductor layers 521 and 522 and the conductive layers 531 and 532 can be manufactured through the following steps. A two-layer oxide semiconductor film which forms the semiconductor layers 521 and 522 is formed. A single-layer or stacked-layer conductive film is formed over the oxide semiconductor film. This conductive film is etched to form a hard mask. With the use of this hard mask, the two-layer oxide semiconductor film is etched to form a stack of the semiconductor layer 521 and the semiconductor layer 522. Next, the hard mask is etched to form the conductive layer 531 and the conductive layer 532.

For the conductive layer 530 and the conductive layer 530, a material similar to that of the conductive layer 531 and the conductive layer 532 can be used.

[Semiconductor layer]
The semiconductor layer 522 is an oxide semiconductor containing indium (In), for example. For example, when the semiconductor layer 522 contains indium, the carrier mobility (electron mobility) increases. The semiconductor layer 522 preferably contains the element M. The element M is preferably aluminum (Al), gallium (Ga), yttrium (Y), tin (Sn), or the like. Other elements applicable to the element M include boron (B), silicon (Si), titanium (Ti), iron (Fe), nickel (Ni), germanium (Ge), zirconium (Zr), molybdenum (Mo ), Lanthanum (La), cerium (Ce), neodymium (Nd), hafnium (Hf), tantalum (Ta), tungsten (W), and the like. However, the element M may be a combination of a plurality of the aforementioned elements. The element M is an element having a high binding energy with oxygen, for example. For example, it is an element whose binding energy with oxygen is higher than that of indium. Alternatively, the element M is an element having a function of increasing the energy gap of the oxide semiconductor, for example. The semiconductor layer 522 preferably contains zinc (Zn). An oxide semiconductor may be easily crystallized when it contains zinc.

Note that the semiconductor layer 522 is not limited to the oxide semiconductor containing indium. The semiconductor layer 522 may be an oxide semiconductor containing zinc, an oxide semiconductor containing gallium, an oxide semiconductor containing tin, or the like that does not contain indium, such as zinc tin oxide and gallium tin oxide. . For the semiconductor layer 522, an oxide with a wide energy gap is used, for example. The energy gap of the semiconductor layer 522 is, for example, not less than 2.5 eV and not more than 4.2 eV, preferably not less than 2.8 eV and not more than 3.8 eV, more preferably not less than 3 eV and not more than 3.5 eV. The semiconductor region 520 is preferably formed using a CAAC-OS (C Axis Crystalline Oxide Semiconductor), which will be described later. Alternatively, at least the semiconductor layer 522 is preferably formed using a CAAC-OS.

For example, the semiconductor layer 521 and the semiconductor layer 523 are oxide semiconductors including one or more elements other than oxygen included in the semiconductor layer 522 or two or more elements. Since the semiconductor layer 521 and the semiconductor layer 523 are formed using one or more elements other than oxygen constituting the semiconductor layer 522 or two or more elements, the interface between the semiconductor layer 521 and the semiconductor layer 522, and the semiconductor layer 522 and the semiconductor layer 523. Interface states are difficult to form at the interface.

Note that when the semiconductor layer 521 is an In-M-Zn oxide, when the sum of In and M is 100 atomic%, In is preferably less than 50 atomic%, M is higher than 50 atomic%, and more preferably, In is 25 atomic%. And M is higher than 75 atomic%. In the case where the semiconductor layer 521 is formed by a sputtering method, a sputtering target that satisfies the above composition is preferably used. For example, In: M: Zn = 1: 3: 2 is preferable.

In the case where the semiconductor layer 522 is an In—M—Zn oxide, when the sum of In and M is 100 atomic%, In is preferably higher than 25 atomic%, M is less than 75 atomic%, and more preferably In is 34 atomic%. Higher, and M is less than 66 atomic%. In the case where the semiconductor layer 522 is formed by a sputtering method, a sputtering target that satisfies the above composition is preferably used. For example, In: M: Zn = 1: 1: 1, In: M: Zn = 1: 1: 1.2, In: M: Zn = 2: 1: 3, In: M: Zn = 3: 1: 2, In: M: Zn = 4: 2: 4.1 is preferable. In particular, when an atomic ratio of In: Ga: Zn = 4: 2: 4.1 is used as a sputtering target, the atomic ratio of the semiconductor layer 522 formed is In: Ga: Zn = 4: 2: There are cases where there are 3 neighborhoods.

In the case where the semiconductor layer 523 is an In—M—Zn oxide, when the sum of In and M is 100 atomic%, In is preferably less than 50 atomic%, M is higher than 50 atomic%, and more preferably In is 25 atomic%. Less than, M is higher than 75 atomic%. Note that the semiconductor layer 523 may be formed using the same kind of oxide as the semiconductor layer 521. Note that the semiconductor layer 521 and / or the semiconductor layer 523 may not contain indium in some cases. For example, the semiconductor layer 521 and / or the semiconductor layer 523 may be gallium oxide.

With reference to FIG. 15, functions and effects of the semiconductor region 520 formed by stacking the semiconductor layer 521, the semiconductor layer 522, and the semiconductor layer 523 will be described. FIG. 15A is a partially enlarged view of FIG. 14B and is an enlarged view of an active layer (channel portion) of the transistor 581. FIG. FIG. 15B illustrates an energy band structure of an active layer formation region of the transistor 581 and illustrates an energy band structure of a portion indicated by a dotted line Z1-Z2 in FIG.

In FIG. 15B, Ec514, Ec521, Ec522, Ec523, and Ec515 indicate the energy at the lower end of the conduction band of the insulating layer 514, the semiconductor layer 521, the semiconductor layer 522, the semiconductor layer 523, and the insulating layer 515, respectively.

Here, the difference between the vacuum level and the energy at the bottom of the conduction band (also referred to as “electron affinity”) is defined as the energy gap based on the difference between the vacuum level and the energy at the top of the valence band (also referred to as ionization potential). Subtracted value. The energy gap can be measured using a spectroscopic ellipsometer. The energy difference between the vacuum level and the upper end of the valence band can be measured using an ultraviolet photoelectron spectroscopy (UPS) apparatus.

Since the insulating layers 515 and 516 are insulators, Ec513 and Ec512 are closer to the vacuum level (smaller electron affinity) than Ec521, Ec522, and Ec523.

For the semiconductor layer 522, an oxide having an electron affinity higher than those of the semiconductor layers 521 and 523 is used. For example, as the semiconductor layer 522, the electron affinity of the semiconductor layer 521 and the semiconductor layer 523 is 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less, more preferably 0.15 eV or more and 0.4 eV or less. Large oxides are used. Note that the electron affinity is the difference between the vacuum level and the energy at the bottom of the conduction band.

Note that indium gallium oxide has a small electron affinity and a high oxygen blocking property. Therefore, the semiconductor layer 523 preferably contains indium gallium oxide. The gallium atom ratio [Ga / (In + Ga)] is, for example, 70% or more, preferably 80% or more, and more preferably 90% or more. At this time, when a gate voltage is applied, a channel is formed in the semiconductor layer 522 having high electron affinity among the semiconductor layer 521, the semiconductor layer 522, and the semiconductor layer 523.

Here, in some cases, there is a mixed region of the semiconductor layer 521 and the semiconductor layer 522 between the semiconductor layer 521 and the semiconductor layer 522. Further, in some cases, there is a mixed region of the semiconductor layer 522 and the semiconductor layer 523 between the semiconductor layer 522 and the semiconductor layer 523. In the mixed region, the interface state density is low. Therefore, the stack of the semiconductor layer 521, the semiconductor layer 522, and the semiconductor layer 523 has a band structure in which energy continuously changes (also referred to as a continuous junction) in the vicinity of each interface.

At this time, electrons move mainly in the semiconductor layer 522 instead of in the semiconductor layer 521 and the semiconductor layer 523. As described above, when the interface state density at the interface between the semiconductor layer 521 and the semiconductor layer 522 and the interface state density at the interface between the semiconductor layer 522 and the semiconductor layer 523 are reduced, electrons move in the semiconductor layer 522. The on-state current of the transistor can be increased without being disturbed.

The on-state current of the transistor can be increased as the factor that hinders the movement of electrons is reduced. For example, when there is no factor that hinders the movement of electrons, it is estimated that electrons move efficiently. Electron movement is inhibited, for example, even when the physical unevenness of the channel formation region is large. Alternatively, for example, even when the density of defect states in a region where a channel is formed is high, the movement of electrons is inhibited.

In order to increase the on-state current of the transistor 581, for example, a root mean square (RMS) value in the range of 1 μm × 1 μm of the upper surface or the lower surface of the semiconductor layer 522 (formation surface, here, the semiconductor layer 521). The roughness may be less than 1 nm, preferably less than 0.6 nm, more preferably less than 0.5 nm, more preferably less than 0.4 nm. The average surface roughness (also referred to as Ra) in the range of 1 μm × 1 μm is less than 1 nm, preferably less than 0.6 nm, more preferably less than 0.5 nm, and more preferably less than 0.4 nm. The maximum height difference (also referred to as PV) in the range of 1 μm × 1 μm is less than 10 nm, preferably less than 9 nm, more preferably less than 8 nm, and more preferably less than 7 nm. RMS roughness, Ra, and PV can be measured using a scanning probe microscope system.

For example, in the case where the semiconductor layer 522 has oxygen vacancies (also referred to as V 2 _O ), donor levels may be formed by entry of hydrogen into sites of oxygen vacancies. The following may be referred to a state that has entered the hydrogen to oxygen vacancies in the site as V _{O H.} Since V _O H scatters electrons, it causes a reduction in the on-state current of the transistor. Note that oxygen deficient sites are more stable when oxygen enters than when hydrogen enters. Therefore, the on-state current of the transistor can be increased by reducing oxygen vacancies in the semiconductor layer 522 in some cases.

For example, in certain depths of the semiconductor layer 522, or in a region of the semiconductor layer 522, secondary ion mass spectrometry: the hydrogen concentration measured in (SIMS Secondary Ion Mass Spectrometry) is, 1 × ¹⁰ 16 atoms / cm ³ or more, 2 × 10 ²⁰ atoms / cm ³ or less, preferably 1 × 10 ¹⁶ atoms / cm ³ or more, 5 × 10 ¹⁹ atoms / cm ³ or less, more preferably 1 × 10 ¹⁶ atoms / cm ³ or more, 1 × 10 ¹⁹ atoms / cm ³ or less, more preferably 1 × 10 ¹⁶ atoms / cm ³ or more and 5 × 10 ¹⁸ atoms / cm ³ or less.

In order to reduce oxygen vacancies in the semiconductor layer 522, for example, there is a method in which excess oxygen contained in the insulating layer 515 is moved to the semiconductor layer 522 through the semiconductor layer 521. In this case, the semiconductor layer 521 is preferably a layer having oxygen permeability (a layer through which oxygen passes or permeates).

In the case where the transistor 581 has an s-channel structure, a channel is formed in the entire semiconductor layer 522. Accordingly, the thicker the semiconductor layer 522, the larger the channel region. That is, as the semiconductor layer 522 is thicker, the on-state current of the transistor 581 can be increased.

In order to increase the on-state current of the transistor 581, the thickness of the semiconductor layer 523 is preferably as small as possible. The semiconductor layer 523 may have a region of less than 10 nm, preferably 5 nm or less, more preferably 3 nm or less, for example. On the other hand, the semiconductor layer 523 has a function of blocking entry of elements other than oxygen (such as hydrogen and silicon) included in the adjacent insulator into the semiconductor layer 522 where a channel is formed. Therefore, the semiconductor layer 523 preferably has a certain thickness. The semiconductor layer 523 may have a region with a thickness of 0.3 nm or more, preferably 1 nm or more, more preferably 2 nm or more, for example. The semiconductor layer 523 preferably has a property of blocking oxygen in order to suppress outward diffusion of oxygen released from the insulating layer 515 or the like.

In order to increase the reliability of the transistor 581, the semiconductor layer 521 is preferably thick and the semiconductor layer 523 is preferably thin. The semiconductor layer 521 may have a region with a thickness of 10 nm or more, preferably 20 nm or more, more preferably 40 nm or more, more preferably 60 nm or more, for example. By increasing the thickness of the semiconductor layer 521, the distance from the interface between the adjacent insulator and the semiconductor layer 521 to the semiconductor layer 522 where a channel is formed can be increased. However, since the productivity of the semiconductor device may be reduced, the semiconductor layer 521 may have a region with a thickness of 200 nm or less, preferably 120 nm or less, more preferably 80 nm or less, for example.

In order to impart stable electric characteristics to the transistor 581, it is effective to reduce the impurity concentration in the semiconductor region 520 so that the semiconductor layer 522 is intrinsic or substantially intrinsic. Note that in this specification and the like, in the case where an oxide semiconductor is substantially intrinsic, the carrier density of the oxide semiconductor is less than 8 × 10 ¹¹ pieces / cm ³ , preferably less than 1 × 10 ¹¹ pieces / cm ^3. More preferably, it is less than 1 × 10 ¹⁰ pieces / cm ³ and 1 × 10 ⁻⁹ pieces / cm ³ or more.

In an oxide semiconductor, hydrogen, nitrogen, carbon, silicon, and metal elements other than main components are impurities. For example, hydrogen and nitrogen contribute to the formation of donor levels and increase the carrier density. Silicon contributes to the formation of impurity levels in an oxide semiconductor. The impurity level becomes a trap and may deteriorate the electrical characteristics of the transistor. Therefore, it is preferable to reduce the impurity concentration in the semiconductor layer 521, the semiconductor layer 522, and the semiconductor layer 523, or at each interface.

For example, a region having a silicon concentration of 1 × 10 ¹⁶ atoms / cm ³ or more and less than 1 × 10 ¹⁹ atoms / cm ³ is provided between the semiconductor layer 522 and the semiconductor layer 521. Silicon concentration more be less than 1 × ¹⁰ 16 atoms / cm ³ or more and 5 × ¹⁰ 18 atoms / cm ³ is preferably less than 1 × ¹⁰ 16 atoms / cm ³ or more and 2 × ¹⁰ 18 atoms / cm ³ preferable. Further, a region having a silicon concentration of 1 × 10 ¹⁶ atoms / cm ³ or more and less than 1 × 10 ¹⁹ atoms / cm ³ is provided between the semiconductor layer 522 and the semiconductor layer 523. The silicon concentration is preferably 1 × 10 ¹⁶ atoms / cm ³ or more and less than 5 × 10 ¹⁸ atoms / cm ^3, more preferably 1 × 10 ¹⁶ atoms / cm ³ or more and less than 2 × 10 ¹⁸ atoms / cm ³ . The silicon concentration can be measured by SIMS, for example.

In order to reduce the hydrogen concentration in the semiconductor layer 522, it is preferable to reduce the hydrogen concentrations in the semiconductor layer 521 and the semiconductor layer 523. The semiconductor layer 521 and the semiconductor layer 523 have a region where the hydrogen concentration is 1 × 10 ¹⁶ atoms / cm ³ or more and 2 × 10 ²⁰ atoms / cm ³ or less. The hydrogen concentration is preferably 1 × 10 ¹⁶ atoms / cm ³ or more and 5 × 10 ¹⁹ atoms / cm ³ or less, more preferably 1 × 10 ¹⁶ atoms / cm ³ or more and 1 × 10 ¹⁹ atoms / cm ³ or less. More preferably, it is at least 10 ¹⁶ atoms / cm ³ and at most 5 × 10 ¹⁸ atoms / cm ³ . The hydrogen concentration can be measured by SIMS, for example.

In order to reduce the nitrogen concentration of the semiconductor layer 522, it is preferable to reduce the nitrogen concentrations of the semiconductor layer 521 and the semiconductor layer 523. The semiconductor layer 521 and the semiconductor layer 523 have a region where the nitrogen concentration is 1 × 10 ¹⁶ atoms / cm ³ or more and less than 5 × 10 ¹⁹ atoms / cm ³ . The nitrogen concentration is preferably 1 × 10 ¹⁶ atoms / cm ³ or more and 5 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × 10 ¹⁶ atoms / cm ³ or more and 1 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × More preferably, it is 10 ¹⁶ atoms / cm ³ or more and 5 × 10 ¹⁷ atoms / cm ³ or less. The nitrogen concentration can be measured by SIMS.

Further, the off-state current of the transistor in which the oxide semiconductor purified as described above is used for a channel formation region is extremely small. For example, when the voltage between the source and the drain is about 0.1 (V), 5 (V), or 10 (V), the off-current normalized by the channel width of the transistor is several yA / μm. To a few zA / μm.

FIG. 14 shows an example in which the semiconductor region 520 has three layers, but the invention is not limited to this. For example, a two-layer structure without the semiconductor layer 521 or the semiconductor layer 523 may be employed. Alternatively, a semiconductor layer similar to the semiconductor layers 521 to 523 may be provided over or under the semiconductor layer 521, or over or under the semiconductor layer 523, so that a four-layer structure can be obtained. Alternatively, a semiconductor layer similar to the semiconductor layers 521 to 523 is provided at any two or more positions on the semiconductor layer 521, below the semiconductor layer 521, above the semiconductor layer 523, and below the semiconductor layer 523, and has an n-layer structure. (N is an integer of 5 or more).

In the case where the transistor 581 is a transistor without a back gate electrode, the conductive layer 533 is not necessarily provided. In this case, the insulating layers 512 and 513 are not provided, and the insulating layer 513 may be formed over the insulating layer 511.

<Configuration example 2>
In the transistor 581 illustrated in FIG. 14, the semiconductor layer 523 and the insulating layer 515 can be etched using the conductive layer 530 as a mask. A structural example of an OS transistor which has undergone such a process is illustrated in FIG. In the transistor 582 illustrated in FIG. 16A, end portions of the semiconductor layer 523 and the insulating layer 515 are substantially aligned with end portions of the conductive layer 530. The semiconductor layer 523 and the insulating layer 513 exist only below the conductive layer 530.

<Configuration example 3>
A transistor 583 illustrated in FIG. 16B has a device structure in which a conductive layer 535 and a conductive layer 536 are added to the transistor 582. A pair of electrodes as a source electrode and a drain electrode of the transistor 582 includes a stacked layer of a conductive layer 535 and a conductive layer 531 and a stacked layer of a conductive layer 536 and a conductive layer 532.

The conductive layers 535 and 536 are formed of a single layer or stacked layers of conductors. For example, boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum and tungsten One or more kinds of conductors can be used. The conductor may be an alloy film or a compound, including a conductor including aluminum, a conductor including copper and titanium, a conductor including copper and manganese, a conductor including indium, tin and oxygen, and titanium and nitrogen. A conductor or the like may be used.

The conductive layers 535 and 536 may have a property of transmitting visible light. Alternatively, the conductive layers 535 and 536 may have a property of not transmitting visible light, ultraviolet light, infrared light, or X-rays by reflection or absorption. With such a property, variation in electrical characteristics of the transistor 582 due to stray light may be suppressed in some cases.

As the conductive layers 535 and 536, a layer that does not form a Schottky barrier with the semiconductor layer 522 or the like may be preferably used. Thus, the on-state characteristics of the transistor 583 can be improved.

As the conductive layers 535 and 536, a film having higher resistance than the conductive layers 531 and 532 may be preferably used. The conductive layers 535 and 536 may preferably have lower resistance than the channel of the transistor 583 (specifically, the semiconductor layer 522). For example, the resistivity of the conductive layers 535 and 536 may be 0.1 Ωcm to 100 Ωcm, 0.5 Ωcm to 50 Ωcm, or 1 Ωcm to 10 Ωcm. By setting the resistivity of the conductive layers 535 and 536 within the above range, electric field concentration at the boundary between the channel and the drain can be reduced. Therefore, variation in electrical characteristics of the transistor 583 can be reduced. In addition, the punch-through current due to the electric field generated from the drain can be reduced. Therefore, saturation characteristics can be improved even in a transistor with a short channel length. Note that in a circuit configuration in which the source and the drain are not interchanged, it may be preferable to dispose only one of the conductive layers 535 and 536 (for example, the drain side).

<Configuration example 4>
In the transistor 581 illustrated in FIG. 14, the conductive layer 531 and the conductive layer 532 may be in contact with the side surfaces of the semiconductor layers 521 and 522. An example of such a structure is shown in FIG. In the transistor 584 illustrated in FIG. 16C, the conductive layer 531 and the conductive layer 532 are in contact with the side surface of the semiconductor layer 521 and the side surface of the semiconductor layer 522.

<Crystal structure of oxide semiconductor film>
The structure of the oxide semiconductor film included in the semiconductor region 520 is described below. Note that in this specification, when a crystal is trigonal or rhombohedral, it is represented as a hexagonal system.

An oxide semiconductor film is roughly classified into a non-single-crystal oxide semiconductor film and a single-crystal oxide semiconductor film. The non-single-crystal oxide semiconductor film refers to a CAAC-OS film, a polycrystalline oxide semiconductor film, a microcrystalline oxide semiconductor film, an amorphous oxide semiconductor film, or the like.

In this specification, “parallel” refers to a state in which two straight lines are arranged at an angle of −10 ° to 10 °. Therefore, the case of −5 ° to 5 ° is also included. Further, “substantially parallel” means a state in which two straight lines are arranged at an angle of −30 ° to 30 °. “Vertical” refers to a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included. Further, “substantially vertical” means a state in which two straight lines are arranged at an angle of 60 ° to 120 °.

[CAAC-OS film]
The CAAC-OS film is one of oxide semiconductor films having a plurality of c-axis aligned crystal parts.

Confirming a plurality of crystal parts by observing a bright field image of a CAAC-OS film and a combined analysis image (also referred to as a high-resolution TEM image) of a CAAC-OS film with a transmission electron microscope (TEM: Transmission Electron Microscope). Can do. On the other hand, a clear boundary between crystal parts, that is, a crystal grain boundary (also referred to as a grain boundary) cannot be confirmed even by a high-resolution TEM image. Therefore, it can be said that the CAAC-OS film is unlikely to decrease in electron mobility due to crystal grain boundaries.

When a high-resolution TEM image of a cross section of the CAAC-OS film is observed from a direction substantially parallel to the sample surface, it can be confirmed that metal atoms are arranged in layers in the crystal part. Each layer of metal atoms has a shape reflecting unevenness of a surface (also referred to as a formation surface) or an upper surface on which the CAAC-OS film is formed, and is arranged in parallel with the formation surface or the upper surface of the CAAC-OS film. .

On the other hand, when a high-resolution TEM image of a plane of the CAAC-OS film is observed from a direction substantially perpendicular to the sample surface, it can be confirmed that metal atoms are arranged in a triangular shape or a hexagonal shape in a crystal part. However, there is no regularity in the arrangement of metal atoms between different crystal parts.

When structural analysis is performed on a CAAC-OS film using an X-ray diffraction (XRD) apparatus, for example, in the analysis of a CAAC-OS film having an InGaZnO ₄ crystal by an out-of-plane method, A peak may appear when the diffraction angle (2θ) is around 31 °. Since this peak is attributed to the (009) plane of the InGaZnO ₄ crystal, the crystal of the CAAC-OS film has c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the formation surface or the top surface. Can be confirmed.

In the analysis of a CAAC-OS film having an InGaZnO ₄ crystal by an out-of-plane method, a peak may also appear when 2θ is around 36 ° in addition to a peak where 2θ is around 31 °. A peak at 2θ of around 36 ° indicates that a crystal having no c-axis alignment is included in part of the CAAC-OS film. The CAAC-OS film preferably has a peak at 2θ of around 31 ° and no peak at 2θ of around 36 °.

The CAAC-OS film is an oxide semiconductor film with a low impurity concentration. The impurity is an element other than the main component of the oxide semiconductor film, such as hydrogen, carbon, silicon, or a transition metal element. In particular, an element such as silicon, which has a stronger bonding force with oxygen than the metal element included in the oxide semiconductor film, disturbs the atomic arrangement of the oxide semiconductor film by depriving the oxide semiconductor film of oxygen, and has crystallinity. It becomes a factor to reduce. In addition, heavy metals such as iron and nickel, argon, carbon dioxide, and the like have large atomic radii (or molecular radii). Therefore, if they are contained inside an oxide semiconductor film, the atomic arrangement of the oxide semiconductor film is disturbed, resulting in crystallinity. It becomes a factor to reduce. Note that the impurity contained in the oxide semiconductor film might serve as a carrier trap or a carrier generation source.

The CAAC-OS film is an oxide semiconductor film with a low density of defect states. For example, oxygen vacancies in the oxide semiconductor film can serve as carrier traps or can generate carriers by capturing hydrogen.

A low impurity concentration and a low density of defect states (small number of oxygen vacancies) is called high purity intrinsic or substantially high purity intrinsic. A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has few carrier generation sources, and thus can have a low carrier density. Therefore, a transistor including the oxide semiconductor film is unlikely to have electrical characteristics (also referred to as normally-on) in which the threshold voltage is negative. A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has few carrier traps. Therefore, a transistor including the oxide semiconductor film has a small change in electrical characteristics and has high reliability. Note that the charge trapped in the carrier trap of the oxide semiconductor film takes a long time to be released, and may behave as if it were a fixed charge. Therefore, a transistor including an oxide semiconductor film with a high impurity concentration and a high density of defect states may have unstable electrical characteristics.

An OS transistor using a CAAC-OS film has little variation in electrical characteristics due to irradiation with visible light or ultraviolet light.

[Microcrystalline oxide semiconductor film]
The microcrystalline oxide semiconductor film includes a region where a crystal part can be confirmed and a region where a clear crystal part cannot be confirmed in a high-resolution TEM image. In most cases, a crystal part included in the microcrystalline oxide semiconductor film has a size of 1 nm to 100 nm, or 1 nm to 10 nm. In particular, an oxide semiconductor film including a nanocrystal (nc) that is a microcrystal of 1 nm to 10 nm, or 1 nm to 3 nm is referred to as an nc-OS (nanocrystalline Oxide Semiconductor) film. In the nc-OS film, for example, a crystal grain boundary may not be clearly confirmed in a high-resolution TEM image.

The nc-OS film has periodicity in atomic arrangement in a very small region (eg, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In addition, the nc-OS film does not have regularity in crystal orientation between different crystal parts. Therefore, orientation is not seen in the whole film. Therefore, the nc-OS film may not be distinguished from an amorphous oxide semiconductor film depending on an analysis method. For example, when structural analysis is performed on the nc-OS film using an XRD apparatus using X-rays having a diameter larger than that of the crystal part, a peak indicating a crystal plane is not detected in the analysis by the out-of-plane method. Further, when electron diffraction (also referred to as limited-field electron diffraction) using an electron beam with a probe diameter larger than that of the crystal part (eg, 50 nm or more) is performed on the nc-OS film, a diffraction pattern such as a halo pattern is observed. Is done. On the other hand, when nanobeam electron diffraction is performed on the nc-OS film using an electron beam having a probe diameter that is close to or smaller than the size of the crystal part, spots are observed. In addition, when nanobeam electron diffraction is performed on the nc-OS film, a region with high luminance may be observed so as to draw a circle (in a ring shape). Further, when nanobeam electron diffraction is performed on the nc-OS film, a plurality of spots may be observed in the ring-shaped region.

The nc-OS film is an oxide semiconductor film that has higher regularity than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. Note that the nc-OS film does not have regularity in crystal orientation between different crystal parts. Therefore, the nc-OS film has a higher density of defect states than the CAAC-OS film.

[Amorphous oxide semiconductor film]
An amorphous oxide semiconductor film is an oxide semiconductor film having an irregular atomic arrangement in the film and having no crystal part. An oxide semiconductor film having an amorphous state such as quartz is an example.

In the amorphous oxide semiconductor film, a crystal part cannot be confirmed in a high-resolution TEM image. When structural analysis using an XRD apparatus is performed on an amorphous oxide semiconductor film, a peak indicating a crystal plane is not detected by analysis using an out-of-plane method. Further, when electron diffraction is performed on the amorphous oxide semiconductor film, a halo pattern is observed. Further, when nanobeam electron diffraction is performed on an amorphous oxide semiconductor film, no spot is observed and a halo pattern is observed.

An oxide semiconductor film may have a structure exhibiting physical properties between the nc-OS film and the amorphous oxide semiconductor film. An oxide semiconductor film having such a structure is particularly referred to as an amorphous-like oxide semiconductor (a-like OS) film.

In the a-like OS film, a void (also referred to as a void) may be observed in a high-resolution TEM image. Moreover, in a high-resolution TEM image, it has the area | region which can confirm a crystal part clearly, and the area | region which cannot confirm a crystal part. In some cases, the a-like OS film is crystallized by a small amount of electron irradiation as observed by a TEM, and a crystal part is grown. On the other hand, in the case of a good-quality nc-OS film, crystallization due to a small amount of electron irradiation comparable to that observed by TEM is hardly observed.

The size of the crystal part of the a-like OS film and the nc-OS film can be measured using a high-resolution TEM image. For example, a crystal of InGaZnO ₄ has a layered structure, and two Ga—Zn—O layers are provided between In—O layers. The unit cell of InGaZnO ₄ crystal has a structure in which a total of nine layers including three In—O layers and six Ga—Zn—O layers are stacked in the c-axis direction. Therefore, the distance between these adjacent layers is approximately the same as the lattice spacing (also referred to as d value) of the (009) plane, and the value is determined to be 0.29 nm from crystal structure analysis. Therefore, paying attention to the lattice fringes in the high-resolution TEM image, each lattice fringe corresponds to the ab plane of the InGaZnO ₄ crystal in a portion where the interval between the lattice fringes is 0.28 nm or more and 0.30 nm or less.

An oxide semiconductor film may have a different film density for each structure. For example, when the composition of a certain oxide semiconductor film is known, the structure of the oxide semiconductor film can be estimated by comparing with the film density of a single crystal oxide semiconductor film having the same composition as the composition. For example, the film density of the a-like OS film is 78.6% or more and less than 92.3% with respect to the film density of the single crystal oxide semiconductor film. For example, the film density of the nc-OS film and the film density of the CAAC-OS film are 92.3% or more and less than 100% with respect to the film density of the single crystal oxide semiconductor film. Note that it is difficult to form an oxide semiconductor film with a film density of less than 78% with respect to the single crystal oxide semiconductor film.

The above will be described using a specific example. For example, in an oxide semiconductor film that satisfies In: Ga: Zn = 1: 1: 1 [atomic ratio], the film density of single crystal InGaZnO ₄ having a rhombohedral structure is 6.357 g / cm ³ . Therefore, for example, in an oxide semiconductor film satisfying In: Ga: Zn = 1: 1: 1 [atomic ratio], the film density of the a-like OS film is 5.0 g / cm ³ or more and 5.9 g / cm ^3. Less than. For example, in the oxide semiconductor film satisfying In: Ga: Zn = 1: 1: 1 [atomic ratio], the film density of the nc-OS film and the film density of the CAAC-OS film are 5.9 g / cm ^3. The above is less than 6.3 g / cm ³ .

Note that a single crystal oxide semiconductor film having the same composition may not exist. In that case, by combining single crystal oxide semiconductor films having different compositions at an arbitrary ratio, the film density corresponding to the single crystal oxide semiconductor film having a desired composition can be calculated. The film density of the single crystal oxide semiconductor film having a desired composition may be calculated using a weighted average with respect to the ratio of combining single crystal oxide semiconductor films having different compositions. Note that the film density is preferably calculated by combining as few kinds of single crystal oxide semiconductor films as possible.

Note that the oxide semiconductor film may be a stacked film including two or more of an amorphous oxide semiconductor film, an a-like OS film, a microcrystalline oxide semiconductor film, and a CAAC-OS film, for example. .

<Film formation method>
As a method for forming an insulating layer, a conductive layer, a semiconductor layer, or the like included in a semiconductor device, a sputtering method or a plasma CVD method is typical. It can be formed by other methods, for example, a thermal CVD method. As the thermal CVD method, for example, an MOCVD (Metal Organic Chemical Deposition) method or an ALD (Atomic Layer Deposition) method can be used.

The thermal CVD method has an advantage that no defect is generated due to plasma damage because it is a film forming method that does not use plasma. In the thermal CVD method, the inside of the chamber may be under atmospheric pressure or reduced pressure, and the source gas and the oxidant may be simultaneously sent into the chamber, reacted in the vicinity of the substrate or on the substrate, and deposited on the substrate. .

Further, in the ALD method, film formation may be performed by setting the inside of the chamber to atmospheric pressure or reduced pressure, sequentially introducing source gases for reaction into the chamber, and repeating the order of introducing the gases. For example, by switching each switching valve (also referred to as a high-speed valve), two or more kinds of source gases are sequentially supplied to the chamber, so that a plurality of kinds of source gases are not mixed with the first source gas at the same time or thereafter. An active gas (such as argon or nitrogen) is introduced, and a second source gas is introduced. When the inert gas is introduced at the same time, the inert gas becomes a carrier gas, and the inert gas may be introduced at the same time when the second raw material gas is introduced. Further, instead of introducing the inert gas, the second raw material gas may be introduced after the first raw material gas is exhausted by evacuation. The first source gas is adsorbed on the surface of the substrate to form a first monoatomic layer, and reacts with a second source gas introduced later, so that the second monoatomic layer becomes the first monoatomic layer. A thin film is formed by being stacked on the atomic layer. By repeating this gas introduction sequence a plurality of times until the desired thickness is achieved, a thin film having excellent step coverage can be formed. Since the thickness of the thin film can be adjusted by the number of times the gas introduction sequence is repeated, precise film thickness adjustment is possible, which is suitable for manufacturing a fine FET.

Thermal CVD methods such as the MOCVD method and the ALD method can form the conductive film and the semiconductor film disclosed in the embodiments described so far, for example, when an InGaZnO _x (X> 0) film is formed. For this, trimethylindium, trimethylgallium, and dimethylzinc are used. Note that the chemical formula of trimethylindium is (CH ₃ ) ₃ In. The chemical formula of trimethylgallium is (CH ₃ ) ₃ Ga. The chemical formula of dimethylzinc is (CH ₃ ) ₂ Zn. The invention is not limited to these combinations, triethyl gallium (chemical formula _{(C 2 H 5) 3 Ga} ) in place of trimethyl gallium can also be used, diethylzinc (Formula instead of dimethylzinc _{(C 2} H _{5) 2} Zn) can also be used.

For example, in the case where a tungsten film is formed by a film forming apparatus using ALD, an initial tungsten film is formed by repeatedly introducing WF ₆ gas and B ₂ H ₆ gas successively, and then WF ₆ gas and H _2. A tungsten film is formed using a gas. Note that SiH ₄ gas may be used instead of B ₂ H ₆ gas.

For example, in the case where an oxide semiconductor film, for example, an InGaZnO _x (X> 0) film is formed by a film formation apparatus using ALD, In (CH ₃ ) ₃ gas and O ₃ gas are sequentially introduced and InO is sequentially introduced. _Two layers are formed, then a GaO layer is formed using Ga (CH ₃ ) ₃ gas and O ₃ gas, and then a ZnO layer is formed using Zn (CH ₃ ) ₂ gas and O ₃ gas. Note that the order of these layers is not limited to this example. Alternatively, a mixed compound layer such as an InGaO ₂ layer, an InZnO ₂ layer, a GaInO layer, a ZnInO layer, or a GaZnO layer may be formed by mixing these gases. Incidentally, instead of the O ₃ gas may be used the H _{2 O} gas obtained by bubbling an inert gas, such as Ar, but better to use an O ₃ gas containing no H are preferred. In addition, In (C ₂ H ₅ ) ₃ gas may be used instead of In (CH ₃ ) ₃ gas. Further, Ga (C ₂ H ₅ ) ₃ gas may be used instead of Ga (CH ₃ ) ₃ gas. Alternatively, Zn (CH ₃ ) ₂ gas may be used.

The structures and methods described in this embodiment can be combined as appropriate with any of the structures and methods described in the other embodiments.

(Embodiment 6)
In this embodiment, an electronic component, an electronic device including the electronic component, and the like will be described as an example of a semiconductor device.

FIG. 17A is a flowchart illustrating an example of a method for manufacturing an electronic component. The electronic component is also referred to as a semiconductor package, an IC package, or a package. This electronic component has a plurality of standards and names depending on the terminal take-out direction and the shape of the terminal. Therefore, in this embodiment, an example will be described.

A semiconductor device including a transistor is completed by combining a plurality of parts that can be attached to and detached from a printed circuit board through an assembly process (post-process). The post-process can be completed through each process shown in FIG. Specifically, after the element substrate obtained in the previous process is completed (step S1), a dicing process for separating the substrate into a plurality of chips is performed (step S2). Before the substrate is divided into a plurality of substrates, the substrate is thinned to reduce the warpage of the substrate in the previous process and to reduce the size of the component.

A die bonding process is performed in which the chip is picked up, mounted on the lead frame, and bonded (step S3). Bonding between the chip and the lead frame in the die bonding process may be performed with resin or tape. As the bonding method, a method suitable for the product may be selected. In the die bonding step, a chip may be mounted on the interposer and bonded. In the wire bonding process, the leads of the lead frame and the electrodes on the chip are electrically connected by metal thin wires (wires) (step S4). A silver wire or a gold wire can be used as the metal thin wire. Wire bonding may be either ball bonding or wedge bonding.

The wire-bonded chip is subjected to a molding process that is sealed with an epoxy resin or the like (step S5). The lead frame lead is plated. Then, the lead is cut and molded (step S6). The plating process prevents rusting of the lead, and soldering when mounted on a printed circuit board later can be performed more reliably. A printing process (marking) is performed on the surface of the package (step S7). An electronic component is completed through an inspection process (step S8) (step S9). By incorporating the semiconductor device of the above embodiment, a small electronic component with low power consumption can be provided.

FIG. 17B is a schematic perspective view of the completed electronic component. As an example, FIG. 17B shows QFP (Quad Flat Package). An electronic component 800 illustrated in FIG. 17B illustrates a lead 801 and a circuit portion 803. The circuit portion 803 includes, for example, the semiconductor device, the memory device, and other logic circuits described in the above embodiments. The electronic component 800 is mounted on a printed circuit board 802, for example. A plurality of such electronic components 800 are combined and each is electrically connected on the printed circuit board 802 so that the electronic component 800 can be mounted on an electronic device. The completed circuit board 804 is provided inside an electronic device or the like. For example, the electronic component 800 can be used in a processing unit that executes various processes such as a random access memory that stores data, a CPU, an MCU, an FPGA, and a wireless IC. By mounting the electronic component 800, the power consumption of the electronic device can be reduced. Alternatively, the electronic device can be easily downsized.

Therefore, the electronic component 800 includes digital signal processing, software radio, avionics (electronic equipment related to aviation such as communication equipment, navigation system, autopilot, and flight management system), ASIC prototyping, medical image processing, voice recognition, It can be applied to electronic parts (IC chips) of electronic devices in a wide range of fields such as cryptography, bioinformatics (biological information science), emulators of mechanical devices, and radio telescopes in radio astronomy. Examples of such an electronic device include a display device, a personal computer (PC), an image reproducing device including a recording medium (a device for reproducing a recording medium such as a DVD, a Blu-ray disc, a flash memory, and an HDD, and an image display device). Apparatus having a display portion of the above. In addition, an electronic device that can use the semiconductor device according to one embodiment of the present invention includes a mobile phone, a portable game machine, a portable data terminal, an electronic book terminal, a camera (a video camera, a digital still camera, or the like). Wearable display devices (head mounted, goggles, glasses, armbands, bracelets, necklaces, etc.) navigation systems, sound playback devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, printers Examples include multifunction peripherals, automatic teller machines (ATMs), and vending machines. Specific examples of these electronic devices are shown in FIGS.

A portable game machine 900 illustrated in FIG. 18A includes a housing 901, a housing 902, a display portion 903, a display portion 904, a microphone 905, a speaker 906, operation keys 907, a stylus 908, and the like.

A portable information terminal 910 illustrated in FIG. 18B includes a housing 911, a housing 912, a display portion 913, a display portion 914, a connection portion 915, operation keys 916, and the like. The display portion 913 is provided in the housing 911 and the display portion 914 is provided in the housing 912. The housing 911 and the housing 912 are connected by the connection unit 915, and the angle between the housing 911 and the housing 912 can be changed by the connection unit 915. Therefore, the image displayed on the display portion 913 may be switched depending on the angle between the housing 911 and the housing 912 in the connection portion 915. Further, a display device with a touch panel may be used for the display portion 913 and / or the display portion 914.

A laptop PC 920 illustrated in FIG. 18C includes a housing 921, a display portion 922, a keyboard 923, a pointing device 924, and the like.

An electric refrigerator-freezer 930 illustrated in FIG. 18D includes a housing 931, a refrigerator door 932, a refrigerator door 933, and the like.

A video camera 940 illustrated in FIG. 18E includes a housing 941, a housing 942, a display portion 943, operation keys 944, a lens 945, a connection portion 946, and the like. The operation key 944 and the lens 945 are provided on the housing 941, and the display portion 943 is provided on the housing 942. The housing 941 and the housing 942 are connected to each other by a connection portion 946, and an angle between the housing 941 and the housing 942 can be changed by the connection portion 946. Depending on the angle of the housing 942 with respect to the housing 941, the orientation of the image displayed on the display portion 943 may be changed, and the display / non-display of the image may be switched.

An automobile 950 illustrated in FIG. 18F includes a vehicle body 951, wheels 952, a dashboard 953, lights 954, and the like.

The structures and methods described in this embodiment can be combined as appropriate with any of the structures and methods described in the other embodiments.

(Example)
In this embodiment, measurement results of characteristics of an OS transistor that can be used in the above embodiments will be described.

<Temperature characteristics>
First, the temperature characteristics of the OS transistor and the Si transistor were measured. FIG. 19A shows the measurement results of the temperature dependence of the gate voltage V _G -drain current _ID characteristic and the gate voltage V _G -field effect mobility μ _FE characteristic of the OS transistor. FIG. 19B shows a gate voltage V _G -drain current _ID characteristic and a gate voltage V _G -field effect mobility μ _FE characteristic of a transistor including silicon in a channel formation region (hereinafter also referred to as Si transistor). The temperature dependence of is shown. 19A and 19B show the measurement results of the electrical characteristics at temperatures of -25 ° C, 50 ° C, and 150 ° C. Further, the drain voltage _{V D} is set to 1V.

Note that the electrical characteristics of the OS transistor illustrated in FIG. 19A are graphs where the channel length L = 0.45 μm, the channel width W = 10 μm, and the thickness of the oxide film of the gate insulating layer is Tox = 20 nm. In addition, the electrical characteristics of the Si transistor illustrated in FIG. 19B are graphs when L = 0.35 μm, W = 10 μm, and Tox = 20 nm.

The oxide semiconductor layer of the OS transistor was formed using an In—Ga—Zn-based oxide, and the Si transistor was formed using a silicon wafer.

19A and 19B that the temperature dependence of the rising gate voltage is small in the OS transistor. Further, the off-state current of the OS transistor is equal to or lower than the measurement lower limit (I ₀ ) regardless of the temperature, but the off-state current of the Si transistor has a large temperature dependency. The measurement result in FIG. 19B shows that at 150 ° C., the off-current of the Si transistor increases and the current on / off ratio does not increase sufficiently.

19A and 19B, the semiconductor device according to one embodiment of the present invention is formed using an OS transistor, so that the semiconductor device can be operated even at a temperature of 150 ° C. or higher. Therefore, a semiconductor device with excellent heat resistance can be realized.

<Pressure resistance>
Next, measurement was performed on the pressure resistance of the OS transistor and the Si transistor. FIG. 20 shows the measurement results of the VD-ID characteristics of the Si transistor and the OS transistor. In FIG. 20, in order to compare the breakdown voltage of the Si transistor and the OS transistor under the same conditions, the channel length is 0.9 μm, the channel width is 10 μm, and the thickness of the gate insulating film using silicon oxide is 20 nm. It is said. The gate voltage is 2V.

As shown in FIG. 20, in the Si transistor, the avalanche breakdown occurs at about 4V with respect to the increase in the drain voltage, whereas in the OS transistor, the avalanche breakdown does not occur up to about 26V with respect to the increase in the drain voltage. It can be seen that a constant current can be passed through.

FIG. 21A shows the measurement result of the VD-ID characteristics of the OS transistor when the gate voltage is changed. FIG. 21B shows the measurement result of the VD-ID characteristics of the Si transistor when the gate voltage is changed. In order to compare the breakdown voltage under the same conditions for the Si transistor and the OS transistor, the channel length is 0.9 μm, the channel width is 10 μm, and the thickness of the gate insulating film using silicon oxide is 20 nm. . For the OS transistor in FIG. 21A, measurement was performed by changing the gate voltage to 0.1 V, 2.06 V, 4.02 V, 5.98 V, and 7.94 V. In the Si transistor of FIG. 21B, measurement was performed by changing the gate voltage to 0.1 V, 1.28 V, 2.46 V, 3.64 V, and 4.82 V.

As shown in FIGS. 21A and 21B, in the Si transistor, the avalanche breakdown occurs at about 4V to 5V with respect to the increase in the drain voltage, whereas in the OS transistor, the increase in the drain voltage. It can be seen that a constant current can flow without avalanche breakdown at about 9V.

20 and 21 that the OS transistor has a higher breakdown voltage than the Si transistor. Therefore, in the memory cell according to one embodiment of the present invention, the range of voltages that can be taken by the node FN can be widened to increase the distribution of potentials that can be held.

DESCRIPTION OF SYMBOLS 10 Semiconductor device 20 Memory cell 21 Holding part 21a Holding part 21b Holding part 22 Transistor 23 Capacitor 30 Circuit 30a Circuit 30b Circuit 30c Circuit 31 Transistor 31a Transistor 31b Transistor 32a Transistor 32b Transistor 33a Capacitor 33b Capacitor 40 Circuit 40a Circuit 40b Circuit 41 transistor 41a transistor 41b transistor 100 semiconductor substrate 101a impurity region 101b impurity region 102 insulating layer 103 conductive layer 104 insulating layer 105 conductive layer 106 conductive layer 111 conductive layer 112 conductive layer 113 conductive layer 114 insulating layer 115 conductive layer 116 conductive layer 121 conductive Layer 122 Conductive layer 123 Insulating layer 131 Semiconductor layer 132 Semiconductor layer 133a Conductive layer 133b Conductive layer 134a Conductive layer 134b Conductive layer 135 Edge layer 136 conductive layer 137 conductive layer 138 conductive layer 139 insulating layer 140 conductive layer 141 conductive layer 151 conductive layer 152 conductive layer 153 insulating layer 161 conductive layer 162 insulating layer 163 conductive layer 171 conductive layer 172 conductive layer 173 insulating layer 181 semiconductor layer 182 Semiconductor layer 183a Conductive layer 183b Conductive layer 184a Conductive layer 184b Conductive layer 185 Insulating layer 186 Conductive layer 187 Conductive layer 188 Conductive layer 189 Insulating layer 190 Conductive layer 191 Conductive layer 192 Conductive layer 201 Conductive layer 202 Conductive layer 203 Conductive layer 204 Insulating Layer 205 conductive layer 206 conductive layer 211 conductive layer 212 insulating layer 221 conductive layer 222 conductive layer 251 connecting portion 252 connecting portion 261 connecting portion 262 connecting portion 263 connecting portion 264 connecting portion 265 connecting portion 271 connecting portion 272 connecting portion 273 connecting portion 274 Connection part 275 Connection part 3 0 storage device 310 memory cell array 320 row selection driver 321 decoder 322 control circuit 330 column selection driver 331 decoder 332 latch circuit 333 D / A converter 334 switch circuit 335 transistor 336 transistor 340 A / D converter 341 comparator 342 encoder 343 latch circuit 344 buffer 400 Computer 410 Input device 420 Output device 430 Central processing unit 431 Control circuit 432 Arithmetic circuit 510 Substrate 511 Insulating layer 512 Insulating layer 513 Insulating layer 514 Insulating layer 515 Insulating layer 516 Insulating layer 520 Semiconductor region 521 Semiconductor layer 522 Semiconductor layer 523 Semiconductor Layer 530 conductive layer 531 conductive layer 532 conductive layer 533 conductive layer 535 conductive layer 536 conductive layer 581 transistor 582 transistor 5 83 Transistor 584 Transistor 800 Electronic component 801 Lead 802 Printed circuit board 803 Circuit unit 804 Circuit board 900 Portable game machine 901 Case 902 Case 903 Display unit 904 Display unit 905 Microphone 906 Speaker 907 Operation key 908 Stylus 910 Portable information terminal 911 Case Body 912 Case 913 Display unit 914 Display unit 915 Connection unit 916 Operation key 920 Notebook PC
921 Housing 922 Display unit 923 Keyboard 924 Pointing device 930 Electric refrigerator-freezer 931 Housing 932 Refrigerating room door 933 Freezing room door 940 Video camera 941 Housing 942 Housing 943 Display unit 944 Operation key 945 Lens 946 Connection unit 950 Automobile 951 Car body 952 Wheel 953 Dashboard 954 Light

Claims (7)

Having a memory cell;
The memory cell includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first capacitor, and a second capacitor. Have
A gate of the first transistor is electrically connected to a first wiring;
One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor and the first capacitor;
The other of the source and the drain of the first transistor is electrically connected to a second wiring;
One of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the fourth transistor;
The other of the source and the drain of the second transistor is electrically connected to one of the source and the drain of the fifth transistor;
A gate of the third transistor is electrically connected to a third wiring;
One of a source and a drain of the third transistor is electrically connected to a gate of the fourth transistor and the second capacitor;
The other of the source and the drain of the third transistor is electrically connected to a fourth wiring;
The other of the source and the drain of the fourth transistor is electrically connected to a fifth wiring;
A gate of the fifth transistor is electrically connected to a sixth wiring;
A semiconductor device in which the other of the source and the drain of the fifth transistor is electrically connected to a seventh wiring. In claim 1,
A function of supplying a first potential corresponding to a potential of a gate of the second transistor to the fifth wiring;
A semiconductor device having a function of supplying a second potential corresponding to a gate potential of the fourth transistor to the fifth wiring; In claim 2,
The supply of the first potential to the fifth wiring is performed when the fourth transistor and the fifth transistor are on.
A semiconductor device in which the second potential is supplied to the fifth wiring when the second transistor and the fifth transistor are on. In any one of Claims 1 thru | or 3,
The first transistor and the third transistor are semiconductor devices each including an oxide semiconductor in a channel formation region. In any one of Claims 1 thru | or 4,
The first transistor and the second transistor are provided on the fifth transistor;
The third transistor and the fourth transistor are semiconductor devices provided on the first transistor and the second transistor. A memory device comprising the semiconductor device according to claim 1 and a drive circuit. A semiconductor device according to any one of claims 1 to 5, or a storage device according to claim 6,
An electronic device having a display portion, a microphone, a speaker, or operation keys.