JP2016111203A - Thin film transistor substrate and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin film transistor substrate in which a thin film transistor which uses an oxide semiconductor for a channel layer is formed on a substrate, and which can improve voltage withstanding characteristics of a gate insulation layer without destabilizing electric characteristics of the thin film transistor.SOLUTION: A TFT substrate 20 comprises a substrate 110, a gate electrode 120, an oxide semiconductor layer 140, and a gate insulation layer 130 arranged between the gate electrode 120 and the oxide semiconductor layer 140. The gate insulation layer 130 includes a first insulation layer 131, a second insulation layer 132 and a third insulation layer 133 which are sequentially arranged from the gate electrode 120 side and composed of silicon nitride films, in which each of the first through third insulation layers has an atomic weight within a predetermined range; and a difference obtained by subtracting a film thickness of the third insulation layer 133 from a film thickness of the second insulation layer 132 is equal to or less than 50 nm; and a film density of the second insulation layer 132 is lower than each film density of the first insulation layer 131 and a third insulation layer 133.SELECTED DRAWING: Figure 4

Description

  The present disclosure relates to a thin film transistor substrate using an oxide semiconductor and a manufacturing method thereof.

  Thin film transistors (TFTs) are widely used as switching elements or driving elements in active matrix display devices such as liquid crystal display devices or organic EL (Electro-Luminescence) display devices. In addition, with the increase in screen size of display devices, the size of glass substrates on which TFTs are stacked is increasing. Here, when a TFT is provided on a large glass substrate, there is a problem that the yield is deteriorated due to a short circuit between different layer wirings. In order to solve this problem, in a TFT using amorphous silicon as a channel layer, a technique is known in which a gate insulating layer is composed of a plurality of different types of silicon nitride films (Non-Patent Document 1).

Yue Kuo, “Thin Film Transistors with Graded SiNx Gate Dielectrics”, J. Am. Electrochem. Soc. , 141 (4), 1061 (1994)

  In recent years, research and development have been actively conducted on a structure in which an oxide semiconductor such as zinc oxide (ZnO), indium gallium oxide (InGaO), or indium gallium zinc oxide (InGaZnO) is used for a channel layer of a TFT. . A TFT using an oxide semiconductor for a channel layer has a high carrier mobility even in an amorphous state and can be formed by a low-temperature process. Even in a TFT using such an oxide semiconductor for a channel layer, there is a problem that the yield is deteriorated due to a short circuit between different layer wirings, as in the case of using amorphous silicon.

  The present disclosure provides a thin film transistor substrate in which a thin film transistor using an oxide semiconductor for a channel layer is formed on a substrate, and can improve the withstand voltage characteristics of a gate insulating layer, and a method for manufacturing the same.

In order to solve the above problems, one embodiment of a thin film transistor substrate according to the present disclosure includes a substrate, a gate electrode disposed above the substrate, a gate electrode, and a gate electrode disposed at a position facing the gate electrode. An oxide semiconductor layer used as a channel layer; and a gate insulating layer disposed between the gate electrode and the oxide semiconductor layer. The gate insulating layer includes a first insulating layer sequentially disposed from the gate electrode side; A second insulating layer and a third insulating layer, wherein the first insulating layer, the second insulating layer, and the third insulating layer are formed of a silicon nitride film, and nitrogen in the first insulating layer, the second insulating layer, and the third insulating layer; The amount of hydrogen atoms bonded to the atoms and silicon atoms is 3.3 × 10 ²² cm ⁻³ or less and 2.3 × 10 ²¹ cm ⁻³ or less, respectively. The difference obtained by subtracting the thickness of the insulating layer is 50 The film density of the second insulating layer is smaller than that of the first insulating layer and the third insulating layer.

One embodiment of a method for manufacturing a thin film transistor substrate according to the present disclosure is a method for manufacturing a thin film transistor substrate, the step of forming a gate electrode above the substrate, and the upper side of the gate electrode and facing the gate electrode. A step of forming an oxide semiconductor layer used as a channel layer at a position and a step of forming a gate insulating layer between the gate electrode and the oxide semiconductor layer. Including a step of forming a first insulating layer, a second insulating layer, and a third insulating layer, which are sequentially arranged from the electrode side, wherein the first insulating layer, the second insulating layer, and the third insulating layer are formed of a silicon nitride film. , the first insulating layer, a hydrogen atom amount attached to a nitrogen atom and a silicon atom in the second insulating layer and the third insulating layer, respectively, 3.3 × ¹⁰ 22 ^{cm -3} or less, and, 2.3 × 10 ² cm ^-3 or less, the film thickness difference obtained by subtracting the from the film thickness of the second insulating layer a third insulating layer has a 50nm or less, the film density of the second insulating layer, the first insulating layer and the third insulating layer Less than the film density.

  According to the present disclosure, it is possible to provide a thin film transistor substrate in which a thin film transistor using an oxide semiconductor as a channel layer is formed on a substrate, and capable of improving a withstand voltage characteristic of a gate insulating layer, and a method for manufacturing the same. it can.

FIG. 1 is a partially cutaway perspective view of an organic EL display device according to an embodiment. FIG. 2 is a perspective view illustrating an example of a pixel bank of the organic EL display device according to the embodiment. FIG. 3 is an electric circuit diagram showing a configuration of a pixel circuit in the organic EL display device according to the embodiment. FIG. 4 is a schematic cross-sectional view showing an example of the thin film transistor substrate according to the embodiment. FIG. 5A is a schematic cross-sectional view showing the manufacturing process of the thin film transistor substrate according to the embodiment. FIG. 5B is a schematic cross-sectional view illustrating the manufacturing process of the thin film transistor substrate according to the embodiment. FIG. 5C is a schematic cross-sectional view illustrating the manufacturing process of the thin film transistor substrate according to the embodiment. FIG. 5D is a schematic cross-sectional view illustrating the manufacturing process of the thin film transistor substrate according to the embodiment. FIG. 6 is a top view showing the arrangement of the silicon substrate on which the silicon nitride film is formed during film formation. FIG. 7 is a table showing the deposition parameters of the silicon nitride film and the physical property values of the deposited silicon nitride film. FIG. 8 is a table showing the deposition parameters of the silicon oxide film and the physical property values of the deposited silicon oxide film. FIG. 9A is a graph showing measurement results of electrical characteristics of a thin film transistor in which a silicon nitride film and a silicon oxide film formed under the condition A are used as a gate insulating layer. FIG. 9B is a graph showing measurement results of electrical characteristics of a thin film transistor using a silicon nitride film and a silicon oxide film formed under the condition B as a gate insulating layer. FIG. 9C is a graph showing measurement results of electrical characteristics of a thin film transistor using a silicon nitride film and a silicon oxide film formed under the condition C as gate insulating layers. FIG. 10 is a table showing the deposition parameters of the silicon nitride film and the physical property values of the deposited silicon nitride film. FIG. 11 is a graph showing the relationship between the pressure in film formation and each physical property value. FIG. 12 is a graph showing the relationship between the silane gas flow rate and each physical property value. FIG. 13A is a graph showing measurement results of electrical characteristics of a thin film transistor using a silicon nitride film and a silicon oxide film formed under the condition A as a gate insulating layer. FIG. 13B is a graph showing measurement results of electrical characteristics of the thin film transistor using the silicon nitride film formed under the condition A4 as the stress relaxation layer of the gate insulating layer. FIG. 14 is a graph showing the H ₂ desorption profile with respect to the substrate temperature with the film formation conditions as parameters. FIG. 15 is a graph showing the amount of H ₂ desorption for each film forming condition when the substrate temperature is 350 ° C. FIG. 16 is a table showing the conditions of the film thickness of each insulating layer in the thin film transistor to be measured, the electrical characteristics of the thin film transistor manufactured under the conditions, and the warpage amount of the TFT substrate. FIG. 17A is a graph showing measurement results of electric characteristics of the thin film transistor manufactured under the condition (a) shown in FIG. FIG. 17B is a graph showing measurement results of electric characteristics of the thin film transistor manufactured under the condition (b) shown in FIG. FIG. 17C is a graph showing measurement results of electrical characteristics of the thin film transistor manufactured under the condition (c) illustrated in FIG. FIG. 17D is a graph showing measurement results of electric characteristics of the thin film transistor manufactured under the condition (d) shown in FIG. FIG. 17E is a graph showing measurement results of electric characteristics of the thin film transistor manufactured under the condition (e) shown in FIG. FIG. 17F is a graph illustrating measurement results of electrical characteristics of the thin film transistor manufactured under the condition (f) illustrated in FIG. FIG. 18 is a graph showing the relationship between the ratio of the thickness of the second insulating layer to the total thickness of the gate insulating layer, and the variation in the amount of warpage of the TFT substrate and the threshold value Vth.

(Knowledge that became the basis of this disclosure)
As a structure for suppressing short-circuits between different layer wirings in TFTs using amorphous silicon as the channel layer, a thick silicon nitride film with a high film formation rate is deposited as a bulk layer of the silicon nitride film constituting the gate insulating layer. As a layer at the interface with the amorphous silicon layer, a structure in which a dense silicon nitride film with a low film formation rate is deposited can be considered.

  With this structure, it is possible to suppress a short circuit between different layer wirings by increasing the thickness of the gate insulating layer without deteriorating productivity, and to improve the interface characteristics between the gate insulating layer and the amorphous silicon layer. .

  The above configuration is expected to be effective in reducing short-circuiting between different layer wirings even in a TFT using an oxide semiconductor for a channel layer. However, the present inventor has found that the following problems occur when the above configuration is applied to a TFT using an oxide semiconductor for a channel layer.

  In the TFT to which the above configuration is applied, an increase in the thickness of the silicon nitride film in the gate insulating layer increases the amount of hydrogen atoms that are detached from the silicon nitride film and injected into the channel layer. Here, in a TFT using amorphous silicon as a channel layer, a large number of active dangling bonds present at the interface between the amorphous silicon layer and the silicon nitride film (gate insulating layer) due to hydrogen atoms desorbed from the silicon nitride film ( Dangling bonds) are terminated. Thereby, since the interface state and the fixed charge can be reduced, the electrical characteristics of the TFT can be improved.

  On the other hand, also in a TFT using an oxide semiconductor as a channel layer, an increase in the thickness of the silicon nitride film in the gate insulating layer increases the amount of hydrogen atoms that are detached from the silicon nitride film and injected into the oxide semiconductor layer. Then, the electrical characteristics of the oxide semiconductor layer are destabilized by the hydrogen atoms. Specifically, when hydrogen atoms are injected into the oxide semiconductor layer, metal atoms (for example, indium atoms In) and oxygen atoms (O) in the oxide semiconductor layer are formed by hydrogen atoms (H). The bond is broken, and an O—H bond (for example, an In—O—H bond) or an oxygen defect is generated. Accordingly, carriers increase due to the occurrence of the defect and the like, so that the threshold value (threshold voltage Vth) of the thin film transistor easily shifts in the negative direction, and the electrical characteristics of the thin film transistor become unstable.

  Therefore, the present disclosure is a thin film transistor substrate in which a thin film transistor using an oxide semiconductor for a channel layer is formed on a substrate, and improves the withstand voltage characteristics of the gate insulating layer without destabilizing the electrical characteristics of the thin film transistor. Provided is a thin film transistor substrate and a method for manufacturing the same.

  Hereinafter, embodiments will be described in detail with reference to the drawings as appropriate. However, more detailed explanation than necessary may be omitted. For example, detailed descriptions of already well-known matters and overlapping descriptions for substantially the same configuration may be omitted. This is to avoid the following description from becoming unnecessarily redundant and to facilitate understanding by those skilled in the art.

  In addition, the inventors provide the accompanying drawings and the following description in order for those skilled in the art to fully understand the present disclosure, and these are intended to limit the subject matter described in the claims. is not.

  Each figure is a mimetic diagram and is not necessarily illustrated strictly. Moreover, in each figure, the same code | symbol is attached | subjected about the same structural member.

  Further, in this specification, the terms “upper” and “lower” do not refer to the upward direction (vertically upward) and the downward direction (vertically downward) in absolute space recognition, but are based on the stacking order in the stacking configuration. Is used as a term defined by the relative positional relationship. The terms “upper” and “lower” are used not only when two components are spaced apart from each other and there is another component between the two components. The present invention is also applied when two components are in close contact with each other and are in contact with each other.

(Embodiment)
[1. Organic EL display device]
First, the configuration of the organic EL display device 10 according to the present embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a partially cutaway perspective view of an organic EL display device 10 according to the present embodiment. FIG. 2 is a perspective view showing an example of a pixel bank of the organic EL display device 10 according to the present embodiment.

[1-1. Constitution]
As shown in FIG. 1, an organic EL display device 10 includes a TFT substrate (TFT array substrate) 20 on which a plurality of thin film transistors are arranged, an anode 41 that is a lower electrode, and an EL layer 42 that is a light emitting layer made of an organic material. And it is comprised by the laminated structure with the organic EL element (light emission part) 40 consisting of the cathode 43 which is a transparent upper electrode.

  A plurality of pixels 30 are arranged in a matrix on the TFT substrate 20, and each pixel 30 is provided with a pixel circuit 31.

  The organic EL element 40 is formed corresponding to each of the plurality of pixels 30, and the light emission of each organic EL element 40 is controlled by the pixel circuit 31 provided in each pixel 30. The organic EL element 40 is formed above an interlayer insulating layer (planarization layer) formed so as to cover a plurality of thin film transistors.

  The organic EL element 40 has a configuration in which an EL layer 42 is disposed between an anode 41 and a cathode 43. A hole transport layer is further laminated between the anode 41 and the EL layer 42, and an electron transport layer is further laminated between the EL layer 42 and the cathode 43. Note that another organic functional layer may be provided between the anode 41 and the cathode 43.

  Each pixel 30 is driven and controlled by a respective pixel circuit 31. The TFT substrate 20 includes a plurality of gate wirings (scanning lines) 50 arranged along the row direction of the pixels 30 and a plurality of gate wirings 50 arranged along the column direction of the pixels 30 so as to intersect the gate wiring 50. Source wiring (signal wiring) 60 and a plurality of power supply wirings (not shown in FIG. 1) arranged in parallel with the source wiring 60 are formed. Each pixel 30 is partitioned by, for example, an orthogonal gate line 50 and a source line 60.

  The gate wiring 50 is connected to the gate electrode of the thin film transistor operating as a switching element included in each pixel circuit 31 for each row. The source wiring 60 is connected to the source electrode of the thin film transistor operating as a switching element included in each pixel circuit 31 for each column. The power supply wiring is connected to the drain electrode of the thin film transistor operating as a drive element included in each pixel circuit 31 for each column.

  As shown in FIG. 2, each pixel 30 of the organic EL display device 10 is composed of sub-pixels 30R, 30G, and 30B of three colors (red, green, and blue), and these sub-pixels 30R, 30G, and 30B. Are formed in a matrix on the display surface. The sub-pixels 30R, 30G, and 30B are separated from each other by the bank 21.

  The banks 21 are formed in a lattice shape so that the ridges extending in parallel to the gate wiring 50 and the ridges extending in parallel to the source wiring 60 intersect each other. Each of the portions surrounded by the protrusions (that is, the opening of the bank 21) and the sub-pixels 30R, 30G, and 30B have a one-to-one correspondence. In the present embodiment, the bank 21 is a pixel bank, but may be a line bank.

  The anode 41 is formed for each of the sub-pixels 30R, 30G, and 30B on the interlayer insulating layer (planarization layer) on the TFT substrate 20 and in the opening of the bank 21. Similarly, the EL layer 42 is formed for each of the sub-pixels 30R, 30G, and 30B on the anode 41 and in the opening of the bank 21. The transparent cathode 43 is continuously formed on the plurality of banks 21 so as to cover all the EL layers 42 (all the sub-pixels 30R, 30G, and 30B).

  Furthermore, the pixel circuit 31 is provided for each of the sub-pixels 30R, 30G, and 30B, and each of the sub-pixels 30R, 30G, and 30B and the corresponding pixel circuit 31 are electrically connected by a contact hole and a relay electrode. Has been. The sub-pixels 30R, 30G, and 30B have the same configuration except that the emission color of the EL layer 42 is different.

[1-2. Pixel circuit]
Here, the circuit configuration of the pixel circuit 31 in the pixel 30 will be described with reference to FIG. FIG. 3 is an electric circuit diagram showing the configuration of the pixel circuit 31 in the organic EL display device 10 according to the present embodiment.

  As shown in FIG. 3, the pixel circuit 31 includes a thin film transistor 32 that operates as a driving element, a thin film transistor 33 that operates as a switching element, and a capacitor 34 that stores data to be displayed on the corresponding pixel 30. . In the present embodiment, the thin film transistor 32 is a drive transistor for driving the organic EL element 40, and the thin film transistor 33 is a switching transistor for selecting the pixel 30.

  The thin film transistor 32 includes a drain electrode 33d of the thin film transistor 33 and a gate electrode 32g connected to one end of the capacitor 34, a drain electrode 32d connected to the power supply wiring 70, the other end of the capacitor 34, and an anode 41 of the organic EL element 40. And a semiconductor film (not shown). The thin film transistor 32 supplies a current corresponding to the data voltage held by the capacitor 34 from the power supply wiring 70 to the anode 41 of the organic EL element 40 through the source electrode 32 s. Thereby, in the organic EL element 40, a drive current flows from the anode 41 to the cathode 43, and the EL layer 42 emits light.

  The thin film transistor 33 includes a gate electrode 33g connected to the gate wiring 50, a source electrode 33s connected to the source wiring 60, a drain electrode 33d connected to one end of the capacitor 34 and the gate electrode 32g of the thin film transistor 32, and a semiconductor film. (Not shown). In the thin film transistor 33, when a predetermined voltage is applied to the connected gate wiring 50 and source wiring 60, the voltage applied to the source wiring 60 is stored in the capacitor 34 as a data voltage.

  Note that the organic EL display device 10 having the above configuration employs an active matrix system in which display control is performed for each pixel 30 located at the intersection of the gate line 50 and the source line 60. Thereby, the corresponding organic EL element 40 selectively emits light by the thin film transistors 32 and 33 of each pixel 30 (each sub-pixel 30R, 30G, and 30B), and a desired image is displayed.

[2. TFT substrate]
Hereinafter, the TFT substrate 20 according to the present embodiment will be described with reference to FIG. Note that the thin film transistor formed on the TFT substrate 20 according to the present embodiment is a bottom gate type and channel protection type thin film transistor.

  FIG. 4 is a schematic cross-sectional view of the TFT substrate 20 according to the present embodiment. For example, a plurality of thin film transistors 100 are formed on the TFT substrate 20.

  As shown in FIG. 4, the TFT substrate 20 according to this embodiment includes a substrate 110, a gate electrode 120, a gate insulating layer 130, an oxide semiconductor layer 140, a channel protective layer 150, a drain electrode 160d, , Source electrode 160s, interlayer insulating layer 170, upper electrode 180, and upper insulating layer 190. Note that in the TFT substrate 20, the thin film transistor 100 includes a gate electrode 120, a gate insulating layer 130, an oxide semiconductor layer 140, a channel protective layer 150, a drain electrode 160d, and a source electrode 160s.

  The thin film transistor 100 is, for example, the thin film transistor 32 shown in FIG. That is, the thin film transistor 100 can be used as a drive transistor. Specifically, when the thin film transistor 100 is the thin film transistor 32 (drive transistor), the gate electrode 120 corresponds to the gate electrode 32g, the source electrode 160s corresponds to the source electrode 32s, and the drain electrode 160d corresponds to the drain electrode 32d.

  The thin film transistor 100 may be, for example, the thin film transistor 33 shown in FIG. That is, the thin film transistor 100 may be used as a switching transistor.

[2-1. substrate]
The substrate 110 is a substrate made of a material having electrical insulation. For example, the substrate 110 may be a glass material such as alkali-free glass, quartz glass, or high heat resistance glass, a resin material such as polyethylene, polypropylene, or polyimide, a semiconductor material such as silicon or gallium arsenide, or stainless steel coated with an insulating layer. A substrate made of a metal material.

  The substrate 110 may be a flexible substrate such as a resin substrate. In this case, the thin film transistor 100 can be used for a flexible display or the like.

[2-2. Gate electrode]
The gate electrode 120 is an electrode disposed above the substrate 110. In the present embodiment, the gate electrode 120 is formed on the substrate 110 in a predetermined shape. The film thickness of the gate electrode 120 is, for example, 30 nm to 400 nm. Note that the gate electrode 120 may be formed above the substrate 110 through, for example, a buffer layer.

  The gate electrode 120 is an electrode made of a conductive material. For example, as a material of the gate electrode 120, molybdenum, aluminum, copper, tungsten, titanium, manganese, chromium, tantalum, niobium, silver, gold, platinum, palladium, indium, nickel, neodymium and other metals, metal alloys, indium oxide Conductive metal oxides such as tin (ITO), aluminum-doped zinc oxide (AZO), and gallium-doped zinc oxide (GZO), and conductive polymers such as polythiophene and polyacetylene can be used. The gate electrode 120 may have a multilayer structure in which these materials are stacked.

[2-3. Gate insulation layer]
The gate insulating layer 130 is an insulating layer disposed between the gate electrode 120 and the oxide semiconductor layer 140. In this embodiment, the gate insulating layer 130 is disposed over the gate electrode 120 and the substrate 110 so as to cover the gate electrode 120. The film thickness of the gate insulating layer 130 is, for example, 310 nm to 760 nm.

  The gate insulating layer 130 is made of an electrically insulating material. In the present embodiment, the gate insulating layer 130 includes a first insulating layer 131, a second insulating layer 132, and a third insulating layer 133 that are arranged in this order from the gate electrode 120 side. The gate insulating layer 130 may include a fourth insulating layer 134 disposed between the third insulating layer 133 and the oxide semiconductor layer 140. Further, in the gate insulating layer 130, another insulating layer may be disposed between the first insulating layer 131 and the fourth insulating layer 134.

The first insulating layer 131, the second insulating layer 132, and the third insulating layer 133 are composed of a silicon nitride film, and the amount of hydrogen atoms bonded to the nitrogen atoms and silicon atoms contained in each layer is 3.3 × 10, respectively. ²² cm ⁻³ or less and 2.3 × 10 ²¹ cm ⁻³ or less.

  Note that the basis of the numerical ranges of the parameter values of the layers constituting the gate insulating layer 130 and the gate insulating layer 130 will be described in detail later.

[2-3-1. First insulating layer]
The first insulating layer 131 is an adhesion layer with the gate electrode 120. The film thickness of the first insulating layer 131 is, for example, 10 nm to 60 nm. In the first insulating layer 131, a compressive stress on the substrate 110 is required to be in close contact with the gate electrode 120. Therefore, the stress on the silicon substrate of the first insulating layer 131 according to the present embodiment is preferably −400 MPa or more and −200 MPa or less. The stress of the first insulating layer 131 corresponds to the film density. In this embodiment mode, the film density of the first insulating layer 131 is preferably 2.57 g / cm ³ or more and 2.59 g / cm ³ or less.

[2-3-2. Second insulating layer]
The second insulating layer 132 is a stress relaxation layer for relaxing the stress of the gate insulating layer 130. In order to suppress the stress caused by the second insulating layer 132, the film density of the second insulating layer 132 is smaller than the film density of the first insulating layer 131 and the third insulating layer 133. Moreover, it is preferable that the stress with respect to the silicon substrate of the 2nd insulating layer 132 is -100 Mpa or more and 100 Mpa or less. The film density of the second insulating layer 132 is preferably 2.53 g / cm ³ or more and 2.55 g / cm ³ or less.

  Moreover, the total film thickness of the film thickness of the 2nd insulating layer 132 and the film thickness of the 3rd insulating layer 133 mentioned later is 300 nm-600 nm, for example. Accordingly, sufficient withstand voltage characteristics between the gate electrode 120 and the oxide semiconductor layer 140 can be ensured. From the viewpoint of withstand voltage characteristics, the total film thickness is preferably large. However, in order to prevent the process (film formation) time from becoming too long, the total film thickness may be 600 nm or less. preferable. In addition, when the stress on the substrate 110 due to the gate insulating layer 130 increases as the thickness of the gate insulating layer 130 increases, the amount of warpage of the substrate 110 increases. Therefore, in order to reduce the amount of warping of the substrate 110, the ratio of the thickness of the second insulating layer 132 that is a stress relaxation layer to the total thickness of the gate insulating layer 130 is preferably 35% or more. Note that the ratio may be appropriately adjusted according to an allowable range with respect to the warp amount of the substrate 110 in the TFT substrate 20 manufacturing apparatus.

[2-3-3. Third insulating layer]
The third insulating layer 133 is a hydrogen atom blocking layer for suppressing the permeation of hydrogen atoms. In the second insulating layer 132 below the third insulating layer 133, there are hydrogen atoms that are not bonded to silicon atoms or hydrogen atoms that are located at sites that are very weakly bonded to silicon atoms. Is detached from the second insulating layer 132. The third insulating layer 133 is a layer for suppressing transmission of the hydrogen atoms to the oxide semiconductor layer 140 side. The third insulating layer 133 is composed of a dense film (that is, a high density) in order to suppress permeation of hydrogen atoms. Here, since the denseness of the film (that is, the film density) and the stress of the film have a correlation, the third insulating layer 133 is necessary for the third insulating layer to sufficiently suppress the transmission of hydrogen atoms. Stress can be defined. In the present embodiment, the stress on the silicon substrate of the third insulating layer 133 is preferably −400 MPa or more and −200 MPa or less. The film density of the third insulating layer 133 is preferably 2.57 g / cm ³ or more and 2.59 g / cm ³ or less.

  Further, when the thickness of the second insulating layer 132 is increased, the amount of hydrogen atoms desorbed from the second insulating layer 132 is increased, so that the thickness of the third insulating layer 133 is increased to improve the hydrogen atom blocking effect. There is a need. Therefore, in this embodiment, the thickness of each layer is determined so that the difference obtained by subtracting the thickness of the third insulating layer 133 from the thickness of the second insulating layer 132 is 50 nm or less.

[2-3-4. Fourth insulating layer]
The fourth insulating layer 134 is an insulating layer disposed between the third insulating layer 133 and the oxide semiconductor layer 140. In this embodiment, the fourth insulating layer 134 is a layer in contact with the oxide semiconductor layer 140. The fourth insulating layer 134 is preferably composed of a silicon oxide film. The film thickness of the fourth insulating layer 134 is, for example, 10 nm to 100 nm, and more preferably 30 nm to 50 nm.

  By forming the fourth insulating layer 134 from a silicon oxide film, the amount of hydrogen atoms in the film (that is, the hydrogen atom content) can be reduced as compared with the case where the fourth insulating layer 134 is formed from a silicon nitride film or the like. Accordingly, the amount of hydrogen atoms taken in by the oxide semiconductor layer 140 in contact with the fourth insulating layer 134 can be reduced, so that resistance reduction of the oxide semiconductor layer 140 can be suppressed. Note that it is not preferable to form the entire gate insulating layer 130 with only a silicon oxide film for the following reason. That is, since it is difficult to control the stress of the silicon oxide film according to the film formation conditions, when forming a silicon oxide film that is dense enough to be applied to the thin film transistor 100, the compressive stress of the silicon oxide film is large. Unavoidable. Therefore, when the entire gate insulating layer 130 is formed using only the silicon oxide film, the gate insulating layer 130 having a large compressive stress and a large film thickness is formed, so that the substrate 110 is warped.

[2-4. Oxide semiconductor layer]
The oxide semiconductor layer 140 is a layer used as a channel layer of the thin film transistor 100 and is disposed above the substrate 110 so as to face the gate electrode 120. Specifically, the oxide semiconductor layer 140 is provided over the gate insulating layer 130 and at a position facing the gate electrode 120. For example, the oxide semiconductor layer 140 is formed in an island shape over the gate insulating layer 130 above the gate electrode 120. The film thickness of the oxide semiconductor layer 140 is, for example, 30 nm to 150 nm.

  As a material of the oxide semiconductor layer 140, an oxide semiconductor material containing at least one of indium (In), gallium (Ga), and zinc (Zn) is used. For example, the oxide semiconductor layer 140 is made of a transparent amorphous oxide semiconductor (TAOS) such as amorphous indium gallium zinc oxide (InGaZnO: IGZO).

  The ratio of In: Ga: Zn is, for example, about 1: 1: 1. The ratio of In: Ga: Zn may be in the range of 0.8 to 1.2: 0.8 to 1.2: 0.8 to 1.2, but is not limited to this range.

  The oxide semiconductor layer 140 is a channel layer of the thin film transistor 100. A thin film transistor in which a channel layer is formed using a transparent amorphous oxide semiconductor has high carrier mobility and is suitable for a large-screen and high-definition display device. Further, since the transparent amorphous oxide semiconductor can be formed at a low temperature, it can be easily formed on a flexible substrate such as a plastic or a film.

[2-5. Channel protective layer]
The channel protective layer 150 is disposed on the oxide semiconductor layer 140. For example, the channel protective layer 150 is disposed over the oxide semiconductor layer 140 and the gate insulating layer 130 so as to cover the oxide semiconductor layer 140. The channel protective layer 150 is an insulating layer provided to protect the oxide semiconductor layer 140. The film thickness of the channel protective layer 150 is, for example, 100 nm to 400 nm.

  The channel protective layer 150 is made of an electrically insulating material. The channel protective layer 150 is composed of a silicon oxide film. Alternatively, the channel protective layer 150 may be composed of an aluminum oxide film. The channel protective layer 150 may be a single layer film or a laminated film.

  The channel protective layer 150 is provided with contact holes for connecting the drain electrode 160d and the source electrode 160s to the oxide semiconductor layer 140, respectively. The materials constituting the drain electrode 160d and the source electrode 160s reach the oxide semiconductor layer 140 along the wall surfaces of the contact holes, respectively. Alternatively, the contact holes may be filled with materials constituting the drain electrode 160d and the source electrode 160s, respectively.

[2-6. Drain electrode and source electrode]
The drain electrode 160d and the source electrode 160s are formed in a predetermined shape on the channel protective layer 150. For example, the drain electrode 160d and the source electrode 160s are disposed on the channel protective layer 150 so as to face each other while being separated in the substrate horizontal direction. Specifically, the drain electrode 160d and the source electrode 160s are respectively disposed on the channel protective layer 150 so as to be connected to the oxide semiconductor layer 140 through contact holes. The film thickness of the drain electrode 160d and the source electrode 160s is, for example, 30 nm to 300 nm.

  The drain electrode 160d and the source electrode 160s are electrodes made of a conductive material. The drain electrode 160d and the source electrode 160s include, for example, a copper single layer film (Cu film), a laminated structure of copper film and tungsten film (Cu / W), a laminated structure of copper film and titanium nitride film (Cu / TiN), Alternatively, a laminated structure (CuMn / Cu / Mo) of a copper and manganese alloy film, a copper film, and a molybdenum film is used. Alternatively, as the material of the drain electrode 160d and the source electrode 160s, for example, the same material as the material of the gate electrode 120 can be used.

[2-7. Interlayer insulation layer]
The interlayer insulating layer 170 is disposed above the channel protective layer 150. The interlayer insulating layer 170 is disposed on the channel protective layer 150, the drain electrode 160d, and the source electrode 160s. For example, the interlayer insulating layer 170 is disposed on the channel protective layer 150 and on the drain electrode 160d and the source electrode 160s so as to cover the drain electrode 160d and the source electrode 160s.

  The interlayer insulating layer 170 is a passivation film for the thin film transistor 100. The film thickness of the interlayer insulating layer 170 is, for example, 200 nm to 500 nm.

  A part of the interlayer insulating layer 170 is opened so as to penetrate therethrough. That is, a contact hole for exposing a part of the source electrode 160s is formed in the interlayer insulating layer 170.

  The contact hole is a contact hole formed to electrically connect the upper electrode 180 and the source electrode 160s. The material constituting the upper electrode 180 reaches, for example, the source electrode 160s along the wall surface of the contact hole. Alternatively, the contact hole may be filled with a material constituting the upper electrode 180.

  The interlayer insulating layer 170 includes a plurality of layers. Specifically, as illustrated in FIG. 4, the interlayer insulating layer 170 has a three-layer structure, and includes a lower interlayer insulating layer 171, a barrier layer 172, and an upper interlayer insulating layer 173 that are sequentially stacked. Yes.

[2-7-1. Lower interlayer insulation layer]
The lower interlayer insulating layer 171 is an insulating layer provided on the drain electrode 160d and the source electrode 160s. The thickness of the lower interlayer insulating layer 171 is such that the thickness of the interlayer insulating layer 170 is 500 nm or less.

  The lower interlayer insulating layer 171 is made of a material having electrical insulation. For example, the lower interlayer insulating layer 171 is formed of a film made of an inorganic material such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or an aluminum oxide film, or an inorganic material containing silicon, oxygen, and carbon. It is a single layer film such as a film, or a laminated film thereof.

[2-7-2. Barrier layer]
The barrier layer 172 is an insulating layer provided on the lower interlayer insulating layer 171. The barrier layer 172 is a layer for suppressing moisture in the air and the like from entering the oxide semiconductor layer 140 from the outside.

  The barrier layer 172 is, for example, an aluminum oxide film. The film thickness of the barrier layer 172 is, for example, 30 nm to 100 nm.

[2-7-3. Upper interlayer insulation layer]
The upper interlayer insulating layer 173 is an insulating layer provided on the barrier layer 172. The film thickness of the upper interlayer insulating layer 173 is such that the film thickness as the interlayer insulating layer 170 is 500 nm or less.

  The upper interlayer insulating layer 173 is made of a material having electrical insulation. For example, the upper interlayer insulating layer 173 is made of the same material as the lower interlayer insulating layer 171.

[2-8. Upper electrode]
The upper electrode 180 is formed in a predetermined shape above the drain electrode 160d and the source electrode 160s. Specifically, the upper electrode 180 is formed on the interlayer insulating layer 170. The film thickness of the upper electrode 180 is, for example, 200 nm to 500 nm.

  The upper electrode 180 is connected to one of the drain electrode 160d and the source electrode 160s. Specifically, the upper electrode 180 is electrically connected to the source electrode 160s through a contact hole.

  The upper electrode 180 is made of the same material as the drain electrode 160d and the source electrode 160s, for example. In order to improve the adhesion between the layers, the ITO film and the metal film may be laminated in this order.

[2-9. Upper insulating layer]
The upper insulating layer 190 is an insulating layer provided on the upper electrode 180. In the present embodiment, the upper insulating layer 190 is disposed on the upper electrode 180 and the interlayer insulating layer 170 so as to cover the upper electrode 180. The film thickness of the upper insulating layer 190 is, for example, 100 nm to 200 nm.

  The upper insulating layer 190 is preferably composed of a silicon nitride film having a high barrier property against water, hydrogen, and the like.

  A part of the upper insulating layer 190 is opened so as to penetrate therethrough. That is, a contact hole 191 for exposing a part of the upper electrode 180 is formed in the upper insulating layer 190. For example, a terminal electrode or the like is formed in the contact hole 191.

[3. Manufacturing method of TFT substrate]
Subsequently, a manufacturing method of the TFT substrate 20 according to the present embodiment will be described with reference to FIGS. 5A to 5D are schematic cross-sectional views showing the manufacturing process of the TFT substrate 20 according to the present embodiment.

[3-1. Formation of gate electrode]
First, as shown in FIG. 5A, a substrate 110 is prepared, and a gate electrode 120 having a predetermined shape is formed above the substrate 110. For example, a metal film is formed on the substrate 110 by sputtering, and the metal film is processed by photolithography and etching, whereby the gate electrode 120 having a predetermined shape is formed.

  Specifically, first, a glass substrate is prepared as the substrate 110, and a 20 nm Mo film and a 200 nm Cu film are sequentially formed on the substrate 110 by sputtering. Then, after forming a resist pattern by photolithography, the gate electrode 120 is formed by processing the Mo film and the Cu film by wet etching.

  The wet etching of the Mo film and the Cu film can be performed at room temperature using a PAN (Phosphoric-Acetic-Nitric-acid) solution. For removing the resist, a stripping solution containing an alkali additive may be used. The substrate 110 is, for example, a G8.5 glass substrate (thickness: 0.5 mm, X: 2500 mm × Y: 2200 mm).

[3-2. Formation of gate insulating layer]
Next, as illustrated in FIGS. 5A to 5E, a gate insulating layer 130 is formed over the substrate 110. For example, the gate insulating layer 130 is formed by plasma CVD or sputtering so as to cover the gate electrode 120. The gate insulating layer 130 includes a first insulating layer 131, a second insulating layer 132, a third insulating layer 133, and a fourth insulating layer 134.

  Specifically, first, as shown in FIG. 5A (b), a first insulating layer 131 made of a 50 nm silicon nitride film is formed on the substrate 110 so as to cover the gate electrode 120.

  Next, as shown in (c) of FIG. 5A, a second insulating layer 132 composed of a 175 nm silicon nitride film is formed on the first insulating layer 131.

  Next, as shown in FIG. 5A (d), a third insulating layer 133 made of a 125 nm silicon nitride film is formed on the second insulating layer 132.

  Next, as shown in FIG. 5A (e), a fourth insulating layer 134 made of a 50 nm silicon oxide film is formed on the third insulating layer 133.

  The first insulating layer 131, the second insulating layer 132, the third insulating layer 133, and the fourth insulating layer 134 are sequentially formed by plasma CVD. The film formation temperature at this time is, for example, 350 ° C. to 400 ° C. When the film forming temperature is lower than 350 ° C., the hydrogen content in the silicon nitride film increases, which is not preferable.

For example, nitrogen gas (N ₂ ), ammonia gas (NH ₃ ), and silane gas (SiH ₄ ) are introduced into the first insulating layer 131, the second insulating layer 132, and the third insulating layer 133 made of a silicon nitride film. It can be formed into a film by using it. Specific film forming conditions include power density of 0.12 W / cm ^{2 to} 0.22 W / cm ² , process distance (distance between electrodes) of 550 mil (0.55 inch) to 750 mil (0.75 inch), standard reduction has been _{N 2} gas flow rate ^{0.8sccm / cm 2 ~1.5sccm / cm 2} , NH 3 gas flow rate is normalized is ^{5sccm / cm 2 ~10sccm / cm 2} . Note that the standardized flow rate of each gas is a value obtained by dividing the gas flow rate by the electrode area of the plasma CVD apparatus. The same applies to the standardized flow rates of gas shown below.

The process pressure at the time of film formation is 70 Pa to 250 Pa in the formation of the first insulating layer 131 and the third insulating layer 133, and the first insulating layer 131 and the first insulating film in the formation of the second insulating layer 132. The pressure is higher than that in the formation of the three insulating layers 133. Thus, by using a high process pressure in the second insulating layer 132, the compressive stress of the second insulating layer 132 can be reduced. However, when a high process pressure is used, the amount of hydrogen atoms in the film increases. Therefore, in this embodiment, the flow rate of SiH ₄ gas in forming the second insulating layer 132 is set to the flow rate in forming the first insulating layer 131 and the third insulating layer 133 (0.33 sccm / cm ^{2 to} 0.46 sccm). / Cm ² ). In this manner, in the formation of the second insulating layer 132, the amount of hydrogen atoms in the second insulating layer 132 can be reduced by using a small SiH ₄ gas flow rate.

The fourth insulating layer 134 formed of a silicon oxide film can be formed by using, for example, nitrous oxide gas (N ₂ O), argon gas (Ar), and silane gas (SiH ₄ ) as an introduction gas. . Ar gas is used as a dilution gas for N ₂ O gas. Accordingly, efficient gas is decomposed, high quality oxide film is formed, and it is possible to suppress the amount of N 2 _O gas. Specific film forming conditions include, for example, a film forming temperature of 350 ° C. to 400 ° C., a power density of 0.1 W / cm ^{2 to} 0.3 W / cm ² , and a process distance (distance between electrodes) of 550 mil (0.55). Inch) to 750 mil (0.75 inch), the process pressure is 70 Pa to 250 Pa, the N ₂ O gas flow rate is 0 to 0.55 sccm / cm ² , and the Ar gas flow rate is 1.2 sccm / cm ^{2 to} 1.8 sccm / cm ^2. The SiH ₄ gas flow rate is 0.015 sccm / cm ^{2 to} 0.025 sccm / cm ² .

  Note that the first insulating layer 131, the second insulating layer 132, the third insulating layer 133, and the fourth insulating layer 134 are continuously formed. That is, after the first insulating layer 131 is formed using a plasma CVD apparatus, the second insulating layer 132, the third insulating layer 133, and the fourth insulating layer 134 are not broken without breaking the vacuum in the chamber of the plasma CVD apparatus. Film formation is performed. Thereby, the possibility that impurities are mixed can be reduced.

[3-3. Plasma treatment]
Next, as illustrated in FIG. 5B, plasma processing, which is an example of nitriding processing, is performed on the fourth insulating layer 134 of the gate insulating layer 130. That is, after the fourth insulating layer 134 is formed, plasma treatment is performed before the oxide semiconductor layer 140 is formed.

Specifically, plasma 201 is generated in the chamber used for forming the fourth insulating layer 134 using ammonia gas (NH ₃ ), nitrogen gas (N ₂ ), or the like. The gas used for the plasma treatment may contain hydrogen atoms. When hydrogen atoms are included in the gas used for the plasma treatment, dangling bonds on the surface of the silicon layer can be terminated, and the defect level at the interface with the oxide semiconductor layer 140 can be reduced. Note that hydrogen atoms bonded to the fourth insulating layer 134 are used only for reducing the defect level at the interface with the oxide semiconductor layer 140; therefore, the amount of the hydrogen atoms depends on the first insulating layer 131, The amount of hydrogen atoms desorbed from the second insulating layer 132 and the third insulating layer 133 is overwhelmingly smaller. Therefore, the influence of the hydrogen atoms bonded to the fourth insulating layer 134 on the reduction in resistance of the oxide semiconductor layer 140 can be ignored. Note that with this treatment, the fourth insulating layer 134 has a higher concentration of nitrogen atoms than the central portion of the fourth insulating layer 134 in the film thickness direction on the surface of the oxide semiconductor layer 140.

The time for generating the plasma 201, that is, the plasma processing time is, for example, 5 seconds to 120 seconds, and preferably 30 seconds to 60 seconds. The plasma processing temperature, that is, the substrate temperature is 350 ° C. to 400 ° C. For example, the substrate temperature is the same as the temperature at which the gate insulating layer 130 is formed. Specific plasma treatment conditions include, for example, a power density of 0.1 W / cm ^{2 to} 0.3 W / cm ² , and a process distance (distance between electrodes) of 550 mil (0.55 inch) to 750 mil (0.75 inch). The process pressure is 70 Pa to 250 Pa, and the NH ₃ gas flow rate is 0.09 sccm / cm ^{2 to} 0.55 sccm / cm ² . Further, nitrogen (N ₂ ) and hydrogen (H ₂ ) may be used as a gas used for the plasma treatment. In this case, _{N 2} gas flow rate is ^{0.09sccm / cm 2 ~0.55sccm / cm 2} , H 2 gas flow rate is ^{0.18sccm / cm 2 ~1.82sccm / cm 2} .

  Note that the plasma treatment is performed continuously after the fourth insulating layer 134 is formed. That is, after the fourth insulating layer 134 is formed using a plasma CVD apparatus, plasma treatment is performed without breaking the vacuum in the chamber of the plasma CVD apparatus. Thereby, the possibility that impurities are mixed can be reduced.

[3-4. Formation of oxide semiconductor layer]
Next, as illustrated in FIG. 5B, the oxide semiconductor layer 140 having a predetermined shape is formed above the substrate 110 and at a position facing the gate electrode 120. For example, an oxide semiconductor film is formed over the gate insulating layer 130 by sputtering. Then, the oxide semiconductor film is processed by photolithography and etching, whereby the oxide semiconductor layer 140 having a predetermined shape is formed.

Specifically, on the gate insulating layer 130 by sputtering in a mixed gas atmosphere of oxygen (O ₂ ) and argon (Ar) using a target material having a composition ratio of In: Ga: Zn = 1: 1: 1. Next, an amorphous InGaZnO film of 90 nm is formed. More specific film forming conditions are, for example, a power of 12 kW, an oxygen partial pressure of the film forming gas of 4.5%, and a film forming rate of 100 nm / min in the DC magnetron sputtering method.

Then, the oxide semiconductor layer 140 is formed by wet etching the amorphous InGaZnO formed over the gate insulating layer 130. InGaZnO wet etching can be performed using, for example, a chemical solution in which phosphoric acid (H ₃ PO ₄ ), nitric acid (HNO ₃ ), and a surfactant are mixed. For removing the resist, a stripping solution containing an alkali additive may be used.

[3-5. Formation of channel protective layer]
Next, as illustrated in FIG. 5B (c), the channel protective layer 150 is formed over the oxide semiconductor layer 140. For example, the channel protective layer 150 is formed by plasma CVD so as to cover the oxide semiconductor layer 140.

Specifically, a channel protective layer 150 is formed by forming a 200 nm silicon oxide film over the gate insulating layer 130 so as to cover the oxide semiconductor layer 140. The film forming temperature at this time is, for example, 230 ° C. The silicon oxide film can be formed by using, for example, silane gas (SiH ₄ ) and nitrous oxide gas (N ₂ O) as introduction gases. Specific film forming conditions include, for example, a power density of 0.238 W / cm ² , a process distance (distance between electrodes) of 600 mil (0.6 inches), a process pressure of 133.32 Pa, and an N ₂ O gas flow rate of 88500 sccm. The SiH ₄ gas flow rate is 980 sccm.

  Note that after the channel protective layer 150 is formed, heat treatment (annealing treatment) at a predetermined temperature may be performed. For example, annealing may be performed at a temperature equal to or higher than the film formation temperature in dry air or an oxygen atmosphere. For example, the annealing temperature may be 350 ° C. The annealing time may be 1 hour after the substrate temperature stabilization time of about 7 minutes has elapsed. Accordingly, oxygen defects in the oxide semiconductor layer 140 are repaired and semiconductor properties can be maintained. The dry air may have a dew point under atmospheric pressure of −70 ° C. or lower.

[3-6. Formation of drain electrode and source electrode]
Next, as shown in FIG. 5B (d), a drain electrode 160d and a source electrode 160s are formed on the channel protective layer 150. Specifically, first, a part of the channel protective layer 150 is removed by photolithography and dry etching to form a contact hole. That is, a contact hole for exposing part of the oxide semiconductor layer 140 is formed in the channel protective layer 150.

For example, when the channel protective layer 150 is a silicon oxide film, reactive ion etching (RIE) can be used as dry etching. At this time, for example, carbon tetrafluoride (CF ₄ ), oxygen gas (O ₂ ), and helium gas (He) can be used as the etching gas. Parameters such as gas flow rate, pressure, applied power, and frequency are appropriately set depending on the substrate size, etching film thickness, and the like. For example, the power density may be 0.255 W / cm ² , the process pressure may be 50 Pa, the O ₂ gas flow rate may be 1300 sccm, the CF ₄ gas flow rate may be 3800 sccm, and the He gas flow rate may be 5000 sccm. For removing the resist, a stripping solution containing an alkali additive may be used.

  Then, a metal film is formed on the channel protective layer 150 by sputtering so as to fill the formed contact hole. For example, a 20 nm Mo film, a 300 nm Cu film, and a 50 nm copper and manganese alloy film (CuMn film) are sequentially stacked on the channel protective layer 150. Thereafter, the stacked metal films are processed by photolithography and etching to form a drain electrode 160d and a source electrode 160s having a predetermined shape. The wet etching of the Mo film, the Cu film, and the CuMn film can be performed at room temperature using a PAN solution, for example. For removing the resist, a stripping solution containing an alkali additive may be used.

[3-7. Formation of interlayer insulation layer]
Next, as shown in FIG. 5C, an interlayer insulating layer 170 is formed. Specifically, first, a lower interlayer insulating layer 171 is formed by plasma CVD or sputtering so as to cover the drain electrode 160d and the source electrode 160s. For example, a 200 nm silicon oxide film is formed by plasma CVD on the channel protective layer 150 so as to cover the drain electrode 160d and the source electrode 160s. Specific film formation conditions are, for example, a film formation temperature of 230 ° C., a power density of 0.238 W / cm ² , a process distance (distance between electrodes) of 600 mil (0.6 inches), a process pressure of 133.32 Pa, The N ₂ O gas flow rate is 88500 sccm, and the SiH ₄ gas flow rate is 980 sccm.

Next, a barrier layer 172 is formed on the lower interlayer insulating layer 171 by plasma CVD, ALD (Atomic Layer Deposition), sputtering, or the like. For example, the barrier layer 172 is formed by forming an aluminum oxide film of 30 nm on the lower interlayer insulating layer 171 by sputtering. Specifically, an aluminum oxide film is formed by RF magnetron sputtering in a mixed gas atmosphere of oxygen (O ₂ ) and argon (Ar) using aluminum as a target. The film formation conditions are, for example, a power of 30 kW, an aluminum target purity of 99.99%, a flow rate ratio of Ar and O _{2 as} a film formation gas of 1: 1, and a film formation rate of 6.0 nm / min. .

Next, the upper interlayer insulating layer 173 is formed on the barrier layer 172 by plasma CVD or sputtering. Specifically, an upper interlayer insulating layer 173 is formed by forming a 400 nm silicon nitride film on the barrier layer 172 by plasma CVD. Specific film formation conditions include, for example, a film formation temperature of 290 ° C., a power density of 0.238 W / cm ² , a process distance (distance between electrodes) of 600 mil (0.6 inches), a process pressure of 133.32 Pa, The N ₂ O gas flow rate is 88500 sccm, and the SiH ₄ gas flow rate is 980 sccm.

  Note that since the substrate is placed under vacuum during the formation of the interlayer insulating layer 170, oxygen in the oxide semiconductor layer 140 is lost and the resistance is reduced. For this reason, oxygen defects are repaired by performing an annealing process in dry air or an oxygen atmosphere after film formation. For example, the annealing temperature may be 300 ° C. The annealing time may be 1 hour after the substrate temperature stabilization time of about 7 minutes has elapsed. The dry air may have a dew point under atmospheric pressure of −70 ° C. or lower.

[3-8. Formation of upper electrode]
Next, as shown in FIG. 5C (b), the upper electrode 180 is formed on the interlayer insulating layer 170 (upper interlayer insulating layer 173). Specifically, first, a part of the interlayer insulating layer 170 is removed by photolithography and dry etching to form a contact hole. That is, a contact hole for exposing a part of the source electrode 160s or the drain electrode 16d is formed in the interlayer insulating layer 170.

For example, a part of the interlayer insulating layer 170 is removed by dry etching such as RIE. As an etching gas, for example, carbon tetrafluoride (CF ₄ ) and oxygen gas (O ₂ ) can be used. Parameters such as power density, pressure, and gas flow rate are appropriately set according to the substrate size, etching film thickness, and the like. For example, the power density may be 0.255 W / cm ² , the process pressure may be 50 Pa, the O ₂ gas flow rate may be 1300 sccm, the CF ₄ gas flow rate may be 3800 sccm, and the He gas flow rate may be 5000 sccm. For removing the resist, a stripping solution containing an alkali additive may be used.

  Subsequently, a conductive film is formed on the interlayer insulating layer 170 by sputtering so as to fill the formed contact hole. For example, a 20 nm Mo film, a 300 nm Cu film, and a 50 nm CuMn film are sequentially stacked on the interlayer insulating layer 170. Thereafter, the laminated conductive film is processed by photolithography and etching to form the upper electrode 180 having a predetermined shape. The wet etching of the Mo film, the Cu film, and the CuMn film can be performed at room temperature using a PAN solution, for example. For removing the resist, a stripping solution containing an alkali additive may be used.

[3-9. Formation of upper insulating layer]
Next, as shown in FIG. 5D, the upper insulating layer 190 is formed. Specifically, first, the upper insulating layer 190 is formed by plasma CVD or sputtering so as to cover the upper electrode 180. For example, a 100 nm silicon nitride film is formed by plasma CVD on the interlayer insulating layer 170 (upper interlayer insulating layer 173) so as to cover the upper electrode 180. Specific film formation conditions include, for example, a film formation temperature of 350 ° C., a power density of 0.2 W / cm ² , a process distance (distance between electrodes) of 700 mil (0.7 inches), a process pressure of 160 Pa, and N _2. The gas flow rate is 65000 sccm, the NH ₃ gas flow rate is 25000 sccm, and the SiH ₄ gas flow rate is 2000 sccm. Note that, after the upper insulating layer 190 is formed, the same annealing treatment as that after the interlayer insulating layer 170 is formed may be performed.

  After forming the upper insulating layer 190, as shown in FIG. 5D, a part of the upper insulating layer 190 is removed by photolithography and dry etching to form a contact hole 191. That is, a contact hole 191 for exposing a part of the upper electrode 180 is formed in the upper insulating layer 190. The method for forming the contact hole 191 is the same as the method for forming the contact hole in the interlayer insulating layer 170.

  Through the above steps, the TFT substrate 20 shown in FIG. 4 is manufactured. In the subsequent steps, the organic EL element 40 and the like are further stacked.

[4. Configuration and formation conditions of gate insulating layer]
Subsequently, in the TFT substrate 20 according to the present embodiment, a configuration and formation conditions for improving the withstand voltage characteristics of the gate insulating layer 130 without destabilizing the electrical characteristics of the thin film transistor 100 will be described in detail.

[4-1. Hydrogen atomic weight of silicon nitride film]
First, an experiment for examining the relationship between the formation conditions of the silicon nitride film constituting the gate insulating layer 130 and the amount of hydrogen atoms and the results thereof will be described with reference to the drawings.

  In this experiment, a silicon nitride film was formed on a silicon substrate having a diameter of 6 inches under various conditions, and the characteristics of each silicon nitride film were examined. The silicon substrate used has a thickness of 0.625 μm, a diameter of 150 mm, and a plane orientation of (100).

  FIG. 6 is a top view showing the arrangement of the silicon substrate on which the silicon nitride film is formed during film formation.

  As shown in FIG. 6, the silicon substrate 115 was attached to the center of the G8.5 glass substrate 111, and the silicon substrate 116 was attached to the end of the G8.5 glass substrate 111 (near the orientation flat 112). . Thereby, the relationship between the position on the substrate and the film quality when the film is formed on a large substrate such as the G8.5 glass substrate 111 can be examined.

  In this experiment, the characteristics of the silicon nitride film when the silicon nitride film was formed on the above-described silicon substrates 115 and 116 under the conditions A, B, and C shown in FIG.

  FIG. 7 is a table showing the deposition parameters of the silicon nitride film (SiN film) and the physical property values of the deposited silicon nitride film. In FIG. 7, the physical property values of the silicon nitride film formed on each of the silicon substrate 115 disposed at the center of the G8.5 glass substrate 111 and the silicon substrate 116 disposed at the end are shown. .

  The silicon nitride film was formed so as to have a film thickness of 400 nm under each condition. The film thickness was measured with a spectroscopic ellipsometer.

  As shown in FIG. 7, as the physical property values of the silicon nitride film, the stress on the silicon substrate 115, the bonding amount of hydrogen atoms bonded to silicon atoms (Si—H bonding amount), and bonding to nitrogen atoms are performed. The amount of hydrogen atoms bonded (NH bond amount) was measured. The stress of the silicon nitride film on the silicon substrate 115 was evaluated by a thin film stress measuring device from the amount of change in the warp (radius of curvature) and the film thickness of the silicon substrate on which the silicon nitride film was formed. Further, the Si—H bond amount and the N—H bond amount were evaluated by FT-IR (Fourier Transform Infrared Spectroscopy) spectroscopy.

  As shown in FIG. 7, each gas flow rate is different between condition A and condition B. Further, the power differs mainly between the condition A and the condition C. Under any of the above conditions, compressive stress is generated in the silicon nitride film, but the absolute value of the stress increases in the order of condition C, condition A, and condition B. Further, the Si—H bond amount increases in the order of condition A, condition B, and condition C, and the N—H bond amount decreases in the order of condition A, condition B, and condition C.

  Here, the result of investigating the characteristics of the thin film transistor when the silicon nitride film formed under the above conditions is used for the thin film transistor will be described. In the thin film transistor used in this experiment, the gate insulating layer is composed of a silicon nitride film and a silicon oxide film formed thereon. Then, three kinds of thin film transistors in which silicon nitride films were formed using the above conditions A, B, and C were produced. In addition, the silicon nitride film in each experimental thin film transistor was formed to a thickness of 350 nm. Further, the silicon oxide film was formed to a film thickness of 50 nm under the film forming conditions shown in FIG.

  FIG. 8 is a table showing the deposition parameters of the silicon oxide film (SiO film) and the physical property values of the deposited silicon oxide film. FIG. 8 also shows physical property values of the silicon oxide film measured in the same manner as the silicon nitride film. Since a dense film is required as the silicon oxide film formed on the silicon nitride film, as shown in FIG. 8, the stress of the silicon oxide film on the silicon substrate becomes a compressive stress, and the absolute value of the stress becomes large. Therefore, if the thickness of the silicon oxide film is increased more than necessary, the amount of warpage of the substrate increases, which is not preferable.

  Note that the structure of the thin film transistor for this experiment other than the gate insulating layer is the same as that of the thin film transistor 100 described above.

  The electrical characteristics of the experimental thin film transistor manufactured using the above film formation conditions will be described with reference to FIGS. 9A, 9B, and 9C.

9A, 9B, and 9C show measurement results of electrical characteristics of a thin film transistor that uses a silicon nitride film and a silicon oxide film formed under conditions A, B, and C as gate insulating layers, respectively. It is a graph. Here, the relationship between the gate-source voltage Vgs applied to the thin film transistor and the current Ids flowing between the drain and the source was measured as electrical characteristics. The thin film transistors to be measured are formed in a matrix on a G8.5 glass substrate. Here, the channel width W and the channel length L of the thin film transistor 100 are 10 μm and 11 μm, respectively. In FIGS. 9A, 9B and 9C, the electrical characteristics are obtained at a total of 56 points including 8 points in the long side direction and 7 points in the short side direction in the region excluding 200 mm from the edge of the TFT substrate, and the Ids-Vgs curve is obtained. Painted. Then, from the curve, Vds when Ids is W / L × 10 ⁻⁹ (W: channel width, L: channel length) is set as the threshold value Vth, the threshold value Vth for each curve is obtained, and an average value thereof ( Ave) and variation (3σ) were calculated.

  As shown in FIG. 9A, when the condition A is used, the threshold value Vth is 0.73 V, the variation is 0.50 V, and electrical characteristics with small variation are obtained. On the other hand, as shown in FIGS. 9B and 9C, in the case of using the condition B and the condition C, many characteristics that the threshold value Vth is greatly shifted in the negative direction are seen. Further, as shown in FIG. 9C, when the condition C is used, a phenomenon in which the source and the drain of the thin film transistor 100 are substantially conductive (a phenomenon in which the curve of the graph is substantially a horizontal straight line) is also observed. When Condition B and Condition C are used, the amount of Si—H bonds contained in the silicon nitride film is large, and it is estimated that the above-described minus shift of the threshold value Vth occurs.

  The grounds for the estimation are described below. The bond energy of hydrogen atoms H contained in the silicon nitride film is 3.3 eV for Si—H bonds and 4.0 eV for N—H bonds, and hydrogen atoms H are desorbed from Si—H bonds having a low bond energy. easy. Here, at least a part of the detached hydrogen atoms is doped into the oxide semiconductor layer 140. Accordingly, oxygen vacancies in the oxide semiconductor layer 140 increase and the carrier density in the oxide semiconductor layer 140 increases, so that the threshold value Vth of the thin film transistor 100 is estimated to be negatively shifted.

From the above, it can be said that it is particularly necessary to reduce the amount of Si—H bonds in the silicon nitride film used for the gate insulating layer 130 of the thin film transistor 100. The amount of Si—H bonds in the silicon nitride film is preferably 2.3 × 10 ²¹ cm ⁻³ or less from the above experimental results. Further, the amount of N—H bonds in the silicon nitride film is preferably as small as possible, but even if it exists in the same degree as the condition A, it is considered that the threshold value Vth of the thin film transistor 100 is not negatively shifted. Therefore, the N—H bond amount in the silicon nitride film may be 3.3 × 10 ²² cm ⁻³ or less.

[4-2. Stress of silicon nitride film]
Next, an experiment for examining the relationship between the formation conditions and stress of the silicon nitride film and the result thereof will be described with reference to the drawings.

  When the silicon nitride film formed using the above condition A is used in the gate insulating layer, the electric characteristics of the obtained thin film transistor are good as described above. However, as described above, since the compressive stress of the silicon nitride film formed using the above condition A is large, the amount of warpage of the substrate (the amount of substrate sagging) increases. When the amount of sagging of the substrate increases, a problem arises in transporting the substrate in the manufacturing apparatus in a production line using a large glass substrate. For example, transportation troubles such as the edge of the glass substrate being caught easily in equipment that transports the glass substrate with a roller (lithography, wet etching, peeling cleaning device, etc.), and accidents such as the glass substrate breaking due to it The probability of occurrence increases.

  Therefore, an attempt was made to solve the above problem by laminating a silicon nitride film used for the gate insulating layer of the thin film transistor and providing a stress relaxation layer. Hereinafter, an experiment for examining the film forming condition of the stress relaxation layer and a result thereof will be described.

  Also in this experiment, silicon substrates 115 and 116 having a diameter of 6 inches are pasted on a G8.5 glass substrate 111 as shown in FIG. 6, and silicon is formed to a film thickness of 400 nm using the conditions shown in FIG. A nitride film was formed.

  FIG. 10 is a table showing the deposition parameters of the silicon nitride film (SiN film) and the physical property values of the formed silicon nitride film. In FIG. 10, values that are different from the other conditions are shown in italic bold letters in the film forming parameters. FIG. 10 also shows physical property values of the formed silicon nitride film. The measuring method of the film thickness and other physical property values is the same as the measuring method described above.

  The experimental result shown in FIG. 10 is examined using FIG. 11 and FIG.

  FIG. 11 is a graph showing the relationship between the pressure in film formation and each physical property value. FIG. 11 shows data of condition A, condition A1, and condition A2 shown in FIG. 11A, 11B, and 11C show the relationship between the pressure, the stress on the silicon substrate, the Si—H bond amount, and the N—H bond amount, respectively.

FIG. 12 is a graph showing the relationship between the flow rate of silane gas (SiH ₄ ) and each physical property value. FIG. 12 shows data of condition A1, condition A3, and condition A4 shown in FIG. 12A, 12B, and 12C show the relationship between the silane gas flow rate, the stress on the silicon substrate, the Si—H bond amount, and the N—H bond amount, respectively.

As shown in FIGS. 10 and 11, when the pressure in film formation is increased from condition A (condition A1 and condition A2), the stress of the silicon nitride film changes from compressive stress to tensile stress. For example, in the condition A1, the stress on the silicon substrate is −100 MPa or more and 100 MPa or less at both the central portion and the end portion of the G8.5 glass substrate 111. On the other hand, of the amount of hydrogen atoms in the silicon nitride film, the amount of Si—H bonds increases as the pressure increases, and exceeds 2.3 × 10 ²¹ cm ⁻³ under conditions A1 and A2. Therefore, in order to reduce the amount of hydrogen atoms in the silicon nitride film, the silane gas flow rate was reduced in the conditions A3 and A4 than in the condition A1. As a result, as shown in FIGS. 10 and 12, in the conditions A3 and A4, the stress is equivalent to that in the condition A1, but the Si—H bond amount is lower than that in the condition A1. It was possible to maintain 3 × 10 ²¹ cm ⁻³ or less.

In addition, the stress with respect to the silicon substrate of the silicon nitride film measured according to each of the above conditions is a physical property value corresponding to the film density. That is, the greater the compressive stress of the silicon nitride film, the greater the film density. For example, film density of the silicon nitride film formed in the central portion of G8.5 glass substrate 111 by using the conditions A and A4 are each, 2.58 g / cm ^3, and, at 2.54 g / cm ³ is there.

  As described above, in the present embodiment, the stress relaxation of the gate insulating layer is attempted using the silicon nitride film formed using the condition A4 as the stress relaxation layer. Therefore, a thin film transistor using a silicon nitride film formed under condition A4 as a stress relaxation layer was produced. In the thin film transistor, a silicon nitride film having a relatively large compressive stress is formed to a thickness of 50 nm using Condition A as a gate insulating layer, and a silicon nitride film is formed thereon using Condition A4. A film was formed to a thickness of 300 nm. Further, a silicon oxide film was formed on the silicon nitride film so as to have a film thickness of 50 nm under the conditions shown in FIG. Here, the silicon nitride film having a thickness of 50 nm formed under the condition A was used as an adhesion layer for improving adhesion with the gate electrode. Therefore, the thin film transistor was manufactured, its electrical characteristics were measured, and compared with the electrical characteristics of the thin film transistor in which the silicon nitride film and the silicon oxide film formed under the condition A were used as the gate insulating layer. Note that the structure other than the gate insulating layer of the thin film transistor used in this experiment is the same as that of the thin film transistor used in the above experiment.

  FIG. 13A is a graph showing measurement results of electrical characteristics of a thin film transistor using a silicon nitride film and a silicon oxide film formed under the condition A as a gate insulating layer.

  FIG. 13B is a graph showing measurement results of electrical characteristics of the thin film transistor using the silicon nitride film formed under the condition A4 as the stress relaxation layer of the gate insulating layer.

In the example shown in FIG. 13B, the average value of the threshold values Vth is 0.59 V, and the variation is 1.82. Thus, in the example shown in FIG. 13B, the threshold value Vth is negatively shifted and the variation in the threshold value is also increased compared to the example shown in FIG. 13A. As shown in FIGS. 13A and 13B, the silicon nitride film formed using condition A and the silicon nitride film formed using condition A4 have the same amount of Si—H bonds in the film. There is also a difference in electrical characteristics. For the purpose of investigating this cause, an experiment was conducted to compare the amount of hydrogen desorption by thermal desorption gas analysis (TDS) of silicon nitride films formed under conditions A and A4, respectively. It was. In this experiment, a silicon nitride film formed with a film thickness of 400 nm on each silicon substrate using condition A and condition A4 was cut into 10 mm square, and H ₂ (M / z = 2) was measured by TDS. The amount of desorption was measured.

FIG. 14 is a graph showing the H ₂ desorption profile with respect to the substrate temperature with the film formation conditions as parameters.

FIG. 15 is a graph showing the amount of H ₂ desorption for each film forming condition when the substrate temperature is 350 ° C.

  14 and FIG. 15 are normalized by the measured sample weight (silicon nitride film weight).

  As shown in FIGS. 14 and 15, when the substrate temperature is 350 ° C. or higher, the silicon nitride film formed under the condition A4 has a larger desorption amount than the silicon nitride film formed under the condition A. From the results of this experiment, in the example shown in FIGS. 13A and 13B, the silicon nitride film formed using the condition A4 has more hydrogen atoms than the silicon nitride film formed using the condition A. Presumed to have detached. Therefore, in the thin film transistor in which the silicon nitride film formed under the condition A4 is used for the gate insulating layer, a large amount of hydrogen atoms are doped in the oxide semiconductor layer, and the carrier density in the oxide semiconductor layer is increased by the hydrogen atoms. It is estimated that the threshold value Vth has shifted in the negative direction.

Moreover, and H ₂ desorption amount in the silicon nitride film formed using the conditions A4, the difference of H ₂ desorption amount in the silicon nitride film formed using conditions A, the silicon atoms (Si) It is presumed that they are generated by unbonded hydrogen atoms that are not bonded to nitrogen atoms (N). Therefore, the unbonded hydrogen atom cannot be evaluated by FT-IR spectroscopy. Further, it is estimated that the unbonded hydrogen atoms contribute to stress relaxation of the silicon nitride film formed using the condition A4.

  From the above, it can be said that when a low-stress silicon nitride film is used as the gate insulating layer, a means for suppressing the negative shift of the threshold value Vth of the thin film transistor is necessary.

[4-3. Laminated structure of gate insulating layer]
As described above, when a low-stress silicon nitride film is used as the gate insulating layer, means for suppressing a minus shift of the threshold value Vth of the thin film transistor is necessary. Therefore, the results of studying the laminated structure of the gate insulating layer will be described.

  Here, the silicon nitride film formed using the condition A4 is used as a stress relaxation layer for the gate insulating layer, and the silicon nitride film formed using the condition A is stacked on the stress relaxation layer. Thus, a thin film transistor was manufactured. The purpose of this laminated structure is to dispose a silicon atom having a high compressive stress (that is, having a high film density) on the stress relaxation layer so that hydrogen atoms desorbed from the stress relaxation layer are transferred to the oxide semiconductor layer. It is to suppress movement.

  As the laminated structure of the gate insulating layer, a laminated structure composed of the first to fourth insulating layers shown in FIG. 4 and the like is adopted, and the film thickness of the first to fourth insulating layers is changed as shown in FIG. The electrical characteristics of the thin film transistor 100 and the amount of warpage of the substrate were measured. Note that the structure other than the gate insulating layer 130 of the thin film transistor 100 used in this experiment is the same as that of the thin film transistor used in the above experiment.

  FIG. 16 is a table showing the conditions of the thickness of each insulating layer in the thin film transistor 100 to be measured, the electrical characteristics of the thin film transistor 100 manufactured under the conditions, and the warpage amount of the TFT substrate 20.

  17A to 17F are graphs showing measurement results of electrical characteristics of the thin film transistor 100 manufactured under the conditions (a) to (f) shown in FIG. 16, respectively.

  From the condition (b), condition (c), condition (d) of FIG. 16, and FIGS. 17B, 17C, and 17D, the hydrogen atom blocking layer with respect to the film thickness of the second insulating layer 132 that is the stress relaxation layer. It can be seen that the variation in the threshold value Vth decreases as the ratio of the film thickness of a certain third insulating layer 133 increases. This is presumably because the movement of the hydrogen atoms desorbed from the second insulating layer 132 to the oxide semiconductor layer 140 is suppressed by the third insulating layer 133.

  Further, from the conditions (c) and (e) of FIG. 16 and FIGS. 17C and 17E, when the film thickness of the second insulating layer 132 is increased without changing the film thickness of the third insulating layer 133, The variation in threshold value increases. Further, from the conditions (e) and (f) of FIG. 16 and FIGS. 17E and 17F, the sum of the film thicknesses of the second insulating layer 132 and the third insulating layer 133 is made constant, and the third insulating layer 133 When the ratio is increased, the variation in threshold value Vth decreases.

  From the above, it can be said that the third insulating layer 133 that is a hydrogen atom blocking layer needs to be provided with a predetermined thickness over the second insulating layer 132 in order to suppress variation in the threshold value Vth of the thin film transistor 100. Here, for example, in order to set the variation of the threshold value Vth to 0.55 or less, the predetermined film thickness is obtained by subtracting the film thickness of the third insulating layer 133 from the film thickness of the second insulating layer 132 by 50 nm. What is necessary is just to set it as follows.

  Next, the relationship between the conditions of the above laminated structures and the warpage amount of the TFT substrate 20 will be described with reference to the drawings.

  As shown in FIG. 16, the warpage amount of the TFT substrate 20 changes with respect to the conditions (a) to (f) of the laminated structure. Note that the TFT substrate 20 was placed on the stage so that the warp amount (substrate sagging amount) of the TFT substrate 20 was 200 mm inside from the periphery of the TFT substrate 20 (G8.5 glass substrate). It measured by the amount of sagging of the edge of the TFT substrate 20 in the case. Here, the relationship between the ratio of the thickness of the second insulating layer 132 as the stress relaxation layer to the total thickness of the gate insulating layer 130 and the amount of warpage will be described with reference to FIG.

  FIG. 18 is a graph showing the relationship between the ratio of the thickness of the second insulating layer 132 to the total thickness of the gate insulating layer 130 and the variation in the warpage amount and threshold value Vth of the TFT substrate.

  As shown in FIGS. 16 and 18, when the ratio of the second insulating layer 132 is about 35% or more compared to the case where the second insulating layer 132 which is a stress relaxation layer is not provided (condition (a)), It can be seen that the warpage amount is reduced by about 1 mm, and there is an effect of reducing the warpage amount.

  As shown in FIGS. 16 and 18, when the ratio of the second insulating layer 132 is too large (about 45% or more), hydrogen atoms cannot be sufficiently blocked by the third insulating layer 133. The variation in Vth increases.

  From the above, in the gate insulating layer 130 of the stacked structure according to the present embodiment, the film thickness and stress of each layer are determined within a predetermined range, and the amount of hydrogen atoms in each layer is formed to be a predetermined amount or less. It has been found that even when the thickness of the gate insulating layer 130 is increased, the amount of warpage of the TFT substrate 20 can be reduced and variations in the electrical characteristics of the thin film transistor 100 can be suppressed.

[5. Summary]
As described above, the TFT substrate 20 according to the present embodiment is disposed at a position opposite to the gate electrode 120 above the substrate 110, the gate electrode 120 disposed above the substrate 110, and the substrate 110. And an oxide semiconductor layer 140 used as a channel layer, and a gate insulating layer 130 disposed between the gate electrode 120 and the oxide semiconductor layer 140. The gate insulating layer 130 is sequentially formed from the gate electrode 120 side. The first insulating layer 131, the second insulating layer 132, and the third insulating layer 133 are disposed, and the first insulating layer 131, the second insulating layer 132, and the third insulating layer 133 are formed of a silicon nitride film, insulating layer 131, the hydrogen atom content attached to a nitrogen atom and a silicon atom in the second insulating layer 132 and the third insulating layer 133, respectively, 3.3 × ¹⁰ 22 ^{cm -3} or less And, it is 2.3 × ¹⁰ 21 ^{cm -3} or less, the difference obtained by subtracting the thickness of the second insulating layer 132 having a thickness from the third insulating layer 133 is at 50nm or less, the film density of the second insulating layer 132 Is smaller than the film density of the first insulating layer 131 and the third insulating layer 133.

  In this manner, since the gate insulating layer 130 includes the second insulating layer 132 having a low film density, that is, a low compressive stress, the substrate 110 of the gate insulating layer 130 even if the thickness of the gate insulating layer 130 is increased. Compressive stress against can be suppressed. Therefore, the withstand voltage characteristic of the gate insulating layer 130 can be improved by increasing the thickness of the gate insulating layer 130 while suppressing the amount of warpage of the substrate 110. Further, the amount of hydrogen atoms bonded to nitrogen atoms and silicon atoms of the first to third insulating layers constituting the gate insulating layer 130 is suppressed, and the third insulating layer 133 has a predetermined thickness, and By using a silicon nitride film having a high film density (dense), the amount of hydrogen atoms doped into the oxide semiconductor layer 140 can be suppressed. Accordingly, reduction in resistance due to hydrogen atom doping of the oxide semiconductor layer 140 is suppressed, so that the electrical characteristics of the thin film transistor 100 can be stabilized. Further, by providing the first insulating layer 131 having a high film density, that is, a high compressive stress, on the gate electrode 120, adhesion between the gate electrode 120 and the first insulating layer 131 can be ensured.

  Further, for example, the stress on the silicon substrate of the second insulating layer 132 is −100 MPa or more and 100 MPa or less, and the stress on the silicon substrate of the first insulating layer 131 and the third insulating layer 133 is −400 MPa or more and −200 MPa or less. It may be.

  Thereby, the compressive stress with respect to the board | substrate 110 of the gate insulating layer 130 can be suppressed more reliably. In addition, the amount of hydrogen atoms doped into the oxide semiconductor layer 140 can be more reliably suppressed. In addition, the adhesion between the gate electrode 120 and the first insulating layer 131 can be further improved.

  For example, the ratio of the thickness of the second insulating layer 132 to the thickness of the entire gate insulating layer 130 may be 35% or more.

  As described above, since the ratio of the low-stress second insulating layer 132 to the gate insulating layer 130 is large, the stress due to the gate insulating layer 130 can be more reliably suppressed. Therefore, the amount of warpage of the substrate 110 can be more reliably reduced.

  For example, the total film thickness of the second insulating layer 132 and the third insulating layer 133 may be 300 nm or more and 600 nm or less.

  Thereby, the gate insulating layer 130 can have sufficient withstand voltage characteristics. Moreover, since the total film thickness is limited to 600 nm or less, it is possible to suppress an excessively long process (film formation) time, and thus it is possible to suppress a decrease in productivity of the TFT substrate 20.

  For example, the film thickness of the first insulating layer 131 may be 10 nm or more and 60 nm or less.

  Thereby, the adhesiveness between the first insulating layer 131 having a large compressive stress and the gate electrode 120 can be ensured.

  Further, for example, the second insulating layer 132 may be composed of a plurality of insulating layers. Further, another layer may be inserted between the plurality of insulating layers.

  For example, the gate insulating layer 130 further includes a fourth insulating layer 134 disposed between the third insulating layer 133 and the oxide semiconductor layer 140, and the fourth insulating layer 134 is formed of a silicon oxide film. May be.

  Accordingly, since the fourth insulating layer 134 with a small amount of hydrogen atoms is disposed on the oxide semiconductor layer 140 side of the gate insulating layer 130, the amount of hydrogen atoms doped into the oxide semiconductor layer 140 is suppressed. Therefore, the electrical characteristics of the thin film transistor 100 can be stabilized.

  For example, the film thickness of the fourth insulating layer 134 may be 10 nm or more and 100 nm or less.

  For example, the fourth insulating layer 134 may have a higher nitrogen atom concentration on the surface on the oxide semiconductor layer 140 side than in the central portion of the fourth insulating layer 134 in the film thickness direction.

  For example, the oxide semiconductor layer 140 may be made of a transparent amorphous oxide semiconductor.

  For example, the oxide semiconductor layer 140 may be made of InGaZnO.

In addition, the manufacturing method of the TFT substrate 20 according to the present embodiment includes a step of forming the gate electrode 120 above the substrate 110, and a channel layer above the substrate 110 at a position facing the gate electrode 120. The step of forming the oxide semiconductor layer 140 to be used and the step of forming the gate insulating layer 130 between the gate electrode 120 and the oxide semiconductor layer 140. Including a step of forming a first insulating layer 131, a second insulating layer 132, and a third insulating layer 133, which are sequentially disposed from the 120 side, and the first insulating layer 131, the second insulating layer 132, and the third insulating layer 133 are The amount of hydrogen atoms bonded to nitrogen atoms and silicon atoms in the first insulating layer 131, the second insulating layer 132, and the third insulating layer 133 is made of a silicon nitride film. Are respectively, 3.3 × ¹⁰ 22 ^{cm -3} or less, and is at 2.3 × ¹⁰ 21 ^{cm -3} or less, the difference obtained by subtracting the thickness of the film thickness of the second insulating layer 132 third insulating layer 133 Is 50 nm or less, and the film density of the second insulating layer 132 is lower than the film density of the first insulating layer 131 and the third insulating layer 133.

  As described above, since the second insulating layer 132 having a low film density, that is, a low compressive stress is formed as the gate insulating layer 130, even if the thickness of the gate insulating layer 130 is increased, the gate insulating layer 130 Compressive stress on the substrate 110 can be suppressed. Therefore, the withstand voltage characteristic of the gate insulating layer 130 can be improved by increasing the thickness of the gate insulating layer 130 while suppressing the amount of warpage of the substrate 110. Further, the amount of hydrogen atoms bonded to nitrogen atoms and silicon atoms in the first to third insulating layers constituting the gate insulating layer 130 is suppressed, and the third insulating layer 133 has a predetermined film thickness and a film density. By using a large (dense) silicon nitride film, the amount of hydrogen atoms doped into the oxide semiconductor layer 140 can be suppressed. Accordingly, reduction in resistance due to hydrogen atom doping of the oxide semiconductor layer 140 is suppressed, so that the electrical characteristics of the thin film transistor 100 can be stabilized. Further, by providing the first insulating layer 131 having a high film density, that is, a high compressive stress, on the gate electrode 120, adhesion between the gate electrode 120 and the first insulating layer 131 can be ensured.

(Other embodiments)
As described above, the embodiments have been described as examples of the technology disclosed in the present application. However, the technology in the present disclosure is not limited to this, and can also be applied to an embodiment in which changes, replacements, additions, omissions, and the like are appropriately performed.

  Thus, other embodiments will be exemplified below.

  For example, the TFT substrate 20 according to the above embodiment may not include the fourth insulating layer 134.

  Further, for example, in the above embodiment, before the channel protective layer 150 is formed, the oxidation treatment may be performed under appropriate conditions. Specifically, heat treatment, plasma treatment, or a combination thereof may be performed after the oxide semiconductor layer 140 is formed and before the channel protective layer 150 is formed.

  For example, the heat treatment is an annealing treatment with dry air at a temperature of 300 ° C. to 350 ° C. within about one hour.

  Accordingly, oxygen defects in the oxide semiconductor layer 140 can be reduced and impurities on the surface of the oxide semiconductor layer 140 can be removed.

  Further, for example, in the above embodiment, the thin film transistor 100 has a bottom gate type and a channel protection type configuration, but is not limited thereto. For example, the thin film transistor 100 may be a top gate type or a channel etch type.

  For example, in the above embodiment, the organic EL display device 10 is described as a display device using the thin film transistor 100. However, the thin film transistor 100 in the above embodiment uses an active matrix substrate such as a liquid crystal display device. The present invention can also be applied to other display devices.

  In addition, the display device (display panel) such as the organic EL display device 10 described above can be used as a flat panel display, and is applied to all electronic devices having a display panel such as a television set, a personal computer, and a mobile phone. can do. In particular, it is suitable for a large-screen and high-definition display device.

  As described above, the embodiments have been described as examples of the technology in the present disclosure. For this purpose, the accompanying drawings and detailed description are provided.

  Accordingly, among the components described in the attached drawings and detailed description, not only the components essential for solving the problem, but also the components not essential for solving the problem in order to exemplify the above technique. May also be included. Therefore, it should not be immediately recognized that these non-essential components are essential as those non-essential components are described in the accompanying drawings and detailed description.

  Moreover, since the above-mentioned embodiment is for demonstrating the technique in this indication, a various change, substitution, addition, abbreviation, etc. can be performed in a claim or its equivalent range.

  The thin film transistor substrate and the manufacturing method thereof according to the present disclosure can be used for, for example, a display device such as an organic EL display device and a manufacturing method thereof.

10 Organic EL display device 20 TFT substrate 21 Bank 30 Pixel 30B, 30G, 30R Sub pixel 31 Pixel circuit 32, 33, 100 Thin film transistor 32d, 33d, 160d Drain electrode 32g, 33g, 120 Gate electrode 32s, 33s, 160s Source electrode 34 Capacitor 40 Organic EL element 41 Anode 42 EL layer 43 Cathode 50 Gate wiring 60 Source wiring 70 Power supply wiring 110 Substrate 111 G8.5 glass substrate 112 Orientation flat 115, 116 Silicon substrate 130 Gate insulating layer 131 First insulating layer 132 Second Insulating layer 133 Third insulating layer 134 Fourth insulating layer 140 Oxide semiconductor layer 150 Channel protective layer 170 Interlayer insulating layer 171 Lower interlayer insulating layer 172 Barrier layer 173 Upper interlayer insulating layer 180 Upper electrode 190 Upper insulating layer 1 1 contact hole 201 plasma

Claims (12)

A substrate,
A gate electrode disposed above the substrate;
An oxide semiconductor layer disposed above the gate electrode and facing the gate electrode and used as a channel layer;
A gate insulating layer disposed between the gate electrode and the oxide semiconductor layer,
The gate insulating layer includes a first insulating layer, a second insulating layer, and a third insulating layer disposed in order from the gate electrode side,
The first insulating layer, the second insulating layer, and the third insulating layer are composed of a silicon nitride film,
The amount of hydrogen atoms bonded to nitrogen atoms and silicon atoms in the first insulating layer, the second insulating layer, and the third insulating layer is 3.3 × 10 ²² cm ⁻³ or less, and 2.3 ×, respectively. 10 ²¹ cm ⁻³ or less,
The difference obtained by subtracting the thickness of the third insulating layer from the thickness of the second insulating layer is 50 nm or less,
The thin film transistor substrate, wherein a film density of the second insulating layer is smaller than a film density of the first insulating layer and the third insulating layer. The stress on the silicon substrate of the second insulating layer is -100 MPa or more and 100 MPa or less,
The thin film transistor substrate according to claim 1, wherein stresses on the silicon substrate of the first insulating layer and the third insulating layer are −400 MPa or more and −200 MPa or less. The thin film transistor substrate according to claim 1, wherein a ratio of the film thickness of the second insulating layer to the film thickness of the entire gate insulating layer is 35% or more. The thin film transistor substrate according to claim 1, wherein a total film thickness of the second insulating layer and the third insulating layer is 300 nm or more and 600 nm or less. 5. The thin film transistor substrate according to claim 1, wherein a film thickness of the first insulating layer is not less than 10 nm and not more than 60 nm. The thin film transistor substrate according to claim 1, wherein the second insulating layer includes a plurality of insulating layers. The gate insulating layer further includes a fourth insulating layer disposed between the third insulating layer and the oxide semiconductor layer,
The thin film transistor substrate according to claim 1, wherein the fourth insulating layer is formed of a silicon oxide film. The thin film transistor substrate according to claim 7, wherein a film thickness of the fourth insulating layer is 10 nm or more and 100 nm or less. 9. The thin film transistor substrate according to claim 7, wherein the fourth insulating layer has a nitrogen atom concentration higher on a surface on the oxide semiconductor layer side than a central portion in a film thickness direction of the fourth insulating layer. The thin film transistor substrate according to claim 1, wherein the oxide semiconductor layer is made of a transparent amorphous oxide semiconductor. The thin film transistor substrate according to claim 1, wherein the oxide semiconductor layer is made of InGaZnO. A method for manufacturing a thin film transistor substrate, comprising:
Forming a gate electrode above the substrate;
Forming an oxide semiconductor layer used as a channel layer above the gate electrode and at a position facing the gate electrode;
Forming a gate insulating layer between the gate electrode and the oxide semiconductor layer,
The step of forming the gate insulating layer includes a step of forming a first insulating layer, a second insulating layer, and a third insulating layer, which are sequentially arranged from the gate electrode side,
The first insulating layer, the second insulating layer, and the third insulating layer are composed of a silicon nitride film,
The amount of hydrogen atoms bonded to nitrogen atoms and silicon atoms in the first insulating layer, the second insulating layer, and the third insulating layer is 3.3 × 10 ²² cm ⁻³ or less, and 2.3 ×, respectively. 10 ²¹ cm ⁻³ or less,
The difference obtained by subtracting the thickness of the third insulating layer from the thickness of the second insulating layer is 50 nm or less,
A method of manufacturing a thin film transistor substrate, wherein the film density of the second insulating layer is smaller than the film density of the first insulating layer and the third insulating layer.

Images