JP2016100362A - Semiconductor device and semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacturing method of the same, which can inhibit resistance value variation caused when voltage applied between terminals of a resistor body composed of metal of non-metal is changed.SOLUTION: A semiconductor device 10 according to the present embodiment comprises: a substrate 1; a resistor body 5 which is formed above the substrate 1 and surrounded by an insulation layer 2; an intermediate dummy pattern 42 formed between the substrate 1 and the resistor body 5 and an upper dummy pattern 43 formed above the resistor body 5; and a plug 3 which connects the upper dummy pattern 43 and the intermediate dummy pattern 42 with the substrate 1. The resistor body 5 has a portion which overlaps the upper dummy pattern 43 and the intermediate dummy pattern 42 when viewed from the resistor body 5 side toward the substrate 1 side. A heat conductivity of each of the upper dummy pattern 43, the intermediate dummy pattern 42 and the plug 3 is higher than a heat conductivity of the insulation layer 2.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  A resistor made of metal (hereinafter also referred to as “metal resistor”) is known as a resistor having a small frequency dependency of resistance value and a temperature coefficient of resistance and being stable against heat during mounting and use. ing. And there exists a semiconductor device provided with this metal resistor in patent document 1, for example. Japanese Patent Application Laid-Open No. H11-260260 discloses a lower surface anti-oxidation insulating film formed on the lower surface of the metal resistor, an upper surface anti-oxidation insulating film formed on the upper surface of the metal resistor, and a side surface formed only near the side surface of the metal resistor. A semiconductor device having an antioxidant insulating film is described. Patent Document 1 also describes a method for manufacturing the semiconductor device.

JP 2009-302082 A

  The semiconductor device formed on the basis of the manufacturing method described in Patent Document 1 has a so-called resistance value fluctuation that varies when the voltage applied between the terminals of the metal resistor is changed. The inventors of the present application (hereinafter, also simply referred to as “inventor”) have found that the width (that is, the fluctuation range) is large. If the resistance value fluctuates and the fluctuation range is large, the resistance value of the metal resistor is not within a preset allowable range, and the semiconductor device may not be able to perform its intended function. Note that the above-described resistance value fluctuation can occur even in a resistor made of a nonmetal (hereinafter also referred to as “nonmetal resistor”). For this reason, even in a semiconductor device provided with a non-metallic resistor, if the resistance value fluctuates and the fluctuation width is large, the planned function may not be exhibited.

  The present invention has been made in view of such circumstances, and is a semiconductor capable of suppressing resistance value fluctuations that occur when a voltage applied between terminals of a resistor made of metal or nonmetal is changed. An object is to provide an apparatus and a method for manufacturing the same.

  A semiconductor device according to one embodiment of the present invention includes a substrate, a resistive element formed above the substrate and surrounded by an insulating layer, and formed between the substrate and the resistive element, and is not used as an element. 1 dummy pattern and at least one of a second dummy pattern formed above the resistance element and not used as an element, at least one of the first dummy pattern and the second dummy pattern, and the substrate A connecting portion to be connected, and the resistance element has a portion that overlaps at least one of the first dummy pattern and the second dummy pattern when viewed from the resistance element side toward the substrate side. The thermal conductivity of the first dummy pattern, the second dummy pattern, and the connection portion is higher than the thermal conductivity of the insulating layer, respectively. .

  ADVANTAGE OF THE INVENTION According to this invention, the resistance value fluctuation | variation which arises when changing the voltage applied between the terminals of the resistor which consists of a metal or a nonmetal can be suppressed.

1 is a perspective view schematically showing the structure of a semiconductor device according to a first embodiment. It is manufacturing process sectional drawing which showed the manufacturing method of the semiconductor device which concerns on 1st Embodiment in process order. It is manufacturing process sectional drawing which showed the manufacturing method of the semiconductor device which concerns on 1st Embodiment in process order. It is manufacturing process sectional drawing which showed the manufacturing method of the semiconductor device which concerns on 1st Embodiment in process order. It is manufacturing process sectional drawing which showed the manufacturing method of the semiconductor device which concerns on 1st Embodiment in process order. It is a figure which shows the applied voltage dependence of resistance value fluctuation | variation. It is a figure which shows the resistor coverage dependency of the terminal voltage dependence secondary coefficient (alpha). It is the perspective view which showed typically the structure of the semiconductor device used in the experiment regarding the resistor coverage dependency of the inter-terminal voltage dependency secondary coefficient α. It is the top view which showed typically the shape of the upper dummy pattern and intermediate dummy pattern which were used in order to adjust a resistor coverage. It is the perspective view which showed typically the structure of the semiconductor device used in the experiment regarding the resistor width dependence of the inter-terminal voltage dependence secondary coefficient (alpha). It is the perspective view which showed typically the structure of the semiconductor device which concerns on each 2nd-4th embodiment.

In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of embodiments of the present invention. However, it will be apparent that one or more embodiments may be practiced without such specific details. In other instances, well-known structures and devices are schematically shown in order to simplify the drawing.
[First Embodiment]
Hereinafter, the structure of the semiconductor device and the manufacturing method thereof according to the first embodiment of the present invention will be described with reference to FIGS. Note that, in each drawing described below, parts having the same configuration are denoted by the same reference numerals, and repeated description thereof is omitted.

<Overall Structure of Semiconductor Device 10>
FIG. 1 is a perspective view schematically showing the structure of the semiconductor device 10 according to the first embodiment. As shown in FIG. 1, the semiconductor device 10 includes a substrate 1, an insulating layer 2, a plug 3, a dummy pattern 4, a resistor 5, and voltage application terminals 6 and 7 as main components. ing. More specifically, the semiconductor device 10 includes a substrate 1, a resistor 5 formed above the substrate 1, an upper dummy pattern 43 formed above the resistor 5, and between the substrate 1 and the resistor 5. And the lower dummy pattern 41 formed between the intermediate dummy pattern 42 and the substrate 1. The thermal conductivities of the upper, middle, and lower dummy patterns 43, 42, 41 are higher than the thermal conductance of the insulating layer 2 surrounding the resistor 5. The upper, middle, and lower dummy patterns 43, 42, and 41 are connected to the substrate 1 through plugs 3 having a thermal conductivity higher than that of the insulating layer 2. Hereinafter, details of each member constituting the semiconductor device 10 will be described.

(Substrate 1)
The substrate 1 is a semiconductor substrate, for example, a silicon (Si) substrate. More specifically, the substrate 1 is, for example, a single crystal Si substrate into which P-type impurities or N-type impurities are introduced at a concentration of 5 × 10 ¹⁴ pieces / cm ³ to about 1 × 10 ¹⁶ pieces / cm ³ . The plane orientation of the Si substrate surface is (111). Note that the lower the impurity concentration, the higher the thermal conductivity of the substrate 1, which is preferable.

(Resistor 5)
A resistor 5 extending along the Y-axis direction is formed above the substrate 1. Here, the “Y-axis direction” refers to a direction in which a current flows when a voltage is applied to the resistor 5. An “X-axis direction” described later is a direction orthogonal to the Y-axis direction and is horizontal to the surface of the substrate 1. Further, the “Z-axis direction” refers to a direction perpendicular to the Y-axis direction and perpendicular to the surface of the substrate 1.

The resistor 5 has a rectangular parallelepiped shape. Further, the upper surface 5 a located on the opposite side of the substrate 1 and the lower surface 5 b located on the substrate 1 side are disposed substantially parallel to the surface of the substrate 1. For this reason, the shape of the resistor 5 is a quadrangle when viewed from the Z-axis direction.
The resistor 5 is a resistance element made of metal, for example, a resistance element made of tantalum nitride (TaN).

(Voltage application terminals 6, 7)
At both ends of the upper surface 5 a of the resistor 5, voltage application terminals 6 and 7 that are terminals for applying a voltage to the resistor 5 are formed to face each other. The voltage application terminals 6 and 7 extend from the upper surface 5a of the resistor 5 in the Z-axis direction, and the shapes thereof are rectangular parallelepipeds. The sizes of the voltage application terminals 6 and 7 are substantially the same.
The voltage application terminals 6 and 7 are terminals made of metal, for example, terminals made of tungsten (W) or aluminum (Al).

(Upper dummy pattern 43)
The dummy pattern 4 includes upper, middle, and lower dummy patterns 43, 42, and 41, which will be described later. Hereinafter, each dummy pattern will be described in detail.
An upper dummy pattern 43 extending in the X-axis direction is formed above the resistor 5. The upper dummy pattern 43 has a rectangular parallelepiped shape. Further, the upper surface 43 a located on the opposite side of the substrate 1 and the lower surface 43 b located on the substrate 1 side are disposed substantially parallel to the surface of the substrate 1. For this reason, the shape of the upper dummy pattern 43 is a quadrangle when viewed from the Z-axis direction. Further, the upper dummy pattern 43 is disposed between the voltage application terminals 6 and 7 when viewed from the Z-axis direction, and overlaps the central portion of the resistor 5. In other words, the central portion of the resistor 5 is covered with the upper dummy pattern 43 in plan view.

The upper dummy pattern 43 is a dummy pattern made of metal, for example, a dummy pattern made of W or Al. Here, the “dummy pattern” means a pattern that is not used as an element such as a resistor or a wiring.
The upper dummy pattern 43 and the resistor 5 are insulated, and an insulating layer 2 described later is formed between the upper dummy pattern 43 and the resistor 5. The upper dummy pattern 43 is thicker than the resistor 5.

(Intermediate dummy pattern 42)
An intermediate dummy pattern 42 extending in the X-axis direction is formed between the substrate 1 and the lower surface 5 b of the resistor 5. The intermediate dummy pattern 42 has a rectangular parallelepiped shape. Further, the upper surface 42 a located on the side opposite to the substrate 1 and the lower surface 42 b located on the substrate 1 side are respectively arranged in parallel to the surface of the substrate 1. For this reason, the shape of the intermediate dummy pattern 42 is a quadrangle when viewed from the Z-axis direction. Further, the intermediate dummy pattern 42 overlaps the central portion of the resistor 5 when viewed from the Z-axis direction. The planar shape of the intermediate dummy pattern 42 is substantially the same as the planar shape of the upper dummy pattern 43, and the intermediate dummy pattern 42 overlaps with the upper dummy pattern 43 when viewed from the Z-axis direction.

The intermediate dummy pattern 42 is a dummy pattern formed of metal, for example, a dummy pattern formed of W or Al. More specifically, the intermediate dummy pattern 42 is a dummy pattern formed of the same material as the upper dummy pattern 43, for example.
The intermediate dummy pattern 42 and the resistor 5 are insulated from each other, and the insulating layer 2 is formed between the intermediate dummy pattern 42 and the resistor 5. That is, the resistor 5 sandwiched between the intermediate dummy pattern 42 and the upper dummy pattern 43 is covered with the insulating layer 2. The intermediate dummy pattern 42 is thicker than the resistor 5 and thinner than the upper dummy pattern 43.

(Lower dummy pattern 41)
A lower dummy pattern 41 extending in the X-axis direction is formed between the substrate 1 and the lower surface 42b of the intermediate dummy pattern 42. The lower dummy pattern 41 has a rectangular parallelepiped shape and is substantially the same as the intermediate dummy pattern 42. Further, the upper surface 41 a located on the opposite side of the lower dummy pattern 41 from the substrate 1 and the lower surface 41 b located on the substrate 1 side of the lower dummy pattern 41 are arranged in parallel to the surface of the substrate 1. . For this reason, the shape of the lower dummy pattern 41 is a quadrangle when viewed from the Z-axis direction. Further, the planar shape of the lower dummy pattern 41 is substantially the same as the planar shape of the upper and middle dummy patterns 43 and 42, and the lower dummy pattern 41 has the upper and middle dummy patterns when viewed from the Z-axis direction. It overlaps with the patterns 43 and 42.

The lower dummy pattern 41 is a dummy pattern formed of metal, for example, a dummy pattern formed of W or Al. More specifically, the lower dummy pattern 41 is a dummy pattern formed of the same material as the upper and middle dummy patterns 43 and 42, for example.
The lower dummy pattern 41 and the intermediate dummy pattern 42 are insulated, and the insulating layer 2 is formed between the lower dummy pattern 41 and the intermediate dummy pattern 42. Further, the insulating layer 2 is also formed between the lower dummy pattern 41 and the substrate 1. The lower dummy pattern 41 is thicker than the resistor 5 and thinner than the upper dummy pattern 43.

(Plug 3)
The plug 3 includes upper, middle, and lower plugs 33, 32, and 31, which will be described later. This will be described in detail below.
Between the upper dummy pattern 43 and the intermediate dummy pattern 42, a pair of upper plugs 33 that connect the respective ends of the lower surface 43b of the upper dummy pattern 43 and the upper surface 42a of the intermediate dummy pattern 42 are formed to face each other. ing. Further, between the intermediate dummy pattern 42 and the lower dummy pattern 41, a pair of intermediate plugs 32 respectively connecting the end portions of the lower surface 42 b of the intermediate dummy pattern 42 and the upper surface 41 a of the lower dummy pattern 41 are opposed to each other. Is formed. Further, between the lower dummy pattern 41 and the substrate 1, a pair of lower plugs 31 that respectively connect the end of the lower surface 41 b of the lower dummy pattern 41 and the surface of the substrate 1 are formed to face each other. That is, the upper, middle, and lower dummy patterns 43, 42, and 41 are connected to the substrate 1 via the plug 3 and are in thermal contact with each other.

The upper, middle, and lower plugs 33, 32, and 31 extend in the Z-axis direction, and the shapes thereof are rectangular parallelepipeds. The upper, middle, and lower plugs 33, 32, and 31 are formed on the same axis and overlap each other when viewed from the Z-axis direction.
The resistor 5 is located between the upper plugs 33. In other words, the resistor 5 is located between the upper dummy pattern 43 and the intermediate dummy pattern 42 and is located between the upper plugs 33. Further, the resistor 5 is insulated from all of the upper dummy pattern 43, the intermediate dummy pattern 42, and the upper plug 33.

Each of the upper, middle, and lower plugs 33, 32, and 31 is a plug formed of metal, for example, a plug formed of W or Al.
The length of the upper plug 33 in the Z-axis direction is longer than the length of the intermediate plug 32 and the lower plug 31 in the Z-axis direction. The shapes of the intermediate plug 32 and the lower plug 31 are substantially the same.

(Insulating layer 2)
An insulating layer 2 is formed around the upper, middle, and lower dummy patterns 43, 42, and 41, the resistor 5, and the plug 3 to cover them. In other words, each of the upper, middle, and lower dummy patterns 43, 42, 41, the resistor 5, and the plug 3 is covered with the insulating layer 2.

The insulating layer 2 is a layer (film) formed of an insulating material, for example, a layer formed of silicon dioxide (SiO ₂ ). Further, the thermal conductivity of the insulating layer 2 is lower than that of the dummy pattern 4 and the plug 3. The specific values of thermal conductivity are as follows: SiO ₂ is about 1 W / m · k, W is about 173 W / m · k, Al is about 236 W / m · k, and Si is about 168 W. / M · k.
As will be described later, the insulating layer 2 includes lower, middle, first upper, and second upper insulating layers 21, 22, 23, and 24.

(Coverage of resistor 5)
As described above, the resistor 5 according to the present embodiment has a portion that overlaps with the upper dummy pattern 43 and the intermediate dummy pattern 42 when viewed from the Z-axis direction. The ratio of the overlapping portion to the upper surface 5a and the lower surface 5b of the resistor 5 (that is, the coverage C of the resistor 5) is defined by the following formula (2). The coverage C is preferably 60% or more, and more preferably 80% or more in the semiconductor device 10 according to the present embodiment.
C = (SD1 + SD2) / (SR1 + SR2) × 100 (2)
However,
C: Resistor 5 coverage (%)
SD1: Area of the portion where the upper dummy pattern 43 and the upper surface 5a of the resistor 5 overlap when viewed from the Z-axis direction. SD2: The intermediate dummy pattern 42 and the lower surface of the resistor 5 when viewed from the Z-axis direction. SR1: Area of upper surface 5a of resistor 5 SR2: Area of lower surface 5b of resistor 5

  In the semiconductor device 10 according to the present embodiment, the “upper dummy pattern 43” corresponds to a “second dummy pattern”, and the “intermediate dummy pattern 42” corresponds to a “first dummy pattern”. . The “resistor 5” corresponds to a “resistive element”. Further, “the upper surface 5a of the resistor 5” corresponds to “the surface on the second dummy pattern side of the resistor element”, and “the lower surface 5b of the resistor 5” is “the surface of the resistor element on the first dummy pattern side”. It is equivalent to. The “plug 3” corresponds to a “connecting portion”.

<Method for Manufacturing Semiconductor Device 10>
Hereinafter, a method for manufacturing the semiconductor device 10 according to the present embodiment will be described with reference to FIGS. 2 to 5 are manufacturing process cross-sectional views illustrating the manufacturing method of the semiconductor device 10 according to this embodiment in the order of processes. The left side of each figure schematically shows a cross-sectional view taken along the line AA shown in FIG. 1, and the right side schematically shows the cross-sectional view taken along the line BB shown in FIG. ing.

First, as shown in FIGS. 2A and 2B, a lower insulating layer 21 made of SiO ₂ is formed on a substrate 1 made of Si. The lower insulating layer 21 can be formed by, for example, a CVD (Chemical Vapor Deposition) method using TEOS (Tetra Ethyl Ortho Silicate).
Note that the surface of the lower insulating layer 21 shown in FIGS. 2A and 2B is planarized by, for example, CMP (Chemical Mechanical Polishing).

Next, a pair of through holes (not shown) that expose a part of the surface of the substrate 1 are formed in the lower insulating layer 21. This through hole is formed, for example, by dry etching the lower insulating layer 21. This dry etching is performed using, for example, CF (fluorinated carbon) gas when the lower insulating layer 21 is formed of SiO ₂ .
Thereafter, as shown in FIGS. 2C and 2D, a pair of lower plugs 31 are formed which are connected to the exposed surface of the substrate 1 and fill each through hole. The lower plug 31 can be formed, for example, by vapor deposition of W or Al.

Next, as shown in FIGS. 2E and 2F, a lower dummy pattern 41 connected to each lower plug 31 is formed on the lower insulating layer 21. The lower dummy pattern 41 can be formed, for example, by patterning a metal film formed by vapor deposition of W or Al.
Next, as shown in FIGS. 2G and 2H, an intermediate insulating layer 22 made of SiO ₂ is formed so as to cover the lower dummy pattern 41. Similar to the lower insulating layer 21, the intermediate insulating layer 22 can be formed by, for example, a CVD method using TEOS. In the present embodiment, the film thickness of the intermediate insulating layer 22 is made larger than the film thickness of the lower insulating layer 21, but the film thickness of the intermediate insulating layer 22 can be adjusted as appropriate.

Note that the surface of the intermediate insulating layer 22 shown in FIGS. 2G and 2H is planarized by, for example, CMP.
Next, a pair of through-holes (not shown) are formed in the intermediate insulating layer 22 to expose the surfaces located at both ends of the lower dummy pattern 41 and above the lower plug 31. For example, the through hole is formed by dry etching the intermediate insulating layer 22. This dry etching is performed using, for example, a CF-based gas when the intermediate insulating layer 22 is formed of SiO ₂ .

Thereafter, as shown in FIGS. 3A and 3B, a pair of intermediate plugs 32 are formed to connect to the exposed surface 41a of the lower dummy pattern 41 and fill the through holes. The intermediate plug 32 can be formed by, for example, vapor deposition of W or Al, similarly to the lower plug 31.
Next, as shown in FIGS. 3C and 3D, intermediate dummy patterns 42 connected to the intermediate plugs 32 are connected to the intermediate insulating layer so as to overlap the lower dummy patterns 41 when viewed from the stacking direction. 22 is formed. Similar to the lower dummy pattern 41, the intermediate dummy pattern 42 can be formed by patterning a metal film formed by vapor deposition of W or Al, for example.

Next, as shown in FIGS. 3E and 3F, a first upper insulating layer 23 made of SiO ₂ is formed so as to cover the intermediate dummy pattern 42. The first upper insulating layer 23 can be formed by, for example, a CVD method using TEOS, similarly to the lower and intermediate insulating layers 21 and 22. In the present embodiment, the film thickness of the first upper insulating layer 23 is formed to be substantially the same as the film thickness of the intermediate insulating layer 22, but the film thickness of the first upper insulating layer 23 is appropriately adjusted. Is possible.

The surface of the first upper insulating layer 23 shown in FIGS. 3E and 3F is planarized by, for example, CMP, similarly to the surfaces of the lower and intermediate insulating layers 21 and 22. Yes.
Next, as shown in FIGS. 4A and 4B, the resistor 5 made of TaN is placed between the intermediate plugs 32 and overlaps with the intermediate dummy pattern 42 when viewed from the stacking direction. 1 formed on the upper insulating layer 23; The resistor 5 can be formed, for example, by patterning a TaN film formed by a reactive sputtering method.

Next, as shown in FIGS. 4C and 4D, a second upper insulating layer 24 made of SiO ₂ is formed so as to cover the resistor 5. The second upper insulating layer 24 can be formed by, for example, a CVD method using TEOS, similarly to the lower, middle, and first upper insulating layers 21, 22, and 23. In the present embodiment, the film thickness of the second upper insulating layer 24 is formed so as to be smaller than the film thicknesses of the lower, middle and first upper insulating layers 21, 22, 23. 2 The film thickness of the upper insulating layer 24 can be adjusted as appropriate.

The surface of the second upper insulating layer 24 shown in FIGS. 4C and 4D is similar to the surfaces of the lower, middle and first upper insulating layers 21, 22, and 23, for example, Planarized by CMP.
Next, a pair of through-holes (not shown) are formed in the first and second upper insulating layers 23 and 24 to expose the surfaces located at both ends of the intermediate dummy pattern 42 and above the intermediate plug 32. Form consistently. For example, the through holes are formed by dry etching the first and second upper insulating layers 23 and 24. This dry etching can be performed using, for example, a CF-based gas when the first and second upper insulating layers 23 and 24 are formed of SiO ₂ .

Thereafter, as shown in FIGS. 5A and 5B, a pair of upper plugs 33 are formed which are connected to the exposed surface 42a of the intermediate dummy pattern 42 and fill each through hole. The upper plug 33 can be formed, for example, by vapor deposition of W or Al, similarly to the lower and intermediate plugs 31 and 32.
Next, a pair of through holes are formed in the second upper insulating layer 24 to expose part of the surface at both ends of the resistor 5. For example, the through hole is formed by dry etching the second upper insulating layer 24. This dry etching can be performed using, for example, a CF-based gas when the second upper insulating layer 24 is formed of SiO ₂ .

Next, as shown in FIG. 5C and FIG. 5D, each of the second upper insulating layer 24 is overlapped with the lower and intermediate dummy patterns 41 and 42 when viewed from the stacking direction. An upper dummy pattern 43 connected to the upper plug 33 is formed, and a pair of voltage application terminals 6 and 7 that are connected to the exposed surface 5a of the resistor 5 and fill each through hole are formed consistently. The upper dummy pattern 43 and the voltage application terminals 6 and 7 can be formed, for example, by patterning a metal film formed by vapor deposition of W or Al.
The semiconductor device 10 according to this embodiment is manufactured through the above steps.

(Experimental result)
In order to verify the operational effects of the semiconductor device 10 according to the present embodiment, the inventors have (1) a resistance value fluctuation dependent on applied voltage, and (2) a terminal voltage dependent secondary coefficient α resistor. Coverage Dependency and (3) Terminal Voltage Dependence An experiment was conducted on the resistance width dependence of the secondary coefficient α. Hereinafter, these experimental results will be described.

(1) Dependence of resistance value variation on applied voltage The inventors applied each voltage to the resistor 5 included in the semiconductor device 10 according to this embodiment, and measured the resistance value variation. From the resistance value fluctuation for each voltage thus obtained, knowledge about the dependence of the resistance fluctuation on the applied voltage was obtained. Hereinafter, experimental results of the dependency of the resistance value variation on the applied voltage will be described.

FIG. 6 is a diagram showing an experimental result on the applied voltage dependence of the resistance value variation performed by the inventors. In FIG. 6, the vertical axis indicates the standardized resistance value (that is, the resistance value variation), and the horizontal axis indicates the voltage applied to the voltage application terminal 6 of the resistor 5. At this time, the voltage application terminal 7 is fixed at 0V.
From the behavior of the resistance value variation shown in FIG. 6, the resistance value variation has a second-order dependency on the voltage V (hereinafter simply referred to as “applied voltage”) V applied to the voltage application terminal 6. I understand. This means that the resistance value of the resistor 5 varies by “α × V ² ” with respect to the applied voltage V. Here, “α” is a coefficient called a voltage dependency secondary coefficient between terminals, and the voltage dependency secondary coefficient α between terminals of the semiconductor device 10 used in this experiment was −47 ppm / V ² . .
In FIG. 6, each measured data is indicated by “◇”, and the solid line shown in FIG. 6 is a curve obtained by fitting each measured data. The above-mentioned inter-terminal voltage dependency secondary coefficient α is calculated from this fitting curve (solid line).

(2) Voltage dependency between terminals About the resistor coverage dependency of the secondary coefficient α The inventors created several types of semiconductor devices having different coverage C of the resistor 5, and the voltage dependency between terminals in each semiconductor device. The secondary coefficient α was measured. From the voltage dependency secondary coefficient α between terminals for each coverage C thus obtained, knowledge about the resistor coverage dependency of the voltage dependency secondary coefficient α between terminals was obtained. Hereinafter, experimental results of the dependency of the resistance value variation on the applied voltage will be described.

  FIG. 7 is a diagram showing an experimental result of the dependency of the inter-terminal voltage dependency secondary coefficient α on the resistor coverage ratio performed by the inventors. In FIG. 7, the vertical axis represents the inter-terminal voltage dependence quadratic coefficient α, and the horizontal axis represents the coverage C of the resistor 5. Here, data regarding the semiconductor device 10 according to the present embodiment is indicated by “●”, and each data regarding the semiconductor device 20 according to the comparative example described later (see FIGS. 8 and 9) is indicated by “◯”. ing. Moreover, the solid line shown in FIG. 7 is a curve obtained by fitting each data in the semiconductor device 20 according to the comparative example. Also, the broken line shown in FIG. 7 is a curve obtained by fitting data in the semiconductor device 10 according to the present embodiment based on the solid line.

  As shown in FIG. 7, the inter-terminal voltage dependency secondary coefficient α tends to increase as the coverage C of the resistor 5 increases. More specifically, the voltage dependency secondary coefficient α between the terminals tends to decrease and stabilize when the covering ratio C of the resistor 5 is 49% or more, and the covering ratio C of the resistor 5 is 60. If it is at least%, it tends to be particularly stabilized. Further, the inter-terminal voltage dependency quadratic coefficient α of the semiconductor device 10 according to the present embodiment is larger than the inter-terminal voltage dependency quadratic coefficient α (small value in absolute value) of the semiconductor device 20 according to the comparative example. It has become.

From the above experimental results, in the semiconductor device 10 according to the present embodiment, when the covering ratio C of the resistor 5 is 49% or more, the inter-terminal voltage dependency secondary coefficient α may be −25 ppm / V ² or less. all right. In other words, it has been found that the covering ratio C of the resistor 5 is preferably 49% or more in order to set the voltage dependency secondary coefficient α to −25 ppm / V ² or less.
The higher the coverage C of the resistor 5, the better. The coverage C of the resistor 5 is, for example, preferably 60% or more, more preferably 80% or more, and particularly preferably 95% or more.

  In addition, the experimental result shows that the inter-terminal voltage-dependent secondary coefficient α is increased by connecting the upper, middle, and lower dummy patterns 43, 42, and 41 to the substrate 1 via the plug 3 ( It means that the absolute value is smaller). In other words, the dependency on the applied voltage between the terminals is reduced by connecting each dummy pattern 43, 42, 41 and the substrate 1 via the plug 3 to improve the heat radiation efficiency and suppress the resistance value fluctuation. It means that.

(Structure of the semiconductor device 20 according to the comparative example)
Hereinafter, the structure of the semiconductor device 20 according to the comparative example used in this experiment and the shapes of the upper and middle dummy patterns 43 and 42 will be described with reference to FIGS.
First, the basic structure of the semiconductor device 20 according to the comparative example will be described.
FIG. 8 is a perspective view schematically showing the structure of the semiconductor device used in this experiment. FIG. 8A shows the basic structure of the semiconductor device 20 according to the comparative example, and FIG. The structure of the semiconductor device 10 which concerns on this embodiment is shown. The basic structure of the semiconductor device 20 is different from the structure of the semiconductor device 10 according to the present embodiment in that the upper plug 33, the intermediate plug 32, the lower dummy pattern 41, and the lower plug 31 are not provided. The other parts are the same. For this reason, in the semiconductor device 20 according to the comparative example, neither the upper dummy pattern 43 nor the intermediate dummy pattern 42 is connected to the substrate 1.

Next, the shapes of the upper and middle dummy patterns 43 and 42 provided in the semiconductor device 20 according to the comparative example will be described.
FIG. 9 is a plan view schematically showing the shapes of the upper and middle dummy patterns 43 and 42 provided in the semiconductor device 20 according to the comparative example used in this experiment.
FIG. 9A is a diagram schematically showing the structure of the intermediate dummy pattern 42 formed by so-called line and space (hereinafter also simply referred to as “L & S”). FIG. 9B is a diagram schematically showing the structure of the upper dummy pattern 43 formed by L & S. FIG. 9C is a diagram schematically showing the structure of the intermediate dummy pattern 42 formed in a flat plate shape. FIG. 9D is a diagram schematically showing the structure of the upper dummy pattern 43 formed in a flat plate shape.

  In this experiment, the coverage C of the resistor 5 was adjusted by combining the upper dummy pattern 43 and the intermediate dummy pattern 42. Specific examples of the coverage C of the resistor 5 adjusted in this way are shown in Table 1. In Table 1, “M2” means the intermediate dummy pattern 42, “M3” means the upper dummy pattern 43, and “none” means that the dummy pattern itself is not provided. The coverage C is calculated using the above equation (2).

  Here, the covering ratio C of the resistor 5 will be specifically described by taking the form shown in FIG. 9C as an example. In the form shown in FIG. 9C, the entire lower surface 5b of the resistor 5 is covered with the intermediate dummy pattern 42 formed in a flat plate shape, and the coverage of the lower surface 5b of the resistor 5 is 98%. . On the other hand, since the entire upper surface 5a of the resistor 5 is not covered with the upper dummy pattern 43, the coverage of the upper surface 5a of the resistor 5 is 0%. For this reason, the coverage C of the entire resistor 5 determined based on the above-described formula (2) is 49%.

  Strictly speaking, the coverage C of the entire resistor 5 should be calculated in consideration of the coverage of the side surface of the resistor 5. However, since the thickness of the resistor 5 is relatively thin, the area of the side surface of the resistor 5 is extremely smaller than the areas of the upper surface 5a and the lower surface 5b of the resistor 5. In other words, the influence of the covering of the side surface of the resistor 5 is extremely small compared to the influence of the covering of the upper surface 5a and the lower surface 5b of the resistor 5. For this reason, in this experiment, when calculating the coverage C of the resistor 5, only the coverage of the upper surface 5a and the lower surface 5b of the resistor 5 was considered.

  Next, Table 2 shows each coverage shown in Table 1 and the corresponding inter-terminal voltage dependency secondary coefficient α. A plot of these values is shown in FIG.

(3) Voltage dependency between terminals Voltage resistance dependency of secondary coefficient α The inventors created several types of semiconductor devices having different widths W of the resistor 5, and the voltage dependency secondary between terminals of each semiconductor device. The coefficient α was measured. From the terminal voltage dependency secondary coefficient α for each resistor width W thus obtained, knowledge on the resistor width dependency of the terminal voltage dependency secondary coefficient α was obtained. Hereinafter, experimental results of the resistor width dependency of the inter-terminal voltage dependency secondary coefficient α will be described.

  First, the structure of the semiconductor device used in this experiment will be briefly described. FIG. 10 is a perspective view schematically showing the structure of the semiconductor device used in this experiment. FIG. 10A shows the structure of the semiconductor device 30 according to the comparative example, and FIG. 1 shows a structure of a semiconductor device 10 according to an embodiment. As illustrated in FIG. 10A, the semiconductor device 30 according to the comparative example includes a resistor 5 and a pair of voltage application terminals 6 and 7. FIG. 10B shows the semiconductor device 10 according to this embodiment so that the difference in structure can be easily understood. Hereinafter, for convenience, the structure of the semiconductor device 30 according to the comparative example is referred to as “structure A”, and the structure of the semiconductor device 10 according to the present embodiment is referred to as “structure B”.

  In this experiment, the voltage dependency secondary coefficient α between terminals when the width W of the resistor 5 of the structure A and the resistor 5 of the structure B was 2 μm, 8 μm, and 32 μm, respectively, was measured. Table 3 shows the inter-terminal voltage dependency secondary coefficient α thus measured.

As shown in Table 3, at each width W of the resistor 5, the inter-terminal voltage dependency secondary coefficient α of the structure A was larger than the inter-terminal voltage dependency secondary coefficient α of the structure B (absolute value). It was small).
This experimental result shows that even when the width W of the resistor 5 is changed, the upper, middle, and lower dummy patterns 43, 42, and 41 are connected to the substrate 1 via the plug 3. This means that the inter-terminal voltage-dependent secondary coefficient α increases (becomes smaller in absolute value).

(Effect of this embodiment)
(1) The semiconductor device 10 according to this embodiment includes a substrate 1, a resistor 5, an upper dummy pattern 43 and an intermediate dummy pattern 42, and a plug that connects the upper dummy pattern 43 and the intermediate dummy pattern 42 and the substrate 1. 3 is provided. The resistor 5 has a portion that overlaps with the upper dummy pattern 43 and the intermediate dummy pattern 42 when viewed from the Z-axis direction, and each thermal conductivity of the upper dummy pattern 43, the intermediate dummy pattern 42, and the plug 3. Is higher than the thermal conductivity of the insulating layer 2 surrounding the resistor 5.

  For this reason, the semiconductor device 10 has an upper dummy pattern 43 formed of a material having a higher heat conductivity than that of the insulating layer 2 by generating heat accumulated in the insulating layer 2 by applying a voltage to the resistor 5. Then, it can escape to the substrate 1 through the intermediate dummy pattern 42 and the plug 3. That is, the heat released from the resistor 5 due to voltage application can be efficiently conducted (ie, radiated) from the resistor 5 and the insulating layer 2 to the substrate 1. For this reason, the resistance value fluctuation | variation of the resistor 5 which arises by the temperature change of the resistor 5 itself and its periphery can be suppressed effectively.

(2) In the present embodiment, the resistor 5 has a portion that overlaps each of the upper dummy pattern 43 and the intermediate dummy pattern 42 when viewed from the resistor 5 side toward the substrate 1 side. The coverage C of the resistor 5 defined by the above formula (2) is set to 49% or more.
Therefore, heat generated by applying a voltage to the resistor 5 can be surely released to the substrate 1 through the upper dummy pattern 43, the intermediate dummy pattern 42 and the plug 3. For this reason, the resistance value fluctuation | variation of the resistor 5 which arises by the temperature change of the resistor 5 itself and its periphery can be suppressed reliably.

(3) Moreover, in this embodiment, the coverage C of the resistance element is set to 80% or more.
Therefore, the heat generated by applying a voltage to the resistor 5 can be surely released by the substrate 1 through the upper dummy pattern 43, the intermediate dummy pattern 42 and the plug 3. For this reason, the resistance value fluctuation | variation of the resistor 5 which arises by the temperature change of the resistor 5 itself and its periphery can be suppressed more reliably.

(4) In the present embodiment, the resistor 5 is formed of tantalum nitride.
For this reason, the resistor 5 can be made a stable resistor against heat during mounting and use.
(5) In the present embodiment, the upper dummy pattern 43 and the intermediate dummy pattern 42 and the plug 3 are made of metal.
For this reason, formation of a dummy pattern and a plug becomes easy, and it can suppress that the manufacturing cost of a semiconductor device rises.

(6) In this embodiment, the upper dummy pattern 43 and the intermediate dummy pattern 42 and the plug 3 are made of tungsten or aluminum, the insulating layer 2 is made of SiO ₂ , and the substrate 1 is It is made of Si.
For this reason, formation of a dummy pattern and a plug becomes still easier, and it can further suppress that the manufacturing cost of a semiconductor device rises.

Other Embodiments The structure of the semiconductor device according to each of the second to fourth embodiments will be described below with reference to FIG. FIG. 11 is a perspective view schematically showing the structure of the semiconductor device according to each of the second to fourth embodiments. More specifically, FIG. 11A is a perspective view schematically showing the structure of the semiconductor device according to the second embodiment. FIG. 11B is a perspective view schematically showing the structure of the semiconductor device according to the third embodiment. FIG. 11C is a perspective view schematically showing the structure of the semiconductor device according to the fourth embodiment. Details of each embodiment will be described below.
In addition, the same code | symbol is attached | subjected to the part which has the same structure as the semiconductor device 10 which concerns on 1st Embodiment, and the repeated description is abbreviate | omitted.
[Second Embodiment]

(Construction)
As shown in FIG. 11A, the semiconductor device 11 according to the second embodiment includes a substrate 1, a resistor 5 formed above the substrate 1, and an upper dummy pattern formed above the resistor 5. 43 and a lower dummy pattern 41 formed between the substrate 1 and the resistor 5. The thermal conductivities of the upper and lower dummy patterns 43 and 41 are higher than that of an insulating layer (not shown) surrounding the resistor 5. The upper and lower dummy patterns 43 and 41 are connected to the substrate 1 via upper and lower plugs 33 and 31 having a thermal conductivity higher than that of the insulating layer. The resistor 5 includes a pair of voltage application terminals 6 and 7.

(Production method)
Hereinafter, a method for manufacturing the semiconductor device 11 according to the second embodiment will be briefly described with reference to the drawings used when describing the method for manufacturing the semiconductor device 10 according to the first embodiment.
First, the lower insulating layer 21 is formed on the substrate 1. Thereafter, a lower plug 31 connected to the substrate 1 is formed in the lower insulating layer 21.
Next, a lower dummy pattern 41 connected to the lower plug 31 is formed on the lower insulating layer 21. Thereafter, a first upper insulating layer 23 covering the lower dummy pattern 41 is formed on the lower insulating layer 21.

Next, the resistor 5 is formed on the first upper insulating layer 23 so as to be at least partially overlapped with the lower dummy pattern 41 between the lower plugs 31 when viewed from the stacking direction. Thereafter, a second upper insulating layer 24 that covers the resistor 5 is formed on the first upper insulating layer 23.
Next, an upper plug 33 connected to the lower dummy pattern 41 and not connected to the resistor 5 is formed above the lower plug 31 in each of the first and second upper insulating layers 23 and 24. Thereafter, an upper dummy pattern 43 is formed on the second upper insulating layer 24 so as to be at least partially overlapped with the resistor 5 when viewed from the stacking direction, and connected to the resistor 5. Voltage application terminals 6 and 7 are formed.
Thus, the semiconductor device 11 according to the second embodiment is manufactured.

(effect)
Even the semiconductor device 11 according to the second embodiment has the same effects as the semiconductor device 10 according to the first embodiment. Further, in the semiconductor device 11 according to the second embodiment, it is not necessary to provide the intermediate dummy pattern 42 and the intermediate plug 32, so that the number of manufacturing steps can be reduced. Therefore, the tact time can be shortened. In addition, a reduction in the height of the semiconductor device can be realized.

[Third Embodiment]
(Construction)
As shown in FIG. 11B, the semiconductor device 12 according to the third embodiment includes a substrate 1, a resistor 5 formed above the substrate 1, and an upper dummy pattern formed above the resistor 5. 43. The thermal conductivity of the upper dummy pattern 43 is higher than that of an insulating layer (not shown) surrounding the resistor 5. The upper dummy pattern 43 is connected to the substrate 1 through an upper plug 33 having a thermal conductivity higher than that of the insulating layer. The resistor 5 includes a pair of voltage application terminals 6 and 7.
In the semiconductor device 12 according to the present embodiment, the “upper dummy pattern 43” corresponds to the “first dummy pattern”.

(Production method)
Hereinafter, a method for manufacturing the semiconductor device 12 according to the third embodiment will be briefly described with reference to the drawings used when describing the method for manufacturing the semiconductor device 10 according to the first embodiment.
First, the first upper insulating layer 23 is formed on the substrate 1. Thereafter, the resistor 5 is formed on the first upper insulating layer 23.
Next, a second upper insulating layer 24 that covers the resistor 5 is formed on the first upper insulating layer 23. Thereafter, upper plugs 33 connected to the substrate 1 and not connected to the resistor 5 are formed in the first and second upper insulating layers 23 and 24.
Next, an upper dummy pattern 43 is formed on the second upper insulating layer 24 so as to be connected to the upper plug 33 and at least partially overlap with the resistor 5 when viewed from the stacking direction, and connected to the resistor 5. Voltage application terminals 6 and 7 are formed.
Thus, the semiconductor device 12 according to the third embodiment is manufactured.

(effect)
Even the semiconductor device 12 according to the third embodiment has the same effects as the semiconductor device 10 according to the first embodiment. Further, in the semiconductor device 12 according to the third embodiment, it is not necessary to provide the middle and lower dummy patterns 42 and 41 and the middle and lower plugs 32 and 31, thereby reducing the number of manufacturing steps. be able to. Therefore, the tact time can be shortened. In addition, a reduction in the height of the semiconductor device can be realized.

[Fourth Embodiment]
(Construction)
As shown in FIG. 11C, the semiconductor device 13 according to the fourth embodiment is formed between the substrate 1, the resistor 5 formed above the substrate 1, and the substrate 1 and the resistor 5. And a lower dummy pattern 41. The thermal conductivity of the lower dummy pattern 41 is higher than that of an insulating layer (not shown) surrounding the resistor 5. The lower dummy pattern 41 is connected to the substrate 1 via a lower plug 31 having a thermal conductivity higher than that of the insulating layer. The resistor 5 includes a pair of voltage application terminals 6 and 7.
In the semiconductor device 13 according to the present embodiment, the “lower dummy pattern 41” corresponds to the “first dummy pattern”.

(Production method)
Hereinafter, a method for manufacturing the semiconductor device 13 according to the fourth embodiment will be briefly described with reference to the drawings used when describing the method for manufacturing the semiconductor device 10 according to the first embodiment.
First, the lower insulating layer 21 is formed on the substrate 1. Thereafter, a lower plug 31 connected to the substrate 1 is formed in the lower insulating layer 21.
Next, a lower dummy pattern 41 connected to the lower plug 31 is formed on the lower insulating layer 21. Thereafter, a first upper insulating layer 23 covering the lower dummy pattern 41 is formed on the lower insulating layer 21.

Next, the resistor 5 is formed on the first upper insulating layer 23 so as to be at least partially overlapped with the lower dummy pattern 41 between the lower plugs 31 when viewed from the stacking direction. Thereafter, a second upper insulating layer 24 that covers the resistor 5 is formed on the first upper insulating layer 23.
Next, voltage application terminals 6 and 7 connected to the resistor 5 are formed in the second upper insulating layer 24.
Thus, the semiconductor device 13 according to the fourth embodiment is manufactured.

(effect)
Even the semiconductor device 13 according to the fourth embodiment has the same effects as the semiconductor device 10 according to the first embodiment. Further, in the semiconductor device 13 according to the fourth embodiment, it is not necessary to provide the upper and middle dummy patterns 43 and 42 and the upper and middle plugs 33 and 32, thereby reducing the number of manufacturing steps. be able to. Therefore, the tact time can be shortened. In addition, a reduction in the height of the semiconductor device can be realized.

(Other embodiments and modifications)
(1) In the above-described embodiments, the upper, middle, and lower dummy patterns 43, 42, and 41, the upper, middle, and lower plugs 33, 32, and 31, or the voltage application terminals 6 and 7, However, the present invention is not limited to this. You may change the shape mentioned above suitably. The upper, middle, and lower plugs 33, 32, and 31 and the voltage application terminals 6 and 7 may be, for example, cylinders. Even in this case, the above-described effects can be obtained.

(2) In the above-described embodiments, the upper, middle, and lower plugs 33, 32, and 31 are simply connected to the substrate 1 and the upper, middle, and lower dummy patterns 43, 42, and 41, respectively. Although the case has been described, the present invention is not limited to this. For preventing, for example, a decrease in thermal conductivity at each connection point between the upper, middle, and lower plugs 33, 32, and 31 and the upper, middle, and lower dummy patterns 43, 42, and 41. A member (that is, a member for maintaining thermal conductivity) may be inserted. By carrying out like this, heat dissipation efficiency can be raised more.

(3) Further, in each of the above-described embodiments, the case where a Si substrate is used as the substrate 1 has been described, but the present invention is not limited to this. The substrate 1 used in each of the above-described embodiments may be, for example, a Si substrate having p-type conductivity implanted with p-type impurity ions, or an n-type impurity ion implanted with n-type impurity ions. A Si substrate having the above conductivity may be used. Even in this case, the above-described effects can be obtained.

(4) In the above-described embodiments, the case where the dummy pattern 4 and the plug 3 are formed of metal has been described, but the present invention is not limited to this. That is, the material of the dummy pattern 4 and the plug 3 is not particularly limited. For example, the dummy pattern 4 and the plug 3 may be made of non-metal, but the thermal conductivity of the dummy pattern 4 and the plug 3 is higher than the thermal conductivity of the insulating layer 2 surrounding the resistor 5. Need to be.

(5) In the above-described embodiments, the case where the pair of plugs 3 are formed has been described. However, the present invention is not limited to this. For example, the number of plugs provided in the semiconductor device according to each embodiment may be one or three or more. Even in this case, the above-described effects can be obtained.
(6) In the above-described embodiments, the case where the plugs 31, 32, and 33 are formed on the same axis has been described. However, the present invention is not limited to this. For example, the lower and middle plugs 31 and 32 may be formed so as not to overlap the resistor 5 when viewed from the stacking direction.

(7) In the first embodiment described above, the semiconductor device 10 including the upper, middle, and lower three dummy patterns 43, 42, and 41 has been described. However, the present invention is not limited to this. Absent. For example, the semiconductor device having four or more dummy patterns may be used, and even in this case, the above-described effects can be obtained.
Although the present invention has been described above with reference to specific embodiments, it is not intended that the present invention be limited by these descriptions. From the description of the invention, other embodiments of the invention will be apparent to persons skilled in the art, along with various variations of the disclosed embodiments. Therefore, it is to be understood that the claims encompass these modifications and embodiments that fall within the scope and spirit of the present invention.

DESCRIPTION OF SYMBOLS 1 Substrate 2 Insulating layer 21 Lower insulating layer 22 Intermediate insulating layer 23 First upper insulating layer 24 Second upper insulating layer 3 Plug 31 Lower plug 31a Lower plug upper surface 31b Lower plug lower surface 32 Intermediate plug 32a Intermediate plug upper surface 32b Intermediate Lower surface 33 of the upper plug 33a Upper surface 33b of the upper plug Lower surface 4 of the upper plug 4 Dummy pattern 41 Lower dummy pattern 41a Upper surface 41b of the lower dummy pattern Lower surface 42 of the lower dummy pattern Intermediate dummy pattern 42a Upper surface 42b of the intermediate dummy pattern Lower surface 43 Upper dummy pattern 43a Upper dummy pattern upper surface 43b Upper dummy pattern lower surface 5 Resistor 5a Resistor upper surface 5b Resistor lower surface 6 Voltage application terminal 7 Voltage application terminal 10 Semiconductor device 11 Semiconductor device 12 Semiconductor device 13 Semiconductor Device 20 Semiconductor Device 21 Semiconductor Device W Resistor Width α Terminal Voltage Dependent Secondary Coefficient C Coverage SD1 Overlap Area between Upper Dummy Pattern and Upper Surface of Resistor SD2 Overlap Area between Intermediate Dummy Pattern and Upper Surface of Resistor SR1 Area of the upper surface of the resistor SR1 Area of the lower surface of the resistor

Claims (10)

A substrate,
A resistive element formed above the substrate and surrounded by an insulating layer;
At least one of a first dummy pattern formed between the substrate and the resistance element and not used as an element and a second dummy pattern formed above the resistance element and not used as an element;
A connection portion that connects at least one of the first dummy pattern and the second dummy pattern and the substrate;
The resistance element has a portion that overlaps at least one of the first dummy pattern and the second dummy pattern when viewed from the resistance element side toward the substrate side;
The first dummy pattern, the second dummy pattern, and the connection portion each have a higher thermal conductivity than the insulating layer.   The semiconductor device according to claim 1, comprising the first dummy pattern and the second dummy pattern. The resistance element has a portion that overlaps each of the first dummy pattern and the second dummy pattern when viewed from the resistance element side toward the substrate side,
The semiconductor device according to claim 1, wherein a coverage C of the resistance element defined by the following formula (1) is 49% or more.
C = (SD1 + SD2) / (SR1 + SR2) × 100 (1)
However,
C: Coverage ratio of the resistance element (%)
SD1: Area of a portion where the first dummy pattern and the surface on the first dummy pattern side of the resistance element overlap when viewed from the resistance element side toward the substrate side. SD2: The resistance element When viewed from the substrate side toward the substrate side, the area of the portion where the second dummy pattern and the surface on the second dummy pattern side of the resistor element overlap SR1: the first element in the resistor element Area on dummy pattern side SR2: Area on the second dummy pattern side in the resistance element Comprising the first dummy pattern and the second dummy pattern;
The semiconductor device according to claim 3, wherein a covering ratio C of the resistance element is 80% or more.   The semiconductor device according to claim 1, wherein the resistance element is made of tantalum nitride.   6. The semiconductor device according to claim 1, wherein at least one of the first dummy pattern and the second dummy pattern and the connection portion are formed of metal. At least one of the first dummy pattern and the second dummy pattern and the connection portion are formed of tungsten or aluminum;
The insulating layer is made of silicon dioxide;
The semiconductor device according to claim 1, wherein the substrate is made of silicon. Forming a first insulating layer on the substrate;
Forming a first connection portion connected to the substrate in the first insulating layer;
Forming a first dummy pattern which is connected to the first connection portion and is not used as an element on the first insulating layer;
Forming a second insulating layer covering the first dummy pattern on the first insulating layer;
Forming a resistance element on the second insulating layer so as to at least partially overlap the first dummy pattern when viewed from the stacking direction;
Forming a third insulating layer covering the resistive element on the second insulating layer,
A method of manufacturing a semiconductor device, wherein thermal conductivity of the first dummy pattern and the first connection portion is higher than thermal conductivity of the second insulating layer and the third insulating layer surrounding the resistance element. Forming a first insulating layer on the substrate;
Forming a resistance element on the first insulating layer;
Forming a second insulating layer covering the resistance element on the first insulating layer;
Forming a first connection portion connected to the substrate and not connected to the resistance element in the first insulating layer and the second insulating layer;
Forming a first dummy pattern on the second insulating layer so as to be connected to the first connection portion and overlap at least partly with the resistance element when viewed from the stacking direction;
A method of manufacturing a semiconductor device, wherein thermal conductivity of the first dummy pattern and the first connection portion is higher than thermal conductivity of the first insulating layer and the second insulating layer surrounding the resistance element. Forming, in the second insulating layer and the third insulating layer, a second connection portion connected to the first dummy pattern and not connected to the resistance element;
And a step of forming a second dummy pattern on the third insulating layer so as to be connected to the second connection portion and to at least partially overlap the resistance element when viewed from the stacking direction. Item 9. A method for manufacturing a semiconductor device according to Item 8.

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