JP2016096694A - Battery monitoring method and battery monitoring device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a battery monitoring method and a battery monitoring device that can shorten the time required for cell balance of a battery pack.SOLUTION: A battery monitoring method comprises a first step of setting N=0 when the number of battery cells 13 is set to M and the number N of the battery cells 13 is set from 0 to M-1 in the in-series connection order of the battery cells 13 in a process of extracting battery cells 13 having a voltage higher than a reference voltage Vref and directly non-connected to one another from plural battery cells 13 which are connected in series; a second step of determining whether the voltage of the battery cell 13 having the cell number N is higher than the reference voltage value Vref, setting the battery cell 13 having the cell number N as a battery cell to be discharged and setting N=N+1 when the voltage is determined to be higher than the reference voltage value Vref, and setting N=N+2 when the voltage is determined not to be higher than the reference voltage value Vref; and a third step of determining whether N is larger than M-1, and going to the second step when N is not larger than M-1.SELECTED DRAWING: Figure 4

Description

  Embodiments described herein relate generally to a battery monitoring method and a battery monitoring apparatus.

  In a battery pack having a plurality of rechargeable battery cells connected in series, the voltage of each battery cell varies as charging and discharging are repeated. Therefore, in order to maximize the charging capacity of the assembled battery, it is necessary to align the voltage of each battery cell to a predetermined reference voltage before starting charging.

  In order to align the voltage of each battery cell to a predetermined reference voltage, a discharge circuit may be connected to the battery cell having a voltage higher than the reference voltage and discharged until the predetermined reference voltage is reached. However, if this discharge circuit is prepared for each battery cell, the discharge circuit becomes large.

  A discharge circuit is simplified by providing a restriction that battery cells directly connected to each other among a plurality of battery cells connected in series cannot be discharged simultaneously.

  However, there is no known optimal method for indicating in what procedure a plurality of battery cells having a voltage higher than the reference voltage can be discharged to the reference voltage to reduce the time required for cell balance.

JP 2008-48496 A

  It is an object of the present invention to provide a battery monitoring method and a battery monitoring apparatus that can reduce the time required for cell balance of an assembled battery.

  According to one embodiment, the battery monitoring method extracts the battery cells having a voltage higher than a reference voltage and not directly connected to each other from a plurality of battery cells connected in series. The first step of setting N = 0, and the voltage of the battery cell having the cell number N is a reference voltage, where M is the number of the battery cells and the battery cell number N is 0 to M-1 in the order of series connection. A second step of extracting the battery cell having cell number N and setting N = N + 2 if not higher, and N = N + 1 if not higher, and whether N is greater than M−1 And if it is not larger, a third step going to the second step is provided.

  According to another embodiment, the battery monitoring device sets a voltage acquisition unit that acquires voltages of a plurality of battery cells connected in series, and a reference voltage for aligning the voltages of the plurality of battery cells. A battery that is directly connected to each other, a battery cell extraction unit that extracts, from the plurality of battery cells, a battery cell that has a voltage higher than the reference voltage and that is not directly connected to each other. A discharge circuit that discharges the extracted battery cells; a voltage monitoring unit that determines whether or not the voltage of the battery cells being discharged is equal to or lower than the reference voltage; And the battery cell extraction unit sets N = 0 when the number of the battery cells is M and the number N of the battery cells is 0 to M-1 in the order of series connection. And the cell It is determined whether or not the voltage of the battery cell having the symbol N is higher than the reference voltage value. If it is higher, the battery cell having the cell number N is discharged and N = N + 2, otherwise N = It includes a second step of setting N + 1 and a third step of determining whether or not N is larger than M−1 and going to the second step if N is not larger.

1 is a block diagram showing a battery monitoring system having a battery monitoring device according to Embodiment 1. FIG. FIG. 3 is a circuit diagram showing a discharge unit of the battery monitoring device according to the first embodiment. The figure which shows an example of the voltage distribution of the assembled battery which concerns on Embodiment 1. FIG. 3 is a flowchart illustrating a battery monitoring method according to the first embodiment. The figure which shows the advancing state of the battery monitoring method which concerns on Embodiment 1 in order. The figure which shows the progress state of the battery monitoring method which concerns on Embodiment 1. FIG. The figure which shows the advancing state of the battery monitoring method which concerns on Embodiment 1 in order. The figure which shows the advancing state of the battery monitoring method which concerns on Embodiment 1 in order. The figure which shows the progress state of the battery monitoring method which concerns on Embodiment 1 in order. The figure which shows the battery monitoring method of the comparative example which concerns on Embodiment 1. FIG. 6 is a flowchart showing a battery monitoring method according to the second embodiment. The figure which shows the advancing state of the battery monitoring method which concerns on Embodiment 2 in order. The figure which shows the advancing state of the battery monitoring method which concerns on Embodiment 2 in order. The figure which shows an example of another voltage distribution of the assembled battery which concerns on Embodiment 2. FIG. The figure which shows another progress state of the battery monitoring method which concerns on Embodiment 2. FIG. The figure which shows the outline | summary of the logical operation of the battery monitoring method which concerns on Embodiment 3. FIG. 9 is a flowchart showing a main part of a battery monitoring method according to Embodiment 3. The figure which shows the advancing state of the battery monitoring method which concerns on Embodiment 3 in order.

  Hereinafter, embodiments will be described with reference to the drawings.

(Embodiment 1)
A battery monitoring apparatus according to this embodiment will be described with reference to FIGS. FIG. 1 is a block diagram showing a battery monitoring system having a battery monitoring device of the present embodiment, FIG. 2 is a circuit diagram showing a discharging unit of the battery monitoring device, and FIG. 3 is a diagram showing an example of a voltage distribution of an assembled battery.

  As shown in FIG. 1, the battery monitoring system 10 of this embodiment includes an assembled battery 11 and a battery monitoring device 12 that monitors the voltage of the assembled battery 11.

  The assembled battery 11 has a plurality of battery cells 13 connected in series. The battery cell 13 is a rechargeable secondary battery, for example, a lithium ion battery. Although this embodiment demonstrates the case where the six battery cells 13 are connected in series, the number of the battery cells 13 connected in series is not restrict | limited in particular. Further, the arrangement of the battery cells 13 stored in the container of the assembled battery 11 is not particularly limited.

  The assembled battery 11 is used as a main power supply battery for driving a load 21, for example, a motor. The battery monitoring device 12 is driven by an auxiliary power battery 22. Since the auxiliary power battery 22 has a much smaller capacity than the main power battery, the battery monitoring device 12 is required to save power.

  The assembled battery 11 is connected to the load 21 and is discharged to supply power to the load 21. When the remaining capacity decreases, the assembled battery 11 is disconnected from the load 21 and charged by an external power source (not shown). Since the battery pack 13 has slightly different charge / discharge speeds for each battery cell 13, the voltage of each battery cell 13 varies as charge / discharge is repeated.

  In consideration of durability and safety of the battery cell 13 in charging and discharging, the assembled battery 11 prohibits charging when the voltage of the battery cell 13 having the highest voltage reaches the upper limit value, and has the lowest voltage. It is necessary to inhibit discharge when the voltage of the battery cell 13 reaches the lower limit value.

  Therefore, in order to maximize the charging capacity of the assembled battery 11, it is necessary to make the voltage of each battery cell 13 equal to the reference voltage Vref before the charging of the assembled battery 11 is started. Making the voltage of each battery cell 13 equal to the reference voltage Vref is also referred to as cell balancing.

  The battery monitoring device 12 includes a voltage acquisition unit 14 that acquires the voltage of each battery cell 13, a reference voltage setting unit 15 that sets a reference voltage Vref when balancing cells, and a reference voltage Vref from a plurality of battery cells 13. A battery cell extraction unit 16 that extracts a battery cell 13 having a higher voltage, a discharge unit 17 that discharges the extracted battery cell 13, and determines whether or not the voltage of the battery cell 13 being discharged is equal to or lower than a reference voltage Vref And a voltage monitoring unit 18.

  In the present embodiment, the battery monitoring device 12 is realized by an integrated circuit provided on a semiconductor substrate.

  In integrating the battery monitoring device 12, the discharge unit 17 simultaneously discharges the battery cells 13 directly connected to each other among the plurality of battery cells 13 connected in series in order to simplify the discharge circuit. It is configured not to be able to.

  Correspondingly, the battery cell extraction unit 16 is configured to extract battery cells 13 having a voltage higher than the reference voltage Vref and not directly connected to each other from the plurality of battery cells 13 connected in series. ing.

  Here, the battery cells directly connected to each other are a plurality of battery cells connected in series, in which the positive terminal of the first battery cell and the negative terminal of the second battery cell are connected via the third battery cell. It is a battery cell directly connected by wiring etc., without doing.

  That is, there can be various geometrical arrangements of a plurality of battery cells connected in series. When the plurality of battery cells are arranged in a line shape, an L shape, a ring shape, or the like, the battery cells directly connected to each other are adjacent to each other.

  On the other hand, when the plurality of battery cells are arranged in a U-shape, a 99-fold shape, a staggered shape, or the like, there can be a plurality of battery cells adjacent to each other. However, the battery cells directly connected to each other are limited to one set.

  The voltage acquisition unit 14 measures the voltage of each battery cell 13 and outputs the measurement result to the reference voltage setting unit 15, the battery cell extraction unit 16, and the voltage monitoring unit 18. The voltage acquisition unit 14 includes, for example, an AD converter (analog / digital converter) and a scanner. The scanner selects the battery cell 13 whose voltage is to be measured. The AD converter converts the voltage of the selected battery cell 13 into a digital value.

  The reference voltage setting unit 15 sets the lowest voltage among the voltages of the battery cells 13 to the reference voltage Vref when performing cell balancing. The reference voltage Vref is notified to the battery cell extraction unit 16 and the voltage monitoring unit 18.

  The voltage monitoring unit 18 monitors the voltage of the battery cell 13 that is being discharged, and determines whether the voltage is equal to or lower than the reference voltage Vref. The determination result is notified to the battery cell extraction unit 16.

  FIG. 2 shows the principle of the discharge circuit of the discharge unit 17. Here, in the assembled battery 11, the number of battery cells 13 connected in series is M = 6, and cell numbers from 0 to M−1 = 5 are assigned in the order of being connected in series to each battery cell 13. Each battery cell 13 is represented as battery cells E0 to E5, respectively.

  As shown in FIG. 2, the discharge circuit has six switch elements S0 to S5 and seven resistors R, similarly to the number M = 6 of battery cells 13 connected in series. Each switch element S0 to S5 is, for example, a MOS transistor.

  The six switch elements S0 to S5 are connected in series. Each of the five resistors R is connected to a connection node between battery cells whose one ends are directly connected to each other, and is connected to a connection node between switch elements whose other ends are directly connected to each other.

  One of the remaining two resistors R is connected to the battery cell E0 and the switch element S0, and the other is connected to the battery cell E5 and the switch element S5. That is, the battery cells E0 to E5, the switch elements S0 to S5, and the resistor R are connected in a so-called ladder shape.

  For example, when discharging the battery cell E2, the discharge unit 17 turns on the switch element S2 and turns off the switch elements S1 and S3. At this time, the discharge current I1 = V2 / 2R flows through the switch element S2. The MOS transistors of the switch elements S0 to S5 only need to have a withstand current and a withstand voltage with respect to the discharge current I1.

  If the switch elements S2 and S3 are simultaneously turned on and the switch element S1 is turned off, the battery cells E2 and E3 that are directly connected to each other are simultaneously discharged. At this time, the discharge current I2 = (V2 + V3) / 2R flows through the switch elements S2 and S3. Since the discharge current I2 is larger than the discharge current I1, the MOS transistors of the switch elements S0 to S5 are required to have higher current resistance and breakdown voltage with respect to the discharge current I2.

  That is, in the discharge unit 17 configured so that the battery cells 13 directly connected to each other cannot be discharged at the same time, the current resistance and breakdown voltage of the MOS transistors of the switch elements S0 to S5 can be set low. Therefore, the MOS transistor becomes small. The area of the semiconductor chip provided with the battery monitoring device 12 is reduced, and the manufacturing cost is reduced.

  FIG. 3 is a diagram illustrating an example of the voltage distribution of the battery cells 13 of the assembled battery 11. Assume that the voltage distribution of the battery cells E0 to E5 is V3> V0> V5> V2> V1 = V4. The reference voltage Vref is Vref = V1 = V4.

  That is, in the cell balance, there are four battery cells E0, E2, E3, and E5 that are discharged with a voltage higher than the reference voltage Vref. Here, since the battery cells E0 and E5 have a voltage higher than the reference voltage Vref and no battery cells are directly connected to each other, they can be discharged simultaneously. On the other hand, since the battery cells E2 and E3 have battery voltages higher than the reference voltage Vref and are directly connected to each other, they cannot be discharged at the same time.

  In such a situation, in order to minimize the time required for the cell balance, the procedure for discharging the battery cells E0, E2, E3, E5 will be described below.

  FIG. 4 is a flowchart showing a battery monitoring method, that is, a procedure for achieving cell balance.

  As shown in FIG. 4, initial setting is performed first. The number M of battery cells E is set, the initial value of the cell voltage V of each battery cell E is acquired, and the reference voltage Vref is set (step S10).

  Next, the cell number N is initialized and N = 0 (step S11). Step S11 is the first step.

  Next, it is determined whether or not the cell voltage V (N) of the battery cell E (N) is higher than the reference voltage Vref (step S12). If cell voltage V (N) is higher than reference voltage Vref (YES in step S12), battery cell E (N) is extracted as a battery cell to be discharged (discharge permitted), and discharge of battery cell E (N) is started. In addition, 2 is added to the cell number N, so that the cell number N = N + 2 is obtained (step S13).

  On the other hand, if the cell voltage V (N) is not higher than the reference voltage Vref (NO in step S12), the battery cell E (N) is not a battery cell to be discharged (not subject to discharge), so 1 is added to the cell number N. Thus, the cell number N = N + 1 is obtained (step S14). Steps S12 to S14 are the second step.

  Next, it is determined whether or not the cell number N is greater than M-1 (step S15). If the cell number N is not greater than M-1 (NO in step S15), the process goes to step S12. Step S15 is the third step.

  Here, the addition of 2 to N passes the check of the cell voltage V (N + 1) because the battery cell E (N + 1) next to the battery cell E (N) that is allowed to discharge is not allowed to discharge. Because. The reason for adding 1 to N is to check the cell voltage V (N + 1) because the battery cell E (N + 1) next to the battery cell E (N) that is not to be discharged can be discharged.

  Steps S12 to S15 are repeated until the cell number N becomes larger than M-1. When the cell number N becomes larger than M-1 (YES in step S15), the process goes to step S16.

  The current values of the cell voltages V of all the battery cells E are acquired (step S16), and it is determined whether or not the cell voltage V of any battery cell E being discharged is equal to or lower than the reference voltage Vref (step S17).

  If the cell voltage V of any battery cell E being discharged is not less than the reference voltage Vref (NO in step S17), the process goes to step 16. If the cell voltage V of any battery cell E being discharged is equal to or lower than the reference voltage Vref (YES in step S16), the process goes to step S18.

  Steps S16 and S17 are steps for waiting until the cell voltage V of any of the battery cells E being discharged reaches the reference voltage Vref.

  Next, it is determined whether or not the cell voltages V of all the battery cells E are equal to or lower than the reference voltage Vref (step S18). If the cell voltages V of all the battery cells E are not lower than the reference voltage Vref (NO in step S18), the process goes to step S11. If the cell voltages V of all the battery cells E are equal to or lower than the reference voltage Vref (YES in step S18), the cell balance is achieved and the process ends.

  Next, the progress of the battery monitoring method, that is, the progress of cell balance will be described in detail with reference to FIGS. Here, it is assumed that the discharge speeds of the battery cells E0 to E5 are equal.

  As shown in FIG. 5A, initially, since the cell number N = 0, it is determined whether or not the cell voltage V0 is higher than the reference voltage Vref. Since the cell voltage V0 is higher than the reference voltage Vref, the battery cell E0 is extracted as a battery cell to be discharged (discharge permission). At this stage, discharge of the battery cell E0 is started. Further, 2 is added to the cell number N, so that the cell number N = 2.

  As shown in FIG. 5B, since the cell number N = 2, it is determined whether or not the cell voltage V2 is higher than the reference voltage Vref. Since the cell voltage V2 is higher than the reference voltage Vref, the battery cell E2 is extracted as a battery cell to be discharged (discharge permission). At this stage, discharging of the battery cell E2 is started. Battery cell E0 is being discharged. Further, 2 is added to the cell number N, so that the cell number N = 4.

  As shown in FIG. 6A, since the cell number N = 4, it is determined whether or not the cell voltage V4 is higher than the reference voltage Vref. Since the cell voltage V4 is not higher than the reference voltage Vref, the battery cell E2 is not extracted as a battery cell to be discharged (not subject to discharge). Battery cells E0 and E2 are being discharged. Further, 1 is added to the cell number N, so that the cell number N = 5.

  As shown in FIG. 6B, since the cell number N = 5, it is determined whether or not the cell voltage V5 is higher than the reference voltage Vref. Since the cell voltage V5 is higher than the reference voltage Vref, the battery cell E5 is extracted as a battery cell to be discharged (discharge permission). At this stage, discharging of the battery cell E5 is started. Battery cells E0 and E2 are being discharged. Further, 2 is added to the cell number N, so that the cell number N = 7.

  As shown in FIG. 7A, since the cell number N = 7, the cell number N is larger than M−1 = 5. Wait until any one of the cell voltages V0, V2, and V5 becomes equal to or lower than the reference voltage Vref.

  As shown in FIG. 7B, when the cell voltage V2 first becomes equal to or lower than the reference voltage Vref, the discharge of the battery cell E2 is stopped. Further, the cell number N is set to 0, and steps S12 to S15 shown in FIG. 4 are executed.

  Battery cell E0 is being discharged. Since the cell voltage V0 is still higher than the reference voltage Vref, the battery cell E0 is extracted again as a battery cell to be discharged, but is not affected because it is already discharged. Further, 2 is added to the cell number N, so that the cell number N = 2.

  The battery cell E2 has already stopped discharging. Since the cell voltage V2 is equal to or lower than the reference voltage Vref, the battery cell E2 is not extracted as a battery cell to be discharged and is not affected. Further, 1 is added to the cell number N, so that the cell number N = 3.

  As shown in FIG. 8A, since the cell number N = 3, it is determined whether or not the cell voltage V3 is higher than the reference voltage Vref. Since the cell voltage V3 is higher than the reference voltage Vref, the battery cell E3 is extracted as a battery cell to be discharged (discharge permission). At this time, discharging of the battery cell E3 is started. Battery cells E0 and E5 are being discharged. Further, 2 is added to the cell number N, so that the cell number N = 5.

  Battery cell E5 is being discharged. Since the cell voltage V5 is higher than the reference voltage Vref, the battery cell E5 is extracted again as a battery cell to be discharged, but is not affected because it is already discharged. Further, 2 is added to the cell number N, so that the cell number N = 7.

  As shown in FIG. 8B, since N = 7, N is larger than M-1 = 5. Wait until any one of the cell voltages V0, V3, V5 is equal to or lower than the reference voltage Vref.

  When the cell voltage V5 becomes equal to or lower than the reference voltage Vref, the discharge of the battery cell E5 is stopped. Further, the cell number N is set to 0, and steps S12 to S15 shown in FIG. 4 are executed.

  As shown in FIG. 9A, since N = 7, N is larger than M-1 = 5. Wait until one of the cell voltages V0 and V3 falls below the reference voltage Vref.

  When the cell voltage V0 becomes equal to or lower than the reference voltage Vref, the discharge of the battery cell E0 is stopped. Battery cell E3 is being discharged. Further, the cell number N is set to 0, and steps S12 to S15 shown in FIG. 4 are executed.

  As shown in FIG. 9B, since N = 7, N is larger than M−1 = 5. Wait until the cell voltage V3 becomes equal to or lower than the reference voltage Vref.

  When the cell voltage V3 becomes equal to or lower than the reference voltage Vref, the discharge of the battery cell E3 is stopped. At this stage, all the cell voltages V become equal to or lower than the reference voltage Vref. Thereby, cell balance is completed.

  Next, the effect of the battery monitoring method of this embodiment will be described in comparison with a comparative example.

  FIG. 10 is a diagram illustrating a procedure for achieving cell balance in the comparative example. The comparative example is a method in which battery cells with an even cell number N are discharged first, and discharge of battery cells with an even cell number N is stopped, and then battery cells with an odd cell number N are discharged.

  Since the plurality of battery cells are divided into two groups depending on whether the cell number N is even or odd, the battery cells directly connected to each other do not discharge at the same time. Here, it is assumed that the discharge speed of each battery cell is equal. The time required for discharging the battery cell is proportional to the cell voltage.

  In the first case of the comparative example shown in FIG. 10A, the cell voltages V0 to V5 have a relationship of V3> V0> V4> V5> V2> V1 = Vref. Battery cells E0, E2, E3, E4, and E5 are battery cells to be discharged.

  First, discharge of battery cells E0, E2, and E4 having an even cell number N is started simultaneously. Discharging stops in the order of battery cell E2, battery cell E4, and battery cell E0. Next, discharge of the battery cells E3 and E5 having an odd cell number N is started simultaneously. Discharge stops in the order of battery cell E5 and battery cell E3, and cell balance is completed.

  In the first case, the time T required for cell balance is the sum T0 + T3 of the discharge time T0 of the battery cell E0 and the discharge time T3 of the battery cell E3.

  On the other hand, in the present embodiment, the discharge of the battery cells E3 and E5 can be started simultaneously when the discharge of the battery cell E4 is stopped. There is no need to wait until the discharge of the battery cell E0 stops. Therefore, the time required for cell balance is shortened by T0-T4.

  In the second case of the comparative example shown in FIG. 11B, the cell voltages V0 to V5 have a relationship of V0> V5> V1 = V2 = V3 = V4 = Vref. Battery cells E0 and E5 are battery cells to be discharged.

  First, discharge of the battery cell E0 having an even cell number N is started. When the discharge of the battery cell E0 is stopped, the discharge of the battery cell E5 having the odd cell number N is started. The discharge of the battery cell E5 is stopped, and the cell balance is completed.

  In the second case, the time T required for cell balance is the sum T0 + T5 of the discharge time T0 of the battery cell E0 and the discharge time T5 of the battery cell E5.

  On the other hand, in this embodiment, since the battery cells E0 and E5 are not directly connected to each other, the battery cells E0 and E5 can be discharged simultaneously. There is no need to wait until the discharge of the battery cell E0 stops. Therefore, the time required for cell balance is shortened by T5.

  As described above, in the battery monitoring device 20 of the present embodiment, a voltage higher than the reference voltage Vref is provided corresponding to the discharge unit 17 configured so that the battery cells 13 directly connected to each other cannot be discharged at the same time. The battery cell extraction unit 16 is configured to extract battery cells 13 that are not directly connected to each other.

  As a result, the extracted battery cells can be discharged without leaving a gap when the cell balance is set so that the voltage of each battery cell 13 is equal to the reference voltage Vref. Therefore, the time required for cell balance can be shortened.

  If the time required for the cell balance is short, the battery monitoring device 12 does not consume useless power, so that the auxiliary power battery 22 can be extended.

  In the present embodiment, the case where the battery cells E extracted as the battery cells to be discharged in step S13 shown in FIG. 4 are started to discharge individually at the time of extraction has been described. The discharge may be started.

  In the battery monitoring device 12, the voltage acquisition unit 14, the reference voltage setting unit 15, the battery cell extraction unit 16, the discharge unit 17, and the voltage monitoring unit 18 can be executed by hardware. The reference voltage setting unit 15, the battery cell extraction unit 16, and the voltage monitoring unit 18 can be realized mainly using a comparator.

  Alternatively, the voltage acquisition unit 14 and the discharge unit 17 can be executed by hardware, and the reference voltage setting unit 15, the battery cell extraction unit 16 and the voltage monitoring unit 18 can be executed by software using a microcomputer.

(Embodiment 2)
A battery monitoring apparatus according to this embodiment will be described with reference to FIGS. FIG. 11 is a flowchart showing a battery monitoring method. FIG. 12 and FIG. 13 are diagrams showing a procedure for extracting battery cells to be discharged in the progress state of the battery monitoring method.

  In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, description thereof will be omitted, and different portions will be described. The present embodiment is different from the first embodiment in that the battery cell extraction unit executes the first to third steps by the first logical operation.

  A battery monitoring method according to this embodiment, that is, a procedure for achieving cell balance will be described.

  As shown in FIG. 11, first, step S10 shown in FIG. 4 is executed as an initial setting.

  Next, battery cells to be discharged are extracted by the first logical operation that is a feature of the present embodiment (step S21). Step S21 corresponds to step 11 to step 15 (first step to third step) shown in FIG.

  Next, discharging of the extracted battery cell is started (step S22).

  Next, step S16 to step 18 shown in FIG. 4 are executed. In step S18, if the cell voltages V of all the battery cells E are not equal to or lower than the reference voltage Vref (NO in step S18), the process goes to step S21, and if not (YES in step S18), the cell balance ends.

  Next, a first logical operation for extracting battery cells to be discharged will be described with reference to FIG. The voltage distribution of the assembled battery 11 is the same as the voltage distribution of the assembled battery 11 shown in FIG. That is, V3> V0> V5> V2> V1 = V4 = Vref, and the battery cells E0, E2, E3, E5 are battery cells to be discharged.

  As shown in FIG. 12, an M-bit array A that is the same as the number M of battery cells 13 is defined. The cell number N is sequentially associated with the bits of the array A. That is, cell numbers N = 0 to 5 correspond to 1 to 5 bits of the array A, respectively.

  For the array A, a bit corresponding to the cell number N of a battery cell having a cell voltage higher than the reference voltage Vref is set to a logical value 1 (hereinafter simply referred to as 1), and the cell voltage is equal to or lower than the reference voltage Vref. A bit corresponding to the cell number of the battery cell is set to a logical value 0 (hereinafter simply referred to as 0). Array A = (101101) (step 1).

  An array B is obtained by shifting the array A by 1 bit in the upper bit direction. Array B = (010110) (step 2).

  An AND operation is performed on the array A and the array B, and the operation result is an array C. Array C = (000100) (step 3). In this step, it can be seen that there are battery cells E3 directly connected to each other.

  An AND operation is performed on the array C and an array (010101) in which all even bits are 1, and the operation result is an array D. Array D = (000100) (step 4).

  In this step, a battery cell E3 that cannot be discharged at the same time is found.

  An XOR operation is performed on the array A and the array D, and the operation result is an array E. Array E = (101001) (Step 5).

  In this step, it is understood that the battery cells E0, E2, and E5 are battery cell candidates that may be discharged at the same time. Furthermore, the logical operation is continued.

  An array F obtained by shifting the array E by 1 bit in the upper bit direction is obtained. The array F becomes (010100) (step 6).

  An AND operation is performed on the array E and the array F, and the operation result is defined as an array G. The array G becomes (000000) (step 7).

  An AND operation is performed on the array G1 and the array D obtained by shifting the array G by 1 bit in the upper bit direction, the operation result is the array H, the OR operation of the array E and the array H is performed, and the operation result is the array I. Array I = (101001) (step 8).

  This step is a step of restoring invalid bits (bits with consecutive 1s). In this example, it can be seen that there are no invalid bits.

  An array J obtained by shifting the array I by 1 bit in the upper bit direction is obtained. Array J = (010100) (step 9).

  An AND operation is performed on the array I and the array J, and the operation result is an array K. The array K becomes (000000) (step 10).

  An AND operation is performed on the array K and an array (101010) in which all odd bits are 1, and the operation result is an array L. Array L = (000000) (step 11).

  An XOR operation is performed on the array L and the array I, and the operation result is an array M. Array M = (101001) (step 12).

  In this step, since the array E in step 5 and the array M in step 12 are equal, it is confirmed that the battery cells E0, E2, and E5 are battery cells that can be discharged simultaneously.

  According to steps S22, S16, S17, and S18 shown in FIG. 11, discharge of the battery cells E0, E2, and E5 is started simultaneously. Wait until the discharge of the battery cell E2 stops. When the discharge of the battery cell E2 stops, the process goes to step 21 to repeat the first logical operation. Battery cells E0 and E5 continue to discharge.

  FIG. 13 is a diagram illustrating the progress of the first logical operation performed at step 21 for the second time. As shown in FIG. 13, since the cell voltage V2 is equal to or lower than the reference voltage Vref, the battery cells whose cell voltage V is higher than the reference voltage Vref are battery cells E0, E3, and E5. Therefore, the array A = (100101) is obtained (step 1).

  Thereafter, the first logical operation proceeds as in FIG. Specifically, in step 3, it is confirmed that there is no battery cell E that has a cell voltage higher than the reference voltage Vref and is directly connected. In step 4, it is confirmed that there are no battery cells E that should not be discharged. In step 5, it is confirmed that the battery cells E0, E3, E5 are battery cell candidates to be discharged. In step 12, it is confirmed that the battery cells E0, E3, E5 are battery cells to be discharged.

  The battery cell extraction unit 16 of the present embodiment can be easily implemented by combining a logic circuit such as an AND circuit, an OR circuit, and an XOR circuit, a shift register, and the like, and is therefore suitable for incorporation into an integrated circuit. Moreover, since the step of extracting the battery cells to be discharged does not depend on the number of battery cells, it can be executed faster than the first embodiment when the number of battery cells is large. The battery cell extraction unit 16 of the present embodiment is suitable when the number of battery cells is large.

  Next, the case where the assembled battery 11 has a voltage distribution different from the voltage distribution shown in FIG. 3 will be described. FIG. 14 is a diagram showing the voltage distribution of the assembled battery 11. FIG. 15 is a diagram illustrating a progress state of the first logical operation.

  As shown in FIG. 14, the assembled battery 11 has a voltage distribution in which the cell voltages V0, V3, and V4 are higher than the reference voltage Vref. That is, V3> V0> V4 = V1 = V2 = V5 = Vref, and the battery cells E0, E3, E4 are battery cells to be discharged.

  As shown in FIG. 15, the array A is set to (100110) (step 1).

  In step 3, it can be seen that there is a battery cell E4 that is array C = (000010) and is directly connected to each other.

  In step 4, array D = (000000) is obtained, and there is no battery cell that should not be discharged, which is inconsistent with the result of step 3.

  In step 5, the array E = (100110), and battery cells E0, E3, and E4 were obtained as battery cell candidates that may be discharged. 1 is continued in 4 bits and 5 bits of the array E. This is also inconsistent with the result of step 3.

  The array E is invalid if 1 consecutive bits are obtained. In order to restore invalid bits with consecutive 1s, the logical operations from step 6 to step 11 are executed.

  In step 12, array E = (100100), and battery cells E0 and E3 were obtained as battery cells that could be discharged. It can be seen that there is no contradiction with the result of Step 3. It was confirmed that the battery cells E0 and E3 are battery cells that can be discharged.

  It can be seen that depending on the voltage distribution of the assembled battery 11, battery cells that may be discharged in the step 5 may not be determined. However, it can be seen that an error can be prevented by executing the logical operations up to step 12.

  As described above, in the present embodiment, the battery cell extraction unit 16 executes the first step to the third step by the first logical operation. The first logical operation can be easily executed by combining a logic circuit such as an AND circuit, an OR circuit, an XOR circuit, and a shift register. The battery cell extraction unit 16 is suitable for incorporation into an integrated circuit. In addition, the first logical operation can be executed at a speed higher than that executed by software using a microcomputer.

(Embodiment 3)
A battery monitoring apparatus according to this embodiment will be described with reference to FIGS. FIG. 16 is a diagram showing the outline of the logical operation of the battery monitoring method. FIG. 17 is a flowchart showing a main part of the battery monitoring method. FIG. 18 is a diagram showing a procedure for extracting battery cells to be discharged in the progress state of the battery monitoring method.

  In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, description thereof will be omitted, and different portions will be described. The present embodiment is different from the first embodiment in that the battery cell extraction unit executes the first to third steps by the second logical operation.

  First, the gist of the second logical operation that is a feature of the present embodiment will be described. FIG. 16 is a diagram showing the essence of the second logical operation, FIG. 16A is a truth table of the essence of the second logical operation, and FIG. 16B is a logic for executing the essence of the second logical operation. It is a figure which shows an example of a circuit.

  As shown in FIG. 16A, the essence of the second logical operation is a logical operation for obtaining a logical product of an input bit and a bit obtained by inverting the previous output bit.

  When the immediately preceding output bit is 0, the bit obtained by inverting the immediately preceding output bit is 1. Therefore, when the input bit is 0, the output bit is 0, and when the input bit is 1, the output bit is 1. Conversely, when the immediately preceding output bit is 1, the bit obtained by inverting the immediately preceding output bit is 0. Therefore, the output bit is 0 regardless of whether the input bit is 0 or 1.

  That is, the essence of the second logical operation is that when the cell voltage V (N−1) of the battery cell E (N−1) is higher than the reference voltage Vref (the previous output bit corresponds to 1), the battery cell E Even if the cell voltage V (N) of (N) is larger than the reference voltage Vref, the battery cell E (N) is not extracted as a battery cell to be discharged (battery cell E (N-1), battery cell E (N) It is a logical operation that simulates not discharging at the same time.

  As shown in FIG. 16B, the logic circuit 31 that executes the gist of the second logic operation includes, for example, an AND circuit 32 and a NOT circuit 33. The NOT circuit 33 is connected between the output terminal of the AND circuit 32 and one input terminal of the AND circuit 32.

  The NOT circuit 33 outputs a bit obtained by inverting the output bit immediately before the AND circuit 32. The AND circuit 32 outputs a logical product of an input bit and a bit obtained by inverting the previous output bit. The initial value of the output bit is 0.

  A flowchart showing a battery monitoring method, that is, a procedure for achieving cell balance, is the same as the flowchart shown in FIG. In the flowchart shown in FIG. 11, instead of step S21, a step of executing the above-described second logical operation may be provided.

  Here, the voltage distribution of the assembled battery 11 is the same as the voltage distribution of the assembled battery 11 shown in FIG. That is, V3> V0> V5> V2> V1 = V4 = Vref, and the battery cells E0, E2, E3, E5 are battery cells to be discharged.

  FIG. 17 is a flowchart showing a main part of the battery monitoring method. Step S31 for executing the second logical operation includes steps S311 to S314.

  As shown in FIG. 17, the cell number N = 0 and the output bit of the AND circuit 32 are set to 0 as initial settings. (Step S311).

  Next, the outline of the second logical operation is executed on the battery cell E (N). When the calculation result is 1, the battery cell E (N) is extracted as a battery cell to be discharged (step S312), 1 is added to the cell number N, and N = N + 1 (step S313).

  Next, it is determined whether or not the cell number N is larger than M-1 (step S314). If N is not larger than M-1 (No in step S314), the process goes to step S311.

  At this stage, the outline of the first second logical operation is repeated 6 times, and battery cells E0, E2, and E5 that can be discharged simultaneously from the battery cells E0 to E5 are obtained.

  Next, if the cell number N is larger than N-1 (Yes in step S314), the process proceeds to step S22 shown in FIG. Discharging of the battery cells E0, E2, and E5 is started.

  When the discharge of the battery cell E2 is stopped, the battery cell E3 to be discharged still remains, so the process goes from No in step S18 to step S311.

  At this stage, the outline of the second logical operation of the second time is repeated 6 times, and battery cells E0, E3, and E5 that can be discharged simultaneously from the battery cells E0 to E5 are obtained.

  FIG. 18 is a diagram illustrating a progress state of the second logic operation, FIG. 18A is a diagram illustrating a progress state of the first second logic operation, and FIG. 18B is a second logic operation. It is a figure which shows the progress state of a calculation.

  In the same manner as in the second embodiment, the same M-bit array A and array B as the number M of battery cells 13 are defined. Array A is an input bit string, and array B is an output bit string.

  The cell number N is sequentially associated with the bits of the array A and the array B. That is, cell numbers N = 0 to 5 correspond to 1 to 5 bits of array A and 1 to 5 bits of array B, respectively.

  For array A, the bit corresponding to the cell number N of the battery cell having a cell voltage higher than the reference voltage Vref is set to 1, and the bit corresponding to the cell number of the battery cell having a cell voltage equal to or lower than the reference voltage Vref is set. Set to 0 (step 1). Input bit string A = (101101).

  As shown in FIG. 18A, an AND operation is performed on one bit of the array A with the immediately preceding output bit (initial value 0). Since 1 bit of array A is 1, the operation result is 1, and 1 bit of array B is 1 (step 2). Thereafter, the AND operation is similarly performed on 2 bits to 6 bits of the array A (step 3).

  Specifically, an AND operation is performed on 2 bits of array A = 0 and 1 bit of array B (immediate output bit) = 1, and 2 bits of array B = 0. An AND operation is performed on 3 bits of array A = 1 and 2 bits of array B = 0, so that 3 bits of array B = 1.

  Subsequently, AND operation of 4 bits = 1 in array A and 3 bits = 1 in array B is performed, and 4 bits in array B = 0. An AND operation of 5 bits of array A = 0 and 4 bits of array B = 0 is performed, and 5 bits of array B = 0. An AND operation is performed on 6 bits of array A = 1 and 5 bits of array B = 0, so that 5 bits of array B = 1.

  As a result, the output bit string B = (101001), and the battery cells E0, E3, and E5 that can be discharged at the same time are obtained from the battery cells E0 to E5.

  As shown in FIG. 18B, the second second logical operation is performed with the output bit string B = (101001) obtained in FIG. 18A as the new input bit string A. Since the progress state of the second logical operation of the second time is the same as that in FIG.

  As a result, the output bit string B = (100101), and among the battery cells E0 to E5, battery cells E0, E4, and E5 that can be discharged simultaneously are obtained.

  As described above, in the present embodiment, the battery cell extraction unit 16 executes the first step to the third step by the second logical operation. The logic circuit 31 that executes the second logic operation has an AND circuit 32 and a NOT circuit 33.

  Therefore, the second logical operation has an advantage that it can be realized with a smaller number of circuits than the first logical operation shown in the second embodiment. The battery cell extraction unit 16 is suitable for incorporation into an integrated circuit.

  The logic circuit 31 is not limited to the AND circuit and the NOT circuit, and can be realized using various logic circuits.

  Although some embodiments have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

Note that the configurations described in the following supplementary notes are conceivable.
(Additional remark 1) The said discharge part is a battery monitoring apparatus of Claim 3 which starts discharge of the said battery cell extracted whenever the said battery cell made to discharge in the said 2nd step is extracted.

(Supplementary note 2) The battery monitoring device according to claim 3, wherein the discharge unit collectively starts discharging the battery cells extracted in the second step after the end of the third step.

DESCRIPTION OF SYMBOLS 10 Battery monitoring system 11 Battery assembly 12 Battery monitoring apparatus 13 Battery cell 14 Voltage acquisition part 15 Reference voltage setting part 16 Battery cell extraction part 17 Discharge part 18 Voltage monitoring part 21 Motor 22 Auxiliary battery 31 Logic circuit 32 AND circuit 33 NOT circuit

Claims (9)

In extracting the battery cells having a voltage higher than a reference voltage and not directly connected to each other from the plurality of battery cells connected in series,
When the number of the battery cells is M, and the number N of the battery cells is 0 to M-1 in the order of series connection,
A first step with N = 0;
It is determined whether or not the voltage of the battery cell having the cell number N is higher than a reference voltage. If the voltage is higher, the battery cell having the cell number N is extracted and N = N + 2, and if not higher, N = N + 1. Two steps,
Determining whether N is greater than M-1, if not, a third step going to the second step;
A battery monitoring method comprising:   The battery monitoring method according to claim 1, wherein the reference voltage is the lowest voltage among the voltages of the battery cells. A voltage acquisition unit for acquiring voltages of a plurality of battery cells connected in series;
A reference voltage setting unit for setting a reference voltage for aligning the voltages of the plurality of battery cells;
A battery cell extraction unit for extracting the battery cells having a voltage higher than the reference voltage and not directly connected to each other from the plurality of battery cells;
The battery cells directly connected to each other have a discharge circuit that cannot discharge at the same time, and a discharge unit that discharges the extracted battery cells,
A voltage monitoring unit for determining whether the voltage of the battery cell during discharge is equal to or lower than the reference voltage;
Comprising
The battery cell extraction unit includes:
When the number of the battery cells is M, and the number N of the battery cells is 0 to M-1 in the order of series connection,
A first step with N = 0;
It is determined whether or not the voltage of the battery cell having the cell number N is higher than the reference voltage value. If it is higher, the battery cell having the cell number N is discharged and N = N + 2. A second step of setting = N + 1;
Determining whether N is greater than M-1, if not, a third step going to the second step;
A battery monitoring device comprising:   The battery monitoring apparatus according to claim 3, wherein the reference voltage setting unit sets the lowest voltage among the voltages of the battery cells as the reference voltage.   When the voltage of any of the battery cells being discharged is equal to or lower than the reference voltage, the voltage monitoring unit performs a fourth step of going to the first step until the voltages of all the battery cells are equal to or lower than the reference voltage. The battery monitoring device according to claim 3, wherein the battery monitoring device is provided.   The battery monitoring apparatus according to claim 3, wherein the battery cell extraction unit executes the first to third steps by a comparison operation.   The battery monitoring apparatus according to claim 3, wherein the battery cell extraction unit executes the first to third steps by a logical operation. The logical operation is
For the M-bit array A, the bit corresponding to the number of the battery cell having a voltage higher than the reference voltage is a logical value 1, and the bit corresponding to the number of the battery cell having a voltage lower than the reference voltage is a logical value. Step 1 to set to 0,
Step 2 for obtaining an array B obtained by shifting the array A by 1 bit in the upper bit direction;
Performing an AND operation on the array A and the array B and setting the operation result as an array C;
Performing an AND operation on the array C and an array in which even bits are all logical values 1, and setting the operation result as an array D;
Performing an XOR operation on the array A and the array D and setting the operation result as an array E;
Obtaining an array F obtained by shifting the array E by 1 bit in the upper bit direction; and
Performing an AND operation on the array E and the array F and setting the operation result as an array G;
An AND operation is performed on the array G obtained by shifting the array G by 1 bit in the upper bit direction and the array D, the operation result is set as an array H, the OR operation of the array E and the array H is performed, and the operation result is expressed as an array I. Step 8 to
Obtaining an array J obtained by shifting the array I by 1 bit in the upper bit direction; and
Performing an AND operation on the array I and the array J and setting the operation result as an array K;
Performing an AND operation on the array K and an array in which all odd bits are logical values 1, and setting the operation result to an array L;
Performing an XOR operation on the array L and the array I, and setting the operation result as an array M;
The battery monitoring device according to claim 7, comprising: The logical operation is
For the M-bit array A, the bit corresponding to the number of the battery cell having a voltage higher than the reference voltage is a logical value 1, and the bit corresponding to the number of the battery cell having a voltage lower than the reference voltage is a logical value. Step 1 to set to 0,
For n bits of the array A,
If the immediately preceding output bit is a logical value 0, the output bit is a logical value 0 when the input bit is a logical value 0, and the output bit is a logical value 1 when the input bit is a logical value 1,
If the previous output bit is a logical value 1, the logical value table in which the output bit is a logical value 0 regardless of the logical value of the input bit (however, when n = 1, the previous output bit is a logical value 0 And step 2 in which the operation result is array B.
The battery monitoring device according to claim 7, further comprising:

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