JP2016096169A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which makes it easy to remove the cause of an arc scratch on a polished surface.SOLUTION: A semiconductor device manufacturing method comprises: a process of performing first processing of pressing a first layer to a first polishing pad on a first platen while rotating a first polishing head at a first head rotating speed; a process of performing second processing of pressing the fist layer to a second polishing pad on a second platen while rotating the first polishing head at a second head rotating speed; and a process of adjusting a first polishing device having the first platen in a manner such that when a first defect corresponding to at least a part of a first trajectory formed on the first layer by a first definite point on the first polishing pad by the first processing is detected, the cause of the first defect is not supplied to the fist polishing pad, and adjusting a second polishing device having the second platen in a manner such that when a second defect corresponding to at least a part of a second trajectory formed on the first layer by a second definite point on the second polishing pad by the second processing is detected, the cause of the second defect is not supplied to the second polishing pad.SELECTED DRAWING: Figure 9

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  According to CMP (Chemical Mechanical Polishing), the deposited film on the wafer can be planarized.

  Regarding CMP, a technique for improving wafer flatness by polishing a deposited film so that a locus drawn on a polishing pad by a fixed point on a wafer is uniformly distributed has been reported.

Japanese Patent Laid-Open No. 11-70468

  When foreign matter adheres to the polishing pad, arc-shaped scratches (hereinafter referred to as arc scratches) are formed on the polishing surface of the wafer (surface generated by polishing).

  In many cases, the deposited film on the wafer is continuously polished by a plurality of CMP apparatuses (or a CMP apparatus having a plurality of platens). For this reason, even if an arc scratch is found in the inspection after polishing, it is difficult to identify which CMP apparatus (or which platen) has a problem. Therefore, it is not easy to remove the cause of arc scratch.

  In order to solve the above problem, according to one aspect of the present manufacturing method, a step of holding a first semiconductor substrate having a first layer having a first material on a front surface side on a first polishing head on a back surface side; After the holding step, the first layer is pressed against the first polishing pad on the first platen rotating at the first platen rotation speed while rotating the first polishing head at the first head rotation speed. After the step of performing one process and the step of performing the first process, the second layer rotates at the second platen rotation speed while rotating the first polishing head at the second head rotation speed. Performing a second process of pressing against a second polishing pad on the platen; and a first fixed point on the first polishing pad formed in the first layer by the first process after the second process. A first defect corresponding to at least part of the trajectory is detected In this case, a first polishing apparatus having the first platen is adjusted so that the cause of the first defect is not supplied to the first polishing pad, and a second fixed point on the second polishing pad is obtained by the second process. When the second defect corresponding to at least a part of the second locus formed on the first layer is detected, the second platen is prevented from being supplied to the second polishing pad. Adjusting the second polishing apparatus, wherein the first head rotation speed is different from the second head rotation speed, or the first platen rotation speed is different from the second platen rotation speed. A method for manufacturing a semiconductor device is provided.

  According to the disclosed method, the cause of arc scratches on the polished surface formed by CMP can be easily removed.

FIG. 1 is a diagram illustrating a CMP apparatus used in the method for manufacturing a semiconductor device according to the first embodiment. FIG. 2 is a diagram for explaining the polishing process of the first embodiment. FIG. 3 is a diagram for explaining the polishing process of the first embodiment. FIG. 4 is a diagram for explaining the polishing process of the first embodiment. FIG. 5 is a diagram illustrating an example of defect distribution on the polished surface of the first semiconductor substrate after the first and second treatments. FIG. 6 is a diagram illustrating an example of defect distribution on the polished surface of the first semiconductor substrate after the first and second treatments. FIG. 7 is a diagram for explaining arc scratching. FIG. 8 is a diagram illustrating a method for detecting the first defect or the second defect. FIG. 9 is a diagram illustrating a method for detecting the first defect or the second defect. FIG. 10 is a diagram illustrating a detection device that detects a first defect or a second defect from defect data obtained by a defect inspection device. FIG. 11 is a diagram illustrating an example of the first database and the second database. FIG. 12 is a diagram for explaining data registered in the first database and the second database. FIG. 13 is a flowchart of a method for detecting the first defect or the second defect from the defect data obtained by the defect inspection apparatus. FIG. 14 is a diagram illustrating an example of a defect data file. FIG. 15 is a diagram illustrating an example of a systematic region in the first layer. FIG. 16 is a diagram for explaining a method of handling a sector-like systematic region. FIG. 17 is a diagram showing the transition of the defect data file. FIG. 18 is a diagram for explaining the first cluster detection step. FIG. 19 is a diagram showing the transition of the defect data file. FIG. 20 is a diagram illustrating a method for calculating the in-substrate coordinates. FIG. 21 is a diagram illustrating the second cluster detection step. FIG. 22 is a diagram for explaining the second cluster detection step. FIG. 23 is a diagram showing the transition of the defect data file. FIG. 24 is a diagram for explaining the second cluster detection step. FIG. 25 is a flowchart for explaining an example of the first defect or second defect detection step S16. FIG. 26 is a diagram illustrating the third feature of the third cluster. FIG. 27 is a flowchart illustrating an example of matching determination. FIG. 28 is a diagram showing the transition of the defect data file. FIG. 29 is a diagram showing the transition of the defect data file. FIG. 30 is a diagram illustrating a polishing process according to the second embodiment. FIG. 31 is a diagram illustrating a polishing process according to the second embodiment. FIG. 32 is a diagram for explaining a polishing process according to the second embodiment. FIG. 33 is a diagram for explaining a polishing process according to the second embodiment. FIG. 34 is a diagram illustrating a polishing process according to the second embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the technical scope of the present invention is not limited to these embodiments, but extends to the matters described in the claims and equivalents thereof. Note that, even if the drawings are different, corresponding parts are denoted by the same reference numerals, and description thereof is omitted.

(Embodiment 1)
(1) Apparatus FIG. 1 is a diagram for explaining a CMP apparatus used in the method for manufacturing a semiconductor device according to the first embodiment. In the first embodiment, the first to third polishing heads 6a to 6c (see FIG. 1A), the first polishing apparatus 20a (see FIG. 1B), and the second polishing apparatus 20b (see FIG. 1). 1 (c)).

  The first polishing apparatus 20a is an apparatus having a first platen 10a and a first polishing pad 12a on the first platen 10a. The second polishing apparatus 20b is an apparatus having a second platen 10b and a second polishing pad 12b on the second platen 10b.

  The first polishing apparatus 20a and the second polishing apparatus 20b may be the same apparatus. That is, the first platen 10a and the first polishing pad 12a may be provided in the same apparatus as the second platen 10b and the second polishing pad 12b.

(2) Manufacturing Method (2-1) Polishing FIGS. 2 to 4 are diagrams illustrating the polishing process of the first embodiment.

(2-1-1) Mounting of a semiconductor substrate (see FIG. 2 (a))
First, as shown in FIG. 2A, the first semiconductor substrate 4a having the first layer 2a on the front surface side is mounted (held) on the first polishing head 6a on the back surface side. The first layer 2a is a layer having a first material (for example, Cu).

  Specifically, the back surface of the first semiconductor substrate 4a is fixed to the bottom surface of the first polishing head 6a by vacuum suction.

  The first semiconductor substrate 4a is, for example, a silicon substrate in which a transistor or the like is provided on the surface and an interlayer insulating film is provided on the transistor or the like. For example, a via hole and a wiring trench are provided in the interlayer insulating film. A first layer 2a is further provided on the interlayer insulating film. The first layer 2a is, for example, a conductive layer having a barrier layer and a Cu layer.

(2-1-2) Polishing with the first platen (see FIG. 3B)
Next, as shown in FIG. 3B, the first layer 2a is rotated on the first platen 10a rotating at the first platen rotation speed 8a while rotating the first polishing head 6a at the first head rotation speed 26a. Is pressed against the first polishing pad 12a (hereinafter referred to as a first treatment). During the first process, the first platen rotational speed 8a and the first head rotational speed 26a are kept constant.

  Specifically, first, the first semiconductor substrate 4a fixed to the bottom surface of the first polishing head 6a is moved onto the first polishing pad 12a (see FIG. 3B). Next, a membrane (not shown) disposed on the bottom surface of the first polishing head 6a is inflated by air pressure, and the first semiconductor substrate 4a is pressed against the first polishing pad 12a. At this time, a retainer ring (not shown) provided on the outer periphery of the first polishing head 6a is pressed against the first polishing pad 12a. Thereby, the first semiconductor substrate 4a is surrounded by the retainer ring, and the slip-out of the first semiconductor substrate 4a due to the rotation of the first platen 10a is suppressed.

  Thereafter, the first platen 10a and the first polishing head 6a are rotated while supplying the first slurry 22a to the first polishing pad 12a. The first polishing head 6a may be swung (hereinafter the same).

  As described above, the rotation speed of the first platen 10a is the first platen rotation speed 8a. The rotational speed of the first polishing head 6a is the first head rotational speed 26a. Thereby, for example, the Cu layer outside the via hole and the wiring groove in the first layer 2a is removed.

  Next, a first cleaning water (not shown) is supplied to the first polishing pad 12a while keeping the rotation speeds of the first platen 10a and the first polishing head 6a constant. Thereby, the first slurry 22a is removed from the first semiconductor substrate 4a and the first polishing pad 12a.

  In parallel with the first process, the third semiconductor substrate 4c is mounted on the second polishing head 6b by the same procedure as the mounting of the first semiconductor substrate 4a (see FIG. 3A). The third semiconductor substrate 4c is a semiconductor substrate having the third layer 2c on the surface side. The third layer 2c has a first material and has substantially the same structure as the first layer 2a.

(2-1-3) Polishing with the second platen (see FIG. 4C)
Next, as shown in FIG. 4C, the first layer 2a is rotated on the second platen 10b rotating at the second platen rotation speed 8b while rotating the first polishing head 6a at the second head rotation speed 26b. Is pressed against the second polishing pad 12b (hereinafter referred to as second processing). During the second process, the second platen rotation speed 8b and the second head rotation speed 26b are kept constant.

  The second head rotation speed 26b (for example, 55 rpm) is different from the first head rotation speed 26a (for example, 58 rpm). On the other hand, the second platen rotation speed 8b (for example, 60 rpm) is the same as the first platen rotation speed 8a (for example, 60 rpm).

  Specifically, the first semiconductor substrate 4a is moved onto the second polishing pad 12b by the same procedure as the first process, and then the first semiconductor substrate 4a is pressed against the second polishing pad 12b.

  Next, the second platen 10b and the first polishing head 6a are rotated by supplying the second slurry 22b to the second polishing pad 12b by the same procedure as the first process. Thereby, for example, the barrier layer outside the via hole and the wiring groove is removed.

  As described above, the rotation speed of the second platen 10b is the second platen rotation speed 8b. The rotation speed of the first polishing head 6a is the second head rotation speed 26b. The first platen rotational speed 8a (see FIG. 3B) and the second platen rotational speed 8b (see FIG. 4C) are the same. On the other hand, the first head rotation speed 26a (see FIG. 3B) and the second head rotation speed 26b (see FIG. 4C) are different.

  Next, a first cleaning water (not shown) is supplied to the second polishing pad 12b while keeping the rotation speeds of the second platen 10b and the first polishing head 6a constant. Thereby, the second slurry 22b is removed from the first semiconductor substrate 4a and the second polishing pad 12b.

  In parallel with the second process, the third layer 2c of the third semiconductor substrate 4c is polished by the same procedure as the first process (see FIG. 3B) as shown in FIG. 4B.

  Further, the fourth semiconductor substrate 4d is mounted on the third polishing head 6c (see FIG. 4A) by the same procedure as the mounting of the first semiconductor substrate 4a (see FIG. 2A). The fourth semiconductor substrate 4d is a semiconductor substrate having the fourth layer 2d on the surface side. The fourth layer 2d has a first material and has substantially the same structure as the first layer 2a.

  After the second process (see FIG. 4C), the first semiconductor substrate 4a is detached from the first polishing head 6a.

  A new semiconductor substrate in which a layer having a first material is disposed on the surface side is mounted on the first polishing head 6a from which the first semiconductor substrate 4a has been detached. Thereafter, by repeating the mounting, the first treatment, the second treatment, and the desorption, the semiconductor substrate on which the layer having the first material is disposed on the surface side is continuously polished.

(2-2) Inspection After the second processing, the polishing surface (the polishing surface generated by the first processing and the second processing) of the first semiconductor substrate 4a is inspected to detect surface shape defects such as irregularities. . The surface of the first semiconductor substrate 4a is inspected by, for example, an optical defect inspection apparatus or a laser type defect inspection apparatus. An optical defect inspection apparatus is an apparatus that captures a surface image of a semiconductor substrate and analyzes the captured surface image to detect a defect. A laser-type defect inspection apparatus is an apparatus that detects a defect by irradiating the surface of a semiconductor substrate with laser light and analyzing scattered light of the irradiated laser light.

  When the first material is Cu, it is preferable to cover the surface of the first semiconductor substrate 4a with a thin SiC film before the inspection to suppress the oxidation of Cu.

  5 and 6 are diagrams showing an example of defect distribution on the polished surface of the first semiconductor substrate 4a after the first and second treatments. When there is no abnormality in the first and second polishing apparatuses 20a and 20b, for example, as shown in FIG. 5, only the scattered defects 100 are observed on the polishing surface of the first semiconductor substrate 4a. The defect 100 is, for example, a recess caused by poor filling of a via hole during Cu plating.

  On the other hand, when there is an abnormality in the first or second polishing apparatus 20a, 20b, as shown in FIG. 6, for example, an arc-shaped scratch 102 (arc scratch) including a plurality of defects 100 is observed.

  5 and 6 show a defect 100 detected by an optical or laser type defect inspection apparatus. These defect inspection apparatuses are apparatuses that detect defects by determining a surface state (for example, flat or uneven) for each position coordinate on the surface of a semiconductor substrate. Therefore, the defect 100 is detected for each position coordinate on the surface of the semiconductor substrate. For this reason, line defects such as arc scratches are detected as a group of defects arranged in a line.

  FIG. 7 is a diagram for explaining the arc scratch 102. The horizontal axis (arbitrary unit) is the x axis fixed to the semiconductor substrate 4 (the same applies to FIG. 9 described later). The vertical axis (arbitrary unit) is the y axis fixed to the semiconductor substrate 4 (the same applies to FIG. 9 described later).

  Foreign substances (for example, particles larger than the abrasive grains of the slurry) may adhere to the polishing pad. The foreign matter adhering to the polishing pad forms an arc-shaped locus 16 on the surface of the semiconductor substrate 4 as shown in FIG. The foreign matter moves along the locus 16 and forms the arc scratch 102 on the polished surface.

  By the way, the depth of the arc scratch is not constant. For this reason, the appearance inspection apparatus may not react in a place where the arc scratch is shallow. Therefore, as shown in FIG. 6, the arc scratch 102 interrupted in the middle of the semiconductor substrate is detected.

  The trajectory 16 in FIG. 7 can be calculated by the following procedure, for example.

  First, based on the rotational movement of the platen, the transition (time change) of the coordinates (x, y) of the fixed point on the polishing pad is calculated. Next, the transition of the coordinates of the center of the semiconductor substrate is calculated based on the oscillation of the polishing head. Further, based on the rotational motion of the polishing head, the transition of the rotational angle θ (angle with respect to the x axis) of the coordinate axis fixed to the semiconductor substrate is calculated.

  Next, the transition of the coordinates (x, y) of the foreign matter is converted into the transition of the coordinates (x ′, y ′) with respect to the coordinate axis fixed to the semiconductor substrate. This conversion is performed based on the transition of the coordinates of the center of the semiconductor substrate and the transition of the rotation angle θ of the coordinate axis. At that time, coordinate conversion for the parallel movement of the coordinate axes and coordinate conversion for the rotational movement of the coordinate axes are performed.

(2-3) Detection of First Defect or Second Defect After the inspection of the first semiconductor substrate 4a, the defect detected by using the defect inspection apparatus is analyzed, and the first due to the foreign matter on the first polishing pad 12a is analyzed. An attempt is made to detect a defect (arc scratch) or a second defect (arc scratch) caused by a foreign matter on the second polishing pad 12b.

  8 and 9 are diagrams illustrating a method for detecting the first defect 18a or the second defect 18b. FIG. 8A is an example of the first defect 18a caused by the foreign matter on the first polishing pad 12a. FIG. 8B is an example of the second defect 18b caused by the foreign matter on the second polishing pad 12b.

  FIG. 9A is an example of the first locus 16a formed on the first layer 2a by the first fixed point 14a on the first polishing pad 12a in the first process (see FIG. 3B). FIG. 9B is an example of the second locus 16b formed on the first layer 2a by the second fixed point 14b on the second polishing pad 12b in the second process (see FIG. 4C).

  The first defect 18a (see FIG. 8A) is a defect corresponding to at least a part 17a of the first locus 16a (see FIG. 9A). The second defect 18b (see FIG. 8B) is a defect corresponding to at least a part 17b of the second locus 16b (see FIG. 9B).

  The rotational speed of the first polishing head 6a is different between the first polishing pad 12a and the second polishing pad 12b. Therefore, the locus of the fixed points 14a and 14b is different between the first polishing pad 12a and the second polishing pad 12b.

  Therefore, by comparing the fixed point trajectories 16a and 16b on the first and second polishing pads 12a and 12b with the defects on the polishing surface of the first semiconductor substrate 4a, it is caused by the foreign matter on the first or second polishing pad. The first or second defect 18a, 18b can be detected. Therefore, it is possible to identify the polishing pad to which foreign matter has adhered.

  Details of the method for detecting the first defect 18a and the second defect 18b will be described in “(3) Method for detecting the first defect and the second defect” described later.

(2-4) Processing when first defect or second defect is detected
-Adjustment of polishing equipment-
When the first defect 18a is detected on the polishing surface generated by the first process and the second process, the first polishing apparatus 20a is adjusted so that the cause of the first defect 18a is not supplied to the first polishing pad 12a. .

  The cause of the first defect 18a is, for example, diamond particles separated from a dresser (not shown) of the first polishing pad 12a. The dresser is a device that repairs damage to the polishing pad and keeps the surface state constant every time polishing of the semiconductor substrate is completed. If the dresser is the cause of the first defect 18a, the dresser is replaced or repaired.

  The first slurry 22a may aggregate and cause the first defect 18a. In this case, the first slurry 22a or the supply device for the first slurry 22a is replaced or repaired.

  The first polishing pad 12a may deteriorate and cause the first defect 18a. In this case, the first polishing pad 12a is replaced.

  The dirt adhering to the parts in the vicinity of the first platen 10a may peel off and cause the first defect 18a. In this case, the vicinity of the first platen 10a is cleaned.

  The polishing pad is repaired by the dresser every time polishing is completed. Accordingly, the foreign matter on the polishing pad is temporarily removed. However, unless the foreign material supply source is removed, the foreign material is supplied again to the polishing pad, and a defect (arc scratch) occurs. Therefore, when the first defect 18a is detected, the first polishing apparatus 20a is adjusted (repaired) so that the cause of the first defect 18a is not supplied to the first polishing pad 12a. In the adjustment of the first polishing apparatus 20a, for example, a portion that may supply foreign matter to the first polishing pad 12a (such as a dresser) is intensively inspected to identify the source of the foreign matter.

  Similarly, when the second defect 18b is detected on the polished surface generated by the first process and the second process, the second polishing apparatus 20b prevents the second defect 18b from being supplied to the second polishing pad 12b. Adjust.

―Polishing and post-processing―
After adjustment of the first polishing apparatus 20a or the second polishing apparatus 20b, the second layer formed on the surface side of the second semiconductor substrate different from the first semiconductor substrate 4a is applied to the first polishing apparatus 20a and the second polishing apparatus 20b. Polish by.

  The second semiconductor substrate is a semiconductor substrate having the same structure as the first semiconductor substrate 4a. The second layer is a layer having a first material (for example, Cu) and having substantially the same structure as the first layer 2a.

  After the polishing of the second layer, a post-process (for example, formation of an interlayer insulating film) different from the first process (see FIG. 3B) and the second process (see FIG. 4C) is performed on the second semiconductor substrate. To do.

(2-5) Processing when the first defect and the second defect are not detected When the first defect 18a and the second defect 18b are not detected, the post-process (for example, for the first semiconductor substrate 4a (for example, An interlayer insulating film is formed).

(3) First defect and second defect detection method (3-1) Device
FIG. 10 is a diagram illustrating a detection device 200 that detects the first defect 18a or the second defect 18b from defect data obtained by the defect inspection apparatus.

  The detection device 200 is a computer, for example.

  For example, as illustrated in FIG. 10, the detection device 200 includes a calculation unit 202, a main storage unit 204, an auxiliary storage unit 206, an input unit 208, a display unit 210, a communication unit 212, and a bus 214. The calculation unit 202 is, for example, a CPU (Central Processing Unit).

  The main storage unit 204 is, for example, a RAM (Random Access Memory) and a ROM (Read Only Memory). The auxiliary storage unit 206 is, for example, an HDD (Hard Disk Drive) storing HD (Hard Disk). The input unit 208 is, for example, a keyboard and / or a mouse. The display unit 210 is, for example, a liquid crystal display and / or a printer. The communication unit 212 is, for example, a NIC (Network Interface Card).

  The calculation unit 202 controls each hardware 202 to 212 of the detection apparatus 200 and executes a calculation. For example, the calculation unit 202 loads a program recorded in the auxiliary storage unit 206 into the main storage unit 204 (for example, RAM), and executes the loaded program. In addition to the program, data in the middle of calculation is temporarily recorded in the main storage unit 204.

  The auxiliary storage unit 206 stores at least a program (hereinafter referred to as an arc scratch detection program) that causes the calculation unit 202 to execute the first and second defect detection methods (see “(3-2) detection method”). ing.

  For example, the communication unit 212 transmits and receives data to and from the defect inspection apparatus.

  The bus 214 is connected to the calculation unit 202, the main storage unit 204, the auxiliary storage unit 206, the input unit 208, the display unit 210, and the communication unit 212. Data transmission / reception between the hardwares is performed via the bus 214. The operator operates the detection device 200 using the input unit 208 and the display unit 210.

  When the detection device 200 is activated, an arc scratch detection program is loaded into the auxiliary storage unit 206, and the calculation unit 202 executes the arc scratch detection program in accordance with an operator instruction.

―Database―
In the auxiliary storage unit 206, in addition to the arc scratch detection program, a first database and a second database are recorded.

  FIG. 11 is a diagram illustrating an example of the first database 216a and the second database 216b. FIG. 12 is a diagram for explaining data registered in the first database 216a and the second database 216b.

  In the first database 216a, a plurality of first regions 218 included in a first curve simulating a trajectory formed by a plurality of fixed points on the first platen 10a in the first layer 2a by the first processing (see FIG. 12). The first feature 219a is recorded. One of the plurality of fixed point trajectories is the first trajectory 16a described with reference to FIG.

  The first feature is, for example, the aspect ratio (= b / a) of the first region 218, the length a along the longitudinal direction of the first region 218, the position of the start point 220 of the first region 218, and the first region 218. This is a combination of the positions of the end point 222. The position of the starting point 220 is, for example, a circular coordinate radius 224 with the center O of the first semiconductor substrate 4a as the origin. Similarly, the position of the end point 222 is a moving radius 226 in circular coordinates with the center O as the origin.

  The first database 216a is, for example, a tabular database as shown in FIG. In each row of the first database 216a (excluding the first row), the first feature of the first region 218 and the reference data of the first region 218 are registered for each first region 218. In the first column, for example, the identifier (for example, PLATEN1) of the first platen 10a is recorded as reference data. Similarly, in the second column, the first head rotation speed 26a (for example, 58) of the first polishing head 6a on the first platen 10a is recorded as reference data.

  In the third to sixth columns, the first feature of the first region 218 is the aspect ratio (for example, 0.04) of the first region 218, the length along the first region 218 (for example, 15), and the start point 220. (For example, 13) and the position of the end point 222 (for example, 10) are recorded. A unit such as a length along the first region 218 is, for example, cm. The first region 218 is, for example, a region that overlaps each other.

  In the second database 216b, the second feature of each of the plurality of second regions included in the second curve simulating the trajectory that each of the plurality of fixed points on the second platen 10b forms on the first layer 2a by the second processing is stored. It is recorded. One of the plurality of fixed point trajectories is the second trajectory 16b described with reference to FIG.

  Similar to the first feature 219a, the second feature 219b includes, for example, the aspect ratio of the second region, the length of the second region, the position of the start point of the second region (for example, the radius), and the end point of the second region. It is a combination of positions (for example, moving radius).

  The structure of the second database 216b is substantially the same as the structure of the first database 216a, as shown in FIG.

  The first database and the second database may be integrated into one database.

(3-2) Detection Method FIG. 13 is a flowchart of a method for detecting the first defect 18a or the second defect 18b from the defect data obtained by the defect inspection apparatus.

(3-2-1) Acquisition of inspection data (S2)
The detection apparatus 200 acquires position data of defects on the polished surface of the first semiconductor substrate 4a after the second process (see FIG. 4C) from the defect inspection apparatus via the communication unit 212. The detection apparatus 200 records the acquired data in the auxiliary storage unit 206 as, for example, tabular data (hereinafter referred to as a defect data file).

  FIG. 14 is a diagram illustrating an example of the defect data file 228. In each line (excluding the first line) of the defect data file 228, defect position data (hereinafter, defect data) acquired from the defect inspection apparatus and reference data are recorded. 17, 19, 23, 28, and 29 are diagrams showing the transition of the defect data file 228.

  In the first column, for example, as reference data, an identifier (for example, LOT-A) of a lot including the first semiconductor substrate 4a is recorded. Similarly, identifiers (for example, CMP) of the first and second processes are recorded in the second column as reference data. Similarly, an identifier (for example, 17) of the first semiconductor substrate 4a is recorded in the third column as reference data.

  In the fourth column to the fifth column, as part of the defect data, the chip X value (for example, 10) of the chip where the defect is located (for example, an effective chip to be described later, the same applies hereinafter) and the chip of the chip where the defect is located A Y value (for example, 20) is recorded. In the sixth column to the seventh column, a defective in-chip X coordinate (for example, 1000) and a defective in-chip Y coordinate (for example, 10) are recorded as part of the defect data.

  A chip is an area where a semiconductor substrate is partitioned. Each chip can be identified by a chip X value and a chip Y value. The chip X value and the chip Y value will be described later. A determination flag is recorded in each cell in the eighth column (hereinafter referred to as a determination cell). Additional information corresponding to the determination flag is recorded in each cell in the ninth column (hereinafter referred to as an additional information cell).

(3-2-2) Bias determination (S4)
Next, the detection apparatus 200 refers to the defect data file 228 to determine whether or not the distribution of defects on the polished surface is biased (S4). If it is determined that the defect distribution is biased, the process proceeds to the next step S6. If it is determined that the defect distribution is not biased, the detection of the first and second defects 18a and 18b is terminated.

  Specifically, for example, the detection apparatus 200 first calculates a clustering coefficient α for the distribution of the defects 100. Next, the detection apparatus 200 determines whether or not the calculated clustering coefficient α is greater than or equal to a reference value (for example, 1.2). If the clustering coefficient α is greater than or equal to the reference value, the detection apparatus 200 proceeds to step S6. When the clustering coefficient α is less than the reference value, the detection apparatus 200 ends the detection of the first and second defects 18a and 18b.

―Clustering coefficient α―
When defects are randomly distributed on the polished surface of the semiconductor substrate, the ratio Y of chips having no defect among the effective chips included in the semiconductor substrate is expressed by Expression (1). Expression (1) is derived from a yield rate model based on a negative binomial distribution (for example, a yield rate model of International Technology Roadmap for Semiconductors (ITRS)). The effective chip is a chip separated from the outer edge of the semiconductor substrate among the chips that partition the semiconductor substrate. That is, the effective chip is a chip whose end is not cut off by the outer edge of the semiconductor substrate.

  A is the chip area, and D is the number of defects per unit area. Therefore, A · D is the average number of defects per chip. α is a clustering coefficient α.

  If the defects are distributed completely randomly, the clustering coefficient α is 1. As the defect distribution is biased, the clustering coefficient α increases. Therefore, when there is a systematic defect (see “(3-2-3) Removal of systematic defect”) in the semiconductor substrate, the clustering coefficient α increases.

(3-2-3) Systematic defect removal (S6 to S10)
The defect 100 on the polished surface can be classified into a random defect caused by a foreign matter generated in the process apparatus and a defect caused by the characteristics of the process apparatus (hereinafter referred to as a systematic defect). Systematic defects tend to be dense, which makes it difficult to detect the first and second defects.

  For example, when a via hole is formed in an interlayer insulating film with an etching apparatus having a bias in etching rate (so-called in-plane distribution), the opening diameter of the via hole is increased in a specific region. In such a region, the conductive film formed on the interlayer insulating film and in the via hole is lower than the surface of the interlayer insulating film in the via hole. When such a conductive film is polished, a recess (recessed via) is formed on the polished surface, resulting in a defect.

  Therefore, the detection apparatus 200 detects the first or second defect 18a, 18b from a region other than a region where a systematic defect occurs (hereinafter referred to as a systematic region) in steps S6 to S10.

  FIG. 15 is a diagram illustrating an example of the systematic area 230. As shown in FIG. 15, the systematic region 230 often has an annular shape.

(3-2-3-1) Determination of defect density (S6)
First, the detection apparatus 200 has an average density D ₁ (hereinafter referred to as a first average density) of the defects 100 on the polished surface generated by the first process and the second process equal to or higher than a reference value (hereinafter referred to as a second reference value). It is determined whether or not (S6).

When the first average density D ₁ is equal to or greater than the second reference value, the detector 200 proceeds to step S8. When the first average density D ₁ is less than the second reference value, the detector 200 proceeds to step S12. By steps S6 and S8, systematic defects existing at high density can be detected.

Specifically, for example, the detection apparatus 200 first calculates the first average density D ₁ of the defect 100 by the equation (2).

N is the total number of defects in all effective chips, A is the area of effective chips, and N ₀ is the total number of effective chips. The total number N of defects is, for example, the total number of defect data 236 in the defect data file 228. The total number of valid chips N ₀ is also derived based on the defect data file 228. The area A of the chip is input to the detection apparatus 200 in advance.

Thereafter, the detection apparatus 200 determines whether or not the calculated first average density D ₁ is equal to or greater than a second reference value (for example, 0.5 to 1.5 cm ⁻² ). When the first average density D ₁ is equal to or greater than the second reference value, the detector 200 proceeds to step S8. When the first average density D ₁ is less than the second reference value, the detector 200 proceeds to step S12.

(3-2-3-2) Determination of defect density in systematic region (S8)
The detection apparatus 200 determines whether or not the second average density D ₂ of defects in the systematic region 230 (predetermined region) in the polished surface is equal to or higher than a third reference value (for example, 0.5 to 1.5 cm ⁻² ). (S8).

Specifically, for example, the detection apparatus 200 first calculates the second average density D ₂ of the defect 100 in the systematic region 230 by the equation (3).

n is the total number of defects 100 in the systematic region 230 (more than half of the area is a defect in a chip included in the systematic region 230, and so on). A is the area of the effective chip. n ₀ is the total number of effective chips in the systematic region 230 (effective chips in which more than half of the area is included in the systematic region 230). The total number of n and n ₀ can be derived based on the defect data file 228.

Thereafter, the detection apparatus 200 determines whether or not the calculated second average density D2 is greater than or equal to a third reference value (for example, 0.5 to 1.5 cm ⁻² ).

If the second average density D ₂ of the third reference value or more, the detection device 200 proceeds to step S10. If the second average density D ₂ less than the third reference value, the detection device 200 proceeds to step S12.

-Modifications of the systematic region-
The systematic region 230 shown in FIG. 15 has an annular shape. However, the systematic region is not necessarily circular. FIG. 16 is a diagram for explaining a method of handling a sector-like systematic region.

  FIG. 16 shows a plurality of sector regions 232 and a central region 234 (hereinafter referred to as sectors 232, 234) obtained by dividing the polishing surface in the radial direction r and the declination θ direction. Systematic defects may be localized over one or more sector regions 232, 234, etc. In such a case, one or a plurality of sectors 232 and 234 are handled as systematic areas.

(3-2-3-3) Detection of Systematic Out-of-Region Defect (S10)
Detector 200, a second average density D ₂ is in the third or more reference values, to detect defects out systematic Thich 230.

  Specifically, for example, the detection apparatus 200 first determines whether or not the defect 100 corresponding to each defect data 236 recorded in the defect data file 228 (see FIG. 14) is included in the systematic area 230. . The determination is made based on the chip X value and the chip Y value of the defect data 236, for example. The determination may be made based on the in-substrate coordinates of the defect 100. The in-substrate coordinates are coordinates with respect to the coordinate axis fixed to the first semiconductor substrate 4a.

  The detection apparatus 200 records the determination result in the determination cell of the defect data file 228. When a defect corresponding to the defect data 236 is included in the systematic area 230, the detection apparatus 200 records “systematic area” in the determination cell 244, for example, as illustrated in FIG. The detection apparatus 200 performs such processing on all the defect data 236 in the defect data file 228. Then, only the defect outside the systematic region 230 is in a state where “systematic region” is not described in the determination cell 244. As described above, the defect outside the systematic region 230 is detected.

  Thereafter, the detection apparatus 200 deletes the defect data 236 recorded as “systematic area” in the determination cell 244 from the defect data file 228.

(3-2-4) Detection of first cluster (S12)
FIG. 18 is a diagram for explaining the first cluster detection step (S12).

  After the removal of the systematic defect, the detection apparatus 200 overlaps the cell regions 240 of a predetermined size including the defect 100 (see FIG. 18) in the group of the defects 100, and the number of the overlapping cell regions 240 is equal to or greater than the first reference value. A first population 238a is detected.

  Specifically, for example, the detection apparatus 200 determines whether or not the cell regions 240 overlap based on the in-substrate coordinates of the defect 100. The size of one side of the cell region 240 is, for example, 2 to 8 mm.

  The detection apparatus 200 further determines whether or not the number of overlapping cell regions 240 is equal to or greater than a first reference value (for example, 3 to 5). When the number of overlapping cell regions 240 is equal to or greater than the first reference value, the detection apparatus 200 records, for example, “cluster” in the determination cell 244 of the defect data 236 (see FIG. 19) of the defect 100 in the overlapping cell region 240. To do. The detection apparatus 200 further records the identifier (for example, 1, 2, 3,...) Of the first cluster 238a in the additional information cell 245 of the defect data 236. Thereby, the first cluster is detected.

  Thereafter, the detection apparatus 200 deletes the defect data 236 not recorded as “cluster” in the determination cell 244 from the defect data file 228.

  When the defect density is high as described above, the first cluster 238a is detected from outside the systematic region 230 (S6 → S8 → S10 → S12). Therefore, according to the first embodiment, the first and second defects can be easily detected even when a systematic defect exists.

―Calculation method of substrate coordinates―
FIG. 20 is a diagram illustrating a method for calculating the in-substrate coordinates.

  FIG. 20 shows a region 246 (chip) that partitions the first semiconductor substrate 4a. FIG. 20 further shows the center O of the first semiconductor substrate 4a and the origin chip 252. The origin chip 252 is selected from the chips 246 adjacent to the center O.

  In the column of “chip-X” of the defect data file 228 (see FIG. 14), the order (chip X value) of each chip 246 counted from the origin chip 252 along the X axis 248 is recorded. In the column of “chip-Y” of the defect data file 228, the order (chip Y value) of each chip 246 counted from the origin chip 252 along the Y-axis direction 250 is recorded.

  In order to calculate the in-substrate coordinates of the defect 100, first, the chip X value (for example, 1) of the chip 246 including the defect 100 is obtained from the defect data file 228. Next, based on the acquired chip X value and the size of each chip, the distance along the X axis 248 between the vertex 254 of the chip 246 including the defect 100 and the vertex 256 of the origin chip 252 (hereinafter referred to as the inter-vertex distance in the X axis direction). Is called). Next, from the distance L1 between the vertices in the X-axis direction and the distance L2 along the X-axis 248 between the vertex 256 of the origin chip 252 and the substrate center O, the X-coordinate in the substrate of the vertex 254 of the chip 246 including the defect 100 (= L1 + L2) is calculated. The size of each chip is input to the detection device 200 in advance. Similarly, the in-substrate Y coordinate of the vertex 254 of the chip 246 including the defect 100 is calculated. Thereby, the in-substrate coordinates of the vertex 254 of the chip 246 including the defect 100 are calculated.

  Next, the in-chip coordinates (in-chip-X coordinate and in-chip-Y coordinate) of the defect 100 are obtained from the defect data file 228. The in-substrate coordinates of the defect 100 are calculated from the acquired in-chip coordinates and the in-substrate coordinates of the vertex 254 of the chip 246 including the defect 100.

  Thus, the in-substrate coordinates of the defect 100 are calculated.

(3-2-5) Detection of linear defects (S14)
(3-2-5-1) Detection of Second Cluster FIGS. 21, 22, and 24 are diagrams for describing the detection process of the second cluster.

  The detection apparatus 200 detects the second cluster 238b (second group) in which the defect 100 (see FIG. 21) is arranged along the straight line 258 (or curve) in the first cluster 238a (first group). (S14).

  Specifically, for example, the detection apparatus 200 determines whether or not the defect 100 in the first cluster 238a is arranged along the straight line 258 based on Expression (4) described later (hereinafter referred to as line determination). .

  The detection apparatus 200 further records “line” in the determination cell 244 (see FIG. 23) of each defect 100 included in the first cluster 238 a that has determined that the defect 100 is arranged along the straight line 258. The detection apparatus 200 further records the identifier (for example, 1, 2, 3,...) Of the second cluster 238b in the additional information cell 245 (see FIG. 23) of each defect 100 included in the first cluster 238a. . Thereby, the second cluster 238b is detected.

  The detection apparatus 200 performs line determination for all the first clusters 238a detected in step S12, and records the result in the defect data file 228.

―Line judgment―
The line determination is performed based on, for example, the P value of Equation (4) (Sean P. Cunningham and Scott MacKinnon, “Statistical Methods for Visual Defect Metrology”, IEEE, VOL. 11, pp. 48-53, 1998).

  X is the X coordinate of the defect 100 (coordinate in the substrate coordinate system). Y is the Y coordinate of the defect 100 (coordinate in the substrate coordinate system). θ is an angle.

  FIG. 22 is a diagram showing a change in P value with respect to θ. The vertical axis is the P value. The horizontal axis is θ. FIG. 22 shows a change in P value for a plurality of defects 100. When each defect 100 is arranged along a straight line, the p value converges to a small range 260 as shown in FIG. The minute range 260 is a region where θ is constant (for example, 125 °). The smaller the width ΔP of the minute range 260 is, the smaller the difference between each defect 100 and the straight line 258 is.

  Therefore, by determining whether or not the width ΔP of the minute range 260 is equal to or smaller than the reference value, it can be determined whether or not the defect 100 is arranged along a straight line. Specifically, for example, when the width of the minute range 260 is equal to or smaller than a preset reference value, the detection apparatus 200 determines that the defect 100 is arranged along a straight line.

(3-2-5-2) Detection of Third Cluster FIG. 24 is a diagram for explaining a detection process of the third cluster.

  As shown in FIGS. 24A and 24B, the detection apparatus 200 includes at least one second cluster 238b and a third cluster 238c (second cluster) in which the defect 100 is arranged along a straight line 258 or a curved line 262. 3 populations) are detected.

  Specifically, for example, as illustrated in FIG. 24A, the detection apparatus 200 expands the minimum rectangular area 266 including the second cluster 238b in a predetermined size and lengthwise direction. When the defect 100 is included in the extended portion 268 of the rectangular area 266, the detection apparatus 200 detects the third cluster 238c including the defect 100 and the second cluster 238b.

  When the defect 100 is not included in the extended portion 268, the detection apparatus 200 detects the second cluster 238b as the third cluster 238c.

  As shown in FIG. 24B, when the extended portions 268 of the rectangular area 266 overlap each other, the third cluster including the second cluster 238 b in each rectangular area 266 and the defect 100 included in the extended portion 268. 238c is detected. The third cluster 238c is a linear defect (linear defect).

  When detecting the third raster 238c, the detection apparatus 200 records “line” again in the determination cell 244 (see FIG. 23) of each defect included in the third cluster 238c. The detection apparatus 200 further records the identifier (for example, 1, 2, 3,...) Of the third cluster 238c in the additional information cell 245 (see FIG. 23) of each defect included in the third cluster 238c. Thereby, the third cluster 238c is detected.

  Thereafter, the detection apparatus 200 deletes the defect data 236 that is not recorded as “line” in the determination cell 244 from the defect data file 228.

(3-2-6) Detection of first defect or second defect (S16)
FIG. 25 is a flowchart for explaining an example of the first defect or second defect detection step S16 (see FIG. 13).

  In the detection apparatus 200, first, one of the first features 219a registered in the first database 216a (see FIG. 11A) corresponds to the feature of the third cluster 238c (see FIGS. 24A and 24B). It is determined whether or not to perform (hereinafter referred to as coincidence determination) (S20). At this time, the detection apparatus 200 refers to the first database 216a. The feature of the third cluster 238c is hereinafter referred to as a third feature.

  When any of the first features 219a (see FIG. 11A) corresponds to the third feature, the detection apparatus 200 detects the third cluster 238c as the first defect 18a (see FIG. 8A) (see FIG. 8A). S20 → S22).

  When none of the first features 219a corresponds to the third feature, the detection apparatus 200 determines that any of the second features 219b registered in the second database 216b (see FIG. 11B) is the third cluster 238c. It is determined whether or not the third feature is supported (S20 → S24). At this time, the detection apparatus 200 refers to the second database 216b.

  When any of the second features 219b (see FIG. 11B) corresponds to the third feature, the detection apparatus 200 detects the third cluster 238c as the second defect 18b (see FIG. 8B) (see FIG. 8B). S24 → S26).

  The detection apparatus 200 performs steps S20 to S26 for all the third clusters 238c (linear defects) (S28).

  In the above example, when the first defect 18a is detected, the second defect 18b is not detected. However, even when the first defect 18a is detected, detection of the second defect 18b may be attempted.

-Example of third feature-
FIG. 26 is a diagram illustrating a third feature of the third cluster 238c. Note that the third cluster 238c in FIG. 26 is a cluster including one second cluster 238b.

  The third feature includes, for example, the aspect ratio of the third cluster 238c (= c / d, see FIG. 26), the length c along the longitudinal direction of the third cluster 238c, the position of the start point 270 of the third cluster 238c, and the This is a combination of the positions of the end points 272 of the three clusters 238c.

  For example, the start point 270 is a defect having the smallest in-substrate X coordinate among the defects 100 included in the third cluster 238c. The end point 272 is, for example, the defect 100 having the largest in-substrate X coordinate among the defects 100 included in the third cluster 238c. The positions of the start point 270 and the end point 272 are, for example, the moving radius with respect to the center O of the first semiconductor substrate 4a.

―Example of match determination―
FIG. 27 is a flowchart illustrating an example of matching determination.

  The detection device 200 calculates the third feature of the third cluster 238c and records it in the auxiliary storage unit 206, for example, before the match determination. The detection device 200 calls the recorded third feature and performs a match determination.

  In the coincidence determination, the detection apparatus 200 first assigns 0 to the variable I (S30). Next, the detection apparatus 200 compares the “aspect ratio” recorded in the first database 216a (see FIG. 11A) with the “aspect ratio” of the third cluster 238c (see FIG. 26). (S32).

  When the error between them is 10% or less (shape matching degree ≧ 0.9), the detection apparatus 200 adds 1 to the variable I (S34). Thereafter, the detection apparatus 200 proceeds to step S36. On the other hand, if the error between the two is greater than 10%, the detection apparatus 200 immediately proceeds to step S36.

  Next, the detection apparatus 200 detects the “start position” and “end position” recorded in the first database 216a (see FIG. 11A), the start position 270 and the end position of the third cluster 238c (see FIG. 26). 272 is compared (S36).

  When the start point position error is 10% or less and the end point position error is 10% or less (position matching degree ≧ 0.9), the detection apparatus 200 adds 1 to the variable I (S38). Thereafter, the detection device 200 proceeds to step S40. On the other hand, if any of the start point position error and the end point position error is greater than 10%, the detection apparatus 200 immediately proceeds to step S40.

  Next, the detection apparatus 200 compares the “length” recorded in the first data file 216a (see FIG. 11A) with the length c of the third cluster 238c (see FIG. 26) (S40). ).

  When the error between the two is 10% or less (length matching degree ≧ 0.9), the detection apparatus 200 adds 1 to the variable I (S42). Thereafter, the detection apparatus 200 proceeds to step S44. On the other hand, if the error between the two is greater than 10%, the detection apparatus 200 immediately proceeds to step S44.

  Next, the detection apparatus 200 determines whether or not the variable I is 2 or more (S44). When the variable I is 2 or more, the detection apparatus 200 records, for example, “first defect” in the determination cell 244 of the defect data 236 (see FIG. 28) corresponding to each defect in the third cluster 238c. Thereby, the first defect 18a (see FIG. 8A) is detected.

  After that, the detection apparatus 200 deletes the defect data 236 not recorded as “first defect” in the determination cell 244 from the defect data file 228 (see FIG. 29).

  In the above example, the detection apparatus 200 detects the first defect or the second defect. However, a human may detect the first defect or the second defect by visually comparing the first locus 16a and the second locus 16b with the arc scratch on the polished surface.

  The inventors have conventionally performed CMP continuously with a plurality of platens without changing the rotational speed of the polishing head. For this reason, it has been difficult to specify the platen to which the cause of defects (for example, dresser diamond particles) is supplied.

  On the other hand, according to Embodiment 1, since the rotation speed of the polishing head is changed for each platen, the platen to which the cause of the defect is supplied can be specified from the defect (arc scratch) generated on the polishing surface. Therefore, it becomes easy to remove the supply source of the arc scratch.

(Embodiment 2)
The second embodiment is similar to the first embodiment. Therefore, description of portions common to Embodiment 1 is omitted.

  In the first embodiment, after the first layer 2a is polished with the slurry, the first layer 2a is cleaned with cleaning water without changing the rotation speed of the first polishing head 6a. On the other hand, in the second embodiment, after the first layer 2a is polished with the slurry, the first layer 2a is cleaned with cleaning water by changing the rotation speed of the first polishing head 6a.

(1) Apparatus The CMP apparatus used in the second embodiment is substantially the same as the CMP apparatus in the first embodiment (see FIG. 1).

(2) Manufacturing Method (2-1) Polishing FIGS. 30 to 34 are diagrams illustrating a polishing process according to the second embodiment.

(2-1-1) Mounting of a semiconductor substrate (see FIG. 30A)
As shown in FIG. 30A, the first semiconductor substrate 4a having the first layer 2a on the front surface side is mounted (held) on the first polishing head 6a on the back surface side.

(2-1-2) Polishing with the first slurry (see FIG. 31B)
Next, as shown in FIG. 31B, the first layer 2a is rotated on the first platen 10a rotating at the first platen rotation speed 8a while rotating the first polishing head 6a at the first head rotation speed 26a. The first polishing pad 12a is pressed (first treatment). At this time, the first polishing head 6a and the first platen 10a are rotated while supplying the first slurry 22a to the first polishing pad 12a.

(2-1-3) Cleaning with the first cleaning water (see FIG. 32B)
Next, as shown in FIG. 32B, on the first platen 10a rotating the first layer 2a at the third platen rotational speed 8c while rotating the first polishing head 6a at the third head rotational speed 26c. Is pressed against the first polishing pad 12a (third treatment). At this time, the first polishing head 6a and the first platen 10a are rotated while supplying the first cleaning water 24a to the first polishing pad 12a.

  The third head rotation speed 26c is different from the first head rotation speed 26a. On the other hand, the third platen rotational speed 8c and the first platen rotational speed 8a are the same.

(2-1-4) Polishing with the second slurry (see FIG. 33C)
Next, as shown in FIG. 33 (c), the first layer 2a is rotated on the second platen 10b rotating at the second platen rotation speed 8b while rotating the first polishing head 6a at the second head rotation speed 26b. Is pressed against the second polishing pad 12b (second treatment). At this time, the first polishing head 6a and the second platen 10b are rotated while supplying the second slurry 22b to the second polishing pad 12b.

  The second head rotation speed 26b is different from the first head rotation speed 26a and the third head rotation speed 26c. On the other hand, the second platen rotational speed 8b is the same as the first platen rotational speed 8a and the third platen rotational speed 8c.

(2-1-5) Cleaning with the second cleaning water (see FIG. 34 (c))
Next, the first layer 2a is pressed against the second polishing pad 12b on the second platen 10b rotating at the fourth platen rotation speed 8d while the first polishing head 6a is rotated at the fourth head rotation speed 26d. (Fourth process). At this time, the first polishing head 6a and the second platen 10b are rotated while supplying the second cleaning water 24b to the second polishing pad 12b.

  The fourth head rotation speed 26d is different from the first head rotation speed 26a, the second head rotation speed 26b, and the third head rotation speed 26c. On the other hand, the fourth platen rotational speed 8d is the same as the first platen rotational speed 8a, the second platen rotational speed 8b, and the third platen rotational speed 8c.

(2-2) Inspection After the fourth process, the appearance of the polishing surface (the polishing surface generated by the first process to the fourth process) of the first semiconductor substrate 4a is inspected by the same procedure as in the first embodiment. Detect defects such as irregularities.

(2-3) Detection of first to fourth defects After the inspection of the first semiconductor substrate 4a, the defect detected using the defect inspection apparatus is analyzed to try to detect the first to fourth defects.

  The first defect in the second embodiment is a defect generated on the polishing surface of the first semiconductor substrate 4a due to foreign matter on the first polishing pad 12a during the first processing. The first defect corresponds to at least a part of the first locus formed on the first layer 2a by the first fixed point on the first polishing pad 12a by the first process (see FIG. 31B).

  The same applies to the second to fourth defects of the second embodiment. That is, the second defect is a defect generated on the polishing surface of the first semiconductor substrate 4a by the foreign matter on the second polishing pad 12b during the second process. The second defect corresponds to at least a part of the third locus formed on the first layer 2a by the second fixed point on the second polishing pad 12b by the second process (see FIG. 33C).

  The third defect is a defect generated on the polishing surface of the first semiconductor substrate 4a due to the foreign matter on the first polishing pad 12a during the third treatment. The third defect corresponds to at least a part of the third locus formed on the first layer 2a by the third fixed point on the first polishing pad 12a by the third process (see FIG. 32B).

  The fourth defect is a defect generated on the polishing surface of the first semiconductor substrate 4a due to the foreign matter on the second polishing pad 12b during the fourth process. The fourth defect corresponds to at least a part of the fourth locus formed on the first layer 2a by the fourth fixed point on the second polishing pad 12b by the fourth process (see FIG. 34C).

  The first to fourth defects are detected by the same procedure as in the first embodiment (see “(3) First to fourth defect detection method”).

(2-4) Processing when first to fourth defects are detected —Adjustment of polishing apparatus—
When the first defect or the third defect is detected, the first polishing apparatus 20a is adjusted so that the cause of the first defect or the third defect is not supplied to the first polishing pad 12a.

  In the case where the first defect is detected and the third defect is not detected, for example, the parts other than the first cleaning water and the first cleaning water supply device are intensively adjusted. When the first defect is not detected and the third defect is detected, for example, the first cleaning water or the first cleaning water supply device is intensively adjusted.

  When the second defect or the fourth defect is detected, the second polishing apparatus 20b is adjusted so that the cause of the second defect or the fourth defect is not supplied to the second polishing pad 12b.

  When the second defect is detected and the fourth defect is not detected, for example, adjustments other than the second cleaning water and the second cleaning water supply device are intensively adjusted. When the second defect is not detected and the fourth defect is detected, for example, the second cleaning water or the second cleaning water supply device is intensively adjusted.

―Polishing and post-processing―
After the adjustment of the first polishing apparatus 20a or the second polishing apparatus 20b, as in the first embodiment, the second layer formed on the surface side of the second semiconductor substrate different from the first semiconductor substrate 4a is used as the first polishing apparatus. Polishing is performed by 20a and the second polishing apparatus 20b.

  Thereafter, a post-process (for example, formation of an interlayer insulating film) different from the first to fourth processes is performed on the second semiconductor substrate.

(2-5) Processing when the first to fourth defects are not detected When the first to fourth defects are not detected, the post-process (for example, formation of an interlayer insulating film) is performed as the first semiconductor. This is performed on the substrate 4a.

(3) First to Fourth Defect Detection Method The first to fourth defects are detected by the same procedure as in the first embodiment (“(3) First defect and second defect in the first embodiment” Detection method ”).

  First to fourth databases are recorded in the auxiliary storage unit 206 of the detection apparatus 200 (see FIG. 10) according to the second embodiment.

  In the first database of the second embodiment, a plurality of fixed points on the first platen 10a are included in a plurality of first curves that simulate the trajectory formed on the first layer 2a by the first process of the second embodiment. A first feature of each first area is recorded.

  The same applies to the second to fourth databases. That is, the second database includes a plurality of second regions included in a second curve in which a plurality of fixed points on the second platen 10b simulate a locus formed on the first layer 2a by the second processing of the second embodiment. Each second feature is recorded.

  In the third database, each of a plurality of third regions included in a third curve that simulates a trajectory formed by each of a plurality of fixed points on the first platen 10a in the first layer 2a by the third process of the second embodiment. Features are recorded.

  In the fourth database, each of a plurality of fourth regions included in a fourth curve simulating a trajectory formed by each of a plurality of fixed points on the second platen 10b in the first layer 2a by the fourth process of the second embodiment. Features are recorded.

  The detection apparatus 200 tries to detect the first to fourth defects with reference to the first to fourth databases.

  In the second embodiment, the rotation speed of the polishing head is changed for each step (such as “polishing with the first slurry”). For this reason, according to the second embodiment, it is possible to specify the step in which the cause of the defect (arc scratch) is supplied. Therefore, according to the second embodiment, the cause of the defect can be removed more easily than the first embodiment.

(Embodiment 3)
The third embodiment is similar to the first embodiment. Therefore, description of portions common to Embodiment 1 is omitted.

  In the first embodiment, after the first layer 2a is polished by the first platen 10a, the first layer 2a is polished by the second platen 10b by changing the rotational speed of the first polishing head 6a. On the other hand, in the second embodiment, after the first layer 2a is polished by the first platen 10a, the first layer 2a is polished by the second platen 10b having a rotational speed different from that of the first platen 10a.

(1) Apparatus The CMP apparatus used in the method for manufacturing a semiconductor device according to the third embodiment is substantially the same as the CMP apparatus according to the first embodiment (see FIG. 1).

(2) Manufacturing Method (2-1) Polishing In the third embodiment, as in the first embodiment, the first layer 2a is polished by the first treatment (see FIG. 3B) and then washed. During the first process, the rotational speeds 8a and 26a of the first platen 10a and the first polishing head 6a are kept constant.

  Further, as in the first embodiment, the first layer 2a is polished by the second treatment (see FIG. 4C) and then washed. During the second process, the rotation speeds 8b and 26b of the second platen 10b and the second polishing head 6b are kept constant.

  The first head speed 26a (see FIG. 3B) and the second head speed 26b (see FIG. 4C) are the same. On the other hand, the first platen speed 8a (see FIG. 3B) and the second platen speed 8b (see FIG. 4C) are different.

(2-2) Inspection The polished surface of the first semiconductor substrate 4a is inspected by the same procedure as in the first embodiment.

(2-3) Detection of First Defect or Second Defect The detection apparatus 200 tries to detect the first defect or the second defect by the same procedure as in the first embodiment.

  However, the contents of the database referred to when detecting defects are different from the contents of the database of the first embodiment.

  In the first database of the third embodiment, a plurality of fixed points on the first platen 10a are included in a plurality of first curves that simulate a trajectory formed on the first layer 2a by the first process of the third embodiment. A first feature of each first area is recorded.

  In the second database of the third embodiment, a plurality of fixed points on the second platen 10b are included in a plurality of second curves that simulate the trajectory formed on the first layer 2a by the second processing of the third embodiment. A second feature of each second area is recorded.

(2-4) Processing when first defect or second defect is detected
When the first defect or the second defect is detected, the first polishing apparatus 20a or the second polishing apparatus 20b is adjusted by the same procedure as in the first embodiment. Next, the second semiconductor substrate 4b different from the first semiconductor substrate 4a is polished by the same procedure as in the first embodiment.

  Thereafter, a post-process (for example, formation of an interlayer insulating film) different from the first and second processes is performed on the second semiconductor substrate.

(2-5) Processing when the first defect and the second defect are not detected When the first defect and the second defect are not detected, the post-process (for example, interlayer insulation) is performed as in the first embodiment. Film formation) is performed on the first semiconductor substrate.

  In Embodiment 3, the rotation speed is changed for each platen. Therefore, according to the third embodiment, the platen to which the cause of the defect is supplied can be specified from the shape of the defect generated on the polished surface of the semiconductor substrate. Therefore, according to the third embodiment, the cause of the defect can be easily removed.

(Embodiment 4)
The fourth embodiment is similar to the second embodiment. Therefore, description of portions common to the second embodiment is omitted.

  In the second embodiment, the rotational speed of the polishing head is changed for each step. On the other hand, in the fourth embodiment, the rotation speed of the platen is changed for each step.

(1) Apparatus The CMP apparatus used in the method for manufacturing a semiconductor device according to the fourth embodiment is the same as the CMP apparatus according to the first embodiment (see FIG. 1).

(2) Manufacturing Method (2-1) Polishing In the third embodiment, as in the second embodiment, the first process (see FIG. 31 (b)), the second process (see FIG. 33 (c)), the first process The 1st layer 2a is grind | polished by 3 process (refer FIG.32 (b)) and 4th process (refer FIG.34 (c)).

  However, the first head rotation speed 26a (see FIG. 31 (b)), the second head rotation speed 26b (see FIG. 33 (c)), the third head rotation speed 26c (see FIG. 32 (b)), and the fourth head. The rotational speed 26d (see FIG. 34C) is the same. On the other hand, the first platen rotational speed 8a (see FIG. 31 (b)), the second platen rotational speed 8b (see FIG. 33 (c)), the third platen rotational speed 8c (see FIG. 32 (b)), and the fourth platen. The rotational speeds 8d (see FIG. 34 (c)) are different from each other.

(2-2) Inspection The polished surface of the first semiconductor substrate 4a is inspected by the same procedure as in the second embodiment.

(2-3) Detection of First to Fourth Defects The detection apparatus 200 tries to detect the first to fourth defects by the same procedure as in the second embodiment.

  However, the content of the database referred to when detecting the defect is different from the content of the database of the second embodiment.

  In the first database of the fourth embodiment, a plurality of fixed points on the first platen 10a are included in a plurality of first curves that simulate the trajectory formed on the first layer 2a by the first process of the fourth embodiment. A first feature of each first area is recorded.

  The same applies to the second to fourth databases. That is, the second database includes a plurality of second regions included in a second curve in which a plurality of fixed points on the second platen 10b simulate a locus formed on the first layer 2a by the second process of the fourth embodiment. Each second feature is recorded.

  In the third database, each of a plurality of third regions included in a third curve that simulates a trajectory formed by each of a plurality of fixed points on the first platen 10a in the first layer 2a by the third process of the fourth embodiment. Features are recorded.

  In the fourth database, each of a plurality of fourth regions included in a fourth curve simulating a trajectory formed by each of a plurality of fixed points on the second platen 10b in the first layer 2a by the second process of the fourth embodiment. Features are recorded.

(2-4) Processing when first to fourth defects are detected When first to fourth defects are detected, the first polishing apparatus 20a or the second polishing apparatus is performed in the same procedure as in the second embodiment. 20b is adjusted. Next, the second semiconductor substrate 4b different from the first semiconductor substrate 4a is polished by the same procedure as in the second embodiment.

  Thereafter, a post-process (for example, formation of an interlayer insulating film) different from the first to fourth processes is performed on the second semiconductor substrate.

(2-5) Processing when the first to fourth defects are not detected When the first to fourth defects are not detected, as in the second embodiment, the post-process (for example, the interlayer insulating film) Forming) is performed on the first semiconductor substrate.

  In the fourth embodiment, the rotation speed of the platen is changed for each step. For this reason, according to the fourth embodiment, it is possible to specify the step in which the cause of the defect is supplied. Therefore, according to the fourth embodiment, the cause of the defect can be removed more easily than the second embodiment.

  As mentioned above, although embodiment of this invention was described, Embodiment 1-4 is illustration and is not restrictive.

  For example, in Embodiments 1 to 4, linear defects are detected in steps S2 to S14 in FIG. However, a linear defect may be detected by an existing technique such as SSA (Spatial Signature Analysis).

  In the first to fourth embodiments, the first layer 2a is a conductive layer having a Cu layer and a barrier layer. However, the first layer 2a may be other than the conductive layer. For example, the first layer 2a may be an interlayer insulating film or a field insulating film.

  In the first to fourth embodiments, the Cu layer is polished by one polishing apparatus. However, the Cu layer may be polished by a plurality of (for example, two) polishing apparatuses.

  The following additional notes are further disclosed with respect to the first to fourth embodiments.

(Appendix 1)
Holding the first semiconductor substrate having the first layer having the first material on the front surface side on the back surface side in the first polishing head;
After the holding step, the first layer is pressed against the first polishing pad on the first platen rotating at the first platen rotation speed while rotating the first polishing head at the first head rotation speed. Performing a first treatment;
After the step of performing the first treatment, the second polishing pad on the second platen rotating the first layer at the second platen rotation speed while rotating the first polishing head at the second head rotation speed. Performing a second treatment to be pressed against
After the second process, when a first defect corresponding to at least a part of the first locus formed on the first layer by the first fixed point on the first polishing pad is detected by the first process. The first polishing apparatus having the first platen is adjusted so that the cause of the first defect is not supplied to the first polishing pad, and the second fixed point on the second polishing pad is adjusted by the second process. When the second defect corresponding to at least a part of the second locus formed in one layer is detected, the second platen is provided with the second platen so that the cause of the second defect is not supplied to the second polishing pad. 2 adjusting the polishing apparatus,
The first head rotation speed is different from the second head rotation speed, or the first platen rotation speed is different from the second platen rotation speed.

(Appendix 2)
After the adjusting step, the second layer having the first material formed on the surface side of the second semiconductor substrate different from the first semiconductor substrate is polished by the first polishing apparatus and the second polishing apparatus. The method for manufacturing a semiconductor device according to appendix 1, further comprising a step.

(Appendix 3)
3. The method of manufacturing a semiconductor device according to claim 2, further comprising a step of performing a post-process different from the first process and the second process on the second semiconductor substrate after the polishing step. Method.

(Appendix 4)
If the first defect and the second defect are not detected after the step of performing the second process, a post process different from the first process and the second process is performed on the first semiconductor substrate. The method for manufacturing a semiconductor device according to appendix 1, further comprising a step.

(Appendix 5)
Between the first process and the second process, the first layer is rotated on the first platen rotating at the third platen rotation speed while rotating the first polishing head at the third head rotation speed. Performing a third process of pressing against the first polishing pad;
After the second treatment, the first layer is applied to the second polishing pad on the second platen rotating at the fourth platen rotation speed while rotating the first polishing head at the fourth head rotation speed. And a fourth process of pressing.
Adjusting the first polishing apparatus having the first platen so that the cause of the first defect is not supplied to the first polishing pad when the first defect is detected after the fourth process; When the second defect is detected, the second polishing apparatus is adjusted so that the cause of the second defect is not supplied to the second polishing pad, and the third process is performed on the first polishing pad. When a third defect corresponding to at least a part of the third locus formed by the third fixed point on the first layer is detected, the cause of the third defect is not supplied to the first polishing pad. When the first polishing apparatus is adjusted and a fourth defect corresponding to at least a part of the fourth locus formed by the fourth fixed point on the second polishing pad in the first layer is detected by the fourth process. The cause of the fourth defect is the second polishing pad It said second polishing unit to adjust so as not supplied,
The first head rotational speed, the second head rotational speed, the third head rotational speed, and the fourth head rotational speed are different from each other, or the first platen rotational speed, the second platen rotational speed, The method for manufacturing a semiconductor device according to appendix 1, wherein the third platen rotation speed and the fourth platen rotation speed are different from each other.

(Appendix 6)
After the adjusting step, the method includes a step of polishing the second layer formed on the surface side of the second semiconductor substrate different from the first semiconductor substrate by the first polishing apparatus and the second polishing apparatus. The method for manufacturing a semiconductor device according to appendix 5, which is characterized in that.

(Appendix 7)
The method of manufacturing a semiconductor device according to claim 6, further comprising a step of performing a post-process different from the first process to the fourth process on the second semiconductor substrate after the polishing process.

(Appendix 8)
After the fourth process, when the first defect to the fourth defect are not detected, the method includes performing a post process different from the first process to the fourth process on the first semiconductor substrate. Item 6. The method for manufacturing a semiconductor device according to appendix 5, wherein:

(Appendix 9)
Performing the first treatment while supplying the first slurry to the first polishing pad, and then performing the third treatment while supplying the first cleaning water to the first polishing pad,
Supplementary notes 5 to 8 wherein the second treatment is performed while supplying the second slurry to the second polishing pad, and then the fourth treatment is performed while supplying the second cleaning water to the second polishing pad. The method for manufacturing a semiconductor device according to any one of the above.

(Appendix 10)
In the adjustment of the first polishing apparatus, the first polishing pad is replaced,
The method of manufacturing a semiconductor device according to any one of appendices 1 to 9, wherein in the adjustment of the second polishing apparatus, the second polishing pad is replaced.

(Appendix 11)
Referring to a first database in which first features of a plurality of regions included in a first curve simulating a trajectory formed on the first layer by the first processing at each of a plurality of fixed points on the first platen are registered. Determining whether any of the registered first features corresponds to a third feature of a linear defect detected by inspecting at least a polished surface generated by the first process and the second process. Detecting the first defect corresponding to any of the first features;
When it is determined that the first feature does not correspond to the third feature, each of a plurality of fixed points on the second platen is included in a second curve that simulates a locus formed on the first layer by the second processing. Determining whether any of the registered second features corresponds to the third feature of the linear defect, with reference to a second database in which second features of a plurality of regions are registered, and The method for manufacturing a semiconductor device according to claim 1, further comprising a step of detecting the second defect corresponding to any one of the second characteristics.

(Appendix 12)
A step of detecting a first group in which cell regions of a predetermined size including the defects overlap and a number of the overlapping cell regions is equal to or greater than a first reference value among a group of defects detected by inspecting the polished surface;
Detecting a second group in which the defect is arranged along a straight line or a curve among the detected first group;
Including at least one of the detected second populations, wherein the defect is arranged along a straight line or a curve to detect a third population,
The method of manufacturing a semiconductor device according to appendix 11, wherein the linear defect corresponds to the third group.

(Appendix 13)
Determining whether the first average density of the defects on the polished surface is greater than or equal to a second reference value;
A step of determining whether or not a second average density of the defects in a predetermined region in the polishing surface is equal to or higher than a third reference value when the first average density is determined to be equal to or higher than the second reference value;
13. The method of manufacturing a semiconductor device according to appendix 12, wherein when the second average density is determined to be equal to or higher than the third reference value, the first group is detected from outside the predetermined region.

(Appendix 14)
14. The method of manufacturing a semiconductor device according to appendix 13, wherein the predetermined region is a region where defects are systematically generated.

(Appendix 15)
The method for manufacturing a semiconductor device according to appendix 13 or 14, wherein the predetermined region is an annular region (Appendix 16)
Determining whether the distribution of the defects on the polished surface is biased,
16. The method of manufacturing a semiconductor device according to any one of appendices 12 to 15, wherein the first group to the third group are detected when it is determined that the defect distribution is biased.

(Appendix 17)
The method of manufacturing a semiconductor device according to appendix 16, wherein the distribution bias is determined based on a clustering coefficient of a negative binomial distribution model.

2a ... 1st layer 4a ... 1st semiconductor substrate 6a ... 1st polishing head 6b ... 2nd polishing head 8a ... 1st platen rotational speed 8b ... 2nd platen rotational speed 8c ... 3rd platen rotational speed 8d ... 4th platen rotational speed 12a ... 1st polishing pad 12b ... 2nd polishing pad 14a ... 1st fixed point 14b ... 2nd fixed point 16a ... First trajectory 16b second trajectory 18a first defect 18b second defect 20a first polishing apparatus 20b second polishing apparatus 22a first slurry 22b 2nd slurry 24a ... 1st washing water 24b ... 2nd washing water 26a ... 1st head rotational speed 26b ... 2nd head rotational speed 26c ... 3rd head rotational speed 26d ..4th head rotation speed 216a ... 1st de Database 216b ... second database 219a ... first feature 219b ... second feature 230 ... predetermined region 238a ... first population 238b ... second population 238c ... third population

Claims (10)

Holding the first semiconductor substrate having the first layer having the first material on the front surface side on the back surface side in the first polishing head;
After the holding step, the first layer is pressed against the first polishing pad on the first platen rotating at the first platen rotation speed while rotating the first polishing head at the first head rotation speed. Performing a first treatment;
After the step of performing the first treatment, the second polishing pad on the second platen rotating the first layer at the second platen rotation speed while rotating the first polishing head at the second head rotation speed. Performing a second treatment to be pressed against
After the second process, when a first defect corresponding to at least a part of the first locus formed on the first layer by the first fixed point on the first polishing pad is detected by the first process. The first polishing apparatus having the first platen is adjusted so that the cause of the first defect is not supplied to the first polishing pad, and the second fixed point on the second polishing pad is adjusted by the second process. When the second defect corresponding to at least a part of the second locus formed in one layer is detected, the second platen is provided with the second platen so that the cause of the second defect is not supplied to the second polishing pad. 2 adjusting the polishing apparatus,
The first head rotation speed is different from the second head rotation speed, or the first platen rotation speed is different from the second platen rotation speed. After the adjusting step, the second layer having the first material formed on the surface side of the second semiconductor substrate different from the first semiconductor substrate is polished by the first polishing apparatus and the second polishing apparatus. The method for manufacturing a semiconductor device according to claim 1, further comprising a step. The semiconductor device according to claim 2, further comprising a step of performing a post-process different from the first process and the second process on the second semiconductor substrate after the polishing process. Production method. Between the first process and the second process, the first layer is rotated on the first platen rotating at the third platen rotation speed while rotating the first polishing head at the third head rotation speed. Performing a third process of pressing against the first polishing pad;
After the second treatment, the first layer is applied to the second polishing pad on the second platen rotating at the fourth platen rotation speed while rotating the first polishing head at the fourth head rotation speed. And a fourth process of pressing.
Adjusting the first polishing apparatus having the first platen so that the cause of the first defect is not supplied to the first polishing pad when the first defect is detected after the fourth process; When the second defect is detected, the second polishing apparatus is adjusted so that the cause of the second defect is not supplied to the second polishing pad, and the third process is performed on the first polishing pad. When a third defect corresponding to at least a part of the third locus formed by the third fixed point on the first layer is detected, the cause of the third defect is not supplied to the first polishing pad. When the first polishing apparatus is adjusted and a fourth defect corresponding to at least a part of the fourth locus formed by the fourth fixed point on the second polishing pad in the first layer is detected by the fourth process. The cause of the fourth defect is the second polishing pad It said second polishing unit to adjust so as not supplied,
The first head rotational speed, the second head rotational speed, the third head rotational speed, and the fourth head rotational speed are different from each other, or the first platen rotational speed, the second platen rotational speed, The method for manufacturing a semiconductor device according to claim 1, wherein the third platen rotation speed and the fourth platen rotation speed are different from each other. Performing the first treatment while supplying the first slurry to the first polishing pad, and then performing the third treatment while supplying the first cleaning water to the first polishing pad,
5. The method according to claim 4, wherein the second treatment is performed while supplying the second slurry to the second polishing pad, and then the fourth treatment is performed while supplying the second cleaning water to the second polishing pad. The manufacturing method of the semiconductor device of description. Referring to a first database in which first features of a plurality of regions included in a first curve simulating a trajectory formed on the first layer by the first processing at each of a plurality of fixed points on the first platen are registered. Determining whether any of the registered first features corresponds to a third feature of a linear defect detected by inspecting at least a polished surface generated by the first process and the second process. Detecting the first defect corresponding to any of the first features;
When it is determined that the first feature does not correspond to the third feature, each of a plurality of fixed points on the second platen is included in a second curve that simulates a locus formed on the first layer by the second processing. Determining whether any of the registered second features corresponds to the third feature of the linear defect, with reference to a second database in which second features of a plurality of regions are registered, and The method for manufacturing a semiconductor device according to claim 1, further comprising a step of detecting the second defect corresponding to any one of the second characteristics. A step of detecting a first group in which cell regions of a predetermined size including the defects overlap and a number of the overlapping cell regions is equal to or greater than a first reference value among a group of defects detected by inspecting the polished surface;
Detecting a second group in which the defect is arranged along a straight line or a curve among the detected first group;
Including at least one of the detected second populations, wherein the defect is arranged along a straight line or a curve to detect a third population,
The method for manufacturing a semiconductor device according to claim 6, wherein the linear defect corresponds to the third group. Determining whether the first average density of the defects on the polished surface is greater than or equal to a second reference value;
A step of determining whether or not a second average density of the defects in a predetermined region in the polishing surface is equal to or higher than a third reference value when the first average density is determined to be equal to or higher than the second reference value;
The method of manufacturing a semiconductor device according to claim 7, wherein when the second average density is determined to be equal to or higher than the third reference value, the first group is detected from outside the predetermined region. The method of manufacturing a semiconductor device according to claim 8, wherein the predetermined region is a region where defects are systematically generated. Determining whether the distribution of the defects on the polished surface is biased,
10. The method of manufacturing a semiconductor device according to claim 7, wherein when it is determined that the distribution of the defects is biased, the first group to the third group are detected. 11.

Images