JP2016092084A - Semiconductor device, semiconductor device manufacturing method, module and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having favorable electric characteristics; or provide a semiconductor device having stable electric characteristics.SOLUTION: A semiconductor device manufacturing method comprises the steps of: forming a first transistor having a single crystal semiconductor in a channel formation region; forming an insulation film on the first transistor; forming an opening in the insulation film, which reaches the first transistor; forming a conductive film electrically connected with the first transistor via the opening; forming on the insulation film, a second transistor which is electrically connected with the conductive film and has an oxide semiconductor in a channel formation region; forming a capacitive element for electrically connecting the first transistor and the second transistor; and applying a voltage to a gate electrode of the second transistor while performing a heating treatment at a temperature of not less than 120°C and not more than 180°C.SELECTED DRAWING: Figure 1

Description

  One embodiment of the present invention relates to a semiconductor device.

  Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter). Therefore, the technical field of one embodiment of the present invention disclosed in this specification more specifically includes a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, a power storage device, a memory device, an imaging device, A driving method or a manufacturing method thereof can be given as an example.

  Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one embodiment of a semiconductor device. Further, the memory device, the display device, and the electronic device may include a semiconductor device.

  A technique for forming a transistor using a semiconductor thin film formed over a substrate having an insulating surface has attracted attention. The transistor is widely applied to an electronic device such as an integrated circuit (IC) or an image display device (also simply referred to as a display device). As a semiconductor thin film applicable to a transistor, a silicon-based semiconductor material is widely known, but an oxide semiconductor has attracted attention as another material.

  For example, a technique for manufacturing a transistor using zinc oxide or an In—Ga—Zn-based oxide semiconductor as an oxide semiconductor is disclosed (see Patent Documents 1 and 2).

  In recent years, with the increase in performance, size, and weight of electronic devices, there is an increasing demand for integrated circuits in which semiconductor elements such as miniaturized transistors are integrated at high density.

JP 2007-123861 A JP 2007-96055 A

  An object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics. Another object is to provide a semiconductor device with stable electrical characteristics. Another object is to provide a novel method for manufacturing the semiconductor device. Another object is to provide a module including the semiconductor device. Another object is to provide an electronic device including the semiconductor device or the module.

  Note that the description of these problems does not disturb the existence of other problems. Note that one embodiment of the present invention does not have to solve all of these problems. Issues other than these will be apparent from the description of the specification, drawings, claims, etc., and other issues can be extracted from the descriptions of the specification, drawings, claims, etc. It is.

  According to one embodiment of the present invention, a first transistor including a single crystal semiconductor in a channel formation region is formed, an insulating film is formed over the first transistor, an opening reaching the first transistor is formed in the insulating film, Forming a conductive film electrically connected to the first transistor through the opening, and forming a second transistor having an oxide semiconductor in a channel formation region and electrically connected to the conductive film over the insulating film; A capacitor element electrically connected to the first transistor and the second transistor is formed, and a voltage is applied to the gate electrode of the second transistor while performing heat treatment at a temperature of 120 ° C. to 180 ° C. This is a feature of a method for manufacturing a semiconductor device.

  In the above manufacturing method, the second transistor includes a first gate electrode, a base insulating film formed over the first gate electrode, an oxide semiconductor film formed over the base insulating film, Forming a source electrode and a drain electrode over the oxide semiconductor film, forming a gate insulating film over the oxide semiconductor film, over the source electrode and the drain electrode, forming a second gate electrode over the gate insulating film, A voltage is applied to one gate electrode.

  In the above manufacturing method, the voltage is preferably −10 V to −1 V.

  In the above manufacturing method, the heat treatment is preferably performed for 50 hours to 150 hours.

  Another embodiment of the present invention includes a first layer, a second layer over the first layer, a third layer over the second layer, and a capacitor. The first layer includes the first transistor, the third layer includes the second transistor, the channel formation region of the first transistor includes a single crystal semiconductor, and the channel of the second transistor The formation region includes an oxide semiconductor, the second layer includes an insulating film and a conductive film, and the conductive film electrically connects the first transistor and the second transistor. And the capacitor is electrically connected to the gate electrode of the first transistor and one of the source electrode or the drain electrode of the second transistor, and the gate electrode of the first transistor and the source electrode of the second transistor Or a node between one of the drain electrodes and one electrode of the capacitor. Te, the read failure rate of potential was maintained for 50 hours in the node at 0.99 ° C., which is a semiconductor device which is characterized in that less than 5 times the read failure rate of potential was maintained for 10 hours in the node at 0.99 ° C..

  Another embodiment of the present invention includes a first layer, a second layer over the first layer, a third layer over the second layer, and a capacitor. The first layer includes the first transistor, the third layer includes the second transistor, the channel formation region of the first transistor includes a single crystal semiconductor, and the channel of the second transistor The formation region includes an oxide semiconductor, the second layer includes an insulating film and a conductive film, and the conductive film electrically connects the first transistor and the second transistor. And the capacitor is electrically connected to the gate electrode of the first transistor and one of the source electrode or the drain electrode of the second transistor, and the gate electrode of the first transistor and the source electrode of the second transistor Or a node between one of the drain electrodes and one electrode of the capacitor. Te, while performing 250 hours of heat treatment at 0.99 ° C., which is a semiconductor device, wherein the read failure rate of the held potential is less than 8%.

  In the above structure, the voltage supplied to one of the source electrode and the drain electrode of the first transistor is preferably 1.2 V to 1.7 V.

  Another embodiment of the present invention is a module including any one of the semiconductor devices described above.

  Another embodiment of the present invention is an electronic device including any one of the above semiconductor devices or the above module and a speaker, an operation key, or a battery.

  A semiconductor device with favorable electrical characteristics can be provided. Alternatively, a semiconductor device with stable electrical characteristics can be provided. Alternatively, a novel method for manufacturing the semiconductor device can be provided. Alternatively, a module including the semiconductor device can be provided. Alternatively, an electronic device including the semiconductor device or the module can be provided.

  Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention need not have all of these effects. It should be noted that the effects other than these are naturally obvious from the description of the specification, drawings, claims, etc., and it is possible to extract the other effects from the descriptions of the specification, drawings, claims, etc. It is.

10 is a flowchart illustrating an example of a method for creating a semiconductor device. The circuit diagram which shows an example of a measurement system. 6 is a flowchart illustrating an example of a semiconductor device evaluation method. The circuit diagram which shows an example of a measurement system. The circuit diagram which shows an example of a measurement system. The figure explaining an example of a measurement system. FIG. 10 is a cross-sectional view illustrating a structure example of a semiconductor device. 10A and 10B are a top view and a cross-sectional view illustrating a structure example of a transistor. 10A and 10B are a cross-sectional view and an energy band diagram illustrating a structural example of a transistor. 10 is a cross-sectional view illustrating a method for manufacturing a transistor. FIG. 10 is a cross-sectional view illustrating a method for manufacturing a transistor. FIG. FIG. 10 is a cross-sectional view illustrating a structural example of a transistor. FIG. 10 is a cross-sectional view illustrating a structural example of a transistor. FIG. 10 is a cross-sectional view illustrating a structural example of a transistor. 10A and 10B are a top view and a cross-sectional view illustrating a structure example of a transistor. FIG. 6 is a circuit diagram illustrating an example of a memory device. The block diagram which shows an example of CPU. FIG. 14 illustrates an example of an electronic device. The figure which shows an example of RF device. FIG. 6 is a Cs-corrected high-resolution TEM image in a cross section of a CAAC-OS and a schematic cross-sectional view of the CAAC-OS. The Cs correction | amendment high-resolution TEM image in the plane of CAAC-OS. 6A and 6B illustrate structural analysis by XRD of a CAAC-OS and a single crystal oxide semiconductor. The figure which shows the electron diffraction pattern of CAAC-OS. FIG. 6 shows changes in crystal parts of an In—Ga—Zn oxide due to electron irradiation. Sectional drawing of a device structure. The figure explaining the correspondence of a data retention rate and VRM. 1 is a diagram for explaining a correspondence relationship between a retention failure rate and a VRM. FIG. The figure explaining the correspondence of 0 holding failure rate and VRM. The figure explaining the correspondence of a defect rate and holding time. Sectional drawing of a device structure. The figure explaining the Arrhenius plot of lifetime. The figure explaining the Arrhenius plot of lifetime.

  Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in the structures of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated. Note that hatching of the same elements constituting the drawings may be appropriately omitted or changed between different drawings.

  Further, the terms such as first, second, and third used in this specification are given for avoiding confusion between components, and are not limited numerically. Therefore, for example, the description can be made by appropriately replacing “first” with “second” or “third”.

  Further, the functions of “source” and “drain” may be interchanged when the direction of current changes during circuit operation. Therefore, in this specification, the terms “source” and “drain” can be used interchangeably.

  Further, the voltage refers to a potential difference between two points, and the potential refers to electrostatic energy (electric potential energy) possessed by a unit charge in an electrostatic field at a certain point. However, in general, a potential difference between a potential at a certain point and a reference potential (for example, ground potential) is simply referred to as a potential or a voltage, and a potential and a voltage are often used as synonyms. Therefore, in this specification, unless otherwise specified, the potential may be read as a voltage, or the voltage may be read as a potential.

  In addition, since a transistor including an oxide semiconductor film is an n-channel transistor, in this specification, a transistor that can be regarded as having no drain current flowing when the gate voltage is 0 V has normally-off characteristics. It is defined as a transistor. A transistor that can be regarded as having a drain current flowing when the gate voltage is 0 V is defined as a transistor having normally-on characteristics.

  Note that in this specification, the expression “film” and the expression “layer” can be interchanged with each other. Further, the expression “insulator” and the expression “insulating film (or insulating layer)” can be interchanged with each other. In addition, the expression “conductor” and the expression “conductive film (or conductive layer)” can be interchanged with each other. In addition, the expression “semiconductor” can be interchanged with the expression “semiconductor film (or semiconductor layer)”.

(Embodiment 1)
In this embodiment, an example of a semiconductor device, a manufacturing method thereof, and a semiconductor device evaluation method according to one embodiment of the present invention will be described with reference to FIGS. The following configuration of the measurement system can be adopted as the configuration of the characteristic evaluation circuit. Note that the measurement system shown below is merely an example.

<Measurement system>
The circuit diagram illustrated in FIG. 2 includes a transistor M0, a transistor M1, a capacitor Cs, a terminal WWL, a terminal WBL, a terminal RBL, a terminal SL, and a terminal VBG.

  The circuit shown in FIG. 2 is a characteristic evaluation circuit for evaluating the off-current (holding the charge of the node FN) of the transistor M0 that is a device under test (DUT) device.

  In FIG. 2, the gate electrode of the transistor M0 is electrically connected to the terminal WWL, and one of the source electrode and the drain electrode of the transistor M0 is electrically connected to the terminal WBL, and the source electrode or the drain electrode of the transistor M0 is connected. The other is electrically connected to the first terminal of the capacitor Cs, and the back gate electrode of the transistor M0 is electrically connected to the terminal VBG.

  In FIG. 2, the gate electrode of the transistor M1 is electrically connected to the first terminal of the capacitor Cs, and one of the source electrode and the drain electrode of the transistor M1 is electrically connected to the terminal RBL. The other of the source electrode and the drain electrode is electrically connected to the terminal SL.

  In FIG. 2, a low potential is applied to the second terminal of the capacitor Cs. For example, a ground potential may be given as a low potential.

  In FIG. 2, the node FN is in an electrically floating state.

  Here, a method for manufacturing a semiconductor device according to one embodiment of the present invention including the transistor M0, the transistor M1, and the capacitor Cs is described with reference to FIGS.

<Step A1>
First, the transistor M1 is formed, the transistor M0 and the capacitor Cs are formed over the transistor M1, and a semiconductor device is formed. Note that the transistor M1 is a transistor having a single crystal semiconductor in a channel formation region, and the transistor M0 is a transistor having an oxide semiconductor in a channel formation region. The transistor M0 has two gate electrodes. Details of the transistor M1, the transistor M0, and the capacitor Cs will be described in Embodiment 2.

Note that charge (data) is held in a node FN between the gate electrode of the transistor M1, the source electrode or the drain electrode of the transistor M0, and the one electrode of the capacitor Cs.
<Step A2>

Next, heat treatment is performed at a temperature of 120 ° C. to 180 ° C.
<Step A3>

Next, with the heat treatment performed, a voltage is applied to the terminal WWL to turn on the transistor M0, and the voltage applied to the terminal WBL is written to the node FN. In addition, a voltage is applied to the terminal VBG at the same time as charge is written to the node FN. The voltage applied to the terminal VBG is preferably -10V or more and -1V or less.
<Step A4>

  Next, with the voltage applied to the terminal VBG, a voltage is applied to the terminal WWL to turn off the transistor M0, so that the node FN is electrically floated. Note that the heat treatment is also continued from step A3. The heat treatment is preferably performed for 50 hours to 150 hours, more preferably 100 hours to 150 hours.

  By performing heat treatment while applying voltage to the terminal VBG as described above, defects in the oxide semiconductor film including the channel formation region of the transistor M0, defects in the interface between the oxide semiconductor film and the gate insulating film, back surface, There is a possibility that defects at the interface between the gate electrode and the base insulating film are filled with free electrons, and these defects disappear or are reduced. Therefore, the leakage current of the transistor M0 can be reduced and the data retention time can be extended.

  Hereinafter, a method for evaluating charge retention of the node FN will be described. In the following description, the transistor M0 is an n-channel transistor and the transistor M1 is a p-channel transistor. However, the present invention is not limited to this, and the transistor M0 is a p-channel transistor or \ and the transistor M1 is an n-channel transistor. Even if applicable.

<Evaluation method>
FIG. 3 is a flowchart illustrating a method for evaluating the charge retention characteristics of the node FN.

<Step B1>
First, the voltage applied to the terminal SL is changed little by little. By doing so, the voltage difference relative to the capacitive element Cs can be changed. Here, the voltage applied to the terminal SL is changed from 1.00 V to 2.40 V in increments of 0.02 V. For each change, the data held in the node FN is read and confirmed.

  Note that the transistor M1 is a p-channel transistor, and when the transistor M1 is turned on, the data is data 0. When the voltage applied to the terminal SL is higher, the transistor M1 is more likely to be turned on, that is, data 0 is more likely to occur. Further, the transistor M1 is more likely to be turned off, that is, the data 1 is easier when the voltage applied to the terminal SL is lower. Here, the data held in the node FN is binary data of “1” or “0”, and the data “1” is held as an H level potential and the data “0” is held as an L level potential.

<Step B2>
Next, the correspondence between the voltage applied to the terminal SL obtained in step 1 and the read data is examined. Check whether the stored data is the same as the read data. Note that when the charge of the data 1 held in the node FN leaks, the potential of the node FN is lowered and becomes data 0. Here, the fact that the data 1 becomes the data 0 is referred to as “data 1 retention failure”. The probability of data 1 retention failure is referred to as “data 1 retention failure rate”. In addition, the fact that data 0 becomes data 1 is herein referred to as “data 0 retention failure”. The probability of data 0 retention failure is referred to as “data 0 retention failure rate”.

<Step B3>
Next, the dependency of the heat treatment in step A2 on the correspondence between the data 1 retention failure rate and the voltage applied to the terminal SL is evaluated.

  From the above steps, the effect of the heat treatment can be confirmed, and a preferable heat treatment time range can be set. Details of the evaluation results will be described in Examples.

  As described above, data retention characteristics of a semiconductor device can be improved by following the method for manufacturing a semiconductor device. Further, data retention characteristics of the semiconductor device can be evaluated by following the semiconductor device evaluation method.

  Further, the characteristic evaluation circuit shown in FIG. 2 may include a transistor M2 as shown in FIG. The transistor M2 is connected to the terminal RWL. The terminal RWL has a function of supplying a signal for controlling on / off of the transistor M2. Further, as shown in FIG. 5, a terminal BL in which the terminal WBL and the terminal RBL of the circuit for characteristic evaluation shown in FIG. 4 are shared may be provided.

<Measurement environment>
As shown in FIG. 6, a measurement sample including a characteristic evaluation circuit may be put into an inert oven maintained at a constant temperature. Moreover, you may use a constant temperature air generator so that the temperature of the atmosphere surrounding a measuring device may become constant. By preparing the measurement environment as described above, it is possible to reduce the influence of noise due to temperature changes.

  Specifically, for example, the measurement sample is put in an inert oven, and the measurement sample is brought to a constant temperature state. At this time, if dry air is supplied to the inert oven, the humidity in the inert oven can be reduced, and measurement can be performed in a low humidity environment. Further, the sample is connected to the relay unit by a flat cable, and the relay unit is connected to the first measuring device and the second measuring device by a coaxial cable. The first measuring device transmits a signal for sending sample information to the relay unit. The second measuring device obtains sample information from the relay unit. Note that the measurement system (including the sample and the measuring device) is preferably in a constant temperature state. For example, the measurement system is covered with a heat insulating material, plastic cardboard, or the like, and can be brought into a constant temperature state by supplying constant temperature air using a constant temperature air generator and a duct cable. Note that it is preferable that the measurement system is not completely covered with a heat insulating material or plastic corrugated cardboard, and a small amount of constant temperature air is allowed to flow to the outside.

  The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 2)
In this embodiment, an example of a semiconductor device applicable to the measurement system illustrated in FIG. 2 will be described.

<Cross-sectional view of semiconductor device>
FIG. 7A is a cross-sectional view of the semiconductor device of one embodiment of the present invention. A semiconductor device illustrated in FIG. 7A includes a substrate 701, a transistor M0, a transistor M1, a capacitor Cs, an element isolation layer 702, an insulating film 703, a conductive film 704, a conductive film 705, and a conductive film. A film 706, a plug 707, a plug 708, and a plug 709 are provided. In addition, the transistor M1 includes an impurity region 721 functioning as a source region or a drain region, a gate electrode 723, a gate insulating film 724, and a sidewall insulating layer 725.

  The semiconductor device illustrated in FIG. 7A includes a transistor M1 using a first semiconductor material in a lower portion and a transistor M0 using a second semiconductor material in an upper portion. FIG. 7A illustrates a cross-sectional view of the transistor M0 and the transistor M1 in the channel length direction.

  The first semiconductor material and the second semiconductor material are preferably materials having different band gaps. For example, the first semiconductor material can be a semiconductor material other than an oxide semiconductor (such as silicon, germanium, silicon germanium, silicon carbide, or gallium arsenide), and the second semiconductor material can be an oxide semiconductor. A transistor using single crystal silicon as a material other than an oxide semiconductor can easily operate at high speed. On the other hand, a transistor including an oxide semiconductor has low off-state current.

  Details of the transistor M0 will be described in Embodiment 3 to be described later.

  The transistor M1 may be either an n-channel transistor or a p-channel transistor, and an appropriate transistor may be used depending on a circuit. In addition to the use of the transistor of one embodiment of the present invention using an oxide semiconductor, the specific structure of the semiconductor device, such as a material and a structure used, is not necessarily limited to that described here.

  In the transistor M1, an impurity region functioning as an LDD (Lightly Doped Drain) region or an extension region may be provided under the sidewall insulating layer 725. In particular, when the transistor M1 is an n-channel type, it is preferable to provide an LDD region and an extension region in order to suppress deterioration due to hot carriers.

  Alternatively, a transistor having silicide (salicide) or a transistor having no sidewall insulating layer 725 may be used as the transistor M1. When the structure has silicide (salicide), the resistance of the source region and the drain region can be further reduced, and the speed of the semiconductor device can be increased. In addition, since the semiconductor device can operate at a low voltage, power consumption of the semiconductor device can be reduced.

  Thus, by stacking two types of transistors, the area occupied by the circuit is reduced, and a plurality of circuits can be arranged at a higher density.

  The capacitor Cs can be manufactured using the same manufacturing process as the transistor M0. Note that in FIG. 7A, the capacitor Cs is provided in the same layer as the transistor M0; however, the capacitor Cs may be provided in the same layer as the transistor M1. The capacitor Cs may be provided in a hierarchy between the transistor M1 and the transistor M0. Further, the capacitor Cs may be provided in a hierarchy above the transistor M1 and the transistor M0.

  As the substrate 701, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate made of silicon germanium, an SOI (Silicon on Insulator) substrate, or the like can be used. A transistor formed using a semiconductor substrate can easily operate at high speed. Note that in the case where a p-type single crystal silicon substrate is used as the substrate 701, an n-type well is formed by adding an impurity element imparting n-type to part of the substrate 701, whereby the n-type well is formed. It is also possible to form a p-type transistor in the region. As the impurity element imparting n-type conductivity, phosphorus (P), arsenic (As), or the like can be used. As the impurity element imparting p-type conductivity, boron (B) or the like can be used.

  The substrate 701 may be a substrate in which a semiconductor film is provided over an insulating substrate. Examples of the insulating substrate include a glass substrate, a quartz substrate, a plastic substrate, a metal substrate, a stainless steel substrate, a substrate having a stainless steel foil, a tungsten substrate, a substrate having a tungsten foil, a flexible substrate, and a bonded substrate. Examples thereof include a film, paper containing a fibrous material, and a base film. Examples of the glass substrate include barium borosilicate glass, aluminoborosilicate glass, and soda lime glass. As an example of the flexible substrate, there are a plastic typified by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), or a synthetic resin having flexibility such as acrylic. Examples of the laminated film include polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride. Examples of the base film include polyester, polyamide, polyimide, aramid, epoxy, inorganic vapor deposition film, and papers.

  Note that a semiconductor element may be formed using a certain substrate, and then the semiconductor element may be transferred to another substrate. Examples of substrates on which semiconductor elements are transferred include paper substrates, cellophane substrates, aramid film substrates, polyimide film substrates, stone substrates, wood substrates, cloth substrates (natural fibers (silk, cotton, hemp)) , Synthetic fibers (nylon, polyurethane, polyester) or recycled fibers (including acetate, cupra, rayon, recycled polyester), leather substrates, rubber substrates, and the like. By using these substrates, it is possible to form a transistor with good characteristics, a transistor with low power consumption, manufacture a device that is not easily broken, impart heat resistance, reduce weight, or reduce thickness.

  The transistor M1 is separated from other transistors formed on the substrate 701 by an element isolation layer 702. The element isolation layer 702 includes aluminum oxide, aluminum oxynitride, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and hafnium oxide. An insulator containing one or more selected from tantalum oxide and the like can be used.

  Here, when a silicon-based semiconductor material is used for the transistor M1 provided in the lower layer, hydrogen in the insulating layer provided in the vicinity of the semiconductor layer of the transistor M1 terminates a dangling bond of silicon, and the reliability of the transistor M1 is increased. There is an effect to improve. On the other hand, in the case where an oxide semiconductor is used for the transistor M0 provided in the upper layer, hydrogen in the insulating layer provided in the vicinity of the semiconductor layer of the transistor M0 is one of the factors that generate carriers in the oxide semiconductor. In some cases, the reliability of the transistor M0 may be reduced. Therefore, in the case where the transistor M0 using an oxide semiconductor is stacked over the transistor M1 using a silicon-based semiconductor material, it is particularly preferable to provide the insulating film 703 having a function of preventing hydrogen diffusion therebetween. It is effective. In addition to improving the reliability of the transistor M1 by confining hydrogen in the lower layer with the insulating film 703, it is possible to simultaneously improve the reliability of the transistor M0 by suppressing the diffusion of hydrogen from the lower layer to the upper layer. it can.

  As the insulating film 703, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria-stabilized zirconia (YSZ), or the like can be used.

  The conductive films 704 to 706 are formed of copper (Cu), tungsten (W), molybdenum (Mo), gold (Au), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), nickel (Ni), chromium (Cr), lead (Pb), tin (Sn), iron (Fe), a simple substance made of a low-resistance material such as cobalt (Co), an alloy, or a conductive material containing a compound containing these as a main component A single layer or a stacked layer of films is preferable. In particular, it is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity. Moreover, it is preferable to form with low resistance conductive materials, such as aluminum and copper. Further, it is preferable to use a Cu—Mn alloy because manganese oxide is formed at the interface with the oxygen-containing insulator, and the manganese oxide has a function of suppressing Cu diffusion.

  The plugs 707 to 709 are copper (Cu), tungsten (W), molybdenum (Mo), gold (Au), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), nickel (Ni ), Chromium (Cr), lead (Pb), tin (Sn), iron (Fe), cobalt (Co), a simple substance or an alloy made of a low resistance material, or a conductive film containing a compound containing these as a main component A single layer or a stacked layer is preferable. In particular, it is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity. Moreover, it is preferable to form with low resistance conductive materials, such as aluminum and copper. Further, it is preferable to use a Cu—Mn alloy because manganese oxide is formed at the interface with the oxygen-containing insulator, and the manganese oxide has a function of suppressing Cu diffusion.

  Note that in FIG. 7A, a region to which no reference sign and hatching pattern are given represents a region formed of an insulator. These regions include aluminum oxide, aluminum nitride oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide An insulator containing one or more materials selected from tantalum oxide and the like can be used. In the region, an organic resin such as a polyimide resin, a polyamide resin, an acrylic resin, a siloxane resin, an epoxy resin, or a phenol resin can be used.

  As the transistor M1, the transistor 750 illustrated in FIGS. 7B and 7C may be used. FIG. 7C illustrates a cross section of FIG. 7B taken along one-dot chain line EF. The transistor 750 formed over the semiconductor substrate 730 includes a semiconductor layer 756 in which a channel is formed, an impurity region 751, an impurity region 755, a gate insulating film 753, a gate electrode 752, a sidewall insulating layer 754, an element A separation layer 731 is included. The semiconductor layer 756 has a convex shape, and a gate insulating film 753 and a gate electrode 752 are provided along a side surface and an upper surface thereof. Such a transistor is also called a FIN-type transistor because it uses a convex portion of a semiconductor substrate. Note that an insulating film functioning as a mask for forming the convex portion may be provided in contact with the upper portion of the convex portion. Although a case where a part of the semiconductor substrate 730 is processed to form a convex portion is shown here, an SOI substrate may be processed to form a semiconductor layer having a convex shape.

  In FIG. 7, the channel regions of the transistors M0 and M1 are made of different semiconductor materials, but the channel regions of the transistors M0 and M1 may be made of the same semiconductor material. For example, an oxide semiconductor may be used for the channel regions of both the transistor M0 and the transistor M1.

  The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 3)
In this embodiment, an example of a transistor that can be used as the transistor M0 described in Embodiments 1 and 2 will be described.

<Configuration Example 1 of Transistor>
8A to 8D are a top view and a cross-sectional view of the transistor 600. FIG. 8A is a top view, and a cross section in the direction of dashed-dotted line Y1-Y2 in FIG. 8A corresponds to FIG. 8B, and is in the direction of dashed-dotted line X1-X2 in FIG. The cross section corresponds to FIG. 8C, and the cross section in the direction of dashed-dotted line X3-X4 in FIG. 8A corresponds to FIG. Note that in FIGS. 8A to 8D, some elements are illustrated in an enlarged, reduced, or omitted manner for clarity. The direction of the alternate long and short dash line Y1-Y2 may be referred to as a channel length direction, and the direction of the alternate long and short dash line X1-X2 may be referred to as a channel width direction.

  Note that the channel length means, for example, in a top view of a transistor, a region where a semiconductor (or a portion where current flows in the semiconductor when the transistor is on) and a gate electrode overlap, or a region where a channel is formed , The distance between the source (source region or source electrode) and the drain (drain region or drain electrode). Note that in one transistor, the channel length is not necessarily the same in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in this specification, the channel length is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

  The channel width refers to, for example, the width of a source or drain in a region where a semiconductor (or a portion where a current flows in the semiconductor when the transistor is on) and a gate electrode overlap, or a region where a channel is formed. . Note that in one transistor, the channel width is not necessarily the same in all regions. That is, the channel width of one transistor may not be fixed to one value. Therefore, in this specification, the channel width is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

  Note that depending on the structure of the transistor, the channel width in a region where a channel is actually formed (hereinafter referred to as an effective channel width) and the channel width shown in a top view of the transistor (hereinafter, apparent channel width). May be different). For example, in a transistor having a three-dimensional structure, the effective channel width is larger than the apparent channel width shown in the top view of the transistor, and the influence may not be negligible. For example, in a transistor having a fine and three-dimensional structure, the ratio of the channel region formed on the side surface of the semiconductor may be larger than the ratio of the channel region formed on the upper surface of the semiconductor. In that case, the effective channel width in which the channel is actually formed is larger than the apparent channel width shown in the top view.

  By the way, in a transistor having a three-dimensional structure, it may be difficult to estimate an effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, it is difficult to accurately measure the effective channel width when the shape of the semiconductor is not accurately known.

  Therefore, in this specification, in the top view of a transistor, an apparent channel width which is a length of a portion where a source and a drain face each other in a region where a semiconductor and a gate electrode overlap with each other is referred to as an “enclosed channel width (SCW : Surrounded Channel Width) ”. In this specification, in the case where the term “channel width” is simply used, it may denote an enclosed channel width or an apparent channel width. Alternatively, in this specification, in the case where the term “channel width” is simply used, it may denote an effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, enclosed channel width, and the like can be determined by obtaining a cross-sectional TEM image and analyzing the image. it can.

  Note that in the case where the field-effect mobility of a transistor, the current value per channel width, and the like are calculated and calculated, the calculation may be performed using the enclosed channel width. In that case, the value may be different from that calculated using the effective channel width.

  The transistor 600 includes a substrate 640, an insulating film 651 over the substrate 640, a conductive film 674 formed over the insulating film 651, an insulating film 656 formed over the insulating film 651 and the conductive film 674, and an insulating film 656. The insulating film 652 formed thereover, a stack of the semiconductor 661 and the semiconductor 662 formed in that order over the insulating film 652, the conductive film 671 and the conductive film 672 in contact with the top surface of the semiconductor 662, the semiconductor 661 and the semiconductor 662 The conductive film 671 and the semiconductor 663 in contact with the conductive film 672, the insulating film 653 and the conductive film 673 over the semiconductor 663, the insulating film 654 over the conductive film 673 and the insulating film 653, and the insulating film 655 over the insulating film 654 are formed. Have. Note that the semiconductor 661, the semiconductor 662, and the semiconductor 663 are collectively referred to as a semiconductor 660.

  The conductive film 671 functions as a source electrode of the transistor 600. The conductive film 672 functions as a drain electrode of the transistor 600.

  The conductive film 673 functions as the first gate electrode of the transistor 600.

  The insulating film 653 functions as a first gate insulating film of the transistor 600.

  The conductive film 674 functions as the second gate electrode of the transistor 600.

  The insulating film 656 and the insulating film 652 function as a second gate insulating film of the transistor 600.

  The conductive film 673 and the conductive film 674 may be supplied with the same potential or different potentials. Further, the conductive film 674 can be omitted depending on circumstances.

  As illustrated in FIG. 8C, the side surface of the semiconductor 662 is surrounded by a conductive film 673. With the above structure, the semiconductor 662 can be electrically surrounded by the electric field of the conductive film 673 (the structure of the transistor that electrically surrounds the semiconductor by the electric field of the conductive film (gate electrode) is increased to the surrounded channel (s). -Channel) structure). Therefore, a channel may be formed in the entire semiconductor 662 (bulk). In the s-channel structure, a large current can flow between the source and the drain of the transistor, and a current during conduction (on-current) can be increased. Further, the s-channel structure can provide a transistor that can operate at high frequency.

  The s-channel structure can be said to be a structure suitable for a semiconductor device that requires a miniaturized transistor such as an LSI (Large Scale Integration) because a high on-state current can be obtained. Since a transistor can be miniaturized, a semiconductor device including the transistor can be a highly integrated semiconductor device with high integration. For example, the transistor has a channel length of preferably 10 nm or more and less than 1 μm, more preferably 10 nm or more and less than 100 nm, more preferably 10 nm or more and less than 70 nm, more preferably 10 nm or more and less than 60 nm, more preferably 10 nm or more and 30 nm. With less than. For example, the transistor preferably has a channel width of 10 nm or more and less than 1 μm, more preferably 10 nm or more and less than 100 nm, more preferably 10 nm or more and less than 70 nm, more preferably 10 nm or more and less than 60 nm, more preferably 10 nm or more and 30 nm. With less than.

  The s-channel structure can be said to be a structure suitable for a transistor that requires high-frequency operation because a high on-state current can be obtained. The semiconductor device including the transistor can be a semiconductor device that can operate at high frequency.

  The s-channel structure can be said to be a structure suitable for a power control transistor because a high on-state current can be obtained. When the s-channel structure is used for a power control transistor, a high breakdown voltage and a high current are required, so that the channel length and the channel width are preferably long. For example, the transistor preferably has a region with a channel length of preferably 1 μm or more, more preferably 10 μm or more, and even more preferably 100 μm or more. The transistor preferably has a region with a channel width of preferably 1 μm or more, more preferably 10 μm or more, and even more preferably 100 μm or more. In this case, the transistor only needs to have a region with a channel length of less than 1 cm and a region with a channel width of less than 1 cm.

  The insulating film 651 has a function of electrically separating the substrate 640 and the conductive film 674.

  The insulating film 652 preferably contains an oxide. In particular, an oxide material from which part of oxygen is released by heating is preferably included. It is preferable to use an oxide containing oxygen in excess of that in the stoichiometric composition. Part of oxygen is released by heating from the oxide film containing oxygen in excess of the stoichiometric composition. Oxygen released from the insulating film 652 is supplied to the semiconductor 660 which is an oxide semiconductor, so that oxygen vacancies in the oxide semiconductor can be reduced. As a result, variation in electrical characteristics of the transistor can be suppressed and reliability can be improved.

An oxide film containing more oxygen than that in the stoichiometric composition is converted into oxygen atoms at a surface temperature of 100 ° C. or more and 700 ° C. or less by, for example, TDS (Thermal Desorption Spectroscopy) analysis. The oxide film has an oxygen desorption amount of 1.0 × 10 ¹⁸ atoms / cm ³ or more, preferably 3.0 × 10 ²⁰ atoms / cm ³ or more. The surface temperature of the film at the time of the TDS analysis is preferably in the range of 100 ° C. to 700 ° C., or 100 ° C. to 500 ° C.

  The insulating film 656 has a function of preventing oxygen contained in the insulating film 652 from being combined with a metal contained in the conductive film 674 and reducing oxygen contained in the insulating film 652.

  The insulating film 654 has a function of blocking oxygen, hydrogen, water, alkali metal, alkaline earth metal, and the like. By providing the insulating film 654, diffusion of oxygen from the semiconductor 660 to the outside and entry of hydrogen, water, and the like into the semiconductor 660 from the outside can be prevented.

<Description of semiconductor>
Next, semiconductors applicable to the semiconductor 661, the semiconductor 662, the semiconductor 663, and the like are described.

The transistor 600 preferably has a low current (off-state current) flowing between the source and the drain in the non-conduction state. Here, the low off-state current means that at room temperature, the voltage between the source and the drain is 10 V, and the standardized off-current per channel width of 1 μm is 10 × 10 ⁻²¹ A or less. As such a transistor with low off-state current, a transistor including an oxide semiconductor as a semiconductor can be given.

  The semiconductor 662 is an oxide semiconductor containing indium (In), for example. For example, when the semiconductor 662 contains indium, the carrier mobility (electron mobility) increases. The semiconductor 662 preferably contains the element M. The element M is preferably aluminum (Al), gallium (Ga), yttrium (Y), tin (Sn), or the like. Other elements applicable to the element M include boron (B), silicon (Si), titanium (Ti), iron (Fe), nickel (Ni), germanium (Ge), yttrium (Y), zirconium (Zr ), Molybdenum (Mo), lanthanum (La), cerium (Ce), neodymium (Nd), hafnium (Hf), tantalum (Ta), tungsten (W), and the like. However, the element M may be a combination of a plurality of the aforementioned elements. The element M is an element having a high binding energy with oxygen, for example. For example, it is an element whose binding energy with oxygen is higher than that of indium. Alternatively, the element M is an element having a function of increasing the energy gap of the oxide semiconductor, for example. The semiconductor 662 preferably contains zinc (Zn). An oxide semiconductor may be easily crystallized when it contains zinc.

  Note that the semiconductor 662 is not limited to the oxide semiconductor containing indium. The semiconductor 662 may be, for example, an oxide semiconductor containing zinc, an oxide semiconductor containing zinc, an oxide semiconductor containing tin, or the like that does not contain indium, such as zinc tin oxide and gallium tin oxide.

  For the semiconductor 662, for example, an oxide with a wide energy gap is used. The energy gap of the semiconductor 662 is, for example, not less than 2.5 eV and not more than 4.2 eV, preferably not less than 2.8 eV and not more than 3.8 eV, more preferably not less than 3 eV and not more than 3.5 eV.

  The semiconductor 662 is preferably a CAAC-OS film described later.

  For example, the semiconductor 661 and the semiconductor 663 are oxide semiconductors including one or more elements other than oxygen included in the semiconductor 662 or two or more elements. Since the semiconductor 661 and the semiconductor 663 are composed of one or more elements other than oxygen constituting the semiconductor 662 or two or more elements, an interface state at the interface between the semiconductor 661 and the semiconductor 662 and the interface between the semiconductor 662 and the semiconductor 663 is used. The position is difficult to form.

  Note that when the semiconductor 661 is an In-M-Zn oxide and the sum of In and M is 100 atomic%, In is preferably less than 50 atomic%, M is higher than 50 atomic%, and more preferably In is less than 25 atomic%. , M is higher than 75 atomic%. In the case where the semiconductor 661 is formed by a sputtering method, a sputtering target that satisfies the above composition is preferably used. For example, In: M: Zn = 1: 3: 2 is preferable.

  In the case where the semiconductor 662 is an In—M—Zn oxide, when the sum of In and M is 100 atomic%, In is preferably higher than 25 atomic%, M is lower than 75 atomic%, and more preferably In is higher than 34 atomic%. High, and M is less than 66 atomic%. In the case where the semiconductor 662 is formed by a sputtering method, a sputtering target that satisfies the above composition is preferably used. For example, In: M: Zn = 1: 1: 1, In: M: Zn = 1: 1: 1.2, In: M: Zn = 2: 1: 3, In: M: Zn = 3: 1: 2, In: M: Zn = 4: 2: 4.1 is preferable. In particular, when an atomic ratio of In: Ga: Zn = 4: 2: 4.1 is used as a sputtering target, the atomic ratio of the semiconductor 662 to be formed is In: Ga: Zn = 4: 2: 3. May be near.

  In the case where the semiconductor 663 is an In—M—Zn oxide, when the sum of In and M is 100 atomic%, In is preferably less than 50 atomic%, M is higher than 50 atomic%, and more preferably, In is less than 25 atomic%. , M is higher than 75 atomic%. Note that the semiconductor 663 may be formed using the same type of oxide as the semiconductor 661. Note that the semiconductor 661 and / or the semiconductor 663 may not contain indium in some cases. For example, the semiconductor 661 and / or the semiconductor 663 may be gallium oxide.

  Next, functions and effects of the semiconductor 660 including the stack of the semiconductor 661, the semiconductor 662, and the semiconductor 663 will be described with reference to an energy band structure diagram in FIG. 9A is an enlarged view of the channel portion of the transistor 600 illustrated in FIG. 8B, and FIG. 9B is an energy band of a portion indicated by a chain line A1-A2 in FIG. 9A. The structure is shown. FIG. 9B illustrates an energy band structure of a channel formation region of the transistor 600.

  In FIG. 9B, Ec652, Ec661, Ec662, Ec663, and Ec653 indicate the energy at the lower end of the conduction band of the insulating film 652, the semiconductor 661, the semiconductor 662, the semiconductor 663, and the insulating film 653, respectively.

  Here, the difference between the vacuum level and the energy at the bottom of the conduction band (also referred to as “electron affinity”) is defined as the energy gap based on the difference between the vacuum level and the energy at the top of the valence band (also referred to as ionization potential). Subtracted value. The energy gap can be measured using a spectroscopic ellipsometer. The energy difference between the vacuum level and the upper end of the valence band can be measured using an ultraviolet photoelectron spectroscopy (UPS) apparatus.

  Since the insulating film 652 and the insulating film 653 are insulators, Ec653 and Ec652 are closer to the vacuum level (having a lower electron affinity) than Ec661, Ec662, and Ec663.

  As the semiconductor 662, an oxide having an electron affinity higher than those of the semiconductor 661 and the semiconductor 663 is used. For example, as the semiconductor 662, an oxide having an electron affinity greater than or equal to 0.07 eV and less than or equal to 1.3 eV, preferably greater than or equal to 0.1 eV and less than or equal to 0.7 eV, more preferably greater than or equal to 0.15 eV and less than or equal to 0.4 eV, compared with the semiconductors 661 and 663 Is used. Note that the electron affinity is the difference between the vacuum level and the energy at the bottom of the conduction band.

  Note that indium gallium oxide has a small electron affinity and a high oxygen blocking property. Therefore, the semiconductor 663 preferably includes indium gallium oxide. The gallium atom ratio [Ga / (In + Ga)] is, for example, 70% or more, preferably 80% or more, and more preferably 90% or more.

  At this time, when a gate voltage is applied, a channel is formed in the semiconductor 662 having high electron affinity among the semiconductors 661, 662, and 663.

  Here, in some cases, there is a mixed region of the semiconductor 661 and the semiconductor 662 between the semiconductor 661 and the semiconductor 662. Further, in some cases, there is a mixed region of the semiconductor 662 and the semiconductor 663 between the semiconductor 662 and the semiconductor 663. In the mixed region, the interface state density is low. Therefore, the stack of the semiconductor 661, the semiconductor 662, and the semiconductor 663 has a band structure in which energy continuously changes (also referred to as a continuous junction) in the vicinity of each interface.

  At this time, electrons move mainly in the semiconductor 662, not in the semiconductor 661 and the semiconductor 663. As described above, when the interface state density at the interface between the semiconductor 661 and the semiconductor 662 and the interface state density at the interface between the semiconductor 662 and the semiconductor 663 are lowered, movement of electrons in the semiconductor 662 is hindered. Therefore, the on-state current of the transistor can be increased.

  The on-state current of the transistor can be increased as the factor that hinders the movement of electrons is reduced. For example, when there is no factor that hinders the movement of electrons, it is estimated that electrons move efficiently. Electron movement is inhibited, for example, even when the physical unevenness of the channel formation region is large.

  In order to increase the on-state current of the transistor, for example, the root mean square (RMS) roughness of the upper surface or the lower surface of the semiconductor 662 (formation surface, here, the semiconductor 661) in a range of 1 μm × 1 μm is set. The thickness may be less than 1 nm, preferably less than 0.6 nm, more preferably less than 0.5 nm, and more preferably less than 0.4 nm. The average surface roughness (also referred to as Ra) in the range of 1 μm × 1 μm is less than 1 nm, preferably less than 0.6 nm, more preferably less than 0.5 nm, and more preferably less than 0.4 nm. The maximum height difference (also referred to as PV) in the range of 1 μm × 1 μm is less than 10 nm, preferably less than 9 nm, more preferably less than 8 nm, and more preferably less than 7 nm. The RMS roughness, Ra, and PV can be measured using a scanning probe microscope system SPA-500 manufactured by SII Nano Technology.

  Alternatively, for example, even when the density of defect states in a region where a channel is formed is high, the movement of electrons is inhibited.

For example, in the case where the semiconductor 662 has oxygen vacancies (also referred to as V 2 _O ), donor levels may be formed when hydrogen enters oxygen vacancy sites. The following may be referred to a state that has entered the hydrogen to oxygen vacancies in the site as V _{O H.} Since V _O H scatters electrons, it causes a reduction in the on-state current of the transistor. Note that oxygen deficient sites are more stable when oxygen enters than when hydrogen enters. Therefore, the on-state current of the transistor can be increased by reducing oxygen vacancies in the semiconductor 662 in some cases.

For example, the hydrogen concentration measured by secondary ion mass spectrometry (SIMS) at a certain depth of the semiconductor 662 or in a certain region of the semiconductor 662 is 1 × 10 ¹⁶ atoms / cm ³ or more. 2 × 10 ²⁰ atoms / cm ³ or less, preferably 1 × 10 ¹⁶ atoms / cm ³ or more, 5 × 10 ¹⁹ atoms / cm ³ or less, more preferably 1 × 10 ¹⁶ atoms / cm ³ or more, 1 × 10 ¹⁹ atoms / cm ³ or less, more preferably 1 × 10 ¹⁶ atoms / cm ³ or more and 5 × 10 ¹⁸ atoms / cm ³ or less.

  In order to reduce oxygen vacancies in the semiconductor 662, for example, there is a method in which excess oxygen contained in the insulating film 652 is moved to the semiconductor 662 through the semiconductor 661. In this case, the semiconductor 661 is preferably a layer having oxygen permeability (a layer through which oxygen passes or permeates).

  Note that in the case where the transistor has an s-channel structure, a channel is formed in the entire semiconductor 662. Accordingly, the thicker the semiconductor 662, the larger the channel region. That is, the thicker the semiconductor 662, the higher the on-state current of the transistor.

  In order to increase the on-state current of the transistor, the thickness of the semiconductor 663 is preferably as small as possible. The semiconductor 663 may have a region of, for example, less than 10 nm, preferably 5 nm or less, more preferably 3 nm or less. On the other hand, the semiconductor 663 has a function of blocking entry of elements other than oxygen (such as hydrogen and silicon) included in the adjacent insulator into the semiconductor 662 where a channel is formed. Therefore, the semiconductor 663 preferably has a certain thickness. The semiconductor 663 may have a region with a thickness of 0.3 nm or more, preferably 1 nm or more, more preferably 2 nm or more, for example. The semiconductor 663 preferably has a property of blocking oxygen in order to suppress outward diffusion of oxygen released from the insulating film 652 and the like.

  In order to increase reliability, the semiconductor 661 is preferably thick and the semiconductor 663 is preferably thin. The semiconductor 661 may have a region with a thickness of 10 nm or more, preferably 20 nm or more, more preferably 40 nm or more, and more preferably 60 nm or more. By increasing the thickness of the semiconductor 661, the distance from the interface between the adjacent insulator and the semiconductor 661 to the semiconductor 662 where a channel is formed can be increased. However, since the productivity of the semiconductor device may be reduced, the semiconductor 661 may have a region with a thickness of 200 nm or less, preferably 120 nm or less, more preferably 80 nm or less, for example.

For example, between the semiconductor 662 and the semiconductor 661, for example, in SIMS analysis, 1 × 10 ¹⁶ atoms / cm ³ or more and less than 1 × 10 ¹⁹ atoms / cm ³ , preferably 1 × 10 ¹⁶ atoms / cm ³ or more and 5 × It has a region having a silicon concentration of less than 10 ¹⁸ atoms / cm ³ , more preferably 1 × 10 ¹⁶ atoms / cm ³ or more and less than 2 × 10 ¹⁸ atoms / cm ³ . Further, between SIMS 662 and 663, in SIMS, 1 × 10 ¹⁶ atoms / cm ³ or more and less than 1 × 10 ¹⁹ atoms / cm ³ , preferably 1 × 10 ¹⁶ atoms / cm ³ or more and 5 × 10 ¹⁸ atoms. It has a region having a silicon concentration of less than / cm ³ , more preferably 1 × 10 ¹⁶ atoms / cm ³ or more and less than 2 × 10 ¹⁸ atoms / cm ³ .

In addition, in order to reduce the hydrogen concentration of the semiconductor 662, it is preferable to reduce the hydrogen concentration of the semiconductor 661 and the semiconductor 663. The semiconductor 661 and the semiconductor 663 have a SIMS structure of 1 × 10 ¹⁶ atoms / cm ³ or more and 2 × 10 ²⁰ atoms / cm ³ or less, preferably 1 × 10 ¹⁶ atoms / cm ³ or more and 5 × 10 ¹⁹ atoms / cm ³ or less. More preferably, a region having a hydrogen concentration of 1 × 10 ¹⁶ atoms / cm ^{3 to} 1 × 10 ¹⁹ atoms / cm ³ is more preferably 1 × 10 ¹⁶ atoms / cm ^{3 to} 5 × 10 ¹⁸ atoms / cm ^3. Have. In order to reduce the nitrogen concentration of the semiconductor 662, it is preferable to reduce the nitrogen concentrations of the semiconductor 661 and the semiconductor 663. The semiconductor 661 and the semiconductor 663 have a SIMS of 1 × 10 ¹⁶ atoms / cm ³ or more and less than 5 × 10 ¹⁹ atoms / cm ³ , preferably 1 × 10 ¹⁶ atoms / cm ³ or more and 5 × 10 ¹⁸ atoms / cm ³ or less. More preferably, a region having a nitrogen concentration of 1 × 10 ¹⁶ atoms / cm ^{3 to} 1 × 10 ¹⁸ atoms / cm ³ is more preferably 1 × 10 ¹⁶ atoms / cm ^{3 to} 5 × 10 ¹⁷ atoms / cm ^3. Have.

  The above three-layer structure is an example. For example, a two-layer structure without the semiconductor 661 or the semiconductor 663 may be used. Alternatively, a four-layer structure including any one of the semiconductors 661, 662, and 663 as the semiconductor 663 may be provided above or below the semiconductor 661 or above or below the semiconductor 663. Alternatively, the n-layer structure includes any one of the semiconductors 661, the semiconductor 662, and the semiconductor exemplified as the semiconductor 663 in any two or more positions over the semiconductor 661, the semiconductor 661, the semiconductor 663, and the semiconductor 663. (N is an integer of 5 or more).

<Method for Manufacturing Transistor>
Hereinafter, a method for manufacturing the transistor 600 illustrated in FIGS. 8A to 8C will be described with reference to FIGS. Note that a cross-sectional view in the channel length direction of the transistor (a cross-sectional view in the direction of dashed-dotted line Y1-Y2 in FIG. 8A) is shown on the left side of FIGS. 10 and 11, and on the right side of FIGS. FIG. 9A is a cross-sectional view of a transistor in a channel width direction (a cross-sectional view in the direction of dashed-dotted line X1-X2 in FIG. 8A).

  First, the insulating film 651a is formed over the substrate 640, the conductive film 674 is formed, and then the insulating film 651b is formed (see FIG. 10A).

  As the substrate 640, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria stabilized zirconia substrate), and a resin substrate. Examples of the semiconductor substrate include a single semiconductor substrate such as silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, there is a semiconductor substrate having an insulator region inside the semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Alternatively, there are a substrate having a metal nitride, a substrate having a metal oxide, and the like. Further, there are a substrate in which a conductor or a semiconductor is provided on an insulator substrate, a substrate in which a conductor or an insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided on a conductor substrate, and the like. Alternatively, a substrate in which an element is provided may be used. Examples of the element provided on the substrate include a capacitor element, a resistor element, a switch element, a light emitting element, and a memory element.

  Further, a flexible substrate may be used as the substrate 640. Note that as a method for providing a transistor over a flexible substrate, there is a method in which after a transistor is formed over a non-flexible substrate, the transistor is peeled off and transferred to a substrate 640 which is a flexible substrate. In that case, a separation layer is preferably provided between the non-flexible substrate and the transistor. Note that a sheet, a film, a foil, or the like in which fibers are knitted may be used as the substrate 640. Further, the substrate 640 may have elasticity. Further, the substrate 640 may have a property of returning to its original shape when bending or pulling is stopped. Or you may have a property which does not return to an original shape. The thickness of the substrate 640 is, for example, 5 μm to 700 μm, preferably 10 μm to 500 μm, and more preferably 15 μm to 300 μm. When the substrate 640 is thinned, the semiconductor device can be reduced in weight. Further, by making the substrate 640 thin, it may have elasticity even when glass or the like is used, or may have a property of returning to its original shape when bending or pulling is stopped. Therefore, an impact applied to the semiconductor device over the substrate 640 due to dropping or the like can be reduced. That is, a durable semiconductor device can be provided.

As the substrate 640 which is a flexible substrate, for example, metal, alloy, resin, glass, or fiber thereof can be used. The substrate 640 which is a flexible substrate is preferable because the deformation due to the environment is suppressed as the linear expansion coefficient is lower. As the substrate 640 which is a flexible substrate, for example, a material having a linear expansion coefficient of 1 × 10 ⁻³ / K or less, 5 × 10 ⁻⁵ / K or less, or 1 × 10 ⁻⁵ / K or less is used. Good. Examples of the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, acrylic, and polytetrafluoroethylene (PTFE). In particular, since aramid has a low coefficient of linear expansion, it is suitable for the substrate 640 that is a flexible substrate.

  As a material used for the insulating film 651a and the insulating film 651b, a material containing silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide is preferably used. Alternatively, a metal oxide such as aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, or hafnium oxynitride can be used. Note that in this specification, an oxynitride refers to a material having a higher oxygen content than nitrogen as its composition, and a nitride oxide refers to a material having a higher nitrogen content than oxygen as its composition. Indicates.

  Alternatively, the insulating film 651a and the insulating film 651b may be formed using silicon oxide with good step coverage formed by reacting TEOS (Tetra-Ethyl-Ortho-Silicate) or silane with oxygen or nitrous oxide. Good.

  The insulating film 651a and the insulating film 651b include a sputtering method, a CVD (Chemical Vapor Deposition) method (including a thermal CVD method, a MOCVD (Metal Organic CVD) method, a PECVD (Plasma Enhanced CVD) method, and the like), an MBE (Molecular Beam). Alternatively, a film may be formed by a method, an ALD (Atomic Layer Deposition) method, a PLD (Pulsed Laser Deposition) method, or the like. In particular, it is preferable to form the insulating film by a CVD method, preferably a plasma CVD method, because the coverage can be improved. In order to reduce plasma damage, thermal CVD, MOCVD or ALD is preferred.

  In the case where a semiconductor substrate is used as the substrate 640, the insulating film 651a may be formed using a thermal oxide film.

  The conductive film 674 includes copper (Cu), tungsten (W), molybdenum (Mo), gold (Au), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), nickel (Ni), Made of low resistance material such as chromium (Cr), lead (Pb), tin (Sn), iron (Fe), cobalt (Co), ruthenium (Ru), platinum (Pt), iridium (Ir), strontium (Sr) It is preferable to form a single layer or a stacked layer of a conductive film containing a single substance, an alloy, or a compound containing these as a main component. In particular, it is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity. Moreover, it is preferable to form with low resistance conductive materials, such as aluminum and copper. Further, it is preferable to use a Cu—Mn alloy because manganese oxide is formed at the interface with the oxygen-containing insulator, and the manganese oxide has a function of suppressing Cu diffusion.

  The conductive film 674 can be formed by, for example, a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, or the like), an MBE method, an ALD method, a PLD method, or the like.

  Next, the surface of the insulating film 651b is planarized by a CMP (Chemical Mechanical Polishing) method (see FIG. 10B).

  Further, a planarization film may be used as the insulating film 651b. In that case, the planarization is not necessarily performed by the CMP method or the like. For example, an atmospheric pressure CVD method or a coating method can be used to form the planarizing film. Examples of the film that can be formed using the atmospheric pressure CVD method include BPSG (Boron Phosphorus Silicate Glass). Moreover, as a film | membrane which can be formed using the apply | coating method, HSQ (hydrogen silsesquioxane) etc. are mentioned, for example.

  Hereinafter, the insulating film 651a and the insulating film 651b are collectively referred to as an insulating film 651.

  Next, an insulating film 656, an insulating film 652, a semiconductor 661, and a semiconductor 662 are formed (see FIG. 10C).

  The insulating film 656 and the insulating film 652 may be formed by a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, or the like), an MBE method, an ALD method, a PLD method, or the like.

  The insulating film 656 preferably has a blocking effect of oxygen, hydrogen, water, alkali metal, alkaline earth metal, or the like. As the insulating film 656, for example, a nitride insulating film can be used. Examples of the nitride insulating film include silicon nitride, silicon nitride oxide, aluminum nitride, and aluminum nitride oxide. Note that an oxide insulating film may be provided instead of the nitride insulating film. Examples of the oxide insulating film having a blocking effect of oxygen, hydrogen, water, and the like include aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, and hafnium oxynitride.

  The insulating film 652 preferably contains an oxide that can supply oxygen to the semiconductor 660. For example, the insulating film 652 is preferably formed using a material containing silicon oxide or silicon oxynitride. Alternatively, a metal oxide such as aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, or hafnium oxynitride can be used.

  In order to make the insulating film 652 contain excessive oxygen, for example, the insulating film 652 may be formed in an oxygen atmosphere. Alternatively, oxygen may be introduced into the insulating film 652 after film formation to form a region containing excess oxygen, or both means may be combined.

  For example, oxygen (including at least one of oxygen radicals, oxygen atoms, and oxygen ions) is introduced into the insulating film 652 that has been formed, so that a region containing excess oxygen is formed. As a method for introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, plasma treatment, or the like can be used.

  A gas containing oxygen can be used for the oxygen introduction treatment. As the gas containing oxygen, for example, oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide, carbon monoxide, or the like can be used. Further, in the oxygen introduction treatment, a gas containing oxygen may contain a rare gas. Alternatively, hydrogen or the like may be included. For example, a mixed gas of carbon dioxide, hydrogen, and argon may be used.

  Alternatively, after the insulating film 652 is formed, planarization treatment using a CMP method or the like may be performed in order to improve planarity of the upper surface.

  The semiconductor 661 and the semiconductor 662 are preferably formed successively without being exposed to the air. The semiconductor 661 and the semiconductor 662 may be formed by a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, or the like), an MBE method, a PLD method, an ALD method, or the like.

  For the materials that can be used for the semiconductor 661 and the semiconductor 662, the description of the semiconductor 661 and the semiconductor 662 in FIGS.

  Note that in the case where an In—Ga—Zn oxide layer is formed by a MOCVD method as the semiconductor 661 and the semiconductor 662, trimethylindium, trimethylgallium, dimethylzinc, or the like may be used as a source gas. The combination of the source gases is not limited, and triethylindium or the like may be used instead of trimethylindium. Further, triethylgallium or the like may be used instead of trimethylgallium. Further, diethyl zinc or the like may be used instead of dimethyl zinc.

  Here, oxygen may be introduced into the semiconductor 661 after the semiconductor 661 is formed. For example, oxygen (including at least one of oxygen radicals, oxygen atoms, and oxygen ions) is introduced into the semiconductor 661 after film formation to form a region containing excess oxygen. As a method for introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, plasma treatment, or the like can be used.

  A gas containing oxygen can be used for the oxygen introduction treatment. As the gas containing oxygen, for example, oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide, carbon monoxide, or the like can be used. Further, in the oxygen introduction treatment, a gas containing oxygen may contain a rare gas. Alternatively, hydrogen or the like may be included. For example, a mixed gas of carbon dioxide, hydrogen, and argon may be used.

  Heat treatment is preferably performed after the semiconductor 661 and the semiconductor 662 are formed. The heat treatment may be performed at a temperature of 250 ° C. to 650 ° C., preferably 300 ° C. to 500 ° C., in an inert gas atmosphere, an atmosphere containing an oxidizing gas of 10 ppm or more, or a reduced pressure state. The atmosphere for the heat treatment may be an atmosphere containing 10 ppm or more of an oxidizing gas in order to supplement the desorbed oxygen after the heat treatment in an inert gas atmosphere. The heat treatment may be performed immediately after the semiconductor film is formed, or may be performed after the semiconductor film is processed to form the island-shaped semiconductor 661 and the semiconductor 662. By the heat treatment, oxygen is supplied from the insulating film 652 and the oxide film to the semiconductor, so that oxygen vacancies in the semiconductor can be reduced.

  Thereafter, a resist mask is formed, and unnecessary portions are removed by etching. After that, by removing the resist mask, a stacked structure of the island-shaped semiconductor 661 and the island-shaped semiconductor 662 can be formed (see FIG. 10D). Note that when the semiconductor film is etched, part of the insulating film 652 is etched, and the insulating film 652 in a region not covered with the semiconductor 661 and the semiconductor 662 may be thinned. Therefore, it is preferable to form the insulating film 652 thick in advance so that the insulating film 652 is not lost by the etching.

  Note that, depending on the etching conditions of the semiconductor film, the resist may disappear during the etching, so a material having high etching resistance, for example, a so-called hard mask made of an inorganic film or a metal film may be used. Here, an example in which a conductive film is used as the hard mask 678 is described. An example in which a semiconductor film is processed using the hard mask 678 to form the semiconductor 661 and the semiconductor 662 is described. (See FIG. 10E).

  As the hard mask 678, copper (Cu), tungsten (W), molybdenum (Mo), gold (Au), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), nickel (Ni), Made of low resistance material such as chromium (Cr), lead (Pb), tin (Sn), iron (Fe), cobalt (Co), ruthenium (Ru), platinum (Pt), iridium (Ir), strontium (Sr) It is preferable to form a single layer or a stacked layer of a conductive film containing a single substance, an alloy, or a compound containing these as a main component. In particular, it is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity. Moreover, it is preferable to form with low resistance conductive materials, such as aluminum and copper. Further, it is preferable to use a Cu—Mn alloy because manganese oxide is formed at the interface with the oxygen-containing insulator, and the manganese oxide has a function of suppressing Cu diffusion.

  The hard mask 678 is preferably formed using a conductive oxide containing a noble metal such as iridium oxide, ruthenium oxide, or strontium ruthenite. These conductive oxides hardly take oxygen from the oxide semiconductor even when in contact with the oxide semiconductor, and do not easily form oxygen vacancies in the oxide semiconductor.

  The hard mask 678 can be formed using, for example, a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, or the like), an MBE method, an ALD method, or a PLD method.

  Next, a resist mask is formed, and the hard mask 678 is processed into a conductive film 671 and a conductive film 672 by etching (see FIG. 11A). Here, when the hard mask 678 is etched, a part of the upper portion of the semiconductor 662 or the insulating film 652 is etched, and a portion that does not overlap with the conductive film 671 and the conductive film 672 may be thinned. Therefore, it is preferable that the thickness of the semiconductor 662 be formed in advance in consideration of the depth to be etched.

  Next, a semiconductor 663 and an insulating film 653 are formed. After that, a resist mask is formed and processed by etching, and then the resist mask is removed (see FIG. 11B).

  Next, a conductive film 673 is formed, a resist mask is formed, the conductive film 673 is processed by etching, and then the resist mask is removed to form a gate electrode (see FIG. 11C).

  The semiconductor 663, the insulating film 653, and the conductive film 673 may be formed by a sputtering method, a CVD method (including a thermal CVD method, a MOCVD method, a PECVD method, or the like), an MBE method, a PLD method, an ALD method, or the like. In particular, a CVD method, preferably a plasma CVD method, is preferable because coverage can be improved. In order to reduce plasma damage, thermal CVD, MOCVD or ALD is preferred.

  The semiconductor 663 and the insulating film 653 may be etched after the conductive film 673 is formed. Etching may be performed using a resist mask, for example. Alternatively, the insulating film 653 and the semiconductor 663 may be etched using the formed conductive film 673 as a mask.

  Alternatively, oxygen may be introduced into the semiconductor 663 after the semiconductor 663 is formed. For example, oxygen (including at least one of oxygen radicals, oxygen atoms, and oxygen ions) is introduced into the semiconductor 663 after film formation to form a region containing excess oxygen. As a method for introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, plasma treatment, or the like can be used.

  A gas containing oxygen can be used for the oxygen introduction treatment. As the gas containing oxygen, for example, oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide, carbon monoxide, or the like can be used. Further, in the oxygen introduction treatment, a gas containing oxygen may contain a rare gas. Alternatively, hydrogen or the like may be included. For example, a mixed gas of carbon dioxide, hydrogen, and argon may be used.

  For the material that can be used for the semiconductor 663, the description of the semiconductor 663 in FIGS.

  The insulating film 653 is formed using aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. One or more insulating films can be used. The insulating film 653 may be a stack of the above materials. Note that the insulating film 653 may contain lanthanum (La), nitrogen, zirconium (Zr), or the like as an impurity.

  An example of a stacked structure of the insulating film 653 will be described. The insulating film 653 includes, for example, oxygen, nitrogen, silicon, hafnium, or the like. Specifically, it preferably contains hafnium oxide and silicon oxide or silicon oxynitride.

  Hafnium oxide has a higher dielectric constant than silicon oxide or silicon oxynitride. Therefore, since the physical film thickness can be increased with respect to the equivalent oxide film thickness, the leakage current due to the tunnel current can be reduced even when the equivalent oxide film thickness is 10 nm or less or 5 nm or less. That is, a transistor with a small off-state current can be realized.

  Next, an insulating film 654 is formed. The insulating film 654 has a function of blocking oxygen, hydrogen, water, alkali metal, alkaline earth metal, and the like. The insulating film 654 can be formed by, for example, a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, or the like), an MBE method, an ALD method, a PLD method, or the like. In particular, it is preferable to form the insulating film by a CVD method, preferably a plasma CVD method, because the coverage can be improved. In order to reduce damage caused by plasma, the thermal CVD method, the MOCVD method, or the ALD method is preferable.

  The insulating film 654 preferably has a blocking effect of oxygen, hydrogen, water, alkali metal, alkaline earth metal, or the like. As the insulating film 654, for example, a nitride insulating film can be used. Examples of the nitride insulating film include silicon nitride, silicon nitride oxide, aluminum nitride, and aluminum nitride oxide. Note that an oxide insulating film having a blocking effect of oxygen, hydrogen, water, or the like may be provided instead of the nitride insulating film. Examples of the oxide insulating film include aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, and hafnium oxynitride.

  The aluminum oxide film is preferable for application to the insulating film 654 because the aluminum oxide film has a high blocking effect of preventing both the hydrogen and moisture impurities and oxygen from permeating through the film. In addition, oxygen contained in the aluminum oxide film can be diffused into the semiconductor 660.

  Heat treatment is preferably performed after the insulating film 654 is formed. Through this heat treatment, oxygen can be supplied from the insulating film 652 and the like to the semiconductor 660, so that oxygen vacancies in the semiconductor 660 can be reduced. At this time, oxygen released from the insulating film 652 is blocked by the insulating film 656 and the insulating film 654, so that the oxygen can be effectively confined. Therefore, the amount of oxygen that can be supplied to the semiconductor 660 can be increased, and oxygen vacancies in the semiconductor 660 can be effectively reduced.

  Subsequently, an insulating film 655 is formed. The insulating film 655 can be formed by, for example, a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, or the like), an MBE method, an ALD method, a PLD method, or the like. In particular, a CVD method, preferably a plasma CVD method, is preferable because coverage can be improved. In order to reduce plasma damage, thermal CVD, MOCVD or ALD is preferred. In the case where an organic insulating material such as an organic resin is used for the insulating film 655, a coating method such as a spin coating method may be used. Further, after the insulating film 655 is formed, planarization treatment is preferably performed on the top surface thereof.

  The insulating film 655 includes aluminum oxide, aluminum nitride oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and hafnium oxide. An insulator containing one or more selected from tantalum oxide and the like can be used. The insulating film 655 can be formed using an organic resin such as a polyimide resin, a polyamide resin, an acrylic resin, a siloxane resin, an epoxy resin, or a phenol resin. The insulating film 655 may be a stack of the above materials.

<Configuration Example 2 of Transistor>
In the transistor 600 illustrated in FIGS. 8A and 8B, the semiconductor 663 and the insulating film 653 may be etched at the same time when the conductive film 673 is formed by etching. An example is shown in FIG.

  FIG. 12 illustrates the case where the semiconductor 663 and the insulating film 653 exist only under the conductive film 673 in FIG.

<Configuration Example 3 of Transistor>
In the transistor 600 illustrated in FIG. 8, the conductive film 671 and the conductive film 672 may be in contact with the side surface of the semiconductor 661 and the side surface of the semiconductor 662. An example is shown in FIG.

  FIG. 13 illustrates the case where the conductive film 671 and the conductive film 672 are in contact with the side surface of the semiconductor 661 and the side surface of the semiconductor 662 in FIG.

<Configuration Example 4 of Transistor>
In the transistor 600 illustrated in FIGS. 8A and 8B, the conductive film 671 may have a stacked structure of a conductive film 671a and a conductive film 671b. Alternatively, the conductive film 672 may have a stacked structure of a conductive film 672a and a conductive film 672b. An example is shown in FIG.

  FIG. 14 illustrates the case where the conductive film 671 has a stacked structure of conductive films 671a and 671b and the conductive film 672 has a stacked structure of conductive films 672a and 672b in FIG. 8B.

  As the conductive film 671b and the conductive film 672b, for example, a transparent conductor, an oxide semiconductor, a nitride semiconductor, or an oxynitride semiconductor may be used. Examples of the conductive film 671b and the conductive film 672b include a film containing indium, tin and oxygen, a film containing indium and zinc, a film containing indium, tungsten and zinc, a film containing tin and zinc, and a film containing zinc and gallium. A film containing zinc and aluminum, a film containing zinc and fluorine, a film containing zinc and boron, a film containing tin and antimony, a film containing tin and fluorine, or a film containing titanium and niobium may be used. Alternatively, these films may contain hydrogen, carbon, nitrogen, silicon, germanium, or argon.

  The conductive films 671b and 672b may have a property of transmitting visible light. Alternatively, the conductive film 671b and the conductive film 672b may have a property of not transmitting visible light, ultraviolet light, infrared light, or X-rays by reflection or absorption. By having such a property, a change in electrical characteristics of the transistor due to stray light may be suppressed in some cases.

  The conductive films 671b and 672b may preferably be formed using a layer that does not form a Schottky barrier with the semiconductor 662 or the like. Thus, the on-state characteristics of the transistor can be improved.

  As the conductive film 671a and the conductive film 672a, for example, boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, A conductor including one or more of silver, indium, tin, tantalum, and tungsten may be used in a single layer or a stacked layer. For example, it may be an alloy film or a compound film, and includes a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin and oxygen, titanium and nitrogen. A conductor or the like may be used.

  Note that there may be a case where it is preferable that the conductive films 671b and 672b be higher resistance than the conductive films 671a and 672a. In some cases, the conductive film 671b and the conductive film 672b each preferably have a lower resistance than the channel of the transistor. For example, the resistivity of the conductive films 671b and 672b may be 0.1 Ωcm to 100 Ωcm, 0.5 Ωcm to 50 Ωcm, or 1 Ωcm to 10 Ωcm. By setting the resistivity of the conductive films 671b and 672b in the above range, electric field concentration at the boundary between the channel and the drain can be reduced. Therefore, variation in electrical characteristics of the transistor can be reduced. In addition, the punch-through current due to the electric field generated from the drain can be reduced. Therefore, saturation characteristics can be improved even in a transistor with a short channel length. Note that in a circuit configuration in which the source and the drain are not interchanged, it may be preferable to dispose only one of the conductive films 671b and 672b (for example, the drain side).

<Structure Example 5 of Transistor>
15A and 15B are a top view and a cross-sectional view of the transistor 300. FIG. FIG. 15A is a top view, and a cross section in the direction of dashed-dotted line AB in FIG. 15A corresponds to FIG. Note that in FIGS. 15A and 15B, some elements are illustrated in an enlarged, reduced, or omitted form for clarity. In addition, the direction of the alternate long and short dash line AB may be referred to as a channel length direction.

  A transistor 300 illustrated in FIG. 15B includes a conductive film 380 functioning as a first gate, a conductive film 388 functioning as a second gate, a semiconductor 382, a conductive film 383 functioning as a source and a drain, and a conductive film. A film 384, an insulating film 381, an insulating film 385, an insulating film 386, and an insulating film 387 are included.

  The conductive film 380 is provided over the insulating surface. The conductive film 380 and the semiconductor 382 overlap with each other with the insulating film 381 interposed therebetween. The conductive film 388 and the semiconductor 382 overlap with each other with the insulating film 385, the insulating film 386, and the insulating film 387 interposed therebetween. The conductive films 383 and 384 are connected to the semiconductor 382.

  For the details of the conductive films 380 and 388, the description of the conductive films 673 and 674 illustrated in FIGS.

  The conductive film 380 and the conductive film 388 may be supplied with different potentials or may be supplied with the same potential at the same time. In the transistor 300, the threshold value can be stabilized by providing the conductive film 388 functioning as the second gate electrode. Note that the conductive film 388 may be omitted depending on circumstances.

  For the details of the semiconductor 382, the description of the semiconductor 662 illustrated in FIG. Further, the semiconductor 382 may be a single layer or a stacked layer of a plurality of semiconductor layers.

  For the details of the conductive films 383 and 384, the description of the conductive films 671 and 672 illustrated in FIGS.

  For the details of the insulating film 381, the description of the insulating film 653 illustrated in FIGS.

  Note that FIG. 15B illustrates the case where the insulating films 385 to 387 stacked in this order are provided over the semiconductor 382, the conductive film 383, and the conductive film 384; The insulating film provided over the film 383 and the conductive film 384 may be a single layer or a stack of a plurality of insulating films.

  In the case where an oxide semiconductor is used for the semiconductor 382, the insulating film 386 is an insulating film that contains oxygen in a stoichiometric composition or more and has a function of supplying part of the oxygen to the semiconductor 382 by heating. It is desirable. However, in the case where the insulating film 386 is directly provided over the semiconductor 382 and the semiconductor 382 is damaged when the insulating film 386 is formed, the insulating film 385 is formed of the semiconductor 382 and the insulating film 386 as illustrated in FIG. It is good to provide in between. The insulating film 385 is desirably an insulating film that has less damage to the semiconductor 382 at the time of formation than the insulating film 386 and has a function of transmitting oxygen. Note that the insulating film 385 is not necessarily provided as long as the insulating film 386 can be formed directly over the semiconductor 382 while suppressing damage to the semiconductor 382.

  For example, the insulating film 386 and the insulating film 385 are preferably formed using a material containing silicon oxide or silicon oxynitride. Alternatively, a metal oxide such as aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, or hafnium oxynitride can be used.

  The insulating film 387 desirably has a blocking effect that prevents diffusion of oxygen, hydrogen, and water. Alternatively, the insulating film 387 desirably has a blocking effect that prevents diffusion of hydrogen and water.

  The insulating film exhibits a higher blocking effect as it is denser and denser, and as it is chemically stable with fewer dangling bonds. Examples of the insulating film that exhibits a blocking effect to prevent diffusion of oxygen, hydrogen, and water include aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, and hafnium oxynitride. Can be formed. For example, silicon nitride, silicon nitride oxide, or the like can be used as the insulating film exhibiting a blocking effect for preventing diffusion of hydrogen and water.

  In the case where the insulating film 387 has a blocking effect for preventing diffusion of water, hydrogen, and the like, it is possible to prevent the resin in the panel and impurities such as water and hydrogen existing outside the panel from entering the semiconductor 382. In the case where an oxide semiconductor is used for the semiconductor 382, part of water or hydrogen that has entered the oxide semiconductor becomes an electron donor (donor); therefore, the insulating film 387 having the above blocking effect is used, whereby the threshold value of the transistor 300 is obtained. The voltage can be prevented from shifting due to the generation of donors.

  In the case where an oxide semiconductor is used for the semiconductor 382, the insulating film 387 has a blocking effect of preventing oxygen diffusion, so that oxygen from the oxide semiconductor can be prevented from diffusing to the outside. Thus, oxygen vacancies serving as donors in the oxide semiconductor are reduced, so that the threshold voltage of the transistor 300 can be prevented from being shifted due to generation of donors.

  The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 4)
In this embodiment, an example of a memory device to which the transistor M0 described in Embodiments 1 and 2 can be applied will be described.

  The semiconductor device illustrated in FIG. 16A includes a transistor M1, a transistor M0, and a capacitor 3400.

  The transistor M0 is preferably a transistor including an oxide semiconductor in a channel region. Since the transistor M0 has a small off-state current, stored data can be held for a long time by using the transistor M0. In other words, since it is possible to obtain a semiconductor memory device that does not require a refresh operation or has a very low frequency of the refresh operation, power consumption can be sufficiently reduced.

  In FIG. 16A, the first wiring 3001 is electrically connected to the source electrode of the transistor M1, and the second wiring 3002 is electrically connected to the drain electrode of the transistor M1. The third wiring 3003 is electrically connected to one of the source electrode and the drain electrode of the transistor M0, and the fourth wiring 3004 is electrically connected to the gate electrode of the transistor M0. The other of the gate electrode of the transistor M1 and the source and drain electrodes of the transistor M0 is electrically connected to the first terminal of the capacitor 3400, and the fifth wiring 3005 is a second terminal of the capacitor 3400. Is electrically connected.

  In the semiconductor device illustrated in FIG. 16A, data can be written, held, and read as follows by utilizing the feature that the potential of the gate electrode of the transistor M1 can be held.

  Data writing and holding will be described. First, the potential of the fourth wiring 3004 is set to a potential at which the transistor M0 is turned on, so that the transistor M0 is turned on. Accordingly, the potential of the third wiring 3003 is supplied to the gate electrode of the transistor M1 and the capacitor 3400. That is, a predetermined charge is given to the gate of the transistor M1 (writing). Here, it is assumed that one of two charges (hereinafter, referred to as low level charge and high level charge) that gives two different potential levels is given. After that, the potential of the fourth wiring 3004 is set to a potential at which the transistor M0 is turned off and the transistor M0 is turned off, so that the charge given to the gate of the transistor M1 is held (held).

  Since the off-state current of the transistor M0 is extremely small, the charge of the gate of the transistor M1 is held for a long time.

Next, data reading will be described. When an appropriate potential (read potential) is applied to the fifth wiring 3005 in a state where a predetermined potential (constant potential) is applied to the first wiring 3001, according to the amount of charge held at the gate of the transistor M1, The second wiring 3002 has different potentials. In general, when the transistor M1 is an n-channel type, the apparent threshold value _{Vth_H} when a high level charge is applied to the gate electrode of the transistor M1 is a low level charge applied to the gate electrode of the transistor M1. This is because it becomes lower than the apparent threshold value V _{th_L} of the case. Here, the apparent threshold voltage means a potential of the fifth wiring 3005 necessary for turning on the transistor M1. Therefore, by _setting the potential of the fifth wiring 3005 to a potential V ₀ between V _{th_H} and V _{th_L} , the charge given to the gate of the transistor M1 can be determined. For example, in the case where a high-level charge is applied in writing, the transistor M1 is turned “on” when the potential of the fifth wiring 3005 becomes V ₀ (> V _{th_H} ). When the low-level charge is applied, the transistor M1 remains in the “off state” even when the potential of the fifth wiring 3005 becomes V ₀ (<V _{th_L} ). Therefore, the stored data can be read by determining the potential of the second wiring 3002.

Note that in the case of using memory cells arranged in an array, it is necessary to read only data of desired memory cells. In the case where data is not read out in this manner, the fifth wiring 3005 may be _{supplied with a} potential at which the transistor M1 is turned off regardless of the state of the gate, that is, a potential lower than _{Vth_H} . _{Alternatively} , the fifth wiring 3005 may be _{supplied with a} potential at which the transistor M1 is turned on regardless of the gate state, that is, a potential higher than V _{th_L} .

  The semiconductor device illustrated in FIG. 16B is different from FIG. 16A in that the transistor M1 is not provided. In this case, data can be written and held by the same operation as described above.

  Next, reading of data from the semiconductor device illustrated in FIG. When the transistor M0 is turned on, the third wiring 3003 in a floating state and the capacitor 3400 are brought into conduction, and charge is redistributed between the third wiring 3003 and the capacitor 3400. As a result, the potential of the third wiring 3003 changes. The amount of change in potential of the third wiring 3003 varies depending on the potential of the first terminal of the capacitor 3400 (or charge accumulated in the capacitor 3400).

  For example, the potential of the first terminal of the capacitor 3400 is V, the capacitance of the capacitor 3400 is C, the capacitance component of the third wiring 3003 is CB, and the potential of the third wiring 3003 before charge is redistributed Is VB0, the potential of the third wiring 3003 after the charge is redistributed is (CB × VB0 + C × V) / (CB + C). Therefore, when the potential of the first terminal of the capacitor 3400 assumes two states of V1 and V0 (V1> V0) as the state of the memory cell, the third wiring 3003 in the case where the potential V1 is held. The potential (= (CB × VB0 + C × V1) / (CB + C)) is higher than the potential of the third wiring 3003 when the potential V0 is held (= CB × VB0 + C × V0) / (CB + C)). I understand that.

  Then, data can be read by comparing the potential of the third wiring 3003 with a predetermined potential.

  In the semiconductor device described in this embodiment, stored data can be held for an extremely long time by using a transistor with an extremely small off-state current that uses an oxide semiconductor for a channel formation region. That is, the refresh operation is not necessary or the frequency of the refresh operation can be extremely low, so that power consumption can be sufficiently reduced. In addition, stored data can be held for a long time even when power is not supplied (note that a potential is preferably fixed).

  Further, in the semiconductor device described in this embodiment, high voltage is not required for writing data and there is no problem of deterioration of elements. For example, unlike the conventional nonvolatile memory, it is not necessary to inject electrons into the floating gate or extract electrons from the floating gate, so that there is no problem of deterioration of the gate insulating film. That is, in the semiconductor device according to the disclosed invention, the number of rewritable times that is a problem in the conventional nonvolatile memory is not limited, and the reliability is dramatically improved. Further, data is written depending on the on / off state of the transistor, so that high-speed operation can be easily realized.

  The storage device described in this embodiment can be applied to, for example, a CPU (Central Processing Unit), a DSP (Digital Signal Processor), a custom LSI, a PLD (Programmable Logic Device), or an RF (Radio Frequency) device. is there.

  The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 5)
In this embodiment, a CPU (central processing unit) including the storage device described in Embodiment 4 will be described.

  FIG. 17 is a block diagram illustrating a configuration example of a CPU using at least part of the transistor described in the above embodiment.

  17 includes an ALU 1191 (arithmetic logic unit (ALU)), an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, a register controller 1197, and a bus interface 1198. (Bus I / F), a rewritable ROM 1199, and a ROM interface 1189 (ROM I / F). As the substrate 1190, a semiconductor substrate, an SOI substrate, a glass substrate, or the like is used. The ROM 1199 and the ROM interface 1189 may be provided in separate chips. Needless to say, the CPU illustrated in FIG. 17 is just an example in which the configuration is simplified, and an actual CPU may have various configurations depending on the application. For example, the configuration including the CPU or the arithmetic circuit illustrated in FIG. 17 may be a single core, and a plurality of the cores may be included so that each core operates in parallel. Further, the number of bits that the CPU can handle with the internal arithmetic circuit or the data bus can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, or the like.

  Instructions input to the CPU via the bus interface 1198 are input to the instruction decoder 1193, decoded, and then input to the ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195.

  The ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 generates a signal for controlling the operation of the ALU 1191. The interrupt controller 1194 determines and processes an interrupt request from an external input / output device or a peripheral circuit from the priority or mask state during execution of the CPU program. The register controller 1197 generates an address of the register 1196, and reads and writes the register 1196 according to the state of the CPU.

  In addition, the timing controller 1195 generates a signal for controlling the operation timing of the ALU 1191, the ALU controller 1192, the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197. For example, the timing controller 1195 includes an internal clock generation unit that generates an internal clock signal CLK2 based on the reference clock signal CLK1, and supplies the internal clock signal CLK2 to the various circuits.

  In the CPU illustrated in FIG. 17, a memory cell is provided in the register 1196. As the memory cell of the register 1196, the transistor described in Embodiment 1 or the memory device described in Embodiment 2 can be used.

  In the CPU shown in FIG. 17, the register controller 1197 selects a holding operation in the register 1196 in accordance with an instruction from the ALU 1191. That is, whether to hold data by a flip-flop or hold data by a capacitor in a memory cell included in the register 1196 is selected. When data retention by the flip-flop is selected, the power supply voltage is supplied to the memory cell in the register 1196. When holding of data in the capacitor is selected, data is rewritten to the capacitor and supply of power supply voltage to the memory cells in the register 1196 can be stopped.

  The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 6)
A semiconductor device according to one embodiment of the present invention includes a display device, a personal computer, and an image reproducing device including a recording medium (typically a display that can reproduce a recording medium such as a DVD: Digital Versatile Disc and display the image) Device). In addition, as an electronic device in which the semiconductor device according to one embodiment of the present invention can be used, a mobile phone, a game machine including a portable type, a portable data terminal, an electronic book, a video camera, a camera such as a digital still camera, or a goggle type Display (head-mounted display), navigation system, sound playback device (car audio, digital audio player, etc.), copier, facsimile, printer, printer multifunction device, automatic teller machine (ATM), vending machine, etc. . Specific examples of these electronic devices are shown in FIGS.

  FIG. 18A illustrates a portable game machine, which includes a housing 901, a housing 902, a display portion 903, a display portion 904, a microphone 905, speakers 906, operation keys 907, a stylus 908, and the like. Note that although the portable game machine illustrated in FIG. 18A includes the two display portions 903 and 904, the number of display portions included in the portable game device is not limited thereto.

  FIG. 18B illustrates a mobile phone, which includes a housing 911, a display portion 916, operation buttons 914, an external connection port 913, a speaker 917, a microphone 912, and the like. Information can be input to the cellular phone illustrated in FIG. 18B by touching the display portion 916 with a finger or the like. Any operation such as making a call or inputting a character can be performed by touching the display portion 916 with a finger or the like. Further, the operation of the operation button 914 can switch the power ON / OFF operation and the type of image displayed on the display unit 916. For example, the mail creation screen can be switched to the main menu screen.

  FIG. 18C illustrates a laptop personal computer, which includes a housing 921, a display portion 922, a keyboard 923, a pointing device 924, and the like.

  FIG. 18D illustrates an electric refrigerator-freezer, which includes a housing 931, a refrigerator door 932, a refrigerator door 933, and the like.

  FIG. 18E illustrates a video camera, which includes a first housing 941, a second housing 942, a display portion 943, operation keys 944, a lens 945, a connection portion 946, and the like. The operation key 944 and the lens 945 are provided in the first housing 941, and the display portion 943 is provided in the second housing 942. The first housing 941 and the second housing 942 are connected by a connection portion 946, and the angle between the first housing 941 and the second housing 942 can be changed by the connection portion 946. is there. The video on the display portion 943 may be switched according to the angle between the first housing 941 and the second housing 942 in the connection portion 946.

  FIG. 18F illustrates an ordinary automobile, which includes a vehicle body 951, wheels 952, a dashboard 953, lights 954, and the like.

  Note that this embodiment can be combined with any of the other embodiments or examples in this specification as appropriate.

(Embodiment 7)
In this embodiment, an example of use of an RF device that can include the semiconductor device of one embodiment of the present invention will be described with reference to FIGS. Applications of RF devices are wide-ranging. For example, banknotes, coins, securities, bearer bonds, certificates (driver's license, resident's card, etc., see FIG. 19A), recording media (DVD, video tape, etc.) 19B), packaging containers (wrapping paper, bottles, etc., see FIG. 19C), vehicles (bicycles etc., see FIG. 19D), personal items (bags, glasses, etc.) , Articles such as foods, plants, animals, human bodies, clothing, daily necessities, medical products including drugs and drugs, or electronic devices (liquid crystal display devices, EL display devices, television devices, or mobile phones), Alternatively, it can be used by being provided on a tag attached to each article (see FIGS. 19E and 19F) or the like.

  The RF device 4000 according to one embodiment of the present invention is fixed to an article by being attached to a surface of a printed board or embedded therein. For example, a book is embedded in paper, and a package made of an organic resin is embedded in the organic resin and fixed to each article. Since the RF device 4000 according to one embodiment of the present invention achieves small size, thinness, and light weight, design properties of the article itself are not impaired even after the RF device 4000 is fixed to the article. In addition, by providing the RF device 4000 according to one embodiment of the present invention to bills, coins, securities, bearer bonds, or certificates, etc., an authentication function can be provided, and if this authentication function is utilized, Counterfeiting can be prevented. In addition, by attaching the RF device according to one embodiment of the present invention to packaging containers, recording media, personal items, foods, clothing, daily necessities, or electronic devices, the efficiency of inspection systems and the like can be improved. Can be planned. Even in the case of vehicles, the security against theft or the like can be improved by attaching the RF device according to one embodiment of the present invention.

  As described above, by using the RF device according to one embodiment of the present invention for each application described in this embodiment, operating power including writing and reading of information can be reduced, so that the maximum communication distance is increased. Is possible. In addition, since the information can be held for a very long period even when the power is cut off, it can be suitably used for applications where the frequency of writing and reading is low.

  Next, an example of using a display device that can include the semiconductor device of one embodiment of the present invention is described. As an example, the display device includes a pixel. A pixel has a transistor and a display element, for example. Alternatively, the display device includes a driver circuit that drives pixels. The drive circuit includes, for example, a transistor. For example, the transistors described in other embodiments can be used as these transistors.

  For example, in this specification and the like, a display element, a display device that is a device including a display element, a light-emitting element, and a light-emitting device that is a device including a light-emitting element have various forms or have various elements. I can do it. As an example of a display element, a display device, a light emitting element, or a light emitting device, an EL (electroluminescence) element (an EL element including an organic substance and an inorganic substance, an organic EL element, an inorganic EL element), an LED (white LED, red LED, green LED) , Blue LED, etc.), transistor (transistor that emits light in response to current), electron-emitting device, liquid crystal device, electronic ink, electrophoretic device, grating light valve (GLV), plasma display (PDP), MEMS (micro electro Display device using mechanical system), digital micromirror device (DMD), DMS (digital micro shutter), MIRASOL (registered trademark), IMOD (interference modulation) device, shutter-type MEMS display device, MEMS display element of the interference type, electrowetting element, a piezoelectric ceramic display, or a carbon nanotube, etc., by an electric magnetic action, contrast, brightness, reflectance, etc. transmittance those having a display medium changes. An example of a display device using an EL element is an EL display. As an example of a display device using an electron-emitting device, there is a field emission display (FED), a SED type flat display (SED: Surface-Conduction Electron-Emitter Display), or the like. As an example of a display device using a liquid crystal element, there is a liquid crystal display (a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, a direct view liquid crystal display, a projection liquid crystal display) and the like. An example of a display device using electronic ink, electronic powder fluid, or an electrophoretic element is electronic paper. Note that in the case of realizing a transflective liquid crystal display or a reflective liquid crystal display, part or all of the pixel electrode may have a function as a reflective electrode. For example, part or all of the pixel electrode may have aluminum, silver, or the like. Further, in that case, a memory circuit such as an SRAM can be provided under the reflective electrode. Thereby, power consumption can be further reduced.

  Note that this embodiment can be combined with any of the other embodiments and examples in this specification as appropriate.

(Embodiment 8)
In this embodiment, a crystal structure of an oxide semiconductor that can be applied to the transistor including the oxide semiconductor described in the above embodiment will be described.

  In this specification, “parallel” refers to a state in which two straight lines are arranged at an angle of −10 ° to 10 °. Therefore, the case of −5 ° to 5 ° is also included. Further, “substantially parallel” means a state in which two straight lines are arranged at an angle of −30 ° to 30 °. “Vertical” refers to a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included. Further, “substantially vertical” means a state in which two straight lines are arranged at an angle of 60 ° to 120 °.

  In this specification, when a crystal is trigonal or rhombohedral, it is represented as a hexagonal system.

<Structure of oxide semiconductor>
Hereinafter, the structure of the oxide semiconductor is described.

  An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor. As the non-single-crystal oxide semiconductor, a CAAC-OS (C Axis Crystallized Oxide Semiconductor), a polycrystalline oxide semiconductor, an nc-OS (Nanocrystalline Oxide Semiconductor), a pseudo-amorphous oxide semiconductor (a-liquid oxide OS) like Oxide Semiconductor) and amorphous oxide semiconductor.

  From another viewpoint, oxide semiconductors are classified into amorphous oxide semiconductors and other crystalline oxide semiconductors. Examples of a crystalline oxide semiconductor include a single crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, and an nc-OS.

  As the definition of the amorphous structure, it is generally known that it is not fixed in a metastable state, isotropic and does not have a heterogeneous structure, and the like. Moreover, it can be paraphrased as a structure having a flexible bond angle and short-range order, but not long-range order.

  In other words, an intrinsically stable oxide semiconductor cannot be referred to as a complete amorphous oxide semiconductor. In addition, an oxide semiconductor that is not isotropic (eg, has a periodic structure in a minute region) cannot be referred to as a completely amorphous oxide semiconductor. However, the a-like OS has a periodic structure in a minute region, but has a void and an unstable structure. Therefore, it can be said that it is close to an amorphous oxide semiconductor in terms of physical properties.

<CAAC-OS>
First, the CAAC-OS will be described.

  The CAAC-OS is one of oxide semiconductors having a plurality of c-axis aligned crystal parts (also referred to as pellets).

  A plurality of pellets can be confirmed by observing a composite analysis image (also referred to as a high-resolution TEM image) of a bright-field image and a diffraction pattern of a CAAC-OS with a transmission electron microscope (TEM: Transmission Electron Microscope). . On the other hand, in the high-resolution TEM image, the boundary between pellets, that is, the crystal grain boundary (also referred to as grain boundary) cannot be clearly confirmed. Therefore, it can be said that the CAAC-OS does not easily lower the electron mobility due to the crystal grain boundary.

  Hereinafter, a CAAC-OS observed with a TEM will be described. FIG. 20A shows a high-resolution TEM image of a cross section of the CAAC-OS observed from a direction substantially parallel to the sample surface. For observation of the high-resolution TEM image, a spherical aberration correction function was used. A high-resolution TEM image using the spherical aberration correction function is particularly referred to as a Cs-corrected high-resolution TEM image. Acquisition of a Cs-corrected high-resolution TEM image can be performed by, for example, an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd.

  FIG. 20B shows a Cs-corrected high-resolution TEM image obtained by enlarging the region (1) in FIG. FIG. 20B shows that metal atoms are arranged in layers in the pellet. The arrangement of each layer of metal atoms reflects unevenness on a surface (also referred to as a formation surface) or an upper surface where a CAAC-OS film is formed, and is parallel to the formation surface or upper surface of the CAAC-OS.

  As shown in FIG. 20B, the CAAC-OS has a characteristic atomic arrangement. FIG. 20C shows a characteristic atomic arrangement with auxiliary lines. 20B and 20C, it can be seen that the size of one pellet is about 1 nm to 3 nm, and the size of the gap generated by the inclination between the pellet and the pellet is about 0.8 nm. Therefore, the pellet can also be referred to as a nanocrystal (nc). In addition, the CAAC-OS can be referred to as an oxide semiconductor including CANC (C-Axis aligned nanocrystals).

  Here, based on the Cs-corrected high-resolution TEM image, the arrangement of the CAAC-OS pellets 5100 on the substrate 5120 is schematically shown to be a structure in which bricks or blocks are stacked (FIG. 20D). reference.). A portion where an inclination is generated between the pellets observed in FIG. 20C corresponds to a region 5161 illustrated in FIG.

  FIG. 21A shows a Cs-corrected high-resolution TEM image of the plane of the CAAC-OS observed from a direction substantially perpendicular to the sample surface. The Cs-corrected high-resolution TEM images obtained by enlarging the region (1), the region (2), and the region (3) in FIG. 21A are shown in FIGS. Show. From FIG. 21B, FIG. 21C, and FIG. 21D, it can be confirmed that the metal atoms are arranged in a triangular shape, a quadrangular shape, or a hexagonal shape in the pellet. However, there is no regularity in the arrangement of metal atoms between different pellets.

Next, the CAAC-OS analyzed by X-ray diffraction (XRD: X-Ray Diffraction) will be described. For example, when structural analysis by an out-of-plane method is performed on a CAAC-OS including an InGaZnO ₄ crystal, a peak appears when the diffraction angle (2θ) is around 31 ° as illustrated in FIG. There is. Since this peak is attributed to the (009) plane of the InGaZnO ₄ crystal, the CAAC-OS crystal has c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the formation surface or the top surface. It can be confirmed.

  Note that in structural analysis of the CAAC-OS by an out-of-plane method, in addition to a peak where 2θ is around 31 °, a peak may also appear when 2θ is around 36 °. A peak at 2θ of around 36 ° indicates that a crystal having no c-axis alignment is included in part of the CAAC-OS. In a more preferable CAAC-OS, in the structural analysis by the out-of-plane method, 2θ has a peak in the vicinity of 31 °, and 2θ has no peak in the vicinity of 36 °.

On the other hand, when structural analysis is performed on the CAAC-OS by an in-plane method in which X-rays are incident from a direction substantially perpendicular to the c-axis, a peak appears at 2θ of around 56 °. This peak is attributed to the (110) plane of the InGaZnO ₄ crystal. In the case of CAAC-OS, even if 2θ is fixed at around 56 ° and analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis), FIG. A clear peak does not appear as shown. On the other hand, in the case of a single crystal oxide semiconductor of InGaZnO ₄ , when 2φ is fixed at around 56 ° and φ scan is performed, it belongs to a crystal plane equivalent to the (110) plane as shown in FIG. 6 peaks are observed. Therefore, structural analysis using XRD can confirm that the CAAC-OS has irregular orientations in the a-axis and the b-axis.

Next, a CAAC-OS analyzed by electron diffraction will be described. For example, when an electron beam with a probe diameter of 300 nm is incident on a CAAC-OS having an InGaZnO ₄ crystal in parallel with the sample surface, a diffraction pattern (a limited-field transmission electron diffraction pattern as shown in FIG. 23A) is obtained. Say) may appear. This diffraction pattern includes spots caused by the (009) plane of the InGaZnO ₄ crystal. Therefore, electron diffraction shows that the pellets included in the CAAC-OS have c-axis alignment, and the c-axis is in a direction substantially perpendicular to the formation surface or the top surface. On the other hand, FIG. 23B shows a diffraction pattern obtained when an electron beam with a probe diameter of 300 nm is incident on the same sample in a direction perpendicular to the sample surface. A ring-shaped diffraction pattern is confirmed from FIG. Therefore, electron diffraction shows that the a-axis and the b-axis of the pellet included in the CAAC-OS have no orientation. Note that the first ring in FIG. 23B is considered to originate from the (010) plane and the (100) plane of InGaZnO ₄ crystal. Further, the second ring in FIG. 23B is considered to be due to the (110) plane or the like.

  As described above, the CAAC-OS is an oxide semiconductor with high crystallinity. Since the crystallinity of an oxide semiconductor may be deteriorated by entry of impurities, generation of defects, or the like, in reverse, the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies).

  Note that the impurity means an element other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, or a transition metal element. For example, an element such as silicon, which has a stronger bonding force with oxygen than a metal element included in an oxide semiconductor, disturbs the atomic arrangement of the oxide semiconductor by depriving the oxide semiconductor of oxygen, thereby reducing crystallinity. It becomes a factor. In addition, heavy metals such as iron and nickel, argon, carbon dioxide, and the like have large atomic radii (or molecular radii), which disturbs the atomic arrangement of the oxide semiconductor and decreases crystallinity.

  In the case where an oxide semiconductor has impurities or defects, characteristics may fluctuate due to light, heat, or the like. For example, an impurity contained in the oxide semiconductor might serve as a carrier trap or a carrier generation source. In addition, oxygen vacancies in the oxide semiconductor may serve as carrier traps or may serve as carrier generation sources by capturing hydrogen.

A CAAC-OS with few impurities and oxygen vacancies is an oxide semiconductor with low carrier density. Specifically, the carrier density is less than 8 × 10 ¹¹ / cm ³ , preferably less than 1 × 10 ¹¹ / cm ³ , more preferably less than 1 × 10 ¹⁰ / cm ³ , and 1 × 10 ⁻⁹ / cm ^3. This can be done. Such an oxide semiconductor is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. The CAAC-OS has a low impurity concentration and a low density of defect states. That is, it can be said that the oxide semiconductor has stable characteristics.

<Nc-OS>
Next, the nc-OS will be described.

  The nc-OS has a region where a crystal part can be confirmed and a region where a clear crystal part cannot be confirmed in a high-resolution TEM image. In many cases, a crystal part included in the nc-OS has a size of 1 nm to 10 nm, or 1 nm to 3 nm. Note that an oxide semiconductor in which the size of a crystal part is greater than 10 nm and less than or equal to 100 nm is sometimes referred to as a microcrystalline oxide semiconductor. For example, the nc-OS may not be able to clearly confirm a crystal grain boundary in a high-resolution TEM image. Note that the nanocrystal may have the same origin as the pellet in the CAAC-OS. Therefore, the crystal part of nc-OS is sometimes referred to as a pellet below.

  The nc-OS has periodicity in atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In addition, the nc-OS has no regularity in crystal orientation between different pellets. Therefore, orientation is not seen in the whole film. Therefore, the nc-OS may not be distinguished from an a-like OS or an amorphous oxide semiconductor depending on an analysis method. For example, when an X-ray having a diameter larger than that of the pellet is used for nc-OS, a peak indicating a crystal plane is not detected in the analysis by the out-of-plane method. Further, when electron diffraction using an electron beam having a probe diameter (for example, 50 nm or more) larger than that of the pellet is performed on the nc-OS, a diffraction pattern such as a halo pattern is observed. On the other hand, when nanobeam electron diffraction is performed on the nc-OS using an electron beam having a probe diameter that is close to the pellet size or smaller than the pellet size, spots are observed. Further, when nanobeam electron diffraction is performed on the nc-OS, a region with high luminance may be observed like a circle (in a ring shape). Furthermore, a plurality of spots may be observed in the ring-shaped region.

  Thus, since the crystal orientation does not have regularity between pellets (nanocrystals), nc-OS has an oxide semiconductor having RANC (Random Aligned Nanocrystals) or NANC (Non-Aligned nanocrystals). It can also be called an oxide semiconductor.

  The nc-OS is an oxide semiconductor that has higher regularity than an amorphous oxide semiconductor. Therefore, the nc-OS has a lower density of defect states than an a-like OS or an amorphous oxide semiconductor. Note that the nc-OS does not have regularity in crystal orientation between different pellets. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.

<A-like OS>
The a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor.

  In the a-like OS, a void (also referred to as a void) may be observed in a high-resolution TEM image. Moreover, in a high-resolution TEM image, it has the area | region which can confirm a crystal part clearly, and the area | region which cannot confirm a crystal part.

  Since it has a void, the a-like OS has an unstable structure. Hereinafter, in order to show that the a-like OS has an unstable structure as compared with the CAAC-OS and the nc-OS, changes in the structure due to electron irradiation are shown.

  As samples for electron irradiation, a-like OS (referred to as sample A), nc-OS (referred to as sample B), and CAAC-OS (referred to as sample C) are prepared. Each sample is an In—Ga—Zn oxide.

  First, a high-resolution cross-sectional TEM image of each sample is acquired. It can be seen from the high-resolution cross-sectional TEM image that each sample has a crystal part.

The determination of which part is regarded as one crystal part may be performed as follows. For example, the unit cell of an InGaZnO ₄ crystal has a structure in which three In—O layers and six Ga—Zn—O layers have a total of nine layers stacked in the c-axis direction. Are known. The spacing between these adjacent layers is about the same as the lattice spacing (also referred to as d value) of the (009) plane, and the value is determined to be 0.29 nm from crystal structure analysis. Therefore, a portion where the interval between lattice fringes is 0.28 nm or more and 0.30 nm or less can be regarded as a crystal part of InGaZnO ₄ . Note that the lattice fringes correspond to the ab plane of the InGaZnO ₄ crystal.

FIG. 24 is an example in which the average size of the crystal parts (from 22 to 45) of each sample was examined. However, the length of the lattice fringes described above is the size of the crystal part. From FIG. 24, it can be seen that in the a-like OS, the crystal part becomes larger according to the cumulative dose of electrons. Specifically, as shown by (1) in FIG. 24, the crystal portion (also referred to as initial nucleus) which was about 1.2 nm in the initial stage of observation by TEM has a cumulative irradiation dose of 4.2. It can be seen that the film grows to a size of about 2.6 nm at × 10 ⁸ e ⁻ / nm ² . On the other hand, in the nc-OS and the CAAC-OS, there is no change in the size of the crystal part in the range of the cumulative electron dose from the start of electron irradiation to 4.2 × 10 ⁸ e ⁻ / nm ^2. I understand. Specifically, as indicated by (2) and (3) in FIG. 24, the crystal part sizes of the nc-OS and the CAAC-OS are about 1.4 nm, respectively, regardless of the cumulative electron dose. And about 2.1 nm.

  As described above, in the a-like OS, a crystal part may be grown by electron irradiation. On the other hand, in the nc-OS and the CAAC-OS, the crystal part is hardly grown by electron irradiation. That is, it can be seen that the a-like OS has an unstable structure compared to the nc-OS and the CAAC-OS.

  In addition, since it has a void, the a-like OS has a lower density than the nc-OS and the CAAC-OS. Specifically, the density of the a-like OS is 78.6% or more and less than 92.3% of the density of the single crystal having the same composition. Further, the density of the nc-OS and the density of the CAAC-OS are 92.3% or more and less than 100% of the density of the single crystal having the same composition. An oxide semiconductor that is less than 78% of the density of a single crystal is difficult to form.

For example, in an oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of single crystal InGaZnO ₄ having a rhombohedral structure is 6.357 g / cm ³ . Thus, for example, in an oxide semiconductor that satisfies In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of a-like OS is 5.0 g / cm ³ or more and less than 5.9 g / cm ^3. . For example, in the oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of the nc-OS and the density of the CAAC-OS is 5.9 g / cm ³ or more and 6.3 g / less than cm ³ .

  Note that there may be no single crystal having the same composition. In that case, the density corresponding to the single crystal in a desired composition can be estimated by combining single crystals having different compositions at an arbitrary ratio. What is necessary is just to estimate the density corresponding to the single crystal of a desired composition using a weighted average with respect to the ratio which combines the single crystal from which a composition differs. However, the density is preferably estimated by combining as few kinds of single crystals as possible.

  As described above, oxide semiconductors have various structures and various properties. Note that the oxide semiconductor may be a stacked film including two or more of an amorphous oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS, for example.

  The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

  In this example, data retention characteristics of a first transistor using single crystal silicon as a semiconductor film, a second transistor using an oxide semiconductor as a semiconductor film, and a semiconductor device having a capacitor were evaluated.

  First, an evaluation circuit for a semiconductor device will be described.

<Configuration of evaluation circuit>
An evaluation circuit having the same configuration as that shown in FIG. 5 was used. The first transistor corresponds to the transistor M1 and the transistor M2, the second transistor corresponds to the transistor M0, and the capacitor corresponds to the capacitor Cs. The transistors M1 and M2 are p-channel transistors.

  Design values of the channel length L and the channel width W of the transistors in the evaluation circuit are as follows. The L / W of the transistor M0 is 0.8 μm / 0.8 μm, the L / W of the transistor M1 is 0.35 μm / 2.2 μm, and the L / W of the transistor M2 is 0.35 μm / 2.2 μm.

<Device structure>
FIG. 25 shows a device structure of the evaluation circuit. FIG. 25 is not a cross-sectional view of the evaluation circuit cut along a specific line, but a cross-sectional view that facilitates understanding of the layer structure, connection structure, and the like of the evaluation circuit.

  The transistors M1 and M2 are planar types and are manufactured on an SOI type semiconductor substrate. The substrate 500 is single crystal silicon, and the insulating film 501 is a silicon oxide film. In one single crystal silicon layer 520, channel regions, source regions, and drain regions of the transistors M1 and M2 are formed.

  The transistor M0 and the capacitor Cs are stacked on the transistor M1 and the transistor M2. The evaluation circuit includes the insulating films 502 to 511 and seven wiring layers. As shown in FIG. 5, the transistor M0, the transistor M1, the transistor M2, and the capacitor Cs are wired by the conductive layers formed in the first to seventh wiring layers.

  Conductive layers 531_1 to 531_2 are formed in the first wiring layer. Conductive layers 532_1 to 532_4 are formed in the second wiring layer. Conductive layers 533_1 to 533_5 are formed in the third wiring layer. Conductive layers 534_1 to 534_2 are formed in the fourth wiring layer. Conductive layers 535_1 to 535_2 are formed in the fifth wiring layer. Conductive layers 536_1 to 536_7 are formed in the sixth wiring layer. Conductive layers 537_1 to 537_8 are formed in the seventh wiring layer. The conductive layers (537_1, _3, _4, _5, _7, and _8) each include a portion to be a terminal (SL, RWL, BL, WWL, a capacitor element terminal, VBG). Note that the conductive layer 537_4 and the conductive layer 537_6 are electrically connected.

  The transistor M0 has a structure similar to that of the transistor 600 illustrated in FIG. 8, and has a s-channel structure. The semiconductor of the transistor M0 includes an oxide semiconductor layer 540_1 to an oxide semiconductor layer 540_3. The oxide semiconductor layers 540_1 to 540_3 each include an In—Ga—Zn oxide formed by a sputtering method including an In—Ga—Zn oxide. The atomic ratio (In: Ga: Zn) of the sputtering target is 1: 3: 4 for the oxide semiconductor layer 540_1, 1: 1: 1 for the oxide semiconductor layer 540_2, and 1 for the oxide semiconductor layer 540_3. : 3: 2.

  The capacitor Cs is an MIM type and includes a conductive layer 535_2, an oxide semiconductor layer 540_3, an insulating film 507, and a conductive layer 534_2. The conductive layer 535_2 is included in the node FN.

  The conductive layers 534_1 and 534_2 are each formed of a stack of titanium nitride with a thickness of 10 nm and tungsten with a thickness of 30 nm. The conductive layers 535_1 and 535_2 are made of tungsten with a thickness of 30 nm. The conductive layer 535_2 is in contact with a conductor of a sixth wiring layer (not shown). The conductive layer 537_2 is in contact with the conductor. With such a wiring structure, the capacitive element Cs is electrically connected to the gate electrode of the transistor M1.

  The insulating film 507 is made of silicon oxynitride having a thickness of 10 nm. The insulating films 505 and 508 are made of aluminum oxide formed by a sputtering method so as to have a blocking effect of oxygen, hydrogen, water, or the like. The thickness of the insulating film 505 is 50 nm, and the thickness of the insulating film 508 is 50 nm.

  The conductive layer 533_5 overlaps with the channel of the transistor M0 and is disposed at a position where it can function as a back gate. The insulating film 504 is made of silicon oxide with a thickness of 600 nm, and the insulating film 505 is made of silicon oxynitride with a thickness of 300 nm. In addition, the conductive layer 533_5 is electrically connected to the conductive layer 537_8 through conductive layers (not illustrated) of the fifth wiring layer and the sixth wiring layer.

<Data retention>
In the device structure, data is written to the node FN. In the writing operation, first, heat treatment is performed at 150 ° C. Next, while this heat treatment is performed, the terminal BL is 1.8V (corresponding to data 1) or 0V (ground potential, corresponding to data 0), the terminal RWL is 1.2V, the terminal VBG is -5V, and the terminal SL. 0V (ground potential) was applied to each. Next, 3.3 V was applied to the terminal WWL. After 3.3 V was applied to the terminal WWL for a certain period, terminals other than the terminal VBG were set to 0 V (ground potential) to enter a data holding state. The heat treatment time was from 0 hour to 250 hours in 50 hour increments. After the heat treatment, the data was held at 150 ° C. for 0 hour, 1 hour, 5 hours, 10 hours, and 50 hours.

  Similarly, a total of 1040 circuits (65 rows × 16 columns) are arranged, and data is held in the node FN of each circuit. At this time, the node FN adjacent to the node FN that holds the data 1 (front, back, left, and right) holds the data 0. Specifically, when the n-th row and m-th column (hereinafter referred to as n and m) holds data 1, (n−1, m), (n + 1, m), (n, m−1), (N, m + 1) holds data 0. In this way, when the retained data is evaluated later, it is possible to grasp whether a defect has occurred in the row or the column.

<Evaluation>
Next, the charge retention characteristics of the node FN were evaluated.

  First, the voltage applied to the terminal SL was changed little by little. Here, the voltage applied to the terminal SL (hereinafter also referred to as a read circuit voltage value: VRM) was changed from 1.00 V to 2.40 V in increments of 0.02 V. The data held in the node FN was read and confirmed for every change.

  Next, the dependence of the correspondence between the probability that the read data is the same as the retained data (also referred to as a data retention rate) and the VRM on the heating time during data retention was evaluated. The data retention rate indicates the probability of the number of data that can be normally retained among all (1040) data.

  FIG. 26 shows the evaluation results. FIG. 27 shows an evaluation result of the dependency of the correspondence relationship between the data 1 retention failure rate and the VRM on the time of heat treatment during data retention (hereinafter also referred to as heating time), and FIG. The evaluation result of the dependence of the heating time at the time of data retention of the correspondence relationship between the retention failure rate and VRM is shown.

  26 and FIG. 27 is caused by a failure due to non-operation of the transistor M1 and / or the transistor M2 when the VRM in FIG.

  26 and 27, the longer the heating time during data holding, the higher the VRM at which data can be read, that is, the charge leakage is reduced, and data omission is suppressed. In addition, when attention is paid to the correspondence between the VRM in which data failure occurs in which all data 1 becomes data 0 and the “data 1 retention failure rate is 100%” and the heating time at the time of data retention, the heat treatment is performed for 50 hours or more. Thus, the VRM is higher than that in which the heat treatment is not performed (heating time is 0 hour), and the data retention characteristics can be improved. It was not confirmed that the data retention characteristics were improved even when the heating time was longer than 150 hours. Therefore, it was found that the heat treatment is preferably performed for 50 hours or longer and 150 hours or shorter, and more preferably performed for 100 hours or longer and 150 hours or shorter.

  Further, from FIG. 28, it was confirmed that the data 0 retention failure rate was small in all the heating times and retention times evaluated.

  In addition, the dependency of the change over time in the failure rate (probability of data 0 retention failure or data 1 retention failure) when the VRM is fixed was evaluated. The VRM was evaluated under three conditions of 1.2V, 1.7V, and 1.9V.

  From FIG. 29, it was found that the increase in the defect rate was suppressed as the heat treatment time was increased. Further, it was found that when the VRM is 1.2 V, the defective rate hardly changes even if the holding time is increased when the heat treatment is 50 hours or longer. In addition, when the VRM is 1.7 V, when the heat treatment is 100 hours or more, a rapid increase in the defect rate can be suppressed, and it has been confirmed that the defect rate is less than 10% when the holding time is 50 hours. From the above, it was found that VRM is preferably 1.2 V or more and 1.7 V or less.

  In addition, within the above VRM range, it was found that the defect rate of data held for 50 hours was less than five times the defect rate of data held for 10 hours under the same conditions. Further, it was found that the defective rate of the retained data was less than 8% while performing the heat treatment for 250 hours.

  In this embodiment, as in Embodiment 1, the first transistor using single crystal silicon as a semiconductor film, the second transistor using an oxide semiconductor as a semiconductor film, and the data retention life of a semiconductor device having a capacitor element are used. Was evaluated.

  First, an evaluation circuit for a semiconductor device will be described.

<Configuration of evaluation circuit>
The same evaluation circuit as that shown in FIG. 4 was used. The first transistor corresponds to the transistor M1 and the transistor M2, the second transistor corresponds to the transistor M0, and the capacitor corresponds to the capacitor Cs. The transistors M1 and M2 are p-channel transistors.

  Design values of the channel length L and the channel width W of the transistors in the evaluation circuit are as follows. The L / W of the transistor M0 is 0.8 μm / 0.8 μm, the L / W of the transistor M1 is 0.35 μm / 2.2 μm, and the L / W of the transistor M2 is 0.35 μm / 2.2 μm.

<Device structure>
FIG. 30 shows a device structure of the evaluation circuit. In FIG. 30, the conductive layer 537_4 and the conductive layer 537_6 in FIG. 25 are not electrically connected to each other. The conductive layer 537_4 has a portion serving as a terminal RBL and the conductive layer 537_6 serves as a terminal WBL. Example 1 can be used for other configurations.
<Data retention>
In the device structure, data is written to the node FN. In the writing operation, first, heat treatment is performed at 150 ° C. Next, while this heat treatment is performed, the terminal WBL is 1.8V (corresponding to data 1) or 0V (ground potential, corresponding to data 0), the terminal RWL is 1.8V, the terminal RBL is 1.8V, the terminal −5 V was applied to VBG, and 0 V (ground potential) was applied to the terminal SL. Next, 3.3 V was applied to the terminal WWL. After 3.3 V was applied to the terminal WWL for a certain period, terminals other than the terminal VBG were set to 0 V (ground potential) to enter a data holding state. The temperature in the data holding state was three conditions of 125 ° C, 140 ° C, and 150 ° C.
<Evaluation>
Next, the charge retention characteristics of the node FN were evaluated.

  First, the VRM was adjusted to set the node FN to 0.8V or 1.2V.

  Next, the data held in the node FN was read and confirmed.

  Next, an Arrhenius plot of the lifetime is shown in FIG. Note that the lifetime in FIG. 31 indicates the time when the data retention rate becomes 80%. FIG. 31A shows the result when the node FN is 0.8V, and FIG. 31B shows the result when the node FN is 1.2V.

From FIG. 31A, the lifetime at 85 ° C. by extrapolation was 2.3 × 10 ⁶ hours (262.9 years). From FIG. 31B, the lifetime at 85 ° C. by extrapolation was 5.6 × 10 ⁵ hours (64.4 years).

  Further, FIG. 32 shows an Arrhenius plot of the life time in which the life time is set at a time when the data retention rate becomes 90%. FIG. 32A shows the result when the node FN is 0.8V, and FIG. 32B shows the result when the node FN is 1.2V.

From FIG. 32A, the lifetime at 85 ° C. by extrapolation was 1.1 × 10 ⁶ hours (126.6 years). Further, from FIG. 32B, the lifetime at 85 ° C. by extrapolation was 3.0 × 10 ⁵ hours (34.6 years).

300 transistor 380 conductive film 381 insulating film 382 semiconductor 383 conductive film 384 conductive film 385 insulating film 386 insulating film 387 insulating film 388 conductive film 500 substrate 501 insulating film 502 insulating film 503 insulating film 504 insulating film 505 insulating film 506 insulating film 507 insulating Film 508 insulating film 509 insulating film 510 insulating film 511 insulating film 520 single crystal silicon layer 531_1 conductive layer 531_2 conductive layer 532_1 conductive layer 532_2 conductive layer 532_2 conductive layer 532_4 conductive layer 533_1 conductive layer 533_2 conductive layer 533_3 conductive layer 533_4 conductive layer 533_4 Layer 534_1 conductive layer 534_2 conductive layer 535_1 conductive layer 535_2 conductive layer 536_1 conductive layer 536_2 conductive layer 536_3 conductive layer 536_4 conductive layer 536_5 conductive layer 536_6 conductive layer 536_7 Conductive layer 537_1 Conductive layer 537_2 Conductive layer 537_3 Conductive layer 537_4 Conductive layer 537_5 Conductive layer 537_6 Conductive layer 537_7 Conductive layer 537_8 Conductive layer 540_1 Oxide semiconductor layer 540_2 Oxide semiconductor layer 540_3 Oxide semiconductor layer 600 Transistor 640 Insulating film 651 Insulating film 651 Film 651b insulating film 652 insulating film 653 insulating film 654 insulating film 655 insulating film 656 insulating film 660 semiconductor 661 semiconductor 662 semiconductor 663 semiconductor 671 conductive film 671a conductive film 671b conductive film 672 conductive film 672a conductive film 672b conductive film 673 conductive film 674 conductive Film 678 Hard mask 701 Substrate 702 Element isolation layer 703 Insulating film 704 Conductive film 705 Conductive film 706 Conductive film 707 Plug 708 Plug 709 Plug 721 Impurity region 723 Gate electrode 724 Gate insulating film 725 Side wall insulating layer 730 Semiconductor substrate 731 Element isolation layer 750 Transistor 751 Impurity region 752 Gate electrode 753 Gate insulating film 754 Side wall insulating layer 755 Impurity region 756 Semiconductor layer 901 Housing 902 Housing 903 Display portion 904 Display unit 905 Microphone 906 Speaker 907 Operation key 908 Stylus 911 Case 912 Microphone 913 External connection port 914 Operation button 916 Display unit 917 Speaker 921 Case 922 Display unit 923 Keyboard 924 Pointing device 931 Case 932 Refrigeration room door 933 Freezer compartment Door 941 Case 942 Case 943 Display portion 944 Operation key 945 Lens 946 Connection portion 951 Car body 952 Wheel 953 Dashboard 954 Light 1189 ROM interface Esu 1190 substrate 1191 ALU
1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Register 1197 Register Controller 1198 Bus Interface 1199 ROM
3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 3400 Capacitance element 4000 RF device 5100 Pellet 5120 Substrate 5161 Region

Claims (9)

Forming a first transistor having a single crystal semiconductor in a channel formation region;
Forming an insulating film on the first transistor;
Forming an opening in the insulating film to reach the first transistor;
Forming a conductive film electrically connected to the first transistor through the opening;
Forming a second transistor having an oxide semiconductor in a channel formation region electrically connected to the conductive film over the insulating film;
Forming a capacitor element electrically connected to the first transistor and the second transistor;
A method for manufacturing a semiconductor device, wherein voltage is applied to a gate electrode of the second transistor while heat treatment is performed at a temperature of 120 ° C. to 180 ° C. In claim 1,
The second transistor is
Forming a first gate electrode;
Forming a base insulating film on the first gate electrode;
Forming an oxide semiconductor film over the base insulating film;
Forming a source electrode and a drain electrode on the oxide semiconductor film;
Forming a gate insulating film on the oxide semiconductor film, on the source electrode and on the drain electrode;
Forming a second gate electrode on the gate insulating film;
A method for manufacturing a semiconductor device, wherein a voltage is applied to the first gate electrode. In claim 1 or claim 2,
The method for manufacturing a semiconductor device, wherein the voltage is −10 V or higher and −1 V or lower. In any one of Claim 1 thru | or 3,
The method for manufacturing a semiconductor device is characterized in that the heat treatment is performed for 50 hours to 150 hours. A first layer;
A second layer on the first layer;
A third layer on the second layer;
A capacitive element;
The first layer includes a first transistor;
The third layer includes a second transistor;
The channel formation region of the first transistor includes a single crystal semiconductor,
The channel formation region of the second transistor includes an oxide semiconductor,
The second layer has an insulating film and a conductive film,
The conductive film has a function of electrically connecting the first transistor and the second transistor,
The capacitor element is electrically connected to a gate electrode of the first transistor and one of a source electrode or a drain electrode of the second transistor,
Reading of a potential held at the node at 150 ° C. for 50 hours at a node between the gate electrode of the first transistor, one of the source electrode or the drain electrode of the second transistor, and one electrode of the capacitor A semiconductor device characterized in that the defect rate is less than five times the read defect rate of the potential held at 150 ° C. for 10 hours in the node. A first layer;
A second layer on the first layer;
A third layer on the second layer;
A capacitive element;
The first layer includes a first transistor;
The third layer includes a second transistor;
The channel formation region of the first transistor includes a single crystal semiconductor,
The channel formation region of the second transistor includes an oxide semiconductor,
The second layer has an insulating film and a conductive film,
The conductive film has a function of electrically connecting the first transistor and the second transistor,
The capacitor element is electrically connected to a gate electrode of the first transistor and one of a source electrode or a drain electrode of the second transistor,
While performing heat treatment at 150 ° C. for 250 hours at a node between the gate electrode of the first transistor, one of the source electrode or the drain electrode of the second transistor, and one electrode of the capacitor, the node A semiconductor device characterized in that the read failure rate of the potential held in is less than 8%. In claim 5 or claim 6,
The semiconductor device is characterized in that a voltage supplied to one of a source electrode and a drain electrode of the first transistor is 1.2 V or more and 1.7 V or less.   A module comprising the semiconductor device according to claim 5. A semiconductor device according to any one of claims 5 to 7, or a module according to claim 8,
An electronic device including a speaker, operation keys, or a battery.