JP2016086170A - Semiconductor device and evaluation method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device using a transistor having an oxide semiconductor, and having a transistor excellent in the electrical characteristics, and a transistor excellent in the reliability.SOLUTION: In a semiconductor device having a gate electrode, a gate insulator, an oxide semiconductor, and a passivation oxide insulator, the gate insulator is arranged on the gate electrode, the oxide semiconductor is arranged on the gate insulator, and the passivation oxide insulator is arranged on the oxide semiconductor. In the temperature-programmed desorption gas analysis, the desorption amount of oxygen, in terms of oxygen molecule, is 8.0×10molecule/cmor more, when the surface temperature of a film is in a range of 100°C-700°C, or 100°C-500°C.SELECTED DRAWING: Figure 1

Description

One embodiment of the present invention relates to a semiconductor device including a transistor including an oxide semiconductor and an evaluation method thereof.

Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Or this invention relates to a process, a machine, a manufacture, or a composition (composition of matter). In particular, one embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an imaging device, a driving method thereof, a manufacturing method thereof, or a manufacturing device thereof.

Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A semiconductor element such as a transistor, a semiconductor circuit, an arithmetic device, and a memory device are one embodiment of the semiconductor device. An imaging device, a display device, a liquid crystal display device, a light emitting device, an electro-optical device, a power generation device (including a thin film solar cell, an organic thin film solar cell, and the like) and an electronic device may include a semiconductor device.

A technique for forming a transistor or a thin film transistor (TFT) using a semiconductor thin film formed over a substrate having an insulating surface has attracted attention. The transistor is widely applied to electronic devices such as an integrated circuit (IC) and an image display device (display device). As a semiconductor thin film applicable to a transistor, a semiconductor material typified by silicon is widely known, but an oxide semiconductor has attracted attention as another material (for example, Patent Document 1).

In addition, a semiconductor device is disclosed in which an insulating layer from which oxygen is released by heating is used as a base insulating layer of an oxide semiconductor layer that forms a channel, and oxygen vacancies in the oxide semiconductor layer are reduced (for example, Patent Documents). 2).

In addition, an oxide insulating layer is formed over the oxide semiconductor layer, oxygen is introduced (added) through the oxide insulating layer, and heat treatment is performed. Through the oxygen introduction and the heat treatment, hydrogen, moisture, A method for manufacturing a semiconductor device in which impurities such as a hydroxyl group or a hydride are excluded from an oxide semiconductor layer and the oxide semiconductor layer is highly purified is disclosed (for example, Patent Document 3).

11-505377 JP2012-009836 JP2011-199272A

As a defect included in the oxide semiconductor film, there is an oxygen vacancy. For example, in a transistor including an oxide semiconductor film in which oxygen vacancies are included in the oxide semiconductor film, the threshold voltage is likely to fluctuate in the negative direction, which tends to be normally on. This is because electric charges are generated due to oxygen vacancies in the oxide semiconductor film and resistance is reduced. When the transistor has a normally-on characteristic, various problems such as an operation failure easily occurring during operation or a high power consumption during non-operation occur. In addition, there is a problem in that the electrical characteristics of the transistor, typically the amount of fluctuation of the threshold voltage, increases due to aging and stress tests.

Thus, an object of one embodiment of the present invention is to provide a semiconductor device including a transistor with excellent electrical characteristics. Another object is to provide a semiconductor device including a transistor with excellent reliability. Another object of one embodiment of the present invention is to provide a semiconductor device with reduced power consumption. Another object of one embodiment of the present invention is to provide a novel semiconductor device. Another object of one embodiment of the present invention is to provide a novel display device.

Note that the description of the above problems does not disturb the existence of other problems. Note that one embodiment of the present invention does not have to solve all of these problems. Problems other than those described above are naturally apparent from the description of the specification and the like, and it is possible to extract problems other than the above from the description of the specification and the like.

(1) One embodiment of the present invention includes a gate electrode, a gate insulator, an oxide semiconductor, and a passivation oxide insulator, and the gate insulator is provided over the gate electrode. Is a semiconductor device that is disposed on a gate insulator and a passivation oxide insulator is disposed on an oxide semiconductor, and the surface temperature of the film is 100 ° C. or higher and 700 ° C. or lower in a temperature programmed desorption gas analysis. Alternatively, the semiconductor device is characterized in that the amount of desorption of oxygen measured in the range of 100 ° C. to 500 ° C. and converted to oxygen molecules is 8.0 × 10 ¹⁴ molecule / cm ² or more.
(2) Alternatively, according to one embodiment of the present invention, a substrate, an oxide insulator over the substrate, an oxide semiconductor over the oxide insulator, an oxide insulator over the oxide semiconductor, and an oxide insulator In a semiconductor device having the above inorganic material, an organic insulator, a display layer, and a counter substrate, all layers above the oxide insulator on the oxide semiconductor are removed to a size of 1 cm square. This is an evaluation method in which the amount of desorbed oxygen is measured by measuring the surface temperature of the film in the range of 100 ° C. or higher and 700 ° C. or lower, or 100 ° C. or higher and 500 ° C. or lower, by the temperature-programmed desorption gas analysis method after dividing .
(3) Alternatively, according to one embodiment of the present invention, a substrate, an oxide insulator over the substrate, an oxide semiconductor over the oxide insulator, an oxide insulator over the oxide semiconductor, and an oxide insulator In a semiconductor device having the above inorganic material, an organic insulator, a liquid crystal layer, and a counter substrate, all layers above the oxide insulator on the oxide semiconductor are removed to a size of 1 cm square. After the fragmentation, the amount of desorbed oxygen is measured by temperature-programmed desorption gas analysis in the range where the surface temperature of the film is 100 ° C. or higher and 700 ° C. or lower, or 100 ° C. or higher and 500 ° C. or lower, and converted into oxygen molecules. This is a semiconductor device characterized in that the amount of released oxygen is 1.0 × 10 ¹⁴ molecule / cm ² or more.
(4) Alternatively, according to one embodiment of the present invention, a substrate, an oxide insulator over the substrate, an oxide semiconductor over the oxide insulator, an oxide insulator over the oxide semiconductor, and an oxide insulator In a semiconductor device having the above inorganic material, an organic insulator, a light emitting element layer, and a counter substrate, all layers above the oxide insulator on the oxide semiconductor are removed, and the size is 1 cm square. After the separation, the amount of desorbed oxygen is measured in the temperature range of 100 ° C. to 700 ° C. or 100 ° C. to 500 ° C. by temperature programmed desorption gas analysis, and converted to oxygen molecules The amount of desorbed oxygen is 1.0 × 10 ¹⁴ molecule / cm ² or more.

According to one embodiment of the present invention, a semiconductor device including a transistor with excellent electrical characteristics can be provided. Alternatively, a semiconductor device including a transistor with excellent reliability can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. Alternatively, according to one embodiment of the present invention, a novel semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a novel display device can be provided.

Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. It should be noted that the effects other than these are naturally obvious from the description of the specification, drawings, claims, etc., and it is possible to extract the other effects from the descriptions of the specification, drawings, claims, etc. It is.

8A and 8B are a top view and cross-sectional views illustrating one embodiment of a semiconductor device. 8A and 8B are a top view and cross-sectional views illustrating one embodiment of a semiconductor device. 8A and 8B are a top view and cross-sectional views illustrating one embodiment of a semiconductor device. 10 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. FIG. 10 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. FIG. 10 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. FIG. 8A and 8B are a top view and cross-sectional views illustrating one embodiment of a semiconductor device. Sectional drawing explaining one form of the evaluation sample preparation method. Sectional drawing explaining one form of the evaluation sample preparation method. Sectional drawing explaining one form of the evaluation sample preparation method. Sectional drawing explaining one form of the evaluation sample preparation method. Sectional drawing explaining one form of the evaluation sample preparation method. Sectional drawing explaining one form of the evaluation sample preparation method. FIG. 10 is a cross-sectional view illustrating one embodiment of a semiconductor device. 10A and 10B are a cross-sectional view illustrating one embodiment of a semiconductor device and a cross-sectional view illustrating one embodiment of a method for manufacturing an evaluation sample. FIG. 10 is a cross-sectional view illustrating one embodiment of a semiconductor device. Sectional drawing explaining one form of the evaluation sample preparation method. FIG. 6 is a Cs-corrected high-resolution TEM image in a cross section of a CAAC-OS and a schematic cross-sectional view of the CAAC-OS. The Cs correction | amendment high-resolution TEM image in the plane of CAAC-OS. 6A and 6B illustrate structural analysis by XRD of a CAAC-OS and a single crystal oxide semiconductor. The figure which shows the electron diffraction pattern of CAAC-OS. FIG. 6 shows changes in crystal parts of an In—Ga—Zn oxide due to electron irradiation. 10A and 10B are a block diagram and a circuit diagram illustrating a display device. Sectional drawing explaining an imaging device. The perspective view and sectional drawing explaining an imaging device shape. The figure explaining a display module. FIG. 14 illustrates an example of an electronic device. FIG. 10 illustrates a circuit of a memory device. The block diagram which shows an example of CPU. The figure which shows an example of RF tag. The graph of the TDS analysis result of an Example.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. In the embodiments described below, the same portions or portions having similar functions are denoted by the same reference numerals or the same hatch patterns in different drawings, and description thereof is not repeated.

Note that in each drawing described in this specification, the size, the film thickness, or the region of each component is exaggerated for clarity in some cases. Therefore, it is not necessarily limited to the scale.

Further, the terms such as first, second, and third used in this specification are given for avoiding confusion between components, and are not limited numerically. Therefore, for example, the description can be made by appropriately replacing “first” with “second” or “third”.

Further, the functions of “source” and “drain” may be interchanged when the direction of current changes during circuit operation. Therefore, in this specification, the terms “source” and “drain” can be used interchangeably.

Further, the voltage refers to a potential difference between two points, and the potential refers to electrostatic energy (electric potential energy) possessed by a unit charge in an electrostatic field at a certain point. However, generally, a potential difference between a potential at a certain point and a reference potential (for example, ground potential) is simply referred to as a potential or a voltage, and the potential and the voltage are often used as synonyms. Therefore, in this specification, unless otherwise specified, the potential may be read as a voltage, or the voltage may be read as a potential.

In addition, in this specification and the like, “electrically connected” includes a case of being connected via “thing having some electric action”. Here, the “thing having some electric action” is not particularly limited as long as it can exchange electric signals between connection targets. For example, “thing having some electric action” includes electrodes, wiring, switching elements such as transistors, resistance elements, inductors, capacitors, and other elements having various functions.

In this specification and the like, a silicon oxynitride film refers to a film having a higher oxygen content than nitrogen as the composition, and a silicon nitride oxide film has a nitrogen content as compared to oxygen as a composition. Refers to membranes with a lot of

Further, in this specification and the like, in describing the structure of the invention with reference to the drawings, the same reference numerals are used in different drawings.

Further, in this specification and the like, “parallel” means a state in which two straight lines are arranged at an angle of −10 ° to 10 °. Therefore, the case of −5 ° to 5 ° is also included. “Vertical” refers to a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included.

Note that the terms “film” and “layer” can be interchanged with each other depending on the case or circumstances. For example, the term “conductive layer” may be changed to the term “conductive film”. Alternatively, for example, the term “insulating film” may be changed to the term “insulating layer” in some cases.

(Embodiment 1)
In this embodiment, a semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

<Configuration Example 1 of Semiconductor Device>
FIG. 1A is a top view of a transistor 100 which is a semiconductor device of one embodiment of the present invention, and FIG. 1B is a cross-sectional view taken along a dashed-dotted line X1-X2 in FIG. 1C corresponds to a cross-sectional view of a cross-sectional surface taken along the alternate long and short dash line Y1-Y2 illustrated in FIG. Note that in FIG. 1A, some components (such as an insulating film functioning as a gate insulating film) are not illustrated in order to avoid complexity. The direction of the alternate long and short dash line X1-X2 may be referred to as a channel length direction, and the direction of the alternate long and short dash line Y1-Y2 may be referred to as a channel width direction. Note that in the top view of the transistor, some components may be omitted in the following drawings as in FIG. 1A.

The transistor 100 includes a conductive film 104 functioning as a gate electrode over a substrate 102, an insulating film 106 over the substrate 102 and the conductive film 104, an insulating film 107 over the insulating film 106, and an oxide semiconductor film over the insulating film 107. 108 and conductive films 112 a and 112 b functioning as a source electrode and a drain electrode which are electrically connected to the oxide semiconductor film 108. In addition, insulating films 114 and 116 are provided over the transistor 100, more specifically, over the conductive films 112 a and 112 b and the oxide semiconductor film 108, and a protective film 117 is provided over the insulating film 116. 1B and 1C, an insulating film 118 may be provided over the protective film 117.

The insulating film 106 and the insulating film 107 may be referred to as a first insulating film, and the first insulating film functions as a gate insulating film of the transistor 100. The insulating film 114 and the insulating film 116 may be referred to as second insulating films, and the second insulating film has oxygen and has a function of supplying oxygen into the oxide semiconductor film 108. The insulating film 118 functions as a protective insulating film which suppresses impurities that enter the transistor 100.

The oxide semiconductor film 108 included in the transistor 100 is likely to have normally-on characteristics, for example, when hydrogen enters a site of oxygen vacancies and carriers are generated. Therefore, reducing oxygen vacancies in the oxide semiconductor film 108 is important for obtaining stable transistor characteristics. In the structure of the transistor of one embodiment of the present invention, excess oxygen is introduced into the insulating film over the oxide semiconductor film 108, here, the insulating film 114 over the oxide semiconductor film 108, so that oxidation is performed from the insulating film 114. Oxygen is transferred into the oxide semiconductor film 108 to fill oxygen vacancies in the oxide semiconductor film 108. Alternatively, by introducing excess oxygen into the insulating film 116 over the oxide semiconductor film 108, oxygen is transferred from the insulating film 116 to the oxide semiconductor film 108 through the insulating film 114, so that the oxide semiconductor film 108 includes It is characterized by compensating for oxygen deficiency. Alternatively, excessive oxygen is introduced into the insulating film 114 and the insulating film 116 over the oxide semiconductor film 108, whereby oxygen is transferred from both the insulating film 114 and the insulating film 116 into the oxide semiconductor film 108, whereby the oxide A feature is that oxygen vacancies in the semiconductor film 108 are filled.

The insulating films 114 and 116 preferably have a region containing oxygen in excess of the stoichiometric composition (oxygen-excess region). In other words, the insulating films 114 and 116 are insulating films capable of releasing oxygen. Note that in order to provide the oxygen-excess region in the insulating films 114 and 116, for example, oxygen is introduced into the insulating films 114 and 116 after film formation to form the oxygen-excess region. As a method for introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, a plasma treatment, or the like can be used.

In addition, oxygen contained in the insulating films 114 and 116 is diffused into the oxide semiconductor film 108 by heat treatment. For example, the amount of released oxygen molecules in the insulating films 114 and 116 can be measured by a temperature programmed desorption gas analysis method (TDS (Thermal Desorption Spectroscopy)).

On the other hand, oxygen contained in the insulating films 114 and 116 may be diffused to the outside during heat treatment in the manufacturing process of the transistor 100, and may not move favorably into the oxide semiconductor film 108. However, the semiconductor device of one embodiment of the present invention has a structure in which the protective film 117 is provided above the transistor 100, specifically, over the insulating film 116. The protective film 117 has a function of passing oxygen when oxygen is introduced, and has a function of suppressing release of oxygen during heat treatment. Specifically, the protective film 117 includes at least one metal element that is the same as that of the oxide semiconductor film 108.

As described above, by providing the insulating films 114 and 116 over the oxide semiconductor film 108, oxygen in the insulating films 114 and 116 is moved to the oxide semiconductor film 108, and is formed in the oxide semiconductor film 108. It becomes possible to compensate for oxygen deficiency. However, the insulating films 114 and 116 may not be provided. In addition, by providing the protective film 117 having a function of suppressing release of oxygen over the insulating film 116, the diffusion of oxygen in the insulating films 114 and 116 to the outside during heat treatment in the manufacturing process of the transistor 100 is suppressed. can do. Accordingly, oxygen vacancies in the oxide semiconductor film 108 can be preferably filled, and a highly reliable semiconductor device can be provided.

<Configuration Example 2 of Semiconductor Device>
Next, a structural example different from the transistor 100 illustrated in FIGS. 1A to 1C is described with reference to FIGS. In addition, when it has the function similar to the function demonstrated previously, a hatch pattern may be made the same and a code | symbol may not be attached | subjected especially.

  2A is a top view of the transistor 150 which is a semiconductor device of one embodiment of the present invention, and FIG. 2B is a cross-sectional view taken along the dashed-dotted line X1-X2 in FIG. FIG. 2C corresponds to a drawing, and FIG. 2C corresponds to a cross-sectional view of a cross-sectional surface taken along the alternate long and short dash line Y1-Y2 illustrated in FIG.

  The transistor 150 includes a conductive film 104 functioning as a gate electrode over the substrate 102, an insulating film 106 over the substrate 102 and the conductive film 104, an insulating film 107 over the insulating film 106, and an oxide semiconductor film over the insulating film 107. 108, the insulating film 114 over the oxide semiconductor film 108, the insulating film 116 over the insulating film 114, and the openings 141a and 141b provided in the insulating film 114 and the insulating film 116. Conductive films 112a and 112b functioning as source and drain electrodes connected to each other. Further, a protective film 117 is provided over the transistor 150, more specifically, over the conductive films 112 a and 112 b and the insulating film 116. Alternatively, as illustrated in FIGS. 2B and 2C, an insulating film 118 may be provided over the protective film 117.

  The transistor 100 described above has a channel etch type structure, whereas the transistor 150 illustrated in FIGS. 2A, 2B, and 2C has a channel protection type structure. As described above, the semiconductor device of one embodiment of the present invention can have both a channel etch type and a channel protection type transistor structure.

  Since the transistor 150 is provided with the insulating films 114 and 116 over the oxide semiconductor film 108 as in the transistor 100 described above, oxygen contained in the insulating films 114 and 116 is contained in the oxide semiconductor film 108. Can compensate for oxygen deficiency. In addition, by providing the protective film 117 having a function of suppressing release of oxygen over the insulating film 116, the diffusion of oxygen in the insulating films 114 and 116 to the outside during heat treatment in the manufacturing process of the transistor 150 is suppressed. can do. Accordingly, oxygen vacancies in the oxide semiconductor film 108 can be preferably filled, and a highly reliable semiconductor device can be provided.

<Configuration Example 3 of Semiconductor Device>
Next, a structural example different from the transistor 100 illustrated in FIGS. 1A, 1B, and 1C is described with reference to FIGS. In addition, when it has the function similar to the function demonstrated previously, a hatch pattern may be made the same and a code | symbol may not be attached | subjected especially.

3A is a top view of the transistor 170 which is a semiconductor device of one embodiment of the present invention, and FIG. 3B is a cross-sectional view taken along the dashed-dotted line X1-X2 in FIG. 3A. 3C corresponds to a cross-sectional view of a cross-sectional surface taken along the alternate long and short dash line Y1-Y2 illustrated in FIG.

The transistor 170 includes a conductive film 104 functioning as a gate electrode over the substrate 102, an insulating film 106 over the substrate 102 and the conductive film 104, an insulating film 107 over the insulating film 106, and an oxide semiconductor film over the insulating film 107. 108, conductive films 112a and 112b functioning as a source electrode and a drain electrode electrically connected to the oxide semiconductor film 108, an insulating film 114 over the oxide semiconductor film 108 and the conductive films 112a and 112b, and an insulating film The insulating film 116 over the film 114, the protective film 117 over the insulating film 116, the insulating film 118 over the protective film 117, and the conductive films 120a and 120b over the insulating film 118 are included. In addition, the conductive film 120a is connected to the conductive film 112b through the opening 142c provided in the insulating films 114, 116, and 118 and the protective film 117. In addition, the conductive film 120b is formed so as to overlap with the oxide semiconductor film 108.

In the transistor 170, the insulating films 114, 116, and 118 and the protective film 117 function as a second gate insulating film of the transistor 170. In the transistor 170, the conductive film 120a functions as a pixel electrode used for a display device, for example. In the transistor 170, the conductive film 120b functions as a second gate electrode (also referred to as a back gate electrode).

In addition, as illustrated in FIG. 3C, the conductive film 120b includes the conductive film 104 functioning as a gate electrode in the openings 142a and 142b provided in the insulating films 106, 107, 114, 116, and 118 and the protective film 117. Connected to. Therefore, the same potential is applied to the conductive film 120b and the conductive film 104.

Note that although the opening 142a and 142b are provided and the conductive film 120b and the conductive film 104 are connected in this embodiment mode, the present invention is not limited to this. For example, a structure in which only one of the opening 142a and the opening 142b is formed and the conductive film 120b and the conductive film 104 are connected, or the conductive film 120b without the openings 142a and 142b is provided. The conductive film 104 may not be connected. Note that in the case where the conductive film 120b and the conductive film 104 are not connected to each other, different potentials can be applied to the conductive film 120b and the conductive film 104, respectively.

As shown in FIG. 3B, the oxide semiconductor film 108 is positioned so as to face the conductive film 104 functioning as a gate electrode and the conductive film 120b functioning as a second gate electrode, It is sandwiched between conductive films functioning as two gate electrodes. The length in the channel length direction and the length in the channel width direction of the conductive film 120b functioning as the second gate electrode are longer than the length in the channel length direction and the length in the channel width direction of the oxide semiconductor film 108, respectively. The entire oxide semiconductor film 108 is covered with the conductive film 120 b with the insulating films 114, 116, 118 and the protective film 117 interposed therebetween. In addition, the conductive film 120b functioning as the second gate electrode and the conductive film 104 functioning as the gate electrode are formed in the openings 142a and 142b provided in the insulating films 106, 107, 114, 116, and 118 and the protective film 117. Since the oxide semiconductor film 108 is connected, the side surface in the channel width direction of the oxide semiconductor film 108 is opposed to the conductive film 120 b functioning as the second gate electrode with the insulating films 114, 116, 118 and the protective film 117 interposed therebetween.

In other words, in the channel width direction of the transistor 170, the conductive film 104 functioning as the gate electrode and the conductive film 120b functioning as the second gate electrode are the insulating films 106 and 107 functioning as the gate insulating film and the second gate. Insulating films 114, 116, 118 functioning as insulating films and insulating films 106, 107 functioning as gate insulating films and insulating films functioning as second gate insulating films while being connected in openings provided in the protective film 117 The oxide semiconductor film 108 is surrounded by 114, 116, 118 and the protective film 117.

With such a structure, the oxide semiconductor film 108 included in the transistor 170 can be electrically surrounded by an electric field of the conductive film 104 functioning as a gate electrode and the conductive film 120b functioning as a second gate electrode. it can. A device structure of a transistor that electrically surrounds an oxide semiconductor film in which a channel region is formed by an electric field of the gate electrode and the second gate electrode as in the transistor 170 is referred to as a surrounded channel (s-channel) structure. it can.

Since the transistor 170 has an s-channel structure, an electric field for inducing a channel can be effectively applied to the oxide semiconductor film 108 by the conductive film 104 functioning as a gate electrode. Capability is improved, and high on-current characteristics can be obtained. Further, since the on-state current can be increased, the transistor 170 can be miniaturized. Further, since the transistor 170 has a structure surrounded by the conductive film 104 functioning as a gate electrode and the conductive film 120b functioning as a second gate electrode, the mechanical strength of the transistor 170 can be increased.

Other structures are similar to those of the transistor 100 shown in FIGS. 1A, 1B, and 1C, and have the same effects.

Hereinafter, other components included in the semiconductor device of the present embodiment will be described in detail.

<Board>
There is no particular limitation on the material of the substrate 102, but it is necessary that the substrate 102 have at least heat resistance to withstand heat treatment performed later. For example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like may be used as the substrate 102. In addition, a single crystal semiconductor substrate made of silicon, silicon carbide, or the like, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, or the like can be applied, and a semiconductor element is provided over these substrates. A substrate may be used as the substrate 102. When a glass substrate is used as the substrate 102, the sixth generation (1500 mm × 1850 mm), the seventh generation (1870 mm × 2200 mm), the eighth generation (2200 mm × 2400 mm), the ninth generation (2400 mm × 2800 mm), the tenth generation. By using a large area substrate such as a generation (2950 mm × 3400 mm), a large display device can be manufactured.

Alternatively, a flexible substrate may be used as the substrate 102, and the transistor 100 may be formed directly over the flexible substrate. Alternatively, a separation layer may be provided between the substrate 102 and the transistor 100. The separation layer can be used for separation from the substrate 102 and transfer to another substrate after the semiconductor device is partially or entirely completed thereon. At that time, the transistor 100 can be transferred to a substrate having poor heat resistance or a flexible substrate.

<Conductive film>
As the conductive film 104 functioning as a gate electrode and the conductive films 112a and 112b functioning as a source electrode and a drain electrode, chromium (Cr), copper (Cu), aluminum (Al), gold (Au), silver (Ag) , Zinc (Zn), molybdenum (Mo), tantalum (Ta), titanium (Ti), tungsten (W), manganese (Mn), nickel (Ni), iron (Fe), cobalt (Co) Each of these elements can be formed using an element, an alloy including the above-described metal element as a component, an alloy combining the above-described metal elements, or the like.

In addition, the conductive films 104, 112a, and 112b may have a single-layer structure or a stacked structure including two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is stacked on an aluminum film, a two-layer structure in which a titanium film is stacked on a titanium nitride film, and a two-layer structure in which a tungsten film is stacked on a titanium nitride film Layer structure, two-layer structure in which a tungsten film is stacked on a tantalum nitride film or tungsten nitride film, a three-layer structure in which a titanium film, an aluminum film is stacked on the titanium film, and a titanium film is further formed thereon is there. Alternatively, an alloy film or a nitride film in which aluminum is combined with one or more selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be used.

The conductive films 104, 112a, and 112b include indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, and indium tin oxide containing titanium oxide. Alternatively, a light-transmitting conductive material such as indium zinc oxide or indium tin oxide to which silicon oxide is added can be used.

Further, a Cu—X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) may be applied to the conductive films 104, 112a, and 112b. By using a Cu-X alloy film, it can be processed by a wet etching process, and thus manufacturing costs can be suppressed.

<Gate insulation film>
As the insulating films 106 and 107 functioning as the gate insulating film of the transistor 100, a plasma enhanced chemical vapor deposition (PECVD) method, a sputtering method, or the like is used to form a silicon oxide film, a silicon oxynitride film, or a nitride film. One or more kinds of silicon oxide film, silicon nitride film, aluminum oxide film, hafnium oxide film, yttrium oxide film, zirconium oxide film, gallium oxide film, tantalum oxide film, magnesium oxide film, lanthanum oxide film, cerium oxide film and neodymium oxide film Each insulating layer can be used. Note that instead of the stacked structure of the insulating films 106 and 107, a single-layer insulating film selected from the above materials or an insulating film having three or more layers may be used.

The insulating film 106 functions as a blocking film that suppresses permeation of oxygen. For example, in the case where excess oxygen is supplied into the insulating films 107, 114, and / or the oxide semiconductor film 108, the insulating film 106 can suppress permeation of oxygen.

Note that the insulating film 107 in contact with the oxide semiconductor film 108 functioning as the channel region of the transistor 100 is preferably an oxide insulating film, and includes a region containing oxygen in excess of the stoichiometric composition (oxygen-excess region). ) Is more preferable. In other words, the insulating film 107 is an insulating film capable of releasing oxygen. In order to provide the oxygen-excess region in the insulating film 107, for example, the insulating film 107 may be formed in an oxygen atmosphere. Alternatively, oxygen may be introduced into the insulating film 107 after film formation to form an oxygen excess region. As a method for introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, a plasma treatment, or the like can be used.

Further, when hafnium oxide is used as the insulating film 107, the following effects are obtained. Hafnium oxide has a higher dielectric constant than silicon oxide or silicon oxynitride. Therefore, since the physical film thickness can be increased with respect to the equivalent oxide film thickness, the leakage current due to the tunnel current can be reduced even when the equivalent oxide film thickness is 10 nm or less or 5 nm or less. That is, a transistor with a small off-state current can be realized. Further, hafnium oxide having a crystal structure has a higher dielectric constant than hafnium oxide having an amorphous structure. Therefore, in order to obtain a transistor with low off-state current, it is preferable to use hafnium oxide having a crystal structure. Examples of the crystal structure include a monoclinic system and a cubic system. Note that one embodiment of the present invention is not limited thereto.

Note that in this embodiment, a silicon nitride film is formed as the insulating film 106 and a silicon oxide film is formed as the insulating film 107. A silicon nitride film has a higher relative dielectric constant than a silicon oxide film and a large film thickness necessary for obtaining a capacitance equivalent to that of a silicon oxide film. Therefore, a silicon nitride film is used as a gate insulating film of the transistor 150. Insulating film can be physically thickened. Accordingly, a decrease in the withstand voltage of the transistor 100 can be suppressed, and further, the withstand voltage can be improved, thereby suppressing electrostatic breakdown of the transistor 100.

<Oxide semiconductor film>
The oxide semiconductor film 108 includes oxygen, In, Zn, and M (M is Ti, Ga, Y, Zr, Sn, La, Ce, Nd, or Hf). Typically, an In—Ga oxide, an In—Zn oxide, or an In—M—Zn oxide can be used for the oxide semiconductor film 108. In particular, an In-M-Zn oxide is preferably used for the oxide semiconductor film 108.

In the case where the oxide semiconductor film 108 is an In-M-Zn oxide, the atomic ratio of the metal elements of the sputtering target used for forming the In-M-Zn oxide is M for In and M for Zn. It is preferable to satisfy. As the atomic ratio of the metal elements of such a sputtering target, In: M: Zn = 1: 1: 1, In: M: Zn = 1: 1: 1.2, In: M: Zn = 3: 1: 2, In: M: Zn = 4: 2: 4.1 is preferable. In the case where the oxide semiconductor film 108 is an In-M-Zn oxide, a target including a polycrystalline In-M-Zn oxide is preferably used as the sputtering target. By using a target including a polycrystalline In-M-Zn oxide, the oxide semiconductor film 108 having crystallinity can be easily formed. Note that the atomic ratio of the oxide semiconductor film 108 to be formed includes a variation of plus or minus 40% of the atomic ratio of the metal element contained in the sputtering target as an error.

Note that when the oxide semiconductor film 108 is an In-M-Zn oxide film, the atomic ratio of In and M excluding Zn and O is preferably higher than In at 25 atomic% and lower than 75 at% M. More preferably, In is higher than 34 atomic% and M is lower than 66 atomic%.

The oxide semiconductor film 108 has an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more. In this manner, off-state current of the transistor 100 can be reduced by using an oxide semiconductor film with a wide energy gap.

The thickness of the oxide semiconductor film 108 is 3 nm to 200 nm, preferably 3 nm to 100 nm, more preferably 3 nm to 50 nm.

As the oxide semiconductor film 108, an oxide semiconductor film with low carrier density is used. For example, the oxide semiconductor film 108 has a carrier density of 1 × 10 ⁻⁹ pieces / cm ³ or more and less than 8 × 10 ¹¹ pieces / cm ³ , preferably less than 1 × 10 ¹¹ pieces / cm ³ .

Note that it is preferable to use an oxide semiconductor film with a low impurity concentration and a low density of defect states as the oxide semiconductor film 108 because a transistor having more excellent electrical characteristics can be manufactured. Here, low impurity concentration and low defect level density (low oxygen deficiency) are referred to as high purity intrinsic or substantially high purity intrinsic. A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has few carrier generation sources, and thus can have a low carrier density. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film rarely has electrical characteristics (also referred to as normally-on) in which the threshold voltage is negative. In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and thus may have a low density of trap states. Further, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has an extremely small off-state current, a channel width of 1 × 10 ⁶ μm, and a channel length L of 10 μm. When the voltage between the drain electrodes (drain voltage) is in the range of 1V to 10V, it is possible to obtain a characteristic that the off-current is less than the measurement limit of the semiconductor parameter analyzer, that is, 1 × 10 ⁻¹³ A or less.

Therefore, a transistor in which a channel region is formed in the high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film can have a small variation in electrical characteristics and can be a highly reliable transistor. Note that the charge trapped in the trap level of the oxide semiconductor film takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor in which a channel region is formed in an oxide semiconductor film with a high trap state density may have unstable electrical characteristics. Examples of impurities include hydrogen, nitrogen, alkali metals, and alkaline earth metals.

Hydrogen contained in the oxide semiconductor film reacts with oxygen bonded to metal atoms to become water, and forms oxygen vacancies in a lattice from which oxygen is released (or a portion from which oxygen is released). When hydrogen enters the oxygen vacancies, electrons serving as carriers may be generated. In addition, a part of hydrogen may be combined with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor including an oxide semiconductor film containing hydrogen is likely to be normally on. Therefore, it is preferable that hydrogen be reduced in the oxide semiconductor film 108 as much as possible. Specifically, in the oxide semiconductor film 108, the hydrogen concentration obtained by SIMS analysis is 2 × 10 ²⁰ atoms / cm ³ or less, preferably 5 × 10 ¹⁹ atoms / cm ³ or less, more preferably 1 × 10 ^19. atoms / cm ³ or less, 5 × 10 ¹⁸ atoms / cm ³ or less, preferably 1 × 10 ¹⁸ atoms / cm ³ or less, more preferably 5 × 10 ¹⁷ atoms / cm ³ or less, more preferably 1 × 10 ¹⁶ atoms / cm ³ or less. cm ³ or less.

When silicon or carbon which is one of Group 14 elements is included in the oxide semiconductor film 108, oxygen vacancies increase in the oxide semiconductor film 108 and become n-type. Therefore, the concentration of silicon or carbon in the oxide semiconductor film 108 and the concentration of silicon or carbon in the vicinity of the interface with the oxide semiconductor film 108 (concentration obtained by SIMS analysis) are 2 × 10 ¹⁸ atoms / cm ³ or less. Preferably, it is 2 × 10 ¹⁷ atoms / cm ³ or less.

In the oxide semiconductor film 108, the concentration of alkali metal or alkaline earth metal obtained by SIMS analysis is set to 1 × 10 ¹⁸ atoms / cm ³ or lower, preferably 2 × 10 ¹⁶ atoms / cm ³ or lower. When an alkali metal and an alkaline earth metal are combined with an oxide semiconductor, carriers may be generated, and the off-state current of the transistor may be increased. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the oxide semiconductor film 108.

In addition, when nitrogen is contained in the oxide semiconductor film 108, electrons as carriers are generated, the carrier density is increased, and the oxide semiconductor film 108 is easily n-type. As a result, a transistor including an oxide semiconductor film containing nitrogen is likely to be normally on. Therefore, nitrogen in the oxide semiconductor film is preferably reduced as much as possible. For example, the nitrogen concentration obtained by SIMS analysis is preferably 5 × 10 ¹⁸ atoms / cm ³ or less.

The oxide semiconductor film 108 may have a non-single crystal structure, for example. The non-single-crystal structure includes, for example, a CAAC-OS (C Axis Crystallized Oxide Semiconductor) described later, a polycrystalline structure, a microcrystalline structure, or an amorphous structure. In the non-single-crystal structure, the amorphous structure has the highest density of defect states, and the CAAC-OS has the lowest density of defect states.

For example, the oxide semiconductor film 108 may have an amorphous structure. An oxide semiconductor film having an amorphous structure has, for example, disordered atomic arrangement and no crystal component. Alternatively, an amorphous oxide film has, for example, a completely amorphous structure and does not have a crystal part.

Note that the oxide semiconductor film 108 is a mixed film including two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region. Also good. The mixed film has, for example, a single layer structure including two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region. There is a case. For example, the mixed film has a stacked structure including any two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region. There is a case.

<Insulating film>
The insulating films 114 and 116 have a function of supplying oxygen to the oxide semiconductor film 108. The insulating film 118 has a function as a protective insulating film of the transistor 100. In addition, the insulating films 114 and 116 include oxygen. The insulating film 114 is an insulating film that can transmit oxygen. Note that the insulating film 114 also functions as a damage reducing film for the oxide semiconductor film 108 when an insulating film 116 to be formed later is formed.

As the insulating film 114, silicon oxide, silicon oxynitride, or the like with a thickness of 5 nm to 150 nm, preferably 5 nm to 50 nm can be used.

The insulating film 114 preferably has a small amount of defects. Typically, the ESR measurement indicates that the spin density of a signal appearing at g = 2.001 derived from a dangling bond of silicon is 3 × 10 ¹⁷ spins / It is preferable that it is cm ³ or less. This is because when the density of defects contained in the insulating film 114 is large, oxygen is bonded to the defects, and the amount of oxygen transmitted through the insulating film 114 is reduced.

Note that in the insulating film 114, all of the oxygen that has entered the insulating film 114 from the outside does not move to the outside of the insulating film 114 but also remains in the insulating film 114. Further, oxygen enters the insulating film 114 and oxygen contained in the insulating film 114 may move to the outside of the insulating film 114, so that oxygen may move in the insulating film 114. When an oxide insulating film that can transmit oxygen is formed as the insulating film 114, oxygen released from the insulating film 116 provided over the insulating film 114 is transferred to the oxide semiconductor film 108 through the insulating film 114. Can be made.

As the insulating film 114, an oxide insulating film in which the level density of nitrogen oxide is low between the energy (Ev_os) at the upper end of the valence band of the oxide semiconductor film and the energy (Ec_os) at the lower end of the conduction band is used. Can be formed. As the oxide insulating film having a low nitrogen oxide level density between Ev_os and Ec_os, a silicon oxynitride film with a low nitrogen oxide emission amount, an aluminum oxynitride film with a low nitrogen oxide emission amount, or the like is used. be able to.

Note that a silicon oxynitride film with a small amount of released nitrogen oxide is a film in which the amount of released ammonia is larger than the amount of released nitrogen oxide in the temperature programmed desorption gas analysis method. Typically, the amount of released ammonia is Is 1 × 10 ¹⁸ pieces / cm ³ or more and 5 × 10 ¹⁹ pieces / cm ³ or less. Note that the amount of ammonia released is the amount released by heat treatment at a film surface temperature of 50 ° C. to 650 ° C., preferably 50 ° C. to 550 ° C.

Nitrogen oxide (NO _x , x is 0 or more and 2 or less, preferably 1 or more and 2 or less), typically NO ₂ or NO forms a level in the insulating film 114 or the like. The level is located in the energy gap of the oxide semiconductor film 108. Therefore, when nitrogen oxide diffuses to the interface between the insulating film 114 and the oxide semiconductor film 108, the level may trap electrons on the insulating film 114 side. As a result, trapped electrons remain in the vicinity of the interface between the insulating film 114 and the oxide semiconductor film 108, so that the threshold voltage of the transistor is shifted in the positive direction.

Nitrogen oxide reacts with ammonia and oxygen in heat treatment. Since nitrogen oxide contained in the insulating film 114 reacts with ammonia contained in the insulating film 116 in the heat treatment, nitrogen oxide contained in the insulating film 114 is reduced. Therefore, electrons are hardly trapped at the interface between the insulating film 114 and the oxide semiconductor film 108.

By using an oxide insulating film having a low level density of nitrogen oxide between Ev_os and Ec_os as the insulating film 114, a shift in threshold voltage of the transistor can be reduced, and electrical characteristics of the transistor Fluctuations can be reduced.

Note that the insulating film 114 has a g value of 2.037 in a spectrum obtained by measurement with an ESR of 100 K or lower by heat treatment in a manufacturing process of the transistor, typically 300 ° C. or higher and lower than the substrate strain point. A first signal of 2.039 or less, a second signal of g value of 2.001 or more and 2.003 or less, and a third signal of g value of 1.964 or more and 1.966 or less are observed. The split width of the first signal and the second signal and the split width of the second signal and the third signal are about 5 mT in the X-band ESR measurement. In addition, the first signal having a g value of 2.037 to 2.039, the second signal having a g value of 2.001 to 2.003, and the g value of 1.964 to 1.966. The total density of the spins of the third signal is less than 1 × 10 ¹⁸ spins / cm ³ , typically 1 × 10 ¹⁷ spins / cm ³ or more and less than 1 × 10 ¹⁸ spins / cm ³ .

In the ESR spectrum of 100K or less, a first signal having a g value of 2.037 to 2.039, a second signal having a g value of 2.001 to 2.003, and a g value of 1.964 to 1 A third signal of .966 or less corresponds to a signal caused by nitrogen oxides (NO _x , x is 0 or more and 2 or less, preferably 1 or more and 2 or less). Typical examples of nitrogen oxides include nitrogen monoxide and nitrogen dioxide. That is, the first signal having a g value of 2.037 to 2.039, the second signal having a g value of 2.001 to 2.003, and the g value of 1.964 to 1.966. It can be said that the smaller the total density of spins of the third signal, the smaller the content of nitrogen oxide contained in the oxide insulating film.

In addition, the oxide insulating film in which the level density of nitrogen oxide is low between Ev_os and Ec_os has a nitrogen concentration measured by SIMS of 6 × 10 ²⁰ atoms / cm ³ or less.

Oxidation in which the substrate temperature is 220 ° C. or higher, 280 ° C. or higher, or 350 ° C. or higher, and the level density of nitrogen oxide is low between Ev_os and Ec_os by using a PECVD method using silane and dinitrogen monoxide. By forming the material insulating film, a dense and high hardness film can be formed.

The insulating film 116 is formed using an oxide insulating film containing more oxygen than that in the stoichiometric composition. Part of oxygen is released by heating from the oxide insulating film containing oxygen in excess of that in the stoichiometric composition. An oxide insulating film containing oxygen in excess of the stoichiometric composition has an oxygen desorption amount of 1.0 × 10 ¹⁹ atoms / cm ³ or more in terms of oxygen atoms in TDS analysis. The oxide insulating film is preferably 3.0 × 10 ²⁰ atoms / cm ³ or more. The surface substrate temperature of the film at the time of TDS analysis is preferably in the range of 100 ° C. to 700 ° C., or 100 ° C. to 500 ° C.

As the insulating film 116, silicon oxide, silicon oxynitride, or the like with a thickness of 30 nm to 500 nm, preferably 50 nm to 400 nm can be used.

The insulating film 116 preferably has a small amount of defects. Typically, the ESR measurement shows that the spin density of a signal appearing at g = 2.001 derived from a dangling bond of silicon is 1.5 × 10 ^18. It is preferably less than spins / cm ³ and more preferably 1 × 10 ¹⁸ spins / cm ³ or less. Note that the insulating film 116 is farther from the oxide semiconductor film 108 than the insulating film 114, and thus has a higher defect density than the insulating film 114.

In addition, since the insulating films 114 and 116 can be formed using the same kind of insulating film, the interface between the insulating film 114 and the insulating film 116 may not be clearly confirmed. Therefore, in this embodiment mode, the interface between the insulating film 114 and the insulating film 116 is indicated by a broken line. Note that although a two-layer structure of the insulating film 114 and the insulating film 116 has been described in this embodiment mode, the present invention is not limited thereto, and for example, a single-layer structure of the insulating film 114 may be employed.

The insulating film 118 includes nitrogen. The insulating film 118 includes nitrogen and silicon. The insulating film 118 has a function of blocking oxygen, hydrogen, water, alkali metal, alkaline earth metal, or the like. By providing the insulating film 118, diffusion of oxygen from the oxide semiconductor film 108 to the outside, diffusion of oxygen contained in the insulating films 114 and 116, hydrogen from the outside to the oxide semiconductor film 108, Ingress of water and the like can be prevented. As the insulating film 118, for example, a nitride insulating film can be used. Examples of the nitride insulating film include silicon nitride, silicon nitride oxide, aluminum nitride, and aluminum nitride oxide. Note that an oxide insulating film having a blocking effect of oxygen, hydrogen, water, or the like may be provided instead of the nitride insulating film having a blocking effect of oxygen, hydrogen, water, alkali metal, alkaline earth metal, or the like. Examples of the oxide insulating film having a blocking effect of oxygen, hydrogen, water, and the like include aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, and hafnium oxynitride.

<Protective film>
The protective film 117 includes at least one metal element which is the same as that of the oxide semiconductor film 108. For example, in the case where the oxide semiconductor film 108 includes oxygen, In, Zn, and M (M is Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf), the protective film 117 is formed. Has at least one element selected from In, Zn, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf. In particular, the protective film 117 is preferably formed using In—Sn oxide, In—Zn oxide, In—Ga oxide, Zn oxide, Al—Zn oxide, or In—Ga—Zn oxide.

  In the case where an In—Ga—Zn oxide is used as the oxide semiconductor film 108, the protective film 117 preferably includes at least Ga. In the case where an In—Ga—Zn oxide is used as the oxide semiconductor film 108, the protective film 117 preferably includes at least Zn. Further, in the case where an In—Ga—Zn oxide is used as the oxide semiconductor film 108, the protective film 117 preferably includes at least Ga and Zn.

Further, when the protective film 117 is thin, the function of suppressing the release of oxygen is deteriorated. On the other hand, when the protective film 117 is thick, it is difficult for oxygen to pass through the protective film 117 during the oxygen addition process. Therefore, the thickness of the protective film 117 is 3 nm to 30 nm, preferably 5 nm to 15 nm. The protective film 117 preferably has crystallinity. For example, in the case where an In—Ga—Zn oxide is used as the protective film 117 and the In—Ga—Zn oxide is a CAAC-OS film described later, release of oxygen added to the insulating film 116 is preferably suppressed. Can do. The protective film 117 preferably has a higher resistivity. When the resistivity of the protective film 117 is low, parasitic capacitance may be formed between the conductive films 112a and 112b. The resistivity of the protective film 117 may be, for example, 10 ¹⁰ Ωcm or more and less than 10 ¹⁸ Ωcm.

Note that various films such as the conductive film, the insulating film, the protective film, and the oxide semiconductor film described above can be formed by a sputtering method or a PECVD method, but other methods, for example, thermal CVD (Chemical Vapor) are used. You may form by the Deposition method. As an example of the thermal CVD method, an MOCVD (Metal Organic Chemical Deposition) method or an ALD (Atomic Layer Deposition) method may be used.

The thermal CVD method has an advantage that no defect is generated due to plasma damage because it is a film forming method that does not use plasma.

  In the thermal CVD method, film formation may be performed by sending a source gas and an oxidant into the chamber at the same time, making the inside of the chamber under atmospheric pressure or reduced pressure, reacting in the vicinity of the substrate or on the substrate and depositing on the substrate. .

In addition, in the ALD method, film formation may be performed by setting the inside of the chamber to atmospheric pressure or reduced pressure, sequentially introducing source gases for reaction into the chamber, and repeating the order of introducing the gases. For example, each switching valve (also referred to as a high-speed valve) is switched to supply two or more types of source gases to the chamber in order, so that a plurality of types of source gases are not mixed with the first source gas at the same time or thereafter. An active gas (such as argon or nitrogen) is introduced, and a second source gas is introduced. When the inert gas is introduced at the same time, the inert gas becomes a carrier gas, and the inert gas may be introduced at the same time when the second raw material gas is introduced. Further, instead of introducing the inert gas, the second raw material gas may be introduced after the first raw material gas is exhausted by evacuation. The first source gas is adsorbed on the surface of the substrate to form a first layer, reacts with a second source gas introduced later, and the second layer is stacked on the first layer. As a result, a thin film is formed. By repeating this gas introduction sequence a plurality of times until the desired thickness is achieved, a thin film having excellent step coverage can be formed. Since the thickness of the thin film can be adjusted by the number of times the gas introduction sequence is repeated, precise film thickness adjustment is possible, which is suitable for manufacturing a fine transistor.

The thermal CVD method such as the MOCVD method or the ALD method can form various films such as the conductive film, the insulating film, the oxide semiconductor film, and the metal oxide film of the above-described embodiment, for example, an In—Ga—ZnO film. Is used, trimethylindium, trimethylgallium, and dimethylzinc are used. Note that the chemical formula of trimethylindium is In (CH ₃ ) ₃ . The chemical formula of trimethylgallium is Ga (CH ₃ ) ₃ . The chemical formula of dimethylzinc is Zn (CH ₃ ) ₂ . Moreover, it is not limited to these combinations, Triethylgallium (chemical formula Ga (C ₂ H ₅ ) ₃ ) can be used instead of trimethylgallium, and diethylzinc (chemical formula Zn (C ₂ H ₅ ) is used instead of dimethylzinc. ₂ ) can also be used.

For example, when a hafnium oxide film is formed by a film forming apparatus using ALD, a liquid containing a solvent and a hafnium precursor compound (hafnium alkoxide solution, typically tetrakisdimethylamide hafnium (TDMAH)) is vaporized. Two kinds of gases, that is, source gas and ozone (O ₃ ) as an oxidizing agent are used. Note that the chemical formula of tetrakisdimethylamide hafnium is Hf [N (CH ₃ ) ₂ ] ₄ . Other material liquids include tetrakis (ethylmethylamide) hafnium.

For example, in the case where an aluminum oxide film is formed by a film forming apparatus using ALD, a source gas obtained by vaporizing a liquid (such as trimethylaluminum (TMA)) containing a solvent and an aluminum precursor compound, and H ₂ as an oxidizing agent. Two kinds of gases of O are used. Note that the chemical formula of trimethylaluminum is Al (CH ₃ ) ₃ . Other material liquids include tris (dimethylamido) aluminum, triisobutylaluminum, aluminum tris (2,2,6,6-tetramethyl-3,5-heptanedionate) and the like.

For example, in the case where a silicon oxide film is formed by a film forming apparatus using ALD, hexachlorodisilane is adsorbed on a film formation surface, chlorine contained in the adsorbed material is removed, and an oxidizing gas (O ₂ , N _{2 is used).} O) radicals are supplied to react with the adsorbate.

For example, in the case where a tungsten film is formed by a film forming apparatus using ALD, an initial tungsten film is formed by repeatedly introducing WF ₆ gas and B ₂ H ₆ gas successively, and then WF ₆ gas and H _2. Gases are simultaneously introduced to form a tungsten film. Note that SiH ₄ gas may be used instead of B ₂ H ₆ gas.

For example, in the case where an oxide semiconductor film such as an In—Ga—ZnO film is formed by a film formation apparatus using ALD, In (CH ₃ ) ₃ gas and O ₃ gas are sequentially introduced and In—O is sequentially introduced. Then, Ga (CH ₃ ) ₃ gas and O ₃ gas are simultaneously introduced to form a GaO layer, and then Zn (CH ₃ ) ₂ and O ₃ gas are simultaneously introduced to form a ZnO layer. To do. Note that the order of these layers is not limited to this example. Alternatively, a mixed compound layer such as an In—Ga—O layer, an In—Zn—O layer, or a Ga—Zn—O layer may be formed by mixing these gases. Incidentally, instead of the O ₃ gas may be used the H _{2 O} gas obtained by bubbling with an inert gas such as Ar, but better to use an O ₃ gas containing no H are preferred. In addition, In (C ₂ H ₅ ) ₃ gas may be used instead of In (CH ₃ ) ₃ gas. Further, Ga (C ₂ H ₅ ) ₃ gas may be used instead of Ga (CH ₃ ) ₃ gas. Alternatively, Zn (CH3) ₂ gas may be used.

<Method 1 for Manufacturing Semiconductor Device>
Next, a method for manufacturing the transistor 100 which is a semiconductor device of one embodiment of the present invention will be described in detail with reference to FIGS. 4 to 6 are cross-sectional views illustrating a method for manufacturing a semiconductor device.

Note that a film included in the transistor 100 (an insulating film, an oxide semiconductor film, a conductive film, or the like) is formed by a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, or a pulsed laser deposition (PLD) method. can do. Alternatively, it can be formed by a coating method or a printing method. As a film forming method, a sputtering method and a plasma enhanced chemical vapor deposition (PECVD) method are typical, but a thermal CVD method may be used. As an example of the thermal CVD method, an MOCVD (metal organic chemical deposition) method or an ALD (atomic layer deposition) method may be used.

First, a conductive film is formed over the substrate 102, and the conductive film is processed by a lithography process and an etching process, so that the conductive film 104 functioning as a gate electrode is formed. Next, insulating films 106 and 107 functioning as gate insulating films are formed over the conductive film 104 (see FIG. 4A).

The conductive film 104 functioning as a gate electrode can be formed by a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, or a pulsed laser deposition (PLD) method. Alternatively, it can be formed by a coating method or a printing method. As a film formation method, a sputtering method or a plasma enhanced chemical vapor deposition (PECVD) method is typical, but a thermal CVD method such as the metal organic chemical vapor deposition (MOCVD) method described above, or an atomic layer deposition ( (ALD) method may be used.

In this embodiment, a glass substrate is used as the substrate 102, and a tungsten film with a thickness of 100 nm is formed as the conductive film 104 functioning as a gate electrode by a sputtering method.

The insulating films 106 and 107 functioning as gate insulating films can be formed by a sputtering method, a PECVD method, a thermal CVD method, a vacuum evaporation method, a PLD method, or the like. In this embodiment, a 400-nm-thick silicon nitride film is formed as the insulating film 106 and a 50-nm-thick silicon oxynitride film is formed as the insulating film 107 by PECVD.

Note that the insulating film 106 can have a stacked structure of silicon nitride films. Specifically, the insulating film 106 can have a three-layer structure including a first silicon nitride film, a second silicon nitride film, and a third silicon nitride film. As an example of the three-layer structure, it can be formed as follows.

As the first silicon nitride film, for example, silane having a flow rate of 200 sccm, nitrogen having a flow rate of 2000 sccm, and ammonia gas having a flow rate of 100 sccm are supplied as source gases to the reaction chamber of the PE-CVD apparatus, and the pressure in the reaction chamber is controlled to 100 Pa. Then, a power of 2000 W may be supplied using a 27.12 MHz high frequency power source so that the thickness is 50 nm.

As the second silicon nitride film, silane having a flow rate of 200 sccm, nitrogen having a flow rate of 2000 sccm, and ammonia gas having a flow rate of 2000 sccm are supplied as source gases to the reaction chamber of the PECVD apparatus, and the pressure in the reaction chamber is controlled to 100 Pa; A thickness of 300 nm may be formed by supplying 2000 W of power using a 12 MHz high frequency power source.

As the third silicon nitride film, silane having a flow rate of 200 sccm and nitrogen having a flow rate of 5000 sccm are supplied as source gases to the reaction chamber of the PECVD apparatus, the pressure in the reaction chamber is controlled to 100 Pa, and a high frequency power source of 27.12 MHz is used. Then, the power may be formed so as to have a thickness of 50 nm by supplying power of 2000 W.

Note that the substrate temperature at the time of forming the first silicon nitride film, the second silicon nitride film, and the third silicon nitride film can be 350 ° C.

When the insulating film 106 has a three-layer structure of a silicon nitride film, for example, when a conductive film containing copper (Cu) is used for the conductive film 104, the following effects can be obtained.

The first silicon nitride film can suppress diffusion of copper (Cu) element from the conductive film 104. The second silicon nitride film has a function of releasing hydrogen and can improve the withstand voltage of the insulating film functioning as a gate insulating film. The third silicon nitride film emits less hydrogen from the third silicon nitride film and can suppress diffusion of hydrogen released from the second silicon nitride film.

  The insulating film 107 is preferably formed using an insulating film containing oxygen in order to improve interface characteristics with the oxide semiconductor film 108 to be formed later.

Next, the oxide semiconductor film 108 is formed over the insulating film 107 (see FIG. 4B).

In this embodiment, an oxide semiconductor film is formed by a sputtering method using an In—Ga—Zn metal oxide target (In: Ga: Zn = 1: 1: 1.2 (atomic ratio)). A mask is formed over the oxide semiconductor film by a lithography process, and the oxide semiconductor film is processed into a desired region, whereby the island-shaped oxide semiconductor film 108 is formed.

After the oxide semiconductor film 108 is formed, heat treatment may be performed at 150 ° C. or higher and lower than the strain point of the substrate, preferably 200 ° C. or higher and 450 ° C. or lower, more preferably 300 ° C. or higher and 450 ° C. or lower. The heat treatment here is one of purification treatments of the oxide semiconductor film, and hydrogen, water, and the like contained in the oxide semiconductor film 108 can be reduced. Note that heat treatment for reducing hydrogen, water, and the like may be performed before the oxide semiconductor film 108 is processed into an island shape.

For the heat treatment of the oxide semiconductor film 108, an electric furnace, an RTA apparatus, or the like can be used. By using the RTA apparatus, heat treatment can be performed at a temperature equal to or higher than the strain point of the substrate for a short time. Therefore, it is possible to shorten the heating time.

Note that heat treatment of the oxide semiconductor film 108 is performed using nitrogen, oxygen, ultra-dry air (air with a water content of 20 ppm or less, preferably 1 ppm or less, preferably 10 ppb or less), or a rare gas (argon, helium, or the like). ). Note that it is preferable that hydrogen, water, and the like be not contained in the nitrogen, oxygen, ultra-dry air, or the rare gas. Further, after heat treatment in a nitrogen or rare gas atmosphere, the heat treatment may be performed in an oxygen or ultra-dry air atmosphere. As a result, hydrogen, water, and the like contained in the oxide semiconductor film can be eliminated and oxygen can be supplied into the oxide semiconductor film. As a result, the amount of oxygen vacancies contained in the oxide semiconductor film can be reduced.

Note that when the oxide semiconductor film 108 is formed by a sputtering method, a rare gas (typically argon), oxygen, a rare gas, and a mixed gas of oxygen are used as appropriate as the sputtering gas. In the case of a mixed gas, it is preferable to increase the oxygen gas ratio relative to the rare gas. In addition, it is necessary to increase the purity of the sputtering gas. For example, oxygen gas or argon gas used as a sputtering gas is a gas having a dew point of −40 ° C. or lower, preferably −80 ° C. or lower, more preferably −100 ° C. or lower, more preferably −120 ° C. or lower. By using it, moisture and the like can be prevented from being taken into the oxide semiconductor film 108 as much as possible.

In the case where the oxide semiconductor film 108 is formed by a sputtering method, an adsorption vacuum exhaust pump such as a cryopump is used as a chamber in the sputtering apparatus so as to remove water or the like that is an impurity for the oxide semiconductor film 108 as much as possible. It is preferable to perform high vacuum evacuation (from about 5 × 10 ⁻⁷ Pa to about 1 × 10 ⁻⁴ Pa) using Alternatively, it is preferable to combine a turbo molecular pump and a cold trap so that a gas, particularly a gas containing carbon or hydrogen, does not flow backward from the exhaust system into the chamber.

Next, conductive films 112a and 112b functioning as a source electrode and a drain electrode are formed over the insulating film 107 and the oxide semiconductor film 108 (see FIG. 4C).

In this embodiment, as the conductive films 112a and 112b, a stacked film of a tungsten film with a thickness of 50 nm and an aluminum film with a thickness of 400 nm is formed by a sputtering method, and a mask is formed over the stacked film by a lithography process. Then, the conductive films 112a and 112b are formed by processing the laminated film into a desired region. Note that although a two-layer structure of the conductive films 112a and 112b is used in this embodiment mode, the present invention is not limited to this. For example, the conductive films 112a and 112b may have a three-layer structure of a tungsten film with a thickness of 50 nm, an aluminum film with a thickness of 400 nm, and a titanium film with a thickness of 100 nm.

Alternatively, the surface (back channel side) of the oxide semiconductor film 108 may be washed after the conductive films 112a and 112b are formed. Examples of the cleaning method include cleaning using a chemical solution such as phosphoric acid. By performing cleaning with a chemical solution such as phosphoric acid, impurities attached to the surface of the oxide semiconductor film 108 (for example, elements included in the conductive films 112a and 112b) can be removed.

Note that although not illustrated, a recess may be formed in part of the oxide semiconductor film 108 when the conductive films 112a and 112b are formed and / or in the cleaning step.

Through the above process, the transistor 100 is formed.

Next, insulating films 114 and 116 are formed over the transistor 100, specifically, over the oxide semiconductor film 108 and the conductive films 112a and 112b of the transistor 100 (see FIG. 4D).

Note that after the insulating film 114 is formed, the insulating film 116 is preferably formed continuously without being exposed to the air. After forming the insulating film 114, the insulating film 114 and the insulating film are formed by continuously forming the insulating film 116 by adjusting one or more of the flow rate, pressure, high frequency power, and substrate temperature of the source gas without opening to the atmosphere. The concentration of impurities derived from atmospheric components can be reduced at the interface 116, and oxygen contained in the insulating films 114 and 116 can be transferred to the oxide semiconductor film 108, so that the amount of oxygen vacancies in the oxide semiconductor film 108 can be reduced. Can be reduced.

For example, as the insulating film 114, a silicon oxynitride film can be formed by a PECVD method. In this case, it is preferable to use a deposition gas and an oxidation gas containing silicon as the source gas. Typical examples of the deposition gas containing silicon include silane, disilane, trisilane, and fluorinated silane. Examples of the oxidizing gas include dinitrogen monoxide and nitrogen dioxide. Further, by using a PECVD method in which the oxidizing gas with respect to the depositing gas is greater than 20 times and less than 100 times, preferably 40 times or more and 80 times or less, and the pressure in the processing chamber is less than 100 Pa, preferably 50 Pa or less. The insulating film 114 is an insulating film containing nitrogen and having a small amount of defects.

In this embodiment mode, as the insulating film 114, the temperature at which the substrate 102 is held is 220 ° C., silane with a flow rate of 50 sccm and dinitrogen monoxide with a flow rate of 2000 sccm are used as source gases, the pressure in the processing chamber is 20 Pa, and parallel plates A silicon oxynitride film is formed by a PECVD method in which high-frequency power supplied to the electrode is 13.56 MHz and 100 W (power density is 1.6 × 10 ⁻² W / cm ² ).

As the insulating film 116, a substrate placed in a processing chamber evacuated by a PECVD apparatus is held at 180 ° C. or higher and 280 ° C. or lower, more preferably 200 ° C. or higher and 240 ° C. or lower, and a source gas is introduced into the processing chamber. 100Pa above the pressure in the processing chamber Te 250Pa or less, more preferably not more than 200Pa above 100Pa, processing electrode provided indoors 0.17 W / cm ² or more 0.5 W / cm ² or less, more preferably 0.25 W / cm ^A silicon oxide film or a silicon oxynitride film is formed under conditions for supplying high-frequency power of ^{2 to} 0.35 W / cm ² .

As the conditions for forming the insulating film 116, by supplying high-frequency power with the above power density in the reaction chamber at the above pressure, the decomposition efficiency of the source gas in plasma increases, oxygen radicals increase, and the oxidation of the source gas proceeds. Therefore, the oxygen content in the insulating film 116 is higher than the stoichiometric composition. On the other hand, in a film formed at the above substrate temperature, since the bonding force between silicon and oxygen is weak, part of oxygen in the film is released by heat treatment in a later step. As a result, an oxide insulating film containing more oxygen than that in the stoichiometric composition and from which part of oxygen is released by heating can be formed.

Note that in the formation process of the insulating film 116, the insulating film 114 serves as a protective film of the oxide semiconductor film 108. Therefore, the insulating film 116 can be formed using high-frequency power with high power density while reducing damage to the oxide semiconductor film 108.

Note that the amount of defects in the insulating film 116 can be reduced by increasing the flow rate of the deposition gas containing silicon with respect to the oxidizing gas under the deposition conditions of the insulating film 116. Typically, by ESR measurement, the spin density of a signal appearing at g = 2.001 derived from a dangling bond of silicon is less than 6 × 10 ¹⁷ spins / cm ³ , preferably 3 × 10 ¹⁷ spins / cm ³ or less. An oxide insulating layer with a small amount of defects that is preferably 1.5 × 10 ¹⁷ spins / cm ³ or less can be formed. As a result, the reliability of the transistor can be improved.

In addition, since the insulating films 114 and 116 are formed along the side surfaces of the conductive films 112a and 112b, unevenness is formed on the surfaces thereof.

Further, heat treatment may be performed after the insulating films 114 and 116 are formed. By the heat treatment, nitrogen oxides contained in the insulating films 114 and 116 can be reduced. Further, part of oxygen contained in the insulating films 114 and 116 is moved to the oxide semiconductor film 108 by the heat treatment, so that the amount of oxygen vacancies contained in the oxide semiconductor film 108 can be reduced.

The temperature of heat treatment for the insulating films 114 and 116 is typically 150 ° C to 400 ° C, preferably 300 ° C to 400 ° C, preferably 320 ° C to 370 ° C. The heat treatment may be performed in an atmosphere of nitrogen, oxygen, ultra-dry air (air with a water content of 20 ppm or less, preferably 1 ppm or less, preferably 10 ppb or less), or a rare gas (such as argon or helium). Note that an electric furnace, an RTA apparatus, or the like can be used for the heat treatment in which hydrogen, water, or the like is preferably not contained in the nitrogen, oxygen, ultradry air, or the rare gas.

In this embodiment, heat treatment is performed at 350 ° C. for one hour in a nitrogen atmosphere.

Next, a protective film 117 is formed over the insulating film 116. The protective film 117 is formed so as to cover the uneven surface of the insulating films 114 and 116. (See FIG. 5A).

In this embodiment, an In—Ga—Zn oxide (In: Ga: Zn = 1: 3: 2 [atomic%]) with a thickness of 5 nm is formed as the protective film 117 by a sputtering method. In the case where the protective film 117 is formed by a sputtering method, it is preferable to use oxygen as a deposition gas and increase the oxygen ratio in the deposition gas. For example, in the case where an In—Ga—Zn oxide (In: Ga: Zn = 1: 3: 2 [atomic%]) is formed, oxygen is used as a deposition gas and sputtering is performed in an atmosphere containing 100% oxygen. Can do. By increasing the oxygen ratio in the deposition gas, the protective film 117 has excess oxygen. When the protective film 117 has excess oxygen, oxygen added to the protective film 117 is reduced when oxygen is added later, so that oxygen can be effectively passed through the insulating films 114 and 116.

Next, oxygen 141 is added to the insulating films 114 and 116 and the oxide semiconductor film 108 through the protective film 117 (see FIG. 5B).

As a method for adding oxygen 141 to the insulating films 114 and 116 and the oxide semiconductor film 108 through the protective film 117, there are an ion doping method, an ion implantation method, a plasma treatment method, and the like. Further, when the oxygen 141 is added, the oxygen 141 can be effectively added to the insulating films 114 and 116 and the oxide semiconductor film 108 by applying a bias to the substrate side. As the bias, for example, the power density may be 1 W / cm ² or more and 5 W / cm ² or less. By providing the protective film 117 over the insulating film 116 and adding oxygen, the protective film 117 functions as a protective film that suppresses release of oxygen from the insulating film 116. Therefore, more oxygen can be added to the insulating films 114 and 116 and the oxide semiconductor film 108.

In addition, when oxygen is introduced by plasma treatment, the amount of oxygen introduced into the insulating films 114 and 116 can be increased by exciting oxygen with a microwave to generate high-density oxygen plasma.

Here, FIGS. 6A and 6B are cross-sectional views different from those shown in FIG. 5B when oxygen 141 is added.

6A and 6B illustrate part of a semiconductor device formed through the same manufacturing process as the transistor 100. FIG. 6A and 6B includes an insulating film 106 over a substrate 102, an insulating film 107 over an insulating film 106, a conductive film 112c over an insulating film 107, and an insulating film 107 and a conductive film 112c. The upper insulating film 114, the insulating film 116 on the insulating film 114, and the protective film 117 on the insulating film 116 are included.

FIG. 6A illustrates the case where the protective film 117 is formed so as to cover the uneven surface formed in the insulating films 114 and 116, and FIG. 6B illustrates the protective film 117 as the insulating film 114. , 116 is illustrated as not covering the uneven surface.

More specifically, in FIG. 6A, since the protective film 117 is formed along the surface unevenness of the insulating films 114 and 116 formed of the conductive film 112c, the oxygen 141 is added. In addition, desorption of oxygen from the insulating films 114 and 116 can be suppressed. On the other hand, in FIG. 6B, since the protective film 117 is not formed along the surface unevenness of the insulating films 114 and 116 formed of the conductive film 112c, the region illustrated in FIG. From 144, oxygen is desorbed.

Note that in the structure illustrated in FIG. 6B, when the coverage of the protective film 117 is poor or when the oxygen 141 is added, the protective film 117 and part of the end portions of the insulating film 116 are cut away. Thus, the region 144 may be formed. For example, in the case where a highly conductive metal film (silver, copper, aluminum, titanium, tantalum, molybdenum, or the like) is used as the protective film 117, the protective film 117 is protected by a bias applied to the substrate 102 side when the oxygen 141 is added. In some cases, an electric field concentration occurs at an end portion of the film 117, and a part of the insulating films 114 and 116 and the protective film 117 is removed. Therefore, as in one embodiment of the present invention, the protective film 117 includes at least one metal element which is the same as that of the oxide semiconductor film 108, whereby the electric field concentration can be reduced.

Therefore, as illustrated in FIG. 6A, the protective film 117 is preferably formed to cover the uneven surface of the insulating films 114 and 116.

Next, the insulating film 118 is formed over the protective film 117 (see FIG. 5C).

Note that heat treatment is performed before the insulating film 118 is formed or after the insulating film 118 is formed, so that excess oxygen contained in the insulating films 114 and 116 is diffused into the oxide semiconductor film 108. Oxygen deficiency can be compensated. Alternatively, when the insulating film 118 is formed by heating, excess oxygen contained in the insulating films 114 and 116 can be diffused into the oxide semiconductor film 108 to fill oxygen vacancies in the oxide semiconductor film 108. . At this time, the protective film 117 suppresses oxygen contained in the insulating films 114 and 116 from diffusing outside.

In the case where the insulating film 118 is formed by a PECVD method, it is preferable that the substrate temperature be 300 ° C. or higher and 400 ° C. or lower, preferably 320 ° C. or higher and 370 ° C. or lower because a dense film can be formed.

For example, in the case where a silicon nitride film is formed as the insulating film 118 by a PECVD method, it is preferable to use a deposition gas containing silicon, nitrogen, and ammonia as a source gas. By using a small amount of ammonia as compared with nitrogen, ammonia is dissociated in the plasma and active species are generated. The active species breaks the bond between silicon and hydrogen contained in the deposition gas containing silicon and the triple bond of nitrogen. As a result, the bonding between silicon and nitrogen is promoted, the bonding between silicon and hydrogen is small, the defects are few, and a dense silicon nitride film can be formed. On the other hand, when the amount of ammonia with respect to nitrogen is large, decomposition of the deposition gas containing silicon and nitrogen does not proceed, and silicon and hydrogen bonds remain, resulting in an increased defect and a rough silicon nitride film. End up. For these reasons, in the source gas, the flow rate ratio of nitrogen to ammonia is preferably 5 or more and 50 or less and 10 or more and 50 or less.

In this embodiment, as the insulating film 118, a silicon nitride film with a thickness of 50 nm is formed from a source gas of silane, nitrogen, and ammonia using a PECVD apparatus. The flow rates are 50 sccm for silane, 5000 sccm for nitrogen, and 100 sccm for ammonia. The processing chamber pressure is 100 Pa, the substrate temperature is 350 ° C., and high frequency power of 1000 W is supplied to the parallel plate electrodes using a high frequency power source of 27.12 MHz. The PECVD apparatus is a parallel plate type PECVD apparatus having an electrode area of 6000 cm ^{2. When} the supplied power is converted into power per unit area (power density), it is 1.7 × 10 ⁻¹ W / cm ² .

Further, heat treatment may be performed after the insulating film 118 is formed. The temperature of the heat treatment is typically 150 ° C to 400 ° C, preferably 300 ° C to 400 ° C, preferably 320 ° C to 370 ° C. When the heat treatment is performed, hydrogen and water in the insulating films 114 and 116 are reduced, so that generation of defects in the oxide semiconductor film 108 as described above is suppressed.

Through the above steps, the semiconductor device illustrated in FIG. 1 can be manufactured.

Note that the structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 2)
In this embodiment, a method for decomposing a semiconductor device having a display function (also referred to as a display device) manufactured using the transistor described as an example in Embodiment 1 and measuring residual oxygen is described. To do.

First, the structure of the display device to be disassembled will be described with reference to FIGS. FIG. 7A is a plan view of the display device. FIG. 7B is a cross-sectional view illustrating a cross-sectional structure of a portion indicated by an alternate long and short dash line in FIG. 7A.

Note that a display device in this specification means an image display device or a light source (including a lighting device). In addition, a connector, for example, a module to which an FPC or TCP is attached, a module in which a printed wiring board is provided at the end of TCP, or a module in which an IC (integrated circuit) is directly mounted on the display element by the COG method is all included in the display device. Shall be included.

The pixel portion and the scan line driver circuit provided over the first substrate include a plurality of transistors, and the transistors described in the above embodiments can be used.

As a display element provided in the display device, a liquid crystal element (also referred to as a liquid crystal display element) or a light-emitting element (also referred to as a light-emitting display element) can be used. The light emitting element includes, in its category, an element whose luminance is controlled by current or voltage, and specifically includes an inorganic EL (Electro Luminescence) element, an organic EL element, and the like. In addition, a display medium whose contrast is changed by an electric effect, such as electronic ink, can be used.

FIG. 7B illustrates an example of a liquid crystal display device using a liquid crystal element as a display element. FIG. 7B illustrates an example in which a vertical electric field method is employed.

The display device illustrated in FIG. 7B includes a connection terminal electrode 915 and a terminal electrode 916. The connection terminal electrode 915 and the terminal electrode 916 are electrically connected to each other through a terminal included in the FPC 918 and an anisotropic conductive agent 919. Connected.

The connection terminal electrode 915 is formed using the same conductive film as the first electrode 930, and the terminal electrode 916 is formed using the same conductive film as the pair of electrodes of the transistors 910 and 911.

In addition, the pixel portion 902 and the scan line driver circuit 904 provided over the first substrate 901 include a plurality of transistors. In FIG. 7B, the transistor 910 included in the pixel portion 902 and the scan circuit are scanned. A transistor 911 included in the line driver circuit 904 is illustrated. In FIG. 7B, an insulating film 924 containing excess oxygen and an insulating film 926 functioning as a protective film are provided over the transistors 910 and 911. The insulating film 924 can have two layers as described in the method for manufacturing the semiconductor device in Embodiment 1. The same applies to the insulating film 926. Note that the insulating film 923 is an insulating film functioning as a base film.

In this embodiment, the transistor described in any of the above embodiments can be used as the transistors 910 and 911.

A transistor 910 provided in the pixel portion 902 is electrically connected to a display element to form a display panel. The display element is not particularly limited as long as display can be performed, and various display elements can be used.

In the first electrode and the second electrode (also referred to as a pixel electrode, a common electrode, a counter electrode, or the like) for applying a voltage to the display element, the transmission direction depends on the direction of light to be extracted, the position where the electrode is provided, and the electrode pattern structure. What is necessary is just to select light property and reflectivity.

The first electrode 930 and the second electrode 931 include indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, and indium tin oxide. A light-transmitting conductive material such as a material (hereinafter referred to as ITO), indium zinc oxide, or indium tin oxide to which silicon oxide is added can be used.

The first electrode 930 and the second electrode 931 include tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), Metals such as chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), silver (Ag), or alloys thereof, or metals thereof One or more kinds of nitrides can be used.

The first electrode 930 and the second electrode 931 can be formed using a conductive composition including a conductive high molecule (also referred to as a conductive polymer). As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, a copolymer of two or more of aniline, pyrrole, and thiophene or a derivative thereof can be given.

In FIG. 7B, a liquid crystal element 913 that is a display element includes a first electrode 930, a second electrode 931, and a liquid crystal layer 908. Note that an insulating film 932 and an insulating film 933 which function as alignment films are provided so as to sandwich the liquid crystal layer 908. The second electrode 931 is provided on the second substrate 906 side, and the first electrode 930 and the second electrode 931 overlap with each other with the liquid crystal layer 908 interposed therebetween.

The spacer 935 is a columnar spacer obtained by selectively etching the insulating film, and is provided to control the distance (cell gap) between the first electrode 930 and the second electrode 931. . A spherical spacer may be used.

When a liquid crystal element is used as the display element, a thermotropic liquid crystal, a low molecular liquid crystal, a polymer liquid crystal, a polymer dispersed liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, or the like can be used. These liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, and the like depending on conditions.

Alternatively, a liquid crystal exhibiting a blue phase for which an alignment film is unnecessary may be used. The blue phase is one of the liquid crystal phases. When the temperature of the cholesteric liquid crystal is increased, the blue phase appears immediately before the transition from the cholesteric phase to the isotropic phase. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with a chiral agent is used for the liquid crystal layer in order to improve the temperature range. Since it is optically isotropic, no alignment treatment is required and the viewing angle dependency is small. Further, since it is not necessary to provide an alignment film, a rubbing process is not required, so that electrostatic breakdown caused by the rubbing process can be prevented, and defects or breakage of the liquid crystal display device during the manufacturing process can be reduced. . Therefore, the productivity of the liquid crystal display device can be improved.

The first substrate 901 and the second substrate 906 are fixed with a sealant 925. As the sealant 925, an organic resin such as a thermosetting resin or a photocurable resin can be used.

Note that in the liquid crystal display device illustrated in FIG. 7B, the sealant 925 is in contact with the gate insulating film 922, and the planarization film 921 is provided inside the sealant 925. Note that the gate insulating film 922 is formed by stacking a silicon nitride film and a silicon oxynitride film. In addition, when the insulating film 924 is selectively etched, the silicon oxynitride film over the gate insulating film 922 is preferably etched to expose the silicon nitride film. As a result, the sealant 925 and the silicon nitride film formed on the gate insulating film 922 are in contact with each other, so that water from the outside can be prevented from entering the sealant 925.

The size of the storage capacitor provided in the liquid crystal display device is set so that charges can be held for a predetermined period in consideration of a leakage current of a transistor arranged in the pixel portion. By using a transistor including a high-purity oxide semiconductor film, it is sufficient to provide a storage capacitor having a capacity of 1/3 or less, preferably 1/5 or less of the liquid crystal capacity of each pixel. Therefore, the aperture ratio in the pixel can be increased.

In the display device, a black matrix (light-shielding film), a polarizing member, a retardation member, an optical member (an optical substrate) such as an antireflection member, and the like are provided as appropriate. For example, circularly polarized light using a polarizing substrate and a retardation substrate may be used. Further, a backlight, a sidelight, or the like may be used as the light source.

As a display method in the pixel portion, a progressive method, an interlace method, or the like can be used. Further, the color elements controlled by pixels when performing color display are not limited to three colors of RGB (R represents red, G represents green, and B represents blue). For example, there is RGBW (W represents white) or RGB in which one or more colors of yellow, cyan, magenta, etc. are added. The size of the display area may be different for each dot of the color element. However, the present invention is not limited to a display device for color display, and can also be applied to a display device for monochrome display.

Hereafter, a procedure for disassembling the display device having the above-described structure, which is one embodiment of the present invention, to produce a TDS analysis sample will be described with reference to FIGS.

First, a thin metal plate, for example, the tip of a cutter knife, is inserted into the vicinity of the sealant 925 where the substrate 901 and the substrate 906 are bonded together, and then opened to remove the first substrate 901 and the second substrate 906. Remove. As another method, there is a method of etching a sealing material using a chemical solution or plasma. The second substrate 906 includes a second electrode 931, an insulating film 933 functioning as one alignment film, a liquid crystal element 913, and the like (see FIG. 8).

The peeled outermost surface of the pixel portion 902 of the first substrate 901 has the insulating film 932 functioning as one alignment film. For example, an insulating film containing an organic resin can be easily removed by a plasma etching method using oxygen gas as the insulating film 932. Depending on the components of the insulating film, another gas such as carbon tetrafluoride gas may be added to the oxygen gas as appropriate (see FIG. 9).

After the insulating film 932 is removed, the outermost surface of the pixel portion 902 of the first substrate 901 becomes the first electrode 930. If the first electrode 930 is a transparent conductive film such as ITO or GZO, the first electrode 930 can be removed by a wet etching method using a chemical solution containing oxalic acid as a main component. In the case where the first electrode 930 is a metal such as tantalum, tungsten, aluminum, or titanium, or a metal nitride such as tantalum nitride, tungsten nitride, or titanium nitride, chlorine gas, boron trichloride gas, or carbon tetrafluoride gas is used. Or may be removed using a plasma etching method using a gas obtained by mixing two or more of these gases (see FIG. 10).

After the first electrode 930 is removed, the top surface of the pixel portion of the first substrate 901 becomes an insulating film of a capacitor element, although not shown. As the insulating film of the capacitor element, for example, a silicon nitride film or a silicon nitride oxide film can be removed by a dry etching method using sulfur hexafluoride gas. If the insulating film of the capacitive element is a silicon oxide film, for example, it can be removed by a dry etching method using argon gas as trifluoromethane gas.

After removing the insulating film of the capacitor, the uppermost surface of the pixel portion of the first substrate 901 becomes an electrode of the capacitor, although not shown. The electrode of the capacitor can be removed using a method similar to that of the first electrode 930 described above.

After removing the capacitor electrode, the top surface of the pixel portion of the first substrate 901 becomes a planarization film 921. As the planarizing film 921, for example, an insulating film containing an organic resin can be easily removed by the same method as the insulating film 932 described above, but the substrate is exposed to plasma using oxygen gas for a long time. There is a possibility that excess oxygen is injected into the insulating film below the planarizing film. For this reason, it may be impossible to appropriately measure oxygen remaining in the display device.

For the above reasons, the planarizing film 921 may be removed by a wet etching method using fuming nitric acid, for example. However, in the case where the outermost surface of the planarizing film 921 has an altered layer, the planarizing film 921 may not be completely removed by a wet etching method using fuming nitric acid.

In such a case, the altered layer on the outermost surface of the planarizing film 921 may be removed by a plasma etching method using oxygen gas, and then removed by a wet etching method using fuming nitric acid. At this time, it is desirable that the processing time by the plasma etching method using oxygen gas is as short as possible (see FIG. 11).

After the planarization film 921 is removed, the outermost surface of the pixel portion 902 of the first substrate 901 becomes an insulating film 926 as a protective film. Since there is an insulating film 924 containing excess oxygen below the insulating film 926, a method of removing the insulating film 924 as much as possible is desirable as a method for removing the insulating film 926.

For example, when a silicon nitride film or a silicon nitride oxide film is used as the insulating film 926 and a silicon oxide film or a silicon oxynitride film is used as the insulating film 924, a plasma etching method using, for example, sulfur hexafluoride gas is used. Can be removed. In the plasma etching method using sulfur hexafluoride gas, the insulating film 926 can be removed without removing the insulating film 924 as much as possible. Other gases such as nitrogen trifluoride gas may be used (see FIG. 12).

Thus, the insulating film 924 having excess oxygen over the oxide semiconductor film can be provided on the outermost surface of the substrate. Next, the pixel portion of the substrate is divided for TDS analysis evaluation. What is necessary is just to match | combine the magnitude | size to divide suitably with the magnitude | size of the sample chamber of a TDS analysis evaluation apparatus. The evaluation sample 970 can be manufactured by the above method (see FIG. 13).

Next, TDS analysis of the evaluation sample 970 is performed. As TDS analysis conditions, the temperature of the heating heater is set to 50 ° C. at the start of measurement, 1000 ° C. at the end of the measurement, and the heating rate is set to 32 ° C./min. The surface temperature of the film of the evaluation sample can be measured by a thermocouple installed in the vicinity of the sample surface, and is about 50 ° C. at the start of measurement and about 500 ° C. at the end of measurement. The pressure in the sample chamber at the start of analysis is approximately 1.2 × 10 ⁻⁷ Pa. The temperature raising heater temperature and the temperature raising rate may be appropriately set depending on the type of substance of the evaluation sample and the evaluation purpose. Under the above TDS analysis conditions, the release amount of the mass-to-charge ratio M / z = 32 corresponding to oxygen molecules, which is released from the evaluation sample 970 can be measured.

By using the above method, the remaining amount of excess oxygen in the oxide insulator can be confirmed even after the display device is manufactured. In this embodiment, an example of the vertical electrolysis type liquid crystal display device shown in FIG. 7B is shown, but the present invention is also applied to the horizontal electrolysis type liquid crystal display device shown in FIG. Is possible.

In addition, the present invention can be implemented even in a display device using a channel protection transistor described in the semiconductor structure example 2 of Embodiment 1. FIG. 15A shows an example of a cross-sectional view of a display device using a channel protection transistor. FIG. 15B shows a state where the present invention is implemented and the channel protective film 928 is the outermost surface.

In addition, the present invention can be applied to a display device using the light-emitting element shown in FIG.

FIG. 14B illustrates an example of a light-emitting device using a light-emitting element as a display element. A light-emitting element 963 that is a display element is electrically connected to a transistor 910 provided in the pixel portion 902. Note that the structure of the light-emitting element 963 is a stacked structure of the first electrode 930, the light-emitting layer 961, and the second electrode 931, but is not limited to the structure shown. The structure of the light-emitting element 963 can be changed as appropriate depending on the direction in which light is extracted from the light-emitting element 963, or the like.

A silicon nitride film 950 is provided between the planarization film 921 and the first electrode 930. The silicon nitride film 950 is in contact with the side surfaces of the planarization film 921 and the insulating film 924. A partition wall 960 is provided over the end portions of the silicon nitride film 950 and the first electrode 930. The partition wall 960 is formed using an organic insulating material or an inorganic insulating material. In particular, it is preferable to use a photosensitive resin material and form an opening on the first electrode 930 so that the side wall of the opening is an inclined surface formed with a continuous curvature.

The light emitting layer 961 may be composed of a single layer or may be composed of a plurality of layers stacked.

A protective layer may be formed over the second electrode 931 and the partition 960 so that oxygen, hydrogen, moisture, carbon dioxide, or the like does not enter the light-emitting element 963. As the protective layer, silicon nitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, a DLC film, or the like can be formed. In addition, a filler 964 is provided and sealed in a space sealed by the first substrate 901, the second substrate 906, and the sealant 936. Thus, it is preferable to package (enclose) with a protective film (bonded film, ultraviolet curable resin film, etc.) or a cover material that has high air tightness and little degassing so as not to be exposed to the outside air.

As the sealant 936, an organic resin such as a thermosetting resin or a photocuring resin, a frit glass including a low-melting glass, or the like can be used. Frit glass is preferable because it has a high barrier property against impurities such as water and oxygen. Further, in the case where frit glass is used as the sealant 936, as shown in FIG. 14B, the frit glass is provided over the silicon nitride film 950, thereby improving the adhesion between the silicon nitride film 950 and the frit glass and externally. Intrusion of water into the sealing material 936 can be prevented.

As the filler 964, an ultraviolet curable resin or a thermosetting resin can be used in addition to an inert gas such as nitrogen or argon. PVC (polyvinyl chloride), acrylic resin, polyimide, epoxy resin, silicone resin, PVB ( Polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. For example, nitrogen may be used as the filler.

Further, if necessary, an optical film such as a polarizing plate, a circularly polarizing plate (including an elliptical polarizing plate), a retardation plate (λ / 4 plate, λ / 2 plate), a color filter, or the like is provided on the emission surface of the light emitting element. You may provide suitably. Further, an antireflection film may be provided on the polarizing plate or the circularly polarizing plate. For example, anti-glare treatment can be performed that diffuses reflected light due to surface irregularities and reduces reflection.

In addition, as a display device, electronic paper that drives electronic ink can be provided. Electronic paper is also called an electrophoretic display device (electrophoretic display), and has the same readability as paper, low power consumption compared to other display devices, and the advantage that it can be made thin and light. ing.

In addition, since the transistor is easily broken by static electricity or the like, it is preferable to provide a protective circuit for protecting the driving circuit. The protection circuit is preferably configured using a non-linear element.

For the light-emitting element having the above structure, a TDS analysis sample can be manufactured by disassembling the display device by the same method as described above.

First, the light-emitting element 963 is removed by peeling the second substrate 906 from the sealant 936, and the film remaining on the first substrate may be sequentially removed by wet etching and etching. For this procedure, the above procedure can be taken into account.

As the first substrate and the second substrate of the display device including the light-emitting element, a flexible substrate, a bonded film, a base film, or the like can be used. Examples include plastics typified by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Another example is a synthetic resin such as acrylic. Alternatively, examples include polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride. Alternatively, examples include polyester, polyamide, polyimide, aramid, epoxy, inorganic vapor deposition film, and paper. Even when such a flexible substrate is used, a similar method can be used. However, when the flexible substrate is peeled off, the second electrode 951, the middle of the light-emitting element 963, or the second Since the film may be peeled off at the interface between the electrode and the partition wall 960, the film remaining on the first substrate is confirmed, and a wet etching method or a dry etching method may be selected as appropriate.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 3)
In this embodiment, a method for decomposing a semiconductor device having a memory circuit and measuring remaining excess oxygen is described in this embodiment.

FIG. 16A illustrates an example of a circuit of the memory device, and FIG. 16B illustrates a cross-sectional view.

This semiconductor device includes a transistor 160, a transistor 110, and a capacitor 130. In addition, the transistor 100, the transistor 110, and the capacitor 130 are electrically connected to each other by a conductor embedded in a contact hole. In this embodiment, the transistor 160 uses a silicon single crystal for a channel formation region; however, for example, an oxide semiconductor film may be used for the channel formation region, and the transistor 160 is not limited to a silicon single crystal. . As the transistor 110, a transistor including an oxide semiconductor film as a channel formation region can be used. The insulating film 305 serving as a base film of the oxide semiconductor film 320 is preferably an insulating film containing excess oxygen. By introducing excess oxygen into the insulating film 305, the insulating film 305 can be formed in the oxide semiconductor film 320. Therefore, oxygen can be transferred to the oxide semiconductor film 320, so that oxygen vacancies in the oxide semiconductor film 320 can be filled.

This semiconductor device also uses the same method as in Embodiment 2 to remove a conductor, an insulator, and the like from an upper layer, and uses the oxide semiconductor film 320 and the insulating film 305 containing excess oxygen as the outermost surface. An evaluation sample can be produced (see FIG. 17).

By performing TDS analysis on the evaluation sample manufactured as described above, it can be decomposed even after a semiconductor device having a memory function is manufactured, and the remaining amount of excess oxygen can be confirmed. Embodiment 2 considers the TDS analysis conditions.

Note that the structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 4)
In this embodiment, one embodiment that can be applied to an oxide semiconductor film in the transistor included in the semiconductor device described in the above embodiment is described.

An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor. As examples of the non-single-crystal oxide semiconductor, a CAAC-OS (C Axis Crystalline Oxide Semiconductor), a polycrystalline oxide semiconductor, a microcrystalline oxide semiconductor, an amorphous oxide semiconductor, and the like can be given.

From another viewpoint, oxide semiconductors are classified into amorphous oxide semiconductors and other crystalline oxide semiconductors. Examples of a crystalline oxide semiconductor include a single crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, and a microcrystalline oxide semiconductor.

First, the CAAC-OS will be described. Note that the CAAC-OS can also be referred to as an oxide semiconductor including CANC (C-Axis aligned nanocrystals).

The CAAC-OS is one of oxide semiconductors having a plurality of c-axis aligned crystal parts (also referred to as pellets).

A plurality of pellets can be confirmed by observing a composite analysis image (also referred to as a high-resolution TEM image) of a bright-field image and a diffraction pattern of a CAAC-OS with a transmission electron microscope (TEM: Transmission Electron Microscope). . On the other hand, in the high-resolution TEM image, the boundary between pellets, that is, the crystal grain boundary (also referred to as grain boundary) cannot be clearly confirmed. Therefore, it can be said that the CAAC-OS does not easily lower the electron mobility due to the crystal grain boundary.

Hereinafter, a CAAC-OS observed with a TEM will be described. FIG. 18A shows a high-resolution TEM image of a cross section of the CAAC-OS which is observed from a direction substantially parallel to the sample surface. For observation of the high-resolution TEM image, a spherical aberration correction function was used. A high-resolution TEM image using the spherical aberration correction function is particularly referred to as a Cs-corrected high-resolution TEM image. Acquisition of a Cs-corrected high-resolution TEM image can be performed by, for example, an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd.

FIG. 18B shows a Cs-corrected high-resolution TEM image obtained by enlarging the region (1) in FIG. FIG. 18B shows that metal atoms are arranged in a layered manner in a pellet. The arrangement of each layer of metal atoms reflects unevenness on a surface (also referred to as a formation surface) or an upper surface where a CAAC-OS film is formed, and is parallel to the formation surface or upper surface of the CAAC-OS.

As shown in FIG. 18B, the CAAC-OS has a characteristic atomic arrangement. FIG. 18C shows a characteristic atomic arrangement with auxiliary lines. 18B and 18C, it can be seen that the size of one pellet is about 1 nm to 3 nm, and the size of the gap generated by the inclination between the pellet and the pellet is about 0.8 nm. Therefore, the pellet can also be referred to as a nanocrystal (nc).

Here, based on the Cs-corrected high-resolution TEM image, the layout of the CAAC-OS pellets 5100 on the substrate 5120 is schematically shown as a structure in which bricks or blocks are stacked (FIG. 18D). reference.). A portion where an inclination is generated between pellets observed in FIG. 18C corresponds to a region 5161 shown in FIG.

FIG. 19A shows a Cs-corrected high-resolution TEM image of the plane of the CAAC-OS observed from a direction substantially perpendicular to the sample surface. The Cs-corrected high-resolution TEM images obtained by enlarging the region (1), the region (2), and the region (3) in FIG. 19A are shown in FIGS. 19B, 19C, and 19D, respectively. Show. From FIG. 19B, FIG. 19C, and FIG. 19D, it can be confirmed that the metal atoms are arranged in a triangular shape, a quadrangular shape, or a hexagonal shape in the pellet. However, there is no regularity in the arrangement of metal atoms between different pellets.

Next, the CAAC-OS analyzed by X-ray diffraction (XRD: X-Ray Diffraction) will be described. For example, when structural analysis by an out-of-plane method is performed on a CAAC-OS including an InGaZnO ₄ crystal, a peak appears at a diffraction angle (2θ) of around 31 ° as illustrated in FIG. There is. Since this peak is attributed to the (009) plane of the InGaZnO ₄ crystal, the CAAC-OS crystal has c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the formation surface or the top surface. It can be confirmed.

Note that in structural analysis of the CAAC-OS by an out-of-plane method, in addition to a peak where 2θ is around 31 °, a peak may also appear when 2θ is around 36 °. A peak at 2θ of around 36 ° indicates that a crystal having no c-axis alignment is included in part of the CAAC-OS. In a more preferable CAAC-OS, in the structural analysis by the out-of-plane method, 2θ has a peak in the vicinity of 31 °, and 2θ has no peak in the vicinity of 36 °.

On the other hand, when structural analysis is performed on the CAAC-OS by an in-plane method in which X-rays are incident from a direction substantially perpendicular to the c-axis, a peak appears at 2θ of around 56 °. This peak is attributed to the (110) plane of the InGaZnO ₄ crystal. In the case of CAAC-OS, even if 2θ is fixed at around 56 ° and analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis), FIG. A clear peak does not appear as shown. On the other hand, in the case of an InGaZnO ₄ single crystal oxide semiconductor, when φ scan is performed with 2θ fixed at around 56 °, it belongs to a crystal plane equivalent to the (110) plane as shown in FIG. 6 peaks are observed. Therefore, structural analysis using XRD can confirm that the CAAC-OS has irregular orientations in the a-axis and the b-axis.

Next, a CAAC-OS analyzed by electron diffraction will be described. For example, when an electron beam with a probe diameter of 300 nm is incident on a CAAC-OS including an InGaZnO ₄ crystal in parallel with a sample surface, a diffraction pattern (a limited-field transmission electron diffraction pattern as illustrated in FIG. 21A) is obtained. Say) may appear. This diffraction pattern includes spots caused by the (009) plane of the InGaZnO ₄ crystal. Therefore, electron diffraction shows that the pellets included in the CAAC-OS have c-axis alignment, and the c-axis is in a direction substantially perpendicular to the formation surface or the top surface. On the other hand, FIG. 21B shows a diffraction pattern obtained when an electron beam with a probe diameter of 300 nm is incident on the same sample in a direction perpendicular to the sample surface. From FIG. 21B, a ring-shaped diffraction pattern is confirmed. Therefore, electron diffraction shows that the a-axis and the b-axis of the pellet included in the CAAC-OS have no orientation. Note that the first ring in FIG. 21B is considered to originate from the (010) plane and the (100) plane of the InGaZnO ₄ crystal. Further, the second ring in FIG. 21B is considered to be caused by the (110) plane or the like.

A CAAC-OS is an oxide semiconductor with a low density of defect states. Examples of defects in the oxide semiconductor include defects due to impurities and oxygen vacancies. Therefore, the CAAC-OS can also be referred to as an oxide semiconductor with a low impurity concentration. A CAAC-OS can also be referred to as an oxide semiconductor with few oxygen vacancies.

An impurity contained in the oxide semiconductor might serve as a carrier trap or a carrier generation source. In addition, oxygen vacancies in the oxide semiconductor may serve as carrier traps or may serve as carrier generation sources by capturing hydrogen.

Note that the impurity means an element other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, or a transition metal element. For example, an element such as silicon, which has a stronger bonding force with oxygen than a metal element included in an oxide semiconductor, disturbs the atomic arrangement of the oxide semiconductor by depriving the oxide semiconductor of oxygen, thereby reducing crystallinity. It becomes a factor. In addition, heavy metals such as iron and nickel, argon, carbon dioxide, and the like have large atomic radii (or molecular radii), which disturbs the atomic arrangement of the oxide semiconductor and decreases crystallinity.

An oxide semiconductor with a low defect level density (low oxygen vacancies) can have a low carrier density. Such an oxide semiconductor is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. The CAAC-OS has a low impurity concentration and a low density of defect states. That is, it is likely to be a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Therefore, a transistor using the CAAC-OS rarely has electrical characteristics (also referred to as normally-on) in which the threshold voltage is negative. A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has few carrier traps. The charge trapped in the carrier trap of the oxide semiconductor takes a long time to be released and may behave as if it were a fixed charge. Therefore, a transistor including an oxide semiconductor with a high impurity concentration and a high density of defect states may have unstable electrical characteristics. On the other hand, a transistor using a CAAC-OS has a small change in electrical characteristics and has high reliability.

In addition, since the CAAC-OS has a low defect level density, carriers generated by light irradiation or the like are rarely trapped in the defect level. Therefore, a transistor using the CAAC-OS has little change in electrical characteristics due to irradiation with visible light or ultraviolet light.

Next, a microcrystalline oxide semiconductor will be described.

A microcrystalline oxide semiconductor has a region where a crystal part can be confirmed and a region where a clear crystal part cannot be confirmed in a high-resolution TEM image. In most cases, a crystal part included in the microcrystalline oxide semiconductor has a size of 1 nm to 100 nm, or 1 nm to 10 nm. In particular, an oxide semiconductor including a nanocrystal that is a microcrystal of 1 nm to 10 nm, or 1 nm to 3 nm is referred to as an nc-OS (nanocrystalline Oxide Semiconductor). For example, the nc-OS may not be able to clearly confirm a crystal grain boundary in a high-resolution TEM image. Note that the nanocrystal may have the same origin as the pellet in the CAAC-OS. Therefore, the crystal part of nc-OS is sometimes referred to as a pellet below.

The nc-OS has periodicity in atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In addition, the nc-OS has no regularity in crystal orientation between different pellets. Therefore, orientation is not seen in the whole film. Therefore, the nc-OS may not be distinguished from an amorphous oxide semiconductor depending on an analysis method. For example, when structural analysis is performed on the nc-OS using an XRD apparatus using X-rays having a diameter larger than that of the pellet, a peak indicating a crystal plane is not detected in the analysis by the out-of-plane method. Further, when electron diffraction using an electron beam having a probe diameter (for example, 50 nm or more) larger than that of the pellet is performed on the nc-OS, a diffraction pattern such as a halo pattern is observed. On the other hand, when nanobeam electron diffraction is performed on the nc-OS using an electron beam having a probe diameter that is close to the pellet size or smaller than the pellet size, spots are observed. Further, when nanobeam electron diffraction is performed on the nc-OS, a region with high luminance may be observed like a circle (in a ring shape). Furthermore, a plurality of spots may be observed in the ring-shaped region.

Thus, since the crystal orientation does not have regularity between pellets (nanocrystals), nc-OS has an oxide semiconductor having RANC (Random Aligned Nanocrystals) or NANC (Non-Aligned nanocrystals). It can also be called an oxide semiconductor.

The nc-OS is an oxide semiconductor that has higher regularity than an amorphous oxide semiconductor. Therefore, the nc-OS has a lower density of defect states than an amorphous oxide semiconductor. Note that the nc-OS does not have regularity in crystal orientation between different pellets. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.

Next, an amorphous oxide semiconductor will be described.

An amorphous oxide semiconductor is an oxide semiconductor in which atomic arrangement in a film is irregular and does not have a crystal part. An example is an oxide semiconductor having an amorphous state such as quartz.

In an amorphous oxide semiconductor, a crystal part cannot be confirmed in a high-resolution TEM image.

When structural analysis using an XRD apparatus is performed on an amorphous oxide semiconductor, a peak indicating a crystal plane is not detected by analysis using an out-of-plane method. In addition, when electron diffraction is performed on an amorphous oxide semiconductor, a halo pattern is observed. Further, when nanobeam electron diffraction is performed on an amorphous oxide semiconductor, no spot is observed and only a halo pattern is observed.

Various views have been presented regarding the amorphous structure. For example, a structure having no order in the atomic arrangement may be referred to as a complete amorphous structure. In addition, a structure having ordering up to the nearest interatomic distance or the distance between the second adjacent atoms and having no long-range ordering may be referred to as an amorphous structure. Therefore, according to the strictest definition, an oxide semiconductor having order in the atomic arrangement cannot be called an amorphous oxide semiconductor. At least an oxide semiconductor having long-range order cannot be called an amorphous oxide semiconductor. Thus, for example, the CAAC-OS and the nc-OS cannot be referred to as an amorphous oxide semiconductor or a completely amorphous oxide semiconductor because of having a crystal part.

Note that an oxide semiconductor may have a structure between the nc-OS and an amorphous oxide semiconductor. An oxide semiconductor having such a structure is particularly referred to as an amorphous-like oxide semiconductor (a-like OS).

In the a-like OS, a void (also referred to as a void) may be observed in a high-resolution TEM image. Moreover, in a high-resolution TEM image, it has the area | region which can confirm a crystal part clearly, and the area | region which cannot confirm a crystal part.

Since it has a void, the a-like OS has an unstable structure. Hereinafter, in order to show that the a-like OS has an unstable structure as compared with the CAAC-OS and the nc-OS, changes in the structure due to electron irradiation are shown.

As samples for electron irradiation, a-like OS (referred to as sample A), nc-OS (referred to as sample B), and CAAC-OS (referred to as sample C) are prepared. Each sample is an In—Ga—Zn oxide.

First, a high-resolution cross-sectional TEM image of each sample is acquired. It can be seen from the high-resolution cross-sectional TEM image that each sample has a crystal part.

The determination of which part is regarded as one crystal part may be performed as follows. For example, the unit cell of an InGaZnO ₄ crystal has a structure in which three In—O layers and six Ga—Zn—O layers have a total of nine layers stacked in the c-axis direction. Are known. The spacing between these adjacent layers is about the same as the lattice spacing (also referred to as d value) of the (009) plane, and the value is determined to be 0.29 nm from crystal structure analysis. Therefore, a portion where the interval between lattice fringes is 0.28 nm or more and 0.30 nm or less can be regarded as a crystal part of InGaZnO ₄ . Note that the lattice fringes correspond to the ab plane of the InGaZnO ₄ crystal.

FIG. 22 is an example in which the average size of the crystal parts (from 22 to 45) of each sample was examined. However, the length of the lattice fringes described above is the size of the crystal part. From FIG. 22, it can be seen that in the a-like OS, the crystal part becomes larger according to the cumulative dose of electrons. Specifically, as shown by (1) in FIG. 22, the crystal portion (also referred to as initial nucleus) which was about 1.2 nm in the initial stage of observation by TEM has a cumulative irradiation dose of 4.2. It can be seen that the film grows to a size of about 2.6 nm at × 10 ⁸ e ⁻ / nm ² . On the other hand, in the nc-OS and the CAAC-OS, there is no change in the size of the crystal part in the range of the cumulative electron dose from the start of electron irradiation to 4.2 × 10 ⁸ e ⁻ / nm ^2. I understand. Specifically, as indicated by (2) and (3) in FIG. 22, the sizes of the crystal parts of nc-OS and CAAC-OS are about 1.4 nm, respectively, regardless of the cumulative electron dose. And about 2.1 nm.

As described above, in the a-like OS, a crystal part may be grown by electron irradiation. On the other hand, in the nc-OS and the CAAC-OS, the crystal part is hardly grown by electron irradiation. That is, it can be seen that the a-like OS has an unstable structure compared to the nc-OS and the CAAC-OS.

In addition, since it has a void, the a-like OS has a lower density than the nc-OS and the CAAC-OS. Specifically, the density of the a-like OS is 78.6% or more and less than 92.3% of the density of the single crystal having the same composition. Further, the density of the nc-OS and the density of the CAAC-OS are 92.3% or more and less than 100% of the density of the single crystal having the same composition. An oxide semiconductor that is less than 78% of the density of a single crystal is difficult to form.

For example, in an oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of single crystal InGaZnO ₄ having a rhombohedral structure is 6.357 g / cm ³ . Thus, for example, in an oxide semiconductor that satisfies In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of a-like OS is 5.0 g / cm ³ or more and less than 5.9 g / cm ^3. . For example, in the oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of the nc-OS and the density of the CAAC-OS is 5.9 g / cm ³ or more and 6.3 g / less than cm ³ .

Note that there may be no single crystal having the same composition. In that case, the density corresponding to the single crystal in a desired composition can be estimated by combining single crystals having different compositions at an arbitrary ratio. What is necessary is just to estimate the density corresponding to the single crystal of a desired composition using a weighted average with respect to the ratio which combines the single crystal from which a composition differs. However, the density is preferably estimated by combining as few kinds of single crystals as possible.

As described above, oxide semiconductors have various structures and various properties. Note that the oxide semiconductor may be a stacked film including two or more of an amorphous oxide semiconductor, an a-like OS, a microcrystalline oxide semiconductor, and a CAAC-OS, for example.

Note that the structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 5)
In this embodiment, a display device including the semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

A display device illustrated in FIG. 23A includes a circuit portion (hereinafter referred to as a pixel portion 502) including a pixel of a display element and a circuit for driving the pixel, which is disposed outside the pixel portion 502. , A driver circuit portion 504), a circuit having a function of protecting an element (hereinafter referred to as a protection circuit 506), and a terminal portion 507. Note that the protection circuit 506 may be omitted.

A part or all of the driver circuit portion 504 is preferably formed over the same substrate as the pixel portion 502. Thereby, the number of parts and the number of terminals can be reduced. When part or all of the driver circuit portion 504 is not formed over the same substrate as the pixel portion 502, part or all of the driver circuit portion 504 is formed by COG or TAB (Tape Automated Bonding). Can be implemented.

The pixel portion 502 includes a circuit (hereinafter referred to as a pixel circuit 501) for driving a plurality of display elements arranged in X rows (X is a natural number of 2 or more) and Y columns (Y is a natural number of 2 or more). The driver circuit portion 504 outputs a signal for selecting a pixel (scanning signal) (hereinafter referred to as a gate driver 504a) and a circuit for supplying a signal (data signal) for driving a display element of the pixel (a data signal). Hereinafter, it has a drive circuit such as a source driver 504b).

The gate driver 504a includes a shift register and the like. The gate driver 504a receives a signal for driving the shift register via the terminal portion 507, and outputs a signal. For example, the gate driver 504a receives a start pulse signal, a clock signal, and the like and outputs a pulse signal. The gate driver 504a has a function of controlling the potential of a wiring to which a scan signal is supplied (hereinafter referred to as scan lines GL_1 to GL_X). Note that a plurality of gate drivers 504a may be provided, and the scanning lines GL_1 to GL_X may be divided and controlled by the plurality of gate drivers 504a. Alternatively, the gate driver 504a has a function of supplying an initialization signal. However, the present invention is not limited to this, and the gate driver 504a can supply another signal.

The source driver 504b includes a shift register and the like. In addition to a signal for driving the shift register, the source driver 504b receives a signal (image signal) as a source of a data signal through the terminal portion 507. The source driver 504b has a function of generating a data signal to be written in the pixel circuit 501 based on the image signal. In addition, the source driver 504b has a function of controlling output of a data signal in accordance with a pulse signal obtained by inputting a start pulse, a clock signal, or the like. The source driver 504b has a function of controlling the potential of a wiring to which a data signal is supplied (hereinafter referred to as data lines DL_1 to DL_Y). Alternatively, the source driver 504b has a function of supplying an initialization signal. However, the present invention is not limited to this, and the source driver 504b can supply another signal.

The source driver 504b is configured using, for example, a plurality of analog switches. The source driver 504b can output a signal obtained by time-dividing the image signal as a data signal by sequentially turning on the plurality of analog switches. Further, the source driver 504b may be configured using a shift register or the like.

Each of the plurality of pixel circuits 501 receives a pulse signal through one of the plurality of scanning lines GL to which the scanning signal is applied, and receives the data signal through one of the plurality of data lines DL to which the data signal is applied. Entered. Also. In each of the plurality of pixel circuits 501, writing and holding of data signals are controlled by the gate driver 504a. For example, the pixel circuit 501 in the m-th row and the n-th column receives a pulse signal from the gate driver 504a through the scanning line GL_m (m is a natural number less than or equal to X), and the data line DL_n (n) according to the potential of the scanning line GL_m. Is a natural number less than or equal to Y), a data signal is input from the source driver 504b.

The protection circuit 506 illustrated in FIG. 23A is connected to, for example, the scanning line GL which is a wiring between the gate driver 504a and the pixel circuit 501. Alternatively, the protection circuit 506 is connected to a data line DL that is a wiring between the source driver 504 b and the pixel circuit 501. Alternatively, the protection circuit 506 can be connected to a wiring between the gate driver 504 a and the terminal portion 507. Alternatively, the protection circuit 506 can be connected to a wiring between the source driver 504 b and the terminal portion 507. Note that the terminal portion 507 is a portion where a terminal for inputting a power supply, a control signal, and an image signal from an external circuit to the display device is provided.

The protection circuit 506 is a circuit that brings a wiring into a conductive state when a potential outside a certain range is applied to the wiring to which the protection circuit 506 is connected.

As shown in FIG. 23A, the protection circuit 506 is provided in each of the pixel portion 502 and the driver circuit portion 504, thereby increasing the resistance of the display device to an overcurrent generated by ESD (Electro Static Discharge) or the like. be able to. However, the configuration of the protection circuit 506 is not limited thereto, and for example, a configuration in which the protection circuit 506 is connected to the gate driver 504a or a configuration in which the protection circuit 506 is connected to the source driver 504b may be employed. Alternatively, the protection circuit 506 may be connected to the terminal portion 507.

FIG. 23A illustrates an example in which the driver circuit portion 504 is formed using the gate driver 504a and the source driver 504b; however, the present invention is not limited to this structure. For example, only the gate driver 504a may be formed, and a substrate on which a separately prepared source driver circuit is formed (for example, a driver circuit substrate formed using a single crystal semiconductor film or a polycrystalline semiconductor film) may be mounted.

In addition, the plurality of pixel circuits 501 illustrated in FIG. 23A can have a structure illustrated in FIG.

A pixel circuit 501 illustrated in FIG. 23B includes a liquid crystal element 570, a transistor 550, and a capacitor 560. The transistor described in the above embodiment can be applied to the transistor 550.

One potential of the pair of electrodes of the liquid crystal element 570 is appropriately set according to the specification of the pixel circuit 501. The alignment state of the liquid crystal element 570 is set by written data. Note that a common potential (common potential) may be applied to one of the pair of electrodes of the liquid crystal element 570 included in each of the plurality of pixel circuits 501. Further, a different potential may be applied to one of the pair of electrodes of the liquid crystal element 570 of the pixel circuit 501 in each row.

For example, as a driving method of a display device including the liquid crystal element 570, a TN mode, an STN mode, a VA mode, an ASM (Axial Symmetric Aligned Micro-cell) mode, an OCB (Optically Compensated Birefringence) mode, and an FLC (Ferroelectric mode) , AFLC (Anti Ferroelectric Liquid Crystal) mode, MVA mode, PVA (Patterned Vertical Alignment) mode, IPS mode, FFS mode, TBA (Transverse Bend Alignment) mode, etc. may be used. In addition to the above-described driving methods, there are ECB (Electrically Controlled Birefringence) mode, PDLC (Polymer Dispersed Liquid Crystal) mode, PNLC (Polymer Network Liquid Host mode), and other driving methods for the display device. However, the present invention is not limited to this, and various liquid crystal elements and driving methods thereof can be used.

In the pixel circuit 501 in the m-th row and the n-th column, one of the source electrode and the drain electrode of the transistor 550 is electrically connected to the data line DL_n, and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. The In addition, the gate electrode of the transistor 550 is electrically connected to the scan line GL_m. The transistor 550 has a function of controlling data writing of the data signal by being turned on or off.

One of the pair of electrodes of the capacitor 560 is electrically connected to a wiring to which a potential is supplied (hereinafter, potential supply line VL), and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. The Note that the value of the potential of the potential supply line VL is appropriately set according to the specifications of the pixel circuit 501. The capacitor 560 functions as a storage capacitor for storing written data.

For example, in a display device including the pixel circuit 501 in FIG. 23B, for example, the pixel circuits 501 in each row are sequentially selected by the gate driver 504a illustrated in FIG. Write data.

The pixel circuit 501 in which data is written is brought into a holding state when the transistor 550 is turned off. By sequentially performing this for each row, an image can be displayed.

In addition, the plurality of pixel circuits 501 illustrated in FIG. 23A can have a structure illustrated in FIG.

A pixel circuit 501 illustrated in FIG. 23C includes transistors 552 and 554, a capacitor 562, and a light-emitting element 572. The transistor described in any of the above embodiments can be applied to one or both of the transistor 552 and the transistor 554.

One of a source electrode and a drain electrode of the transistor 552 is electrically connected to a wiring to which a data signal is supplied (hereinafter referred to as a signal line DL_n). Further, the gate electrode of the transistor 552 is electrically connected to a wiring to which a gate signal is supplied (hereinafter referred to as a scanning line GL_m).

The transistor 552 has a function of controlling data writing of the data signal by being turned on or off.

One of the pair of electrodes of the capacitor 562 is electrically connected to a wiring to which a potential is applied (hereinafter referred to as a potential supply line VL_a), and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 552. Is done.

The capacitor 562 functions as a storage capacitor that stores written data.

One of a source electrode and a drain electrode of the transistor 554 is electrically connected to the potential supply line VL_a. Further, the gate electrode of the transistor 554 is electrically connected to the other of the source electrode and the drain electrode of the transistor 552.

One of an anode and a cathode of the light-emitting element 572 is electrically connected to the potential supply line VL_b, and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 554.

As the light-emitting element 572, for example, an organic electroluminescence element (also referred to as an organic EL element) or the like can be used. However, the light-emitting element 572 is not limited thereto, and an inorganic EL element made of an inorganic material may be used.

Note that one of the potential supply line VL_a and the potential supply line VL_b is supplied with the high power supply potential VDD, and the other is supplied with the low power supply potential VSS.

In the display device including the pixel circuit 501 in FIG. 23C, for example, the pixel circuits 501 in each row are sequentially selected by the gate driver 504a illustrated in FIG. Write.

The pixel circuit 501 in which data is written is brought into a holding state when the transistor 552 is turned off. Further, the amount of current flowing between the source electrode and the drain electrode of the transistor 554 is controlled in accordance with the potential of the written data signal, and the light-emitting element 572 emits light with luminance corresponding to the amount of flowing current. By sequentially performing this for each row, an image can be displayed.

The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.
(Embodiment 6)
In this embodiment, a cross-sectional structure of elements included in the imaging device is described with reference to drawings. In this embodiment, a cross-sectional structure in which a pixel is formed using a Si transistor and an OS transistor is described as an example.

24A and 24B are cross-sectional views of elements included in the imaging device. 24A includes an Si transistor 51 provided on the silicon substrate 40, a transistor 52 and a transistor 53 provided on the Si transistor 51, and a photodiode 60 provided on the silicon substrate 40. including. Each transistor and photodiode 60 is electrically connected to various contact plugs 70 and wiring layers 71. Further, the anode 61 of the photodiode 60 is electrically connected to the contact plug 70 through the low resistance region 63.

The imaging device is provided in contact with the layer 1100 having the Si transistor 51 and the photodiode 60 provided on the silicon substrate 40, the layer 1200 having the wiring layer 71, and in contact with the layer 1200. A layer 1300 including the transistor 52 and the transistor 53 and a layer 1400 provided in contact with the layer 1300 and including the wiring layer 72 and the wiring layer 73 are provided.

In the example of the cross-sectional view of FIG. 24A, the silicon substrate 40 has a light receiving surface of the photodiode 60 on the surface opposite to the surface on which the Si transistor 51 is formed. With this configuration, an optical path can be secured without being affected by various transistors and wirings. Therefore, a pixel with a high aperture ratio can be formed. Note that the light receiving surface of the photodiode 60 may be the same as the surface on which the Si transistor 51 is formed.

Note that in the case where a pixel is formed using a transistor whose channel formation region is an oxide semiconductor, the layer 1100 may be omitted, and the pixel may be formed using only a transistor whose channel formation region is an oxide semiconductor.

Note that in the case where a pixel is formed using Si transistors, the layer 1300 may be omitted. An example of a cross-sectional view in which the layer 1300 is omitted is shown in FIG.

The silicon substrate 40 is not limited to a bulk silicon substrate, and may be an SOI substrate. Instead of the silicon substrate 40, a substrate made of germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor can be used.

Here, although the position is not limited, the layer 1100 including the Si transistor 51 and the photodiode 60, the transistor 52 including the oxide semiconductor as a channel formation region, and the layer 1300 including the transistor 53 including the oxide semiconductor as a channel formation region An insulating layer 80 is provided therebetween.

Hydrogen in the insulating layer provided near the active region of the Si transistor 51 has an effect of terminating the dangling bond of silicon and improving the reliability of the Si transistor 51. On the other hand, hydrogen in an insulating layer provided in the vicinity of an oxide semiconductor layer which is an active layer, such as the transistor 52 using an oxide semiconductor provided in an upper layer as a channel formation region and the transistor 53 using an oxide semiconductor as a channel formation region, Since this is one of the factors that generate carriers in the oxide semiconductor film, the reliability of the transistor 52 in which the oxide semiconductor is a channel formation region, the transistor 53 in which the oxide semiconductor is a channel formation region, and the like are reduced. There is a case. Accordingly, in the case where a transistor including an oxide semiconductor is stacked over a transistor including a silicon-based semiconductor material, it is preferable to provide an insulating layer 80 having a function of preventing hydrogen diffusion therebetween. A transistor having an oxide semiconductor as a channel formation region by suppressing hydrogen diffusion from the lower layer to the upper layer in addition to improving the reliability of the Si transistor 51 by confining hydrogen in the lower layer by the insulating layer 80 The reliability of the transistor 53 and the like using the oxide semiconductor 52 and the oxide semiconductor as a channel formation region can be improved at the same time.

As the insulating layer 80, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria-stabilized zirconia (YSZ), or the like can be used.

In the cross-sectional view in FIG. 24A, the photodiode 60 provided in the layer 1100 and the transistor provided in the layer 1300 can be formed to overlap with each other. Then, the integration degree of pixels can be increased. That is, the resolution of the imaging device can be increased.

In addition, as illustrated in FIGS. 25A1 and 25B1, the imaging device may be curved. FIG. 25A1 illustrates a state in which the imaging device is bent in the direction of a two-dot chain line X1-X2. FIG. 25A2 is a cross-sectional view illustrating a portion indicated by dashed-two dotted line X1-X2 in FIG. 25A3 is a cross-sectional view illustrating a portion indicated by dashed-two dotted line Y1-Y2 in FIG.

FIG. 25B1 illustrates a state in which the imaging device is bent in the direction of a two-dot chain line X3-X4 in the drawing and in the direction of a two-dot chain line Y3-Y4 in the drawing. FIG. 25B2 is a cross-sectional view illustrating a portion indicated by dashed-two dotted line X3-X4 in FIG. 25B3 is a cross-sectional view illustrating a portion indicated by dashed-two dotted line Y3-Y4 in FIG.

By curving the imaging device, field curvature and astigmatism can be reduced. Therefore, optical design of a lens or the like used in combination with the imaging device can be facilitated. For example, since the number of lenses for aberration correction can be reduced, the image pickup apparatus can be easily reduced in size and weight. In addition, the quality of the captured image can be improved.

Note that this embodiment can be combined with any of the other embodiments as appropriate.

(Embodiment 7)
In this embodiment, a display module and an electronic device each including the semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

A display module 8000 shown in FIG. 26 includes a touch panel 8004 connected to the FPC 8003, a display panel 8006 connected to the FPC 8005, a backlight 8007, a frame 8009, a printed circuit board 8010, a battery, between an upper cover 8001 and a lower cover 8002. 8011.

The semiconductor device of one embodiment of the present invention can be used for the display panel 8006, for example.

The shapes and dimensions of the upper cover 8001 and the lower cover 8002 can be changed as appropriate in accordance with the sizes of the touch panel 8004 and the display panel 8006.

As the touch panel 8004, a resistive touch panel or a capacitive touch panel can be used by being superimposed on the display panel 8006. In addition, the counter substrate (sealing substrate) of the display panel 8006 can have a touch panel function. In addition, an optical sensor can be provided in each pixel of the display panel 8006 to provide an optical touch panel.

The backlight 8007 has a light source 8008. Note that although FIG. 26 illustrates the configuration in which the light source 8008 is provided over the backlight 8007, the present invention is not limited to this. For example, a light source 8008 may be provided at the end of the backlight 8007 and a light diffusing plate may be used. Note that in the case of using a self-luminous light-emitting element such as an organic EL element, or in the case of a reflective panel or the like, the backlight 8007 may not be provided.

The frame 8009 has a function as an electromagnetic shield for blocking electromagnetic waves generated by the operation of the printed board 8010 in addition to a protective function of the display panel 8006. The frame 8009 may have a function as a heat sink.

The printed board 8010 includes a power supply circuit, a signal processing circuit for outputting a video signal and a clock signal. As a power supply for supplying power to the power supply circuit, an external commercial power supply may be used, or a power supply using a battery 8011 provided separately may be used. The battery 8011 can be omitted when a commercial power source is used.

The display module 8000 may be additionally provided with a member such as a polarizing plate, a retardation plate, or a prism sheet.

FIGS. 27A to 27G illustrate electronic devices. These electronic devices include a housing 9000, a display portion 9001, a speaker 9003, operation keys 9005 (including a power switch or operation switch), a connection terminal 9006, and a sensor 9007 (force, displacement, position, speed, acceleration, angular velocity, Includes functions to measure rotation speed, distance, light, liquid, magnetism, temperature, chemical, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared ), A microphone 9008, and the like.

The electronic devices illustrated in FIGS. 27A to 27G can have a variety of functions. For example, a function for displaying various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a function for displaying a calendar, date or time, a function for controlling processing by various software (programs), Wireless communication function, function for connecting to various computer networks using the wireless communication function, function for transmitting or receiving various data using the wireless communication function, and reading and displaying the program or data recorded on the recording medium It can have a function of displaying on the section. Note that the functions of the electronic devices illustrated in FIGS. 27A to 27G are not limited to these, and can have various functions. Although not illustrated in FIGS. 27A to 27G, the electronic device may have a plurality of display portions. In addition, the electronic device is equipped with a camera, etc., to capture still images, to capture moving images, to store captured images on a recording medium (externally or built into the camera), and to display captured images on the display unit And the like.

Details of the electronic devices illustrated in FIGS. 27A to 27G are described below.

FIG. 27A is a perspective view showing a portable information terminal 9100. A display portion 9001 included in the portable information terminal 9100 has flexibility. Therefore, the display portion 9001 can be incorporated along the curved surface of the curved housing 9000. Further, the display portion 9001 includes a touch sensor and can be operated by touching the screen with a finger, a stylus, or the like. For example, an application can be activated by touching an icon displayed on the display unit 9001.

FIG. 27B is a perspective view showing the portable information terminal 9101. The portable information terminal 9101 has one or a plurality of functions selected from, for example, a telephone, a notebook, an information browsing device, or the like. Specifically, it can be used as a smartphone. Note that the portable information terminal 9101 is illustrated with the speaker 9003, the connection terminal 9006, the sensor 9007, and the like omitted, but can be provided at the same position as the portable information terminal 9100 illustrated in FIG. Further, the portable information terminal 9101 can display characters and image information on the plurality of surfaces. For example, three operation buttons 9050 (also referred to as operation icons or simply icons) can be displayed on one surface of the display portion 9001. Further, information 9051 indicated by a broken-line rectangle can be displayed on another surface of the display portion 9001. As an example of the information 9051, a display for notifying an incoming call such as an e-mail, SNS (social networking service), a telephone call, a title such as an e-mail or SNS, a sender name such as an e-mail or SNS, a date and time, and a time , Battery level, antenna reception strength and so on. Alternatively, an operation button 9050 or the like may be displayed instead of the information 9051 at a position where the information 9051 is displayed.

FIG. 27C is a perspective view showing the portable information terminal 9102. The portable information terminal 9102 has a function of displaying information on three or more surfaces of the display portion 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are displayed on different planes. For example, the user of the portable information terminal 9102 can check the display (information 9053 here) in a state where the portable information terminal 9102 is stored in the chest pocket of clothes. Specifically, the telephone number or name of the caller of the incoming call is displayed at a position where it can be observed from above portable information terminal 9102. The user can check the display and determine whether to receive a call without taking out the portable information terminal 9102 from the pocket.

FIG. 27D is a perspective view showing a wristwatch-type portable information terminal 9200. The portable information terminal 9200 can execute various applications such as a mobile phone, electronic mail, text browsing and creation, music playback, Internet communication, and computer games. Further, the display portion 9001 is provided with a curved display surface, and can perform display along the curved display surface. In addition, the portable information terminal 9200 can execute short-range wireless communication with a communication standard. For example, it is possible to talk hands-free by communicating with a headset capable of wireless communication. In addition, the portable information terminal 9200 includes a connection terminal 9006 and can directly exchange data with other information terminals via a connector. Charging can also be performed through the connection terminal 9006. Note that the charging operation may be performed by wireless power feeding without using the connection terminal 9006.

27E, 27F, and 27G are perspective views illustrating a foldable portable information terminal 9201. FIG. FIG. 27E is a perspective view of a state in which the portable information terminal 9201 is expanded, and FIG. 27F is a state in which the portable information terminal 9201 is being expanded or changed from one of the folded state to the other. FIG. 27G is a perspective view of the portable information terminal 9201 folded. The portable information terminal 9201 is excellent in portability in the folded state, and in the expanded state, the portable information terminal 9201 is excellent in display listability due to a seamless wide display area. A display portion 9001 included in the portable information terminal 9201 is supported by three housings 9000 connected by a hinge 9055. By bending between the two housings 9000 via the hinge 9055, the portable information terminal 9201 can be reversibly deformed from the expanded state to the folded state. For example, the portable information terminal 9201 can be bent with a curvature radius of 1 mm to 150 mm.

The electronic device described in this embodiment includes a display portion for displaying some information. Note that the semiconductor device of one embodiment of the present invention can also be applied to an electronic device that does not include a display portion. In addition, in the display portion of the electronic device described in this embodiment, an example of a configuration that has flexibility and can display along a curved display surface, or a configuration of a foldable display portion is given. However, the present invention is not limited to this, and may have a configuration in which display is performed on a flat portion without having flexibility.

The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

(Embodiment 8)
In this embodiment, an example of a memory device to which the transistor M0 described in Embodiments 1 and 2 can be applied will be described.

The semiconductor device illustrated in FIG. 28A includes a transistor M1, a transistor M0, and a capacitor 3400.

The transistor M0 is preferably a transistor including an oxide semiconductor in a channel region. Since the transistor M0 has a small off-state current, stored data can be held for a long time by using the transistor M0. In other words, since it is possible to obtain a semiconductor memory device that does not require a refresh operation or has a very low frequency of the refresh operation, power consumption can be sufficiently reduced.

In FIG. 28A, the first wiring 3001 is electrically connected to the source electrode of the transistor M1, and the second wiring 3002 is electrically connected to the drain electrode of the transistor M1. The third wiring 3003 is electrically connected to one of the source electrode and the drain electrode of the transistor M0, and the fourth wiring 3004 is electrically connected to the gate electrode of the transistor M0. The other of the gate electrode of the transistor M1 and the source and drain electrodes of the transistor M0 is electrically connected to the first terminal of the capacitor 3400, and the fifth wiring 3005 is a second terminal of the capacitor 3400. Is electrically connected.

In the semiconductor device illustrated in FIG. 28A, data can be written, held, and read as follows by utilizing the feature that the potential of the gate electrode of the transistor M1 can be held.

Data writing and holding will be described. First, the potential of the fourth wiring 3004 is set to a potential at which the transistor M0 is turned on, so that the transistor M0 is turned on. Accordingly, the potential of the third wiring 3003 is supplied to the gate electrode of the transistor M1 and the capacitor 3400. That is, a predetermined charge is given to the gate of the transistor M1 (writing). Here, it is assumed that one of two charges (hereinafter, referred to as low level charge and high level charge) that gives two different potential levels is given. After that, the potential of the fourth wiring 3004 is set to a potential at which the transistor M0 is turned off and the transistor M0 is turned off, so that the charge given to the gate of the transistor M1 is held (held).

Since the off-state current of the transistor M0 is extremely small, the charge of the gate of the transistor M1 is held for a long time.

Next, data reading will be described. When an appropriate potential (read potential) is applied to the fifth wiring 3005 in a state where a predetermined potential (constant potential) is applied to the first wiring 3001, according to the amount of charge held at the gate of the transistor M1, The second wiring 3002 has different potentials. In general, when the transistor M1 is an n-channel type, the apparent threshold value Vth_H when a high level charge is applied to the gate electrode of the transistor M1 is the case where a low level charge is applied to the gate electrode of the transistor M1. This is because it becomes lower than the apparent threshold value Vth_L. Here, the apparent threshold voltage means a potential of the fifth wiring 3005 necessary for turning on the transistor M1. Therefore, by setting the potential of the fifth wiring 3005 to a potential V0 between Vth_H and Vth_L, the charge given to the gate of the transistor M1 can be determined. For example, in the case where a high level charge is applied in writing, the transistor M1 is turned on when the potential of the fifth wiring 3005 is V0 (> Vth_H). When the low-level charge is applied, the transistor M1 remains in the “off state” even when the potential of the fifth wiring 3005 is V0 (<Vth_L). Therefore, the stored data can be read by determining the potential of the second wiring 3002.

Note that in the case of using memory cells arranged in an array, it is necessary to read only data of desired memory cells. In the case where data is not read out in this manner, a potential at which the transistor M1 is turned off regardless of the state of the gate, that is, a potential lower than Vth_H may be supplied to the fifth wiring 3005. Alternatively, a potential that turns on the transistor M1 regardless of the state of the gate, that is, a potential higher than Vth_L may be supplied to the fifth wiring 3005.

The semiconductor device illustrated in FIG. 28B is different from FIG. 28A in that the transistor M1 is not provided. In this case, data can be written and held by the same operation as described above.

Next, reading of data from the semiconductor device illustrated in FIG. 28B is described. When the transistor M0 is turned on, the third wiring 3003 in a floating state and the capacitor 3400 are brought into conduction, and charge is redistributed between the third wiring 3003 and the capacitor 3400. As a result, the potential of the third wiring 3003 changes. The amount of change in potential of the third wiring 3003 varies depending on the potential of the first terminal of the capacitor 3400 (or charge accumulated in the capacitor 3400).

For example, the potential of the first terminal of the capacitor 3400 is V, the capacitance of the capacitor 3400 is C, the capacitance component of the third wiring 3003 is CB, and the potential of the third wiring 3003 before charge is redistributed Is VB0, the potential of the third wiring 3003 after the charge is redistributed is (CB × VB0 + C × V) / (CB + C). Therefore, when the potential of the first terminal of the capacitor 3400 assumes two states of V1 and V0 (V1> V0) as the state of the memory cell, the third wiring 3003 in the case where the potential V1 is held. The potential (= (CB × VB0 + C × V1) / (CB + C)) is higher than the potential of the third wiring 3003 when the potential V0 is held (= CB × VB0 + C × V0) / (CB + C)). I understand that.

Then, data can be read by comparing the potential of the third wiring 3003 with a predetermined potential.

In the semiconductor device described in this embodiment, stored data can be held for an extremely long time by using a transistor with an extremely small off-state current that uses an oxide semiconductor for a channel formation region. That is, the refresh operation is not necessary or the frequency of the refresh operation can be extremely low, so that power consumption can be sufficiently reduced. In addition, stored data can be held for a long time even when power is not supplied (note that a potential is preferably fixed).

Further, in the semiconductor device described in this embodiment, high voltage is not required for writing data and there is no problem of deterioration of elements. For example, unlike the conventional nonvolatile memory, it is not necessary to inject electrons into the floating gate or extract electrons from the floating gate, so that the problem of deterioration of the gate insulating film hardly occurs. That is, in the semiconductor device according to the disclosed invention, the number of rewritable times that is a problem in the conventional nonvolatile memory is not limited, and the reliability is dramatically improved. Further, data is written depending on the on / off state of the transistor, so that high-speed operation can be easily realized.

The storage device described in this embodiment is, for example, a CPU (Central Processing Unit), a DSP (Digital Signal Processor), a custom LSI, an LSI such as a PLD (Programmable Logic Device), or an RF-Tag (Radio Frequency Tag) application. Is possible.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 9)
In this embodiment, a CPU (central processing unit) including the storage device described in Embodiment 4 will be described.

FIG. 29 is a block diagram illustrating a configuration example of a CPU using at least part of the transistor described in the above embodiment.

29 includes an ALU 1191 (ALU: arithmetic logic unit), an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, a register controller 1197, and a bus interface 1198. (Bus I / F), a rewritable ROM 1199, and a ROM interface 1189 (ROM I / F). As the substrate 1190, a semiconductor substrate, an SOI substrate, a glass substrate, or the like is used. The ROM 1199 and the ROM interface 1189 may be provided in separate chips. Needless to say, the CPU illustrated in FIG. 29 is just an example in which the configuration is simplified, and an actual CPU may have various configurations depending on the application. For example, the configuration including the CPU or the arithmetic circuit illustrated in FIG. 29 may be a single core, and a plurality of the cores may be included, and each core may operate in parallel. Further, the number of bits that the CPU can handle with the internal arithmetic circuit or the data bus can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, or the like.

Instructions input to the CPU via the bus interface 1198 are input to the instruction decoder 1193, decoded, and then input to the ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195.

The ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 generates a signal for controlling the operation of the ALU 1191. The interrupt controller 1194 determines and processes an interrupt request from an external input / output device or a peripheral circuit from the priority or mask state during execution of the CPU program. The register controller 1197 generates an address of the register 1196, and reads and writes the register 1196 according to the state of the CPU.

In addition, the timing controller 1195 generates a signal for controlling the operation timing of the ALU 1191, the ALU controller 1192, the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197. For example, the timing controller 1195 includes an internal clock generation unit that generates an internal clock signal based on the reference clock signal, and supplies the internal clock signal to the various circuits.

In the CPU illustrated in FIG. 29, a memory cell is provided in the register 1196. As the memory cell of the register 1196, the transistor described in Embodiment 1 or the memory device described in Embodiment 2 can be used.

In the CPU shown in FIG. 29, the register controller 1197 selects a holding operation in the register 1196 in accordance with an instruction from the ALU 1191. That is, whether to hold data by a flip-flop or to hold data by a capacitor in a memory cell included in the register 1196 is selected. When data retention by the flip-flop is selected, the power supply voltage is supplied to the memory cell in the register 1196. When holding of data in the capacitor is selected, data is rewritten to the capacitor and supply of power supply voltage to the memory cells in the register 1196 can be stopped.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 10)
In this embodiment, application examples of an RF tag that can include the semiconductor device of one embodiment of the present invention will be described with reference to FIGS. Applications of RF tags are wide-ranging. For example, banknotes, coins, securities, bearer bonds, certificates (driver's license, resident's card, etc., see FIG. 30A), recording media (DVD, video tape, etc.) , FIG. 30B), packaging containers (wrapping paper, bottles, etc., see FIG. 30C), vehicles (bicycles, etc., see FIG. 30D), personal items (such as bags and glasses) , Articles such as foods, plants, animals, human bodies, clothing, daily necessities, medical products including drugs and drugs, or electronic devices (liquid crystal display devices, EL display devices, television devices, or mobile phones), Alternatively, it can be used by being provided on a tag (see FIGS. 30E and 30F) attached to each article.

The RF tag 4000 according to one embodiment of the present invention is fixed to an article by being attached to a surface of a printed board or embedded therein. For example, a book is embedded in paper, and a package made of an organic resin is embedded in the organic resin and fixed to each article. The RF tag 4000 according to one embodiment of the present invention achieves small size, thinness, and light weight, and thus does not impair the design of the article itself even after being fixed to the article. In addition, by providing the RF tag 4000 according to one embodiment of the present invention to bills, coins, securities, bearer bonds, or certificates, etc., an authentication function can be provided. Counterfeiting can be prevented. In addition, by attaching the RF tag according to one embodiment of the present invention to packaging containers, recording media, personal items, foods, clothing, daily necessities, electronic devices, etc., the efficiency of a system such as an inspection system can be improved. Can be planned. Even in the case of vehicles, the security against theft or the like can be improved by attaching the RF tag according to one embodiment of the present invention.

As described above, by using the RF tag according to one embodiment of the present invention for each application described in this embodiment, operating power including writing and reading of information can be reduced, so the maximum communication distance can be increased. Is possible. In addition, since the information can be held for a very long period even when the power is cut off, it can be suitably used for applications where the frequency of writing and reading is low.

Next, an example of using a display device that can include the semiconductor device of one embodiment of the present invention is described. As an example, the display device includes a pixel. A pixel has a transistor and a display element, for example. Alternatively, the display device includes a driver circuit that drives pixels. The drive circuit includes, for example, a transistor. For example, the transistors described in the other embodiments can be employed as these cv transistors.

For example, in this specification and the like, a display element, a display device that is a device including a display element, a light-emitting element, and a light-emitting device that is a device including a light-emitting element have various forms or have various elements. Can do. As an example of a display element, a display device, a light emitting element, or a light emitting device, an EL (electroluminescence) element (an EL element including an organic substance and an inorganic substance, an organic EL element, an inorganic EL element), an LED (white LED, red LED, green LED) , Blue LED, etc.), transistor (transistor that emits light in response to current), electron-emitting device, liquid crystal device, electronic ink, electrophoretic device, grating light valve (GLV), plasma display (PDP), MEMS (micro electro Display device using mechanical system), digital micromirror device (DMD), DMS (digital micro shutter), MIRASOL (registered trademark), IMOD (interference modulation) device, shutter-type MEMS display device, Light dry MEMS display element type, electrowetting element, a piezoelectric ceramic display, or a carbon nanotube, etc., by an electric magnetic action, those having contrast, brightness, reflectance, a display medium such as transmittance changes. An example of a display device using an EL element is an EL display. As an example of a display device using an electron-emitting device, there is a field emission display (FED), a SED type flat display (SED: Surface-Conduction Electron-Emitter Display), or the like. As an example of a display device using a liquid crystal element, there is a liquid crystal display (a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, a direct view liquid crystal display, a projection liquid crystal display) and the like. An example of a display device using electronic ink or an electrophoretic element is electronic paper. Note that in the case of realizing a transflective liquid crystal display or a reflective liquid crystal display, part or all of the pixel electrode may have a function as a reflective electrode. For example, part or all of the pixel electrode may have aluminum, silver, or the like. Further, in that case, a memory circuit such as an SRAM can be provided under the reflective electrode. Thereby, power consumption can be further reduced.

Note that this embodiment can be combined with any of the other embodiments and examples in this specification as appropriate.

In Example 1, the display device according to one embodiment of the present invention was decomposed, and it was confirmed that excess oxygen remained.

Here, the display device A, the display device B, and the display device C created in different manufacturing processes were evaluated. The display device has a structure similar to that in FIG. 7B described in the above embodiment. Therefore, unless otherwise specified, description will be made below using the reference numerals illustrated in FIG.

The display device A includes a conductive film over the first substrate 901, a gate insulating film 922 over the substrate and the conductive film, an oxide semiconductor film over the gate insulating film 922, and an insulating film 924 over the oxide semiconductor film. And an insulating film 926 over the insulating film 924, and the insulating film 924 is a silicon oxynitride film containing more oxygen than oxygen that satisfies the stoichiometric composition. In the display device B, as the insulating film 924 over the oxide semiconductor film, a silicon oxynitride film subjected to oxygen plasma treatment for 120 seconds from the same silicon oxynitride film as the display device A was used. In the display device C, as the insulating film 924 over the oxide semiconductor film, a silicon oxynitride film obtained by performing oxygen plasma treatment for 600 seconds from the same silicon oxynitride film as that of the display device A was used.

As an oxygen plasma treatment condition, an inductively coupled plasma (ICP) etching apparatus was used. ICP high frequency power 0 W, Bias high frequency power 4500 W, pressure 15 Pa, oxygen gas flow rate 250 sccm, substrate temperature 40 ° C., and processing time were 120 seconds for display device B and 600 seconds for display device C.

Next, the display device was disassembled and divided to prepare an evaluation sample. First, the second substrate 906 including the second electrode 931, the spacer 935, the insulating film 933, the liquid crystal layer 908, and the like was peeled from the first substrate 901. Peeling is performed by inserting a thin metal plate such as the tip of a cutter knife into the seal material 925 where the second substrate 906 and the first substrate 901 are bonded to each other at the end of the display device. Peeled off.

Next, the insulating film 932 having a function as an alignment film over the first substrate 901 was removed by a dry etching method using oxygen gas. Etching conditions were ICP high frequency power 6000 W, Bias high frequency power 2000 W, pressure 60 Pa, oxygen gas flow rate 900 sccm, etching time 120 sec, and lower electrode temperature 40 ° C. Next, the chemical solution mainly composed of oxalic acid was removed from the first electrode 930 formed of the transparent conductive film ITO at 60 ° C. by a wet etching method.

Next, the insulating film made of the silicon nitride film of the capacitor element was removed by a dry etching method using sulfur hexafluoride gas. Etching conditions were ICP high frequency power 2000 W, Bias high frequency power 1000 W, pressure 2.5 Pa, sulfur hexafluoride gas 900 sccm, etching time 120 sec, and lower electrode temperature 80 ° C.

Next, a chemical solution mainly composed of oxalic acid was removed from the transparent conductive film ITO functioning as an electrode of the capacitive element at 60 ° C. by a wet etching method. Next, only the upper layer portion of the planarizing film 921 formed of an organic resin is removed by a dry etching method using oxygen gas, and then the remaining planarizing film 921 is removed at a liquid temperature of 70 ° C. Removed. The dry etching conditions were the same as those obtained by removing the insulating film 932 described above.

Next, the insulating film 926 made of a silicon nitride film in contact with the insulating film 924 made of a silicon oxynitride film having excess oxygen was removed by a dry etching method using sulfur hexafluoride gas. Etching conditions were the same as those for the insulating film of the capacitor element described above.

Next, the pixel region of the evaluation substrate having excess oxygen and a silicon oxynitride film as the uppermost layer was divided to prepare an evaluation sample. Here, the size of the evaluation sample was 1 cm square.

Next, TDS analysis was performed on each evaluation sample. As TDS analysis conditions, the temperature of the heating heater was set to 50 ° C. at the start of measurement, 900 ° C. at the end of the measurement, and the heating rate was set to 32 ° C./min. The surface temperature of the sample film was about 50 ° C. at the start of measurement and about 500 ° C. at the end of measurement. The pressure in the sample chamber at the start of analysis was 1.2 × 10 ⁻⁷ Pa.

31A and 31B show the TDS analysis results of each evaluation sample. FIG. 31A is a graph of the temperature dependence of the release amount of the mass-to-charge ratio M / z = 32 corresponding to oxygen molecules, and FIG. 31B is a graph showing oxygen based on the data of FIG. The result of having quantified the discharge | release amount of the mass to charge ratio M / z = 32 corresponding to a molecule | numerator is shown.

When the graph of the temperature dependence of the oxygen molecule release amount of each evaluation sample in FIG. 31 (A) was observed, it was confirmed that the display devices A, B, and C were different. Moreover, the release amount of oxygen molecules in the evaluation sample of the display device A was 5.1 × 10 ¹⁴ molecules / cm ² . The release amount of oxygen molecules in the evaluation sample of the display device B was 1.8 × 10 ¹⁵ molecules / cm ² . The amount of released oxygen molecules of the evaluation sample of the display device C was 2.5 × 10 ¹⁵ molecules / cm ² .

From this result, it was found that excess oxygen remains in the oxide insulator even after the display device is manufactured. Further, it was confirmed that the oxygen plasma treatment with a longer treatment time releases more oxygen molecules.

As described above, with the evaluation method according to one embodiment of the present invention, it was confirmed that excess oxygen remained even after the display device was manufactured. In addition, the amount of released oxygen molecules remaining in the display device could be estimated.

40 silicon substrate 51 Si transistor 52 transistor 53 transistor 60 photodiode 61 anode 63 low resistance region 70 contact plug 71 wiring layer 72 wiring layer 73 wiring layer 80 insulating layer 100 transistor 102 substrate 104 conductive film 106 insulating film 107 insulating film 108 oxide Semiconductor film 110 Transistor 112a Conductive film 112b Conductive film 112c Conductive film 114 Insulating film 116 Insulating film 117 Protective film 118 Insulating film 120a Conductive film 120b Conductive film 120 sec Etching time 130 Capacitance element 141 Oxygen 141a Opening 141b Opening 142a Opening 142b Opening Part 142c opening 144 region 150 transistor 160 transistor 170 transistor 305 insulating film 320 oxide semiconductor film 501 pixel circuit 502 pixel part 04 drive circuit portion 504a gate driver 504b source driver 506 protection circuit 507 terminal portion 550 transistor 552 transistor 554 transistor 560 capacitor element 562 capacitor element 570 liquid crystal element 572 light emitting element 901 substrate 902 pixel portion 904 scan line driver circuit 906 substrate 908 liquid crystal layer 910 Transistor 911 Transistor 913 Liquid crystal element 915 Connection terminal electrode 916 Terminal electrode 918 FPC
919 Anisotropic conductive agent 921 Planarizing film 922 Gate insulating film 923 Insulating film 924 Insulating film 925 Sealing material 926 Insulating film 928 Channel protective film 930 Electrode 931 Electrode 932 Insulating film 933 Insulating film 935 Spacer 936 Sealing material 950 Silicon nitride film 951 Electrode 960 Partition 961 Light emitting layer 963 Light emitting element 964 Filler 970 Evaluation sample 1100 Layer 1189 ROM interface 1190 Substrate 1191 ALU
1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Register 1197 Register Controller 1198 Bus Interface 1199 ROM
1200 layer 1300 layer 1400 layer 3001 wiring 3002 wiring 3003 wiring 3004 wiring 3005 wiring 3400 capacitor element 4000 RF tag 5100 pellet 5120 substrate 5161 area 8000 display module 8001 upper cover 8002 lower cover 8003 FPC
8004 Touch panel 8005 FPC
8006 Display panel 8007 Backlight 8008 Light source 8009 Frame 8010 Printed circuit board 8011 Battery 9000 Case 9001 Display unit 9003 Speaker 9005 Operation key 9006 Connection terminal 9007 Sensor 9008 Microphone 9050 Operation button 9051 Information 9052 Information 9053 Information 9054 Information 9055 Hinge 9100 Portable information terminal 9101 portable information terminal 9102 portable information terminal 9200 portable information terminal 9201 portable information terminal

Claims (4)

A gate electrode, a gate insulator, an oxide semiconductor, and a passivation oxide insulator;
The gate insulator is disposed on the gate electrode;
The oxide semiconductor is disposed on the gate insulator;
The passivation oxide insulator is a semiconductor device disposed on the oxide semiconductor,
In the temperature-programmed desorption gas analysis, when the surface temperature of the film is in the range of 100 ° C. to 700 ° C. or 100 ° C. to 500 ° C., the oxygen desorption amount in terms of oxygen molecules is 8.0 × 10 ^14. A semiconductor device having a molecular weight / cm ² or more. A substrate, an oxide insulator on the substrate, an oxide semiconductor on the oxide insulator, an oxide insulator on the oxide semiconductor, an inorganic material on the oxide insulator, and an organic insulator In a semiconductor device having a display layer and a counter substrate,
Removing all layers above the oxide insulator on the oxide semiconductor;
After dividing into the size of 1 cm square, the amount of desorbed oxygen is measured by a temperature-programmed desorption gas analysis method in the range where the surface temperature of the film is 100 ° C. or higher and 700 ° C. or lower, or 100 ° C. or higher and 500 ° C. or lower, Evaluation method to measure. A substrate, an oxide insulator on the substrate, an oxide semiconductor on the oxide insulator, an oxide insulator on the oxide semiconductor, an inorganic material on the oxide insulator, and an organic insulator In a semiconductor device having a liquid crystal layer and a counter substrate,
Removing all layers above the oxide insulator on the oxide semiconductor;
After dividing into 1 cm square size, the amount of desorbed oxygen was determined by temperature-programmed desorption gas analysis.
The surface temperature of the film is measured in the range of 100 ° C. or more and 700 ° C. or less, or 100 ° C. or more and 500 ° C. or less, and the oxygen desorption amount in terms of oxygen molecules is 1.0 × 10 ¹⁴ molecule / cm ² or more. A semiconductor device characterized by the above. A substrate, an oxide insulator on the substrate, an oxide semiconductor on the oxide insulator, an oxide insulator on the oxide semiconductor, an inorganic material on the oxide insulator, and an organic insulator A semiconductor device having a light emitting element layer and a counter substrate.
Removing all layers above the oxide insulator on the oxide semiconductor;
After dividing into 1 cm square size, the amount of desorbed oxygen was determined by temperature-programmed desorption gas analysis.
The surface temperature of the film is measured in the range of 100 ° C. or more and 700 ° C. or less, or 100 ° C. or more and 500 ° C. or less, and the oxygen desorption amount in terms of oxygen molecules is 1.0 × 10 ¹⁴ molecule / cm ² or more. A semiconductor device characterized by the above.