JP2016082430A - On-vehicle electronic controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an on-vehicle electronic controller capable of preventing from erroneously determining an input noise as a failure on an A/D converter as well as capable of swiftly detecting a failure on an A/D converter.SOLUTION: The on-vehicle electronic controller includes: an A/D converter that performs an A/D conversion on an analog signal, which is transmitted from inside a vehicle and is divided into two parts, and outputs two conversion outputs; a first determination section that, when the difference between the two conversion outputs exceeds a first determine value, temporarily determines as abnormal; and an abnormality determination time variation section that varies the abnormality determination time based on whether the difference between the two conversion outputs exceeds a second determine value.SELECTED DRAWING: Figure 2

Description

  The present invention relates to an in-vehicle electronic control device including an A / D converter that A / D converts an analog detection signal output from a sensor mounted on a vehicle.

  An example of an apparatus for detecting a failure of an A / D converter that performs A / D conversion of an analog detection signal is described in Patent Document 1. In this apparatus, when two conversion outputs are output from the A / D converter and the difference between the two conversion outputs becomes larger than a set determination value, it is determined that the A / D converter has failed. It is configured to do. However, in the case of the above configuration, when noise enters, the difference between the two conversion outputs becomes larger than the determination value, so that it may be erroneously determined that the A / D converter has failed.

  As a configuration to prevent this erroneous determination, the number of abnormal times in which the difference between the two conversion outputs is larger than the determination value within a predetermined abnormality determination time is counted, and when the determination time has elapsed, the count value of the abnormal number is A configuration is considered in which it is determined that the A / D converter has failed when the count determination value becomes larger than the set count determination value. According to this configuration, it is possible to prevent erroneous determination when noise enters about once or twice.

Japanese Patent Laid-Open No. 11-22538

  However, in the case of the above configuration, if a situation in which a lot of noise occurs for some reason occurs, when the abnormality determination time has elapsed, the count value of the number of abnormalities becomes larger than the count determination value, and A / D conversion is performed. There is a possibility of misjudging that the instrument has failed. In this case, a countermeasure for setting a large count determination value can be considered, but in order to increase the count determination value, it is necessary to set a long abnormality determination time. If the abnormality determination time is lengthened, there arises a problem that when the A / D converter breaks down, it takes a long time to detect the failure.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an in-vehicle electronic control device that can prevent erroneous determination of an A / D converter failure when noise enters and can quickly detect a failure of an A / D converter. Is to provide.

  An in-vehicle electronic control device according to a first aspect of the present invention includes an A / D converter that takes in an inside of a vehicle and A / D converts an analog signal divided into two to output two conversion outputs, and the two conversions When the difference in output exceeds the first determination value, the abnormality determination is performed based on the first determination unit that determines that the provisional abnormality is present and whether the difference between the two conversion outputs exceeds the second determination value. It has a feature in that it includes an abnormality determination time variable unit that varies the time.

1 is a block diagram illustrating a schematic configuration of a throttle control device according to a first embodiment of the present invention. Flow chart of abnormality detection control Time chart when noise enters Time chart when A / D converter breaks down FIG. 1 equivalent view showing a second embodiment of the present invention FIG. 1 equivalent view showing a third embodiment of the present invention

  Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a block diagram showing a schematic configuration of a throttle control device (on-vehicle electronic control device) 2 that controls driving of a throttle 1 of a vehicle engine. As shown in FIG. 1, the throttle control device 2 includes an input circuit 3, a microcomputer 4, and a drive circuit 5.

  The input circuit 3 receives an analog detection signal Sa output from a sensor (accelerator position sensor) 7 for detecting the opening degree of the accelerator 6 of the vehicle, and divides the detection signal Sa into two to obtain a first detection signal Sa1. The second detection signal Sa2 is output to the microcomputer 4. The microcomputer 4 has an A / D converter 8 and a CPU 9.

  The A / D converter 8 receives the first detection signal Sa1 and the second detection signal Sa2 from the input circuit 3, performs A / D conversion, respectively, and outputs two conversion outputs, for example, the first A / D conversion signal Sb1 and the second detection signal Sa2. 2A / D conversion signal Sb2 is output to CPU9. The CPU 9 inputs the first A / D conversion signal Sb1 and the second A / D conversion signal Sb2 from the A / D converter 8, and based on the two first A / D conversion signals Sb1 and the second A / D conversion signal Sb2. Thus, the A / D converter 8 has a function of detecting whether or not it has failed. When the CPU 9 determines that the A / D converter 8 has not failed, the CPU 9 generates a throttle control signal based on the first A / D conversion signal Sb1 (or the second A / D conversion signal Sb2), The generated throttle control signal is output to the drive circuit 5. In the case of this configuration, the CPU 9 has functions as a first determination unit, an abnormality determination time variable unit, and a second determination unit.

  The drive circuit 5 receives a throttle control signal from the CPU 9 and outputs a drive voltage to an actuator (not shown) including a motor that drives a throttle valve (not shown) of the throttle 1 based on the throttle control signal. The actuator is energized and controlled.

  Next, the operation of the above configuration, in particular, the control for detecting whether or not the A / D converter 8 of the CPU 9 has failed (abnormality detection control) will be described with reference to the flowchart of FIG. First, in step S10 in FIG. 2, as a difference between two conversion outputs output from the A / D converter 8, for example, a voltage between the voltage of the first A / D conversion signal Sb1 and the voltage of the second A / D conversion signal Sb2 It is determined whether or not the difference Va (difference in A / D conversion result) is larger than a first determination value A1 set in advance.

  If the voltage difference Va is larger than the first determination value A1, the process proceeds to step S20, where the current state of the A / D converter 8 is assumed to be a temporary abnormality, and the abnormality determination flag is set to “1”. Set and increment (+1) the temporary abnormality counter. In this case, the abnormality determination flag is used when determining whether or not to perform the abnormality determination time update process. The temporary abnormality counter is used when abnormality determination is performed. On the other hand, when the voltage difference Va is equal to or smaller than the first determination value A1 in step S10, it is assumed that the current state of the A / D converter 8 is normal.

  Thereafter, the process proceeds to step S40, and it is determined whether or not the abnormality determination flag is 1. Here, when the abnormality determination flag is not 1 (that is, when the A / D converter 8 has never become a temporary abnormality and only a normal state is detected), the process proceeds to “NO” and proceeds to step S140. Then, it is determined that the A / D converter 8 is normal, and this control is terminated.

  On the other hand, when the abnormality determination flag is 1 in step S40 (that is, the current state of the A / D converter 8 is a temporary abnormality), the process proceeds to “YES”, and the process proceeds to step S50. In step S50, it is determined whether or not the voltage difference Va for A / D conversion is larger than a preset second determination value A2. Note that the second determination value A2 is set to a value larger than the first determination value A1. Here, when the voltage difference Va is larger than the second determination value A2, the process proceeds to “YES”, the process proceeds to step S60, and the abnormality determination time is shortened by time T1 (for example, 4 ms). The reason for shortening the abnormality determination time in this way is to enable early detection of an abnormality (failure) in the A / D converter 8 so that the abnormality can be promptly dealt with, such as fail-safe and storing of diagnostic information. Because.

  In step S50, when the voltage difference Va is equal to or smaller than the second determination value A2, the process proceeds to “NO”, the process proceeds to step S70, and the abnormality determination time is increased by time T2 (for example, 4 ms). The reason for making the abnormality determination time longer is to prevent erroneous detection even when a lot of noise enters.

  Subsequently, the process proceeds to step S80, where the determination number counter is incremented (+1) and the determination time counter is incremented (time T3 (for example, 4 ms) is added). The determination number counter is used to perform abnormality determination. The determination time counter is used for calculating the determination time.

  Next, the process proceeds to step S90, and it is determined whether or not the determination time counter is equal to or greater than the abnormality determination time. Here, when the determination time counter is less than the abnormality determination time, the process proceeds to “NO”, the abnormality determination is not performed, and the process ends. On the other hand, when the determination time counter is equal to or greater than the abnormality determination time in step S90, the process proceeds to “YES”, and the process proceeds to step S100 to perform abnormality determination. In step S100, it is determined whether or not the temporary abnormality counter / determination count counter (that is, the ratio between the count value of the temporary abnormality counter and the count value of the determination counter) is greater than a predetermined ratio (for example, 50%). . Here, when the temporary abnormality counter / determination count counter is larger than the predetermined ratio, the process proceeds to “YES”, and the process proceeds to step S110, where it is determined that the A / D converter 8 has this abnormality. If the temporary abnormality counter / determination count counter does not reach the predetermined ratio, the process proceeds to “NO”, proceeds to step S120, and determines that the A / D converter 8 is normal.

  In the abnormality determination in step S100, the reason for determining abnormality by comparing the ratios as described above is to prevent erroneous determination that the A / D converter 8 is normal. That is, even when the A / D converter 8 is in an abnormal state, the voltage difference Va of the A / D conversion result may be small depending on the input voltage. In such a case, the abnormality determination process is immediately performed. Then, the A / D converter 8 is erroneously determined to be normal. On the other hand, when the abnormality determination is performed at the rate of the abnormal time in the fixed time as in the present embodiment, the above-described normal erroneous determination can be prevented. In the conventional configuration, since the abnormality determination time is fixed, the abnormality determination processing for calculating and comparing the above-described ratio is not performed.

  Thereafter, the process proceeds to step S130, and the above-described flags, counters, etc. are initialized. Specifically, the abnormality determination flag is set to “0”, the temporary abnormality counter is cleared to “0”, the determination time counter is cleared to “0”, and a predetermined value (for example, 48 ms) is set to the abnormality determination time. . Thereby, abnormality detection control is complete | finished. In the present embodiment, the above-described failure detection process (abnormality detection control) of the A / D converter 8 shown in FIG. 2 is executed at a predetermined sampling period, for example, every 4 ms.

  Next, the operation of the abnormality detection control of the A / D converter 8 will be described with reference to FIGS. 3 and 4 show the first A / D conversion signal Sb1 and the second A / D conversion signal Sb2 output from the A / D converter 8, the voltage of the first A / D conversion signal Sb1, and the second A / D conversion signal Sb2. 5 is a timing chart showing the relationship between the voltage difference Va from the voltage of V, the operation of the abnormality determination time, the operation of the determination time counter, the operation of the temporary abnormality counter, and the determination timing. FIG. 3 is a timing chart when noise enters the input circuit 3 three times. FIG. 4 is a timing chart when the A / D converter 8 that has been operating normally fails in the middle.

  First, the operation when noise enters the input circuit 3 three times will be described with reference to FIG. In FIG. 3, the first A / D conversion signal Sb1 is a signal obtained by sampling and A / D conversion, and is not affected by the above three times of noise (see solid line). The second A / D conversion signal Sb2 is a signal obtained by sampling and A / D conversion, and is a signal affected by the above three times of noise (refer to a one-dot chain line). When noise enters, the voltage value of the first A / D conversion signal Sb1 and the voltage value of the second A / D conversion signal Sb2 are greatly different. For this reason, the voltage difference Va between the voltage of the first A / D conversion signal Sb1 and the voltage of the second A / D conversion signal Sb2 increases when noise enters, and decreases when there is no noise.

  At time t1 shown in FIG. 3, when the first noise is input, the determination time counter starts incrementing (for example, addition of 4 ms). At the same time, since the voltage difference Va between Sb1 and SB2 exceeds the first determination value A1, the temporary abnormality counter is also incremented (+1). Thereafter, noise enters at times t2 and t3, and noise enters a total of three times. As a result, the number of times that the voltage difference Va exceeds the first determination value A1 is 3, so that the value of the temporary abnormality counter is 3.

  In this embodiment, the initial value of the abnormality determination time is 48 ms. When the determination time calculation process shown in steps S50, S60, and S70 of FIG. 2 is executed, when the voltage difference Va exceeds the second determination value V2, the abnormality determination time is shortened, and the voltage difference Va is When it is less than the determination value V2, the abnormality determination time is lengthened. When the above three noises are input, the voltage difference Va is less than the second determination value V2, and therefore the abnormality determination time becomes longer (increases) every time noise is input. In this embodiment, for example, it is set to increase by 4 ms (T2 = 4 ms). In the present embodiment, the maximum setting value (maximum time) of the abnormality determination time is set to 64 ms, for example, and when noise enters four times (when the determination time calculation process is performed four times), the abnormality determination time is set. Is set to 64 ms, so that it does not become larger.

  Thereafter, the A / D conversion voltage difference Va is continuously calculated until the count value (calculation time) of the determination time counter reaches the abnormality determination time (60 ms). Then, when the count value of the determination time counter coincides with the abnormality determination time (when the determination timing comes, at time t4), the ratio of abnormality is calculated based on the value of the temporary abnormality counter, and abnormality determination is performed. To do. In the example shown in FIG. 3, the provisional abnormality / normality determination is performed 15 times, and the value of the provisional abnormality counter is 3, so the ratio of abnormality is 3/15 = 20%. Here, for example, if the threshold value (predetermined ratio) for abnormality determination is set to 50%, for example, in the example shown in FIG. 3, it is determined that the A / D converter 8 is normal.

  Next, with reference to FIG. 4, the operation when the A / D converter 8 which has been normally operating first fails in the middle will be described. In FIG. 4, the first A / D conversion signal Sb1 is a signal obtained by continuing A / D conversion normally even if the A / D converter 8 fails (see solid line). The second A / D conversion signal Sb2 is a signal that has been normally A / D converted, and is a signal from which a signal having a voltage of 0 V has been output since the A / D converter 8 has failed (one point). (See chain line).

  At time t11 shown in FIG. 4, when the A / D converter 8 fails, the determination time counter starts incrementing (for example, addition of 4 ms). Further, since the voltage difference Va between the voltage of the first A / D conversion signal Sb1 and the voltage of the second A / D conversion signal Sb2 exceeds the first determination value A1, the temporary abnormality counter is incremented (+1). After the A / D converter 8 has failed, the voltage difference Va between Sb1 and SB2 is larger than the first determination value A1, and therefore the temporary abnormality counter continues to be incremented until the determination timing comes.

  In this embodiment, the initial value of the abnormality determination time is set to 48 ms, for example. When the determination time calculation process shown in steps S50, S60, and S70 of FIG. 2 is executed, when the voltage difference Va exceeds the second determination value V2, the abnormality determination time is shortened, and the voltage difference Va is When it is less than the determination value V2, the abnormality determination time is lengthened. After the failure of the A / D converter 8, the voltage difference Va is larger than the second determination value A2, so that the abnormality determination time becomes shorter every time the determination time calculation process is executed. In the case of this embodiment, for example, it is set to decrease by 4 ms (T1 = 4 ms). In this embodiment, the minimum setting value (minimum time) of the abnormality determination time is set to 32 ms, for example, and when the determination time calculation process is performed four times (at time t12), the abnormality determination time is 32 ms. Therefore, it is configured not to become smaller.

  Thereafter, the A / D conversion voltage difference Va is continuously calculated until the count value (time) of the determination time counter reaches the abnormality determination time (32 ms). Then, when the count value of the determination time counter coincides with the abnormality determination time (when the determination timing is reached, at time t13), the ratio at which the A / D converter 8 is abnormal is determined based on the value of the temporary abnormality counter. Calculate and perform abnormality determination. In the example shown in FIG. 4, the provisional abnormality / normality determination is performed 8 times, and the value of the provisional abnormality counter is 8. Therefore, the ratio of abnormality is 8/8 = 100%. Here, for example, if the threshold value (predetermined ratio) for abnormality determination is set to 50%, for example, in the example shown in FIG. 4, the A / D converter 8 is determined to be abnormal (failure). The

  According to the present embodiment having such a configuration, when the voltage difference Va between the two digital signals Sb1 and Sb2 exceeds the first determination value A1, it is determined as a temporary abnormality, and the voltages of the two digital signals Sb1 and Sb2 Since the abnormality determination time is variable based on whether or not the difference Va exceeds the second determination value A2, the abnormality determination time can be increased when the voltage difference Va is small. It is possible to prevent erroneous determination when there is a lot of noise. Further, when the voltage difference Va is large, the abnormality determination time can be shortened, so that the abnormality can be determined promptly, so that the abnormality (failure) of the A / D converter 8 can be dealt with promptly.

  In the above embodiment, since the abnormality determination time is configured to be variable between the maximum setting value and the minimum setting value, the abnormality determination time can be prevented from becoming abnormally large or a negative value. .

  Furthermore, in the above embodiment, the abnormality determination time is continuously varied based on whether or not the voltage difference Va between the two digital signals exceeds the second determination value A2 until the abnormality determination is completed. The A / D converter 8 can be dealt with more quickly due to an abnormality (failure).

  In the above embodiment, the A / D converter 8 is determined to be abnormal when the ratio between the number of provisional abnormality detections and the abnormality determination time is equal to or greater than a predetermined ratio (predetermined value). Even if the A / D converter 8 is in an abnormal state, the voltage difference Va may happen to be small depending on the input voltage. By determining with the ratio of being in an abnormal state, it is possible to prevent erroneous determination as normal. The abnormality detection control (see FIG. 2) of the present embodiment can be realized without changing hardware by changing the control program of the microcomputer 4.

  FIG. 5 shows a second embodiment of the present invention. In addition, the same code | symbol is attached | subjected to the same structure as 1st Embodiment. In the second embodiment, the microcomputer 4 includes two A / D converters 11 and 12. The configuration of the second embodiment other than that described above is the same as the configuration of the first embodiment. Therefore, in the second embodiment, substantially the same operational effects as in the first embodiment can be obtained.

  FIG. 6 shows a third embodiment of the present invention. In addition, the same code | symbol is attached | subjected to the same structure as 1st Embodiment. In the third embodiment, an A / D converter 14 is provided in the input circuit 13. The configuration of the third embodiment other than that described above is the same as the configuration of the first embodiment. Therefore, in the third embodiment, substantially the same operational effects as in the first embodiment can be obtained.

  In each of the above embodiments, it is preferable that the abnormality detection process is stopped when the reference voltages of the A / D converters 8, 11, 12, and 14 are lowered. If comprised in this way, the erroneous detection of abnormality at the time of a reference voltage fall can be prevented.

  Further, in each of the embodiments described above, the maximum setting value (maximum time) of the abnormality determination time does not affect the behavior of the vehicle by using the abnormality conversion output of the A / D converters 8, 11, 12, and 14. It is preferable to set the minimum time. If comprised in this way, even when abnormality determination time is the maximum setting value, a user's unintended behavior can be prevented from making a vehicle.

  In each of the above embodiments, it is preferable that the minimum setting value (minimum time) of the abnormality determination time is the maximum time during which the actuator of the throttle 1 can be continuously driven. With this configuration, when an abnormality of the A / D converter 8 is detected, even if the abnormality conversion output of the A / D converter 8 is transmitted to the actuator, fail safe is performed so that the actuator does not operate abnormally. Can do.

  In each of the above embodiments, the difference between the two conversion outputs output from the A / D converter 8 is, for example, the voltage between the voltage of the first A / D conversion signal Sb1 and the voltage of the second A / D conversion signal Sb2. Although the difference Va is configured to be used, the present invention is not limited to this, and a difference between the other two conversion outputs output from the A / D converter 8 may be used.

  In the drawings, 1 is a throttle, 2 is a throttle control device (on-vehicle electronic control device), 3 is an input circuit, 4 is a microcomputer, 6 is an accelerator, 7 is a sensor, 8 is an A / D converter, and 9 is a CPU (first , 11 and 12 are A / D converters, 13 is an input circuit, and 14 is an A / D converter.

Claims (8)

An A / D converter (8) that takes in from the vehicle and A / D converts an analog signal divided into two to output two conversion outputs;
A first determination unit (9) that determines a temporary abnormality when a difference between two conversion outputs output from the A / D converter (8) exceeds a first determination value;
An on-vehicle electronic control device comprising: an abnormality determination time variable unit (9) that varies the abnormality determination time based on whether or not the difference between the two conversion outputs exceeds a second determination value.   The abnormality determination time variable unit (9) shortens the abnormality determination time when the difference between the two conversion outputs is larger than a second determination value, and the difference between the two conversion outputs is smaller than the second determination value. 2. The on-vehicle electronic control device according to claim 1, wherein when the time is small, the abnormality determination time is lengthened.   The on-vehicle electronic control device according to claim 1 or 2, wherein the abnormality determination time variable unit (9) varies the abnormality determination time between a maximum set value and a minimum set value.   The abnormality determination time variable unit (9) is characterized by continuously varying the abnormality determination time based on whether or not a difference between the two conversion outputs exceeds a second determination value until the abnormality determination is completed. The vehicle-mounted electronic control apparatus as described in any one of 1-3.   A second determination unit (9) is provided that determines that the A / D converter (8) is abnormal when the ratio of the number of provisional abnormality detections to the abnormality determination time is equal to or greater than a predetermined value. The on-vehicle electronic control device according to any one of claims 1 to 4.   The vehicle-mounted electronic control device according to claim 1, wherein the abnormality detection process is stopped when a reference voltage of the A / D converter (8) is lowered.   The maximum set value of the abnormality determination time is a minimum time that does not affect the behavior of the vehicle even by using the abnormal conversion output of the A / D converter (8). The vehicle-mounted electronic control apparatus of description.   The in-vehicle electronic control device according to claim 3, wherein the minimum set value of the abnormality determination time is a maximum time during which the actuator can be continuously driven.

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