JP2016082301A - Delay amount measurement circuit and delay amount measurement method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a delay amount measurement circuit capable of implementing measurements over a wide range by selecting the magnitude of a measurable delay amount and achieving power saving and circuit scale reduction with a little circuit resources, and a delay amount measurement method.SOLUTION: A delay amount measurement circuit 10 comprises: a plurality of delay elements 12 for buffer which are connected in an annular shape; a unit delay element 11 for trigger; and a counter 13 which is connected to each of the delay elements 12 for buffer, defines output of the delay element 12 for buffer as clock input and performs counting each time the clock input is inputted. A start signal that is inputted to the delay element 11 for trigger is delayed each time it is circulated through the delay elements 12 for buffer, and inputted to the counter 13. On the basis of a stop signal inputted to each of the delay elements 12 for buffer, the output of the delay element 12 for buffer is stopped and counting by the counter 13 is stopped.SELECTED DRAWING: Figure 4

Description

  The present invention relates to a delay amount measuring circuit and a delay amount measuring method for converting a time difference between input signals into a digital value.

  Conventionally, a product using an LSI (Large Scale Integrated Circuit) such as an Application Specific Integrated Circuit (ASIC) or a Field Programmable Gate Array (FPGA) needs to acquire a delay amount. For example, a delay amount measuring circuit of a phase locked loop (PLL), an input unit of a sensor or an analog-digital converter, or the like. In these, as a method and a circuit for measuring and acquiring the delay amount, a measuring method using a time digitizer (TDC) and its circuit have been proposed and widely used.

  Here, the configuration and operation of the TDC will be described with reference to FIG. FIG. 1 shows a conventional TDC 100. As shown in FIG. 1, the TDC 100 includes a delay line 102 configured by connecting a plurality of delay elements 101 that delay an input reference clock signal (CLK) by a predetermined delay amount τ1, and this delay line 102, A plurality of delay flip-flops (DFF) 103 having a delay signal delayed by the delay line 102 as a data input D and a measured signal as a clock input, and an output Q of each DFF 103, a reference clock signal and a measured signal are obtained. And an encoder circuit 104 for measuring the time difference.

  In such a TDC 100, the delay signal output from each delay element 101 is delayed by the delay amount τ1 and input to the next delay element 101. Therefore, when the signal under measurement is in the “high (H)” state, for example, the delay signal before a certain delay element 101 is in the “high (H)” state, and the delay of the delay element 101 thereafter The signal is in a “low (L)” state. The output Q of each DFF 103 to which the delayed signal in each state is input as the data input D is in a “high (H)” state before a certain DFF 103, and “low (L)” in the DFFs thereafter. State. The position at which the output of the DFF 103 changes from “high (H)” to “low (L)” or “low (L)” to “high (H)” is detected by the encoder circuit 104, so that the reference clock The time difference between the signal (CLK) and the signal under measurement is measured.

  The TDC 100 described above has a limit in the amount of delay that can be measured because the resolution is caused by the delay amount τ1 inherent in the delay element 101. Here, in order to further increase the resolution, the vernier type described in, for example, the following Patent Document 1, Non-Patent Document 1, and Non-Patent Document 2, which uses the difference between the delay amounts of two delay elements having different delay amounts, is used. There is TDC.

  Here, the configuration and operation of the vernier TDC will be described with reference to FIG. FIG. 2 shows a conventional vernier TDC 200. As shown in FIG. 2, the vernier TDC 200 includes a delay line 203 configured by connecting a plurality of delay elements 201 that delay an input reference clock signal (CLK) by a predetermined delay amount τ1 in series. , A second delay line 204 configured by connecting a plurality of delay elements 202 for delaying the input signal under measurement by a predetermined delay amount τ2 is connected in series. In the DFF 205 of the vernier TDC 200, the delayed signal delayed by the first delay line 203 is the data input D, and the delayed signal under measurement delayed by the second delay line 204 is the clock input.

  In such a vernier type TDC 200, the delay signal output from each delay element 201 in the first delay line 203 is delayed by the delay amount τ 1 and input to the next delay element 201. The delayed signal under measurement output from the delay element 202 is delayed by the delay amount τ 2 and input to the next delay element 202. For example, if τ 1> τ 2, the delayed signal input to the data input D is input to the clock input from a state where it becomes “high (H)” before the delayed measured signal input to the clock input. The delayed signal under measurement gradually changes to a state of being “high (H)” before the delayed signal input to the data input D. Since the position where the output of the DFF changes is detected by the encoder circuit 206, measurement with high resolution becomes possible due to the difference in delay amount between the two delay elements 201 and 202 having different delay amounts.

JP 2012-138848 A

P. Dudek et aL. "A high-resolution CMOS time-to-digital converter utility a Vernier delay line," IEEE Journal of Solid-State Circuits, pp. 240-247, Feb. 2000 J. et al. Yu et aL. "A 12-Bit Vernier Ring Time-to-Digital Converter in 0.13 μm CMOS Technology," IEEE Journal of Solid-State Circuits, Vol. 45, no. 4, APRIL. 2010

  However, in the TDC 100 and the vernier TDC 200 described above, since one measurement is completed in principle from the first delay element to the last delay element, the amount of delay that can be measured is limited.

  In particular, the TDC 100 cannot be said to have good detection accuracy, and since the resolution is caused by the delay amount unique to the delay element 101, there is a limit to the delay amount that can be measured. On the other hand, the vernier TDC 200 has a configuration in which the resolution is increased by the difference in delay amount between the two delay elements 201 and 202 having different delay amounts, and conversely, it is difficult to measure a large delay amount with a lowered resolution. Even if the delay elements 201 and 202 can be added to increase the amount of delay that can be measured, the circuit resources increase, the power consumption increases, the circuit scale increases, and the circuit is compact. Implementation becomes difficult.

  Of course, the TDC 100 and the vernier TDC 200 need to add up values by the decoder every time the signal circulates in the loop of each delay line 101, 203, 204, and the vernier TDC 200 is compared with the TDC 100. Thus, the number of delay elements is doubled. From these circumstances, both have problems such as power consumption, circuit scale, and mounting difficulty.

  The present invention has been proposed in view of the above circumstances. In other words, it is possible to realize a wide range of measurements by selecting the amount of delay that can be measured, and a delay amount measurement circuit and delay amount measurement that can realize power saving and a small circuit scale with less circuit resources. The purpose is to provide a method.

  In order to achieve the above object, a delay amount measuring circuit according to the present invention is a delay amount measuring circuit for measuring a time difference between a first signal and a second signal, a plurality of delay elements connected in a ring, A counter connected to a delay element and having the output of the delay element as a clock input and counting each time the clock input is input, and the counter is input to one of the plurality of delay elements. One signal is delayed each time it goes around each delay element and is input to the counter. Based on the second signal input to the delay element, the output of the delay element is stopped and the counter counts. It is characterized by stopping.

  The delay amount measurement circuit according to the present invention is a delay amount measurement circuit for measuring a time difference between a first signal and a second signal, and includes a plurality of delay elements connected in a ring shape and the delay elements connected to the delay elements. A counter that counts each time the clock input is input, and the first signal input to one of the plurality of delay elements is connected to each of the delay elements. The delay element is delayed each time it is circulated and is input to the counter, and based on the second signal input to the delay element, the output of the delay element is stopped and the counting of the counter is stopped. Yes.

  The delay amount measuring circuit according to the present invention is characterized in that an additional delay element is connected between the delay elements to which the counter is connected.

  The delay amount measurement circuit according to the present invention is characterized in that a pulse conversion circuit for converting the first signal and / or the second signal, which are level inputs, into a pulse input is provided.

  The delay amount measurement circuit according to the present invention includes a delay amount measurement circuit group including a plurality of delay amount measurement circuits, and a statistical processing circuit that calibrates a value based on the measurement result of each of the delay amount measurement circuits. It is characterized by that.

  The delay amount measuring method according to the present invention is the delay amount measuring method for measuring the time difference between the first signal and the second signal, wherein the first signal is supplied to one of the plurality of delay elements connected in a ring shape. The first signal is delayed each time the delay element is cycled, and the input of the delay element is input to the counter connected to each delay element as a clock input. And a step of inputting the second signal to the delay element, stopping the output of the delay element based on the second signal, and stopping the counting of the counter. It is said.

  A delay amount measuring method according to the present invention is a delay amount measuring method for measuring a time difference between a first signal and a second signal, wherein one of the first signals input to a plurality of delay elements connected in a ring shape. Selecting the first signal, inputting the selected first signal to one of the plurality of delay elements, and delaying the selected first signal every time the delay elements are circulated Each time the output of the delay element is input as a clock input to the counter connected to each of the delay elements, the second signal is input to the delay element, and the second signal is input to the delay element. Measured each time the procedure of stopping the output of the delay element and the counting of the counter based on the procedure, the procedure of measuring the time difference based on the selected first signal, and the selection of the first signal are repeated. Multiple before Including the steps of calculating the measurement results from the time difference, it is characterized in that.

  The delay amount measuring method according to the present invention includes a procedure of delaying an input of the delay element according to an additional delay element connected between the delay elements to which the counter is connected.

  The delay amount measuring method according to the present invention includes a procedure for converting the first signal and / or the second signal, which are level inputs, into pulse inputs.

  The delay amount measuring method according to the present invention is characterized in that a value is calibrated based on a plurality of measurement results obtained by the delay amount measuring method.

  The delay amount measuring circuit according to the present invention has the above-described configuration and is a so-called asynchronous type. That is, the first signal input to one of the plurality of delay elements is delayed each time it circulates through each delay element, and the output of the delay element is used as a clock input to the counter connected to each delay element. It is counted every time this clock input is input, and this count is repeated until it reaches the upper limit of the counter and overflows. Therefore, it is possible to realize a wide range of measurements by selecting the amount of delay that can be measured from a small delay amount to a large delay amount.

  In addition, the power supply circuit for the reference clock signal is not required compared to the conventional case, the delay line for the data input D is not required, and particularly the number of delay elements is smaller than that of the vernier type TDC. For this reason, a small circuit scale can be realized with a small number of circuit resources.

  Furthermore, since the first signal input to one of the plurality of delay elements circulates through each delay element, a reference clock signal and a power source for that purpose are unnecessary. Therefore, the detection accuracy can be improved and power saving can be realized.

  A delay amount measurement circuit according to the present invention includes an input signal selection circuit that selects one of first signals input to a plurality of delay elements, and a time difference based on the selected first signal, and an input signal And an arithmetic circuit for calculating a measurement result from a plurality of time differences measured each time selection by the selection circuit is repeated. With this configuration, by selecting the first signal to be input to the delay element, a plurality of time differences with respect to the same first signal are measured based on different delay elements, and measured by statistical processing using these as samples. The result is calculated. Therefore, even when the delay amount of the delay element is slightly different for each delay element due to manufacturing variations, for example, the detection accuracy can be improved.

  In the delay amount measuring circuit according to the present invention, an additional delay element is connected between delay elements to which a counter is connected. With this configuration, the amount of delay increases by the amount of the additional delay element. Therefore, the delay amount that can be measured can be increased.

  The delay amount measurement circuit according to the present invention includes a pulse conversion circuit that converts a first signal and / or a second signal, which are level inputs, into a pulse input. With this configuration, malfunction due to noise during level input can be prevented. Therefore, power saving and a small circuit scale can be realized with a small number of circuit resources.

  The delay amount measurement circuit according to the present invention includes a delay amount measurement circuit group including a plurality of delay amount measurement circuits, and a statistical processing circuit that calibrates a value based on the measurement result of each delay amount measurement circuit. Yes. With this configuration, the delay amount measurement circuit is made redundant as a delay amount measurement circuit group, and the measurement result is calculated by statistical processing using the measurement result of each delay amount measurement circuit as a sample. Therefore, the detection accuracy can be further improved.

  The delay amount measuring method according to the present invention can realize a wide range of measurements by selecting the amount of delay that can be measured, similarly to the delay amount measuring circuit described above, and can save power by using less circuit resources. A small circuit scale can be realized.

It is the block diagram in which the basic composition of the conventional TDC was shown. It is the block diagram in which the basic composition of the conventional vernier type TDC was shown. It is a timing diagram of the first signal and the second signal that are input to the delay amount measurement circuit and the delay amount measurement method according to the embodiment of the present invention. 1 is a block diagram illustrating a delay amount measurement circuit according to a first embodiment of the present invention. It is the block diagram in which the delay amount measurement circuit which concerns on 2nd embodiment of this invention was shown. It is the block diagram in which the delay amount measurement circuit which concerns on 3rd embodiment of this invention was shown. FIG. 10 is a block diagram illustrating a delay amount measurement circuit according to a fourth embodiment of the present invention. It is a simulation waveform diagram by the delay amount measuring circuit according to the first embodiment of the present invention.

  Hereinafter, a delay amount measurement circuit and a delay amount measurement method according to an embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a timing diagram of a start signal as a first signal input to the delay amount measurement circuit and a stop signal as a second signal input to the delay amount measurement circuit according to the embodiment of the present invention. FIG. 4 is a block diagram of the delay measurement circuit 10 according to the first embodiment of the present invention.

  In the delay amount measuring circuit 10 according to the embodiment of the present invention, a time difference between two different input signals (start signal and stop signal) is set as a delay amount Δ, and the delay amount Δ is measured. That is, as shown in FIG. 3, the delay amount Δ is increased from “low (L)” to “high (H)”, and the rising edge of the start signal changes from “low (L)” to “high (H)”. Is the time difference from the rising edge of the stop signal. The start signal and the stop signal are not limited to those shown in FIG. 3, and may be falling edges that change from “high (H)” to “low (L)”. The start signal and stop signal may be either a pulse signal or a level signal. If the start signal is a level signal, the level signal is waveform-shaped to form a pulse signal, and matching is achieved by adding a delay amount equivalent to the delay amount required for waveform shaping to the stop signal. In this case, a pulse conversion circuit (not shown) is connected before the input.

  As shown in FIG. 4, the delay amount measuring circuit 10 according to the first embodiment of the present invention has a ring topology, and each element constituting the ring is a delay element. A counter 13 having a bus width of 3 bits is arranged so as to divide these delay elements into a fixed number. That is, the delay amount measurement circuit 10 includes a plurality of delay elements connected in a ring shape, and a counter 13 that is connected to each delay element and uses the output of the delay element as a clock input, and counts each time this clock input is input. And a clock line 14 is formed by connecting a counter 13 between the respective delay elements.

  The delay element has an inherent delay amount that delays an input signal and outputs the delayed signal. The delay elements include a trigger delay element 11 and a buffer delay element 12. Here, one side of the trigger delay element 11 is connected to the output side of the buffer delay element 12 via the clock line 14, and the other side receives a start signal which is a pulse signal. On the other hand, one of the buffer delay elements 12 is connected to the output side of the trigger delay element 11 (or the buffer delay element 12) via the clock line 14 on the input side, and the other is a stop which is a pulse signal. A signal is input.

  The trigger delay element 11 is, for example, an OR gate. That is, if one of the input sides is “high (H)”, the output is “high (H)”. On the other hand, the buffer delay element 12 is, for example, an AND gate, and one of the input side is positive logic and the other is negative logic. That is, if one input is “high (H)” and the other is “low (L)”, the output is “high (H)”, but the other is “high (H)”. The output becomes “low (L)”.

  The counter 13 is a DFF counter, for example. In other words, the output of each buffer delay element 12 (or trigger delay element 11) is connected to the reference clock input on the clock line 14, and the output Q is connected to the input D. The count value of the counter 13 may be positive or negative as long as it is an integer, and the increment may be 1 or more. Although the bus width is 3 bits, since there is no mounting complexity regarding the increase and decrease of the bus width, an arbitrary bus width such as 8 bits may be selected according to the use of the delay amount measurement circuit.

  The delay elements 11 and 12 and the counter 13 described above are not limited to the embodiment of the present invention, and are realized by various logic circuits (sequential circuits). In addition, the number of each of the delay elements 11 and 12 and the counter 13 is arbitrary, and it is desirable to use a necessary number according to the use of the delay amount measuring circuit 10. When the number is large, the mounting becomes complicated accordingly, and in actual applications, it is necessary to trade off the number of delay elements. The total sum of the delay amounts of the respective delay elements 11 and 12 and the delay amount due to the wiring is allowed to be different depending on each counter 13, but when the difference between the sums is large, the detection accuracy of the delay amount Δ decreases. It is desirable to adjust according to the use of the delay amount measuring circuit 10.

  When the delay amount measuring circuit 10 is mounted on an integrated circuit, it is necessary to mount without degrading the detection accuracy of the delay amount Δ. When the delay amount measurement circuit 10 is mounted on an ASIC, the same buffer cell or logic element is used as a delay element, and the counters 13 are wired with the same length. In this regard, the counters 13 are arranged and wired at equal lengths in consideration of the delay amount of the OR element between the start signal and the input from the feedback loop of the clock line 14. Further, the stop signals input to the buffer delay elements 12 between the counters 13 are all arranged at the same length and with the same delay so that the delay amount between the counters 13 is equivalent. On the other hand, when the delay amount measurement circuit 10 is mounted on an FPGA, an LUT (Look-Up-Table) or a memory element (block RAM (Random Access Memory) or distributed RAM) inside the FPGA is used as the delay element. Moreover, in the wiring of FPGA, since wiring is established through the switch block, it is difficult to wire the same length. Therefore, the delay elements 11 and 12 are not necessarily arranged linearly in the vertical direction with respect to the FPGA chip, and it is not always necessary to arrange and wire the elements linearly in the vertical direction in consideration of the element arrangement inside the FPGA. Multiple stages in the vertical direction.

  Next, the operation of the delay amount measurement circuit 10 according to the first embodiment will be described.

  When a start signal (“Pulse_In” in FIG. 4) is input to the trigger delay element 11 which is one of the plurality of delay elements, the pulse signal propagates through the clock line 14 and is used for each buffer. The delay element 12 is circulated. When the pulse signal goes around and is inputted to the trigger delay element 11, a logical sum (OR) is taken in the trigger delay element 11, and is outputted and goes around the clock line 14 again.

  Each time the start signal circulates through the delay elements 11 and 12, the start signal is delayed by the delay amount of the delay elements 11 and 12 and input to the counter 13. When a delayed signal ("Internal_Pulse" in FIG. 4) that is a delayed signal is input to the reference clock input of the counter 13 as a rising edge, the counter value of the counter 13 is incremented by "+1" and counted.

  When a stop signal ("Stop_Flag" in FIG. 4) is input to the buffer delay element 12, a logical product (AND) is taken in the buffer delay element 12, the output of the buffer delay element 12 is stopped, and the clock line 14 Is not propagated to the buffer delay element 12 at the next stage. The stop signal is simultaneously input to all the buffer delay elements 12. Therefore, regardless of which buffer delay element 12 the pulse signal is input to, the output of all buffer delay elements 12 is stopped.

  When the output of the buffer delay element 12 is stopped, the input to the counter 13 is interrupted, so that the counter 13 stops counting. That is, by counting the count value of each counter 13, the transition time difference between the start signal and the stop signal can be measured as the delay amount Δ. After the delay amount Δ is measured, the counter 13 is appropriately initialized by a reset signal. The reset signal may be positive or negative in polarity, and may be either a synchronous reset or an asynchronous reset. However, a clock is required for synchronous reset.

  Next, the effect of the delay amount measurement circuit 10 according to the first embodiment will be described.

  As described above, the delay amount measurement circuit 10 according to the first embodiment is asynchronous, and includes a plurality of buffer delay elements 12 and a single trigger delay element 11 connected in a ring, and each buffer delay element. 12 and a counter 13 that receives the output of the buffer delay element 12 as a clock input. The counter 13 is connected between the buffer delay elements 11 to form a clock line 14. With this configuration, the start signal input to the single trigger delay element 11 is delayed each time it circulates through each buffer delay element 12 (or the trigger delay element 11), and each buffer delay element is delayed. The output of the buffer delay element 12 (or trigger delay element 11) is input to the counter 13 connected to 12 (or the trigger delay element 11) as a clock input. The counter 13 counts each time a clock input is input, and this count is repeated until the counter 13 reaches the upper limit value and overflows. Therefore, a wide range of measurement can be realized by selecting the magnitude of the delay amount Δ that can be measured from a small delay amount to a large delay amount.

  In addition, the power supply circuit for the reference clock signal is not required compared to the conventional case, the delay line for the data input D is not required, and particularly the number of delay elements is smaller than that of the vernier type TDC. For this reason, a small circuit scale can be realized with a small number of circuit resources.

  Furthermore, since the start signal input to one of the plurality of trigger delay elements 11 circulates through each buffer delay element 12, a reference clock signal and a power source for that purpose are not required. Therefore, the detection accuracy can be improved and power saving can be realized.

  Furthermore, since the stop signal is simultaneously input to each buffer delay element 12, the detection accuracy of the delay amount Δ can be maintained.

  Furthermore, by connecting a pulse conversion circuit to the previous stage of input, even if the start signal is a level signal, the level signal is waveform-shaped to form a pulse signal, and the delay amount required for waveform shaping Matching can be achieved by adding an equivalent delay amount to the stop signal. Therefore, malfunction due to noise at the time of level input can be prevented, and power saving and a small circuit scale can be realized with less circuit resources.

  Next, the delay amount measuring circuit 20 and the delay amount measuring method according to the second embodiment of the present invention will be described with reference to the drawings. FIG. 5 is a block diagram of the delay amount measuring circuit 20 according to the second embodiment of the present invention. In the following description, only the configuration different from the first embodiment is described, and the description of the same configuration is omitted.

  As shown in FIG. 5, the delay amount measuring circuit 20 according to the second embodiment is provided between the buffer delay elements 22 to which the counter 23 is connected (or between the buffer delay element 22 and the trigger delay element). 21), a plurality of additional delay elements 25 are connected. If the wiring is arranged so that the delay amount between the counters 23 is the same, the additional delay element 25 may have the same specification as the buffer delay element 22 or a different specification. The amount of delay is arbitrary. With this configuration, the amount of delay on the clock line 24 is increased by the amount of the additional delay element 25, and the input to each delay element 21, 22 is delayed according to the additional delay element 25. Therefore, the delay amount Δ that can be measured can be increased.

  By the way, according to the delay amount measuring circuits 10 and 20 and the delay amount measuring method according to the first embodiment and the second embodiment described above, the delay amount Δ can be detected with sufficiently high detection accuracy. Due to manufacturing variations at times, individual semiconductor elements and wirings have different characteristics for each LSI chip. In particular, due to manufacturing variations, the delay amounts Δ of individual semiconductor elements and wirings are slightly different, resulting in variations in the measured delay amount Δ. Therefore, it is possible to compensate for variations in measurement results and achieve higher detection accuracy based on the delay amount measurement circuit 30 according to the third embodiment, the delay amount measurement circuit 40 according to the fourth embodiment, and the like. This is a delay measurement method.

  Here, the delay amount measuring circuit 30 and the delay amount measuring method according to the third embodiment of the present invention will be described with reference to the drawings. FIG. 6 is a block diagram of the delay amount measuring circuit 30 according to the third embodiment of the present invention. In the following description, only the configuration different from the other embodiments is described, and the description of the same configuration is omitted.

  As shown in FIG. 6, the delay amount measuring circuit 30 according to the third embodiment of the present invention includes a plurality of buffer delay elements 32, an additional delay element 35, and a plurality of trigger delay elements 31 connected in a ring shape. The input signal selection circuit 36 for selecting one of the input signals input to the plurality of trigger delay elements 31 and the time difference Δ based on the start signal input to the selected trigger delay element 31 are measured. And an arithmetic circuit (not shown) for calculating a measurement result from a plurality of time differences Δ measured each time selection by the input signal selection circuit 36 is repeated.

  The first trigger delay element 31 to the nth trigger delay element 31 are connected in front of the respective counters 33 and receive the same start signal. That is, the start signal corresponds to the number n of the trigger delay elements 31 from the first start signal to the n-th start signal ("Pulse_INT0", "Pulse_INT2", "Pulse_INT3", and "Pulse_INTn" in FIG. 6). The input signal selection circuit 36 is configured by, for example, an LUT or a memory element, and one or a plurality of input signal selection circuits 36 are provided.

  As described above, the delay amount measurement circuit 30 according to the third embodiment can input the start signal to a plurality of arbitrary cells instead of fixing the cell to which the start signal is input at one place. It is a specification. With this configuration, when a start signal input to the trigger delay element 31 is selected, a plurality of time differences Δ based on different trigger delay elements 31 are measured for the same start signal, and the same A plurality of trials are performed with the start signal and the stop signal, and statistical processing is performed on the counter value as a result thereof. By calculating the measurement results by statistical processing using these as samples, the most appropriate and accurate delay amount Δ can be derived from a large number of samples as the measurement results. Therefore, even if the delay amount of each delay element 31, 32, 35 is slightly different for each delay element due to manufacturing variations, the detection accuracy can be improved.

  Further, by using a plurality of trigger delay elements 31, the symmetry of the delay amount measuring circuit 30 as a whole can be improved. In addition, it is also useful when it is difficult to place and route the stop signal to all the buffer delay elements 32 simultaneously.

  Furthermore, the input signal selection circuit 36 is arranged at a plurality of locations to make it redundant, and the detection accuracy can be further improved.

  Next, a delay amount measuring circuit 40 and a delay amount measuring method according to a fourth embodiment of the present invention will be described with reference to the drawings. FIG. 7 is a block diagram of a delay amount measuring circuit 40 according to the fourth embodiment of the present invention. In the following description, only the configuration different from the other embodiments is described, and the description of the same configuration is omitted.

  As shown in FIG. 7, the delay amount measurement circuit 40 according to the fourth embodiment of the present invention includes any one of the plurality of delay amount measurement circuits 10, 20, and 30, or any combination thereof is an array type. And a statistical processing circuit 47 that calibrates values based on the measurement results of the respective delay amount measuring circuits 10, 20, and 30. The statistical processing circuit 47 may be any circuit that can realize, for example, averaging or smoothing using a histogram.

  According to this configuration, the detection accuracy is further improved by making the circuit redundant and statistically processing the results of the entire delay measurement circuit group 48 using the measurement results of the respective delay measurement circuits 10, 20, and 30 as samples. Can be made. Further, the accuracy can be compensated by the delay amount measuring circuit and the delay amount measuring method, and the compensated value can be used for the calibration of the circuit to be used as a calibration method and a calibration circuit.

  Next, examples of the present invention will be described.

<Example>
According to the delay amount measurement circuit 10 shown in FIG. 4, 1 ns can be easily realized as a delay amount detection accuracy from a simulation of actual placement and wiring assuming mounting on an inexpensive FPGA (Spartan 6 manufactured by Xilinx). (See FIG. 8). Furthermore, when mounted on a high-function high-end FPGA or ASIC, it is possible to detect a delay amount in tens of picoseconds. In addition to the detection accuracy, in the case of FPGA (Spartan 6 manufactured by Xilinx), the circuit amount to be used is a design example of 8 stages, a counter bus width of 3 bits, LUT number: 32, register number: 36, occupied slice number : 24, and a very lightweight mounting is possible.

  As mentioned above, although embodiment of this invention was explained in full detail, this invention is not limited to the said embodiment. The present invention can be modified in various ways without departing from the scope of the claims. For example, application to circuit design technology, measurement technology for measuring detailed propagation delay differences, semiconductor characteristic evaluation technology for evaluating aging of semiconductors, temperature measurement technology using semiconductors, security technology such as individual authentication and information concealment Can do.

10, 20, 30, 40 Delay amount measurement circuit 11, 21, 31, 41 Trigger delay element (delay element)
12, 22, 32, 42 Delay element for buffer (delay element)
13, 23, 33, 43 Counter 14, 24, 34, 44 Clock line 25, 35 Additional delay element 36 Input signal selection circuit 47 Statistical processing circuit 48 Delay amount measurement circuit group 100 TDC
101 delay element 102 delay line 103 DFF
104 Encoder circuit 200 Vernier TDC
201, 202 delay element 203 first delay line 204 second delay line 205 DFF
206 Encoder circuit

Claims (10)

In the delay measurement circuit that measures the time difference between the first signal and the second signal,
A plurality of delay elements connected in a ring; and
A counter connected to each of the delay elements and having the output of the delay element as a clock input, and counting each time the clock input is input,
The first signal inputted to one of the plurality of delay elements is delayed and inputted to the counter each time it circulates through each of the delay elements,
Based on the second signal input to the delay element, the output of the delay element stops and the counting of the counter stops.
A delay amount measuring circuit. An input signal selection circuit for selecting one of the first signals input to a plurality of delay elements;
An arithmetic circuit that measures the time difference based on the selected first signal and calculates a measurement result from the plurality of time differences measured each time the selection by the input signal selection circuit is repeated; and
The delay amount measuring circuit according to claim 1, wherein: An additional delay element is connected between the delay elements to which the counter is connected.
3. The delay amount measuring circuit according to claim 1, wherein the delay amount measuring circuit is characterized in that: A pulse conversion circuit for converting the first signal and / or the second signal, which is a level input, into a pulse input;
The delay amount measuring circuit according to any one of claims 1 to 3, wherein the delay amount measuring circuit is characterized in that: A delay amount measuring circuit group including a plurality of delay amount measuring circuits according to any one of claims 1 to 4;
A statistical processing circuit that calibrates the value based on the measurement result of each of the delay amount measurement circuits,
A delay amount measuring circuit. In the delay amount measuring method for measuring the time difference between the first signal and the second signal,
A step of inputting the first signal to one of the plurality of delay elements connected in a ring;
A procedure for counting the input each time the first signal is delayed as it cycles through each delay element and the output of the delay element is input as a clock input to a counter connected to each delay element; ,
Including inputting the second signal to the delay element, stopping the output of the delay element based on the second signal, and stopping the counting of the counter.
A method for measuring a delay amount. In the delay amount measuring method for measuring the time difference between the first signal and the second signal,
Selecting one of the first signals input to a plurality of delay elements connected in a ring;
Inputting the selected first signal to one of the plurality of delay elements;
Each time the delay element is cycled, the selected first signal is delayed, and each time the output of the delay element is input to the counter connected to the delay element as a clock input, the input is counted. And the steps to
Inputting the second signal to the delay element, stopping the output of the delay element based on the second signal, and stopping counting of the counter;
Measuring the time difference based on the selected first signal;
Calculating a measurement result from a plurality of the time differences measured each time the selection of the first signal is repeated.
A method for measuring a delay amount. A step of delaying an input of the delay element according to an additional delay element connected between the delay elements to which the counter is connected,
8. The delay amount measuring method according to claim 6, wherein the delay amount is measured. Converting the first signal and / or the second signal, which are level inputs, into pulse inputs;
The delay amount measuring method according to any one of claims 6 to 8, wherein the delay amount is measured. A value is calibrated based on a plurality of measurement results obtained by the delay amount measurement method according to any one of claims 6 to 9.
A method for measuring a delay amount.