JP2016070899A - Heterodyne receiver circuit and radio wave clock composite circuit using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an adjustment circuit with which it is possible to adjust the frequency of a filter circuit with high accuracy while suppressing an increase in current consumption.SOLUTION: A heterodyne receiver circuit according to the present invention has: a local oscillation circuit 20 accepting a reference signal from the outside as input and generating a local oscillation signal; a MIX circuit 50 for generating an intermediate signal; a filter circuit for extracting the intermediate signal and generating an IF signal used in detection; a first adjustment circuit for adjusting manufacturing variations in the intermediate frequency of the filter circuit; first storage means for storing the data adjusted by the first adjustment circuit; a second adjustment circuit for adjusting variation in the intermediate signal caused by a shift from the logical value of the reference signal; and a first communication circuit for inputting the data adjusted by the second adjustment circuit. Regarding the adjustment of variation in the intermediate frequency, the second adjustment circuit corrects the frequency error of the reference signal outputted by an oscillation circuit 5 by adjusting the center frequency of the IF circuit 23 on the basis of the adjustment data, and thereby does not adjust the frequency of the oscillation circuit 5.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an electronic frequency selective receiving circuit.

  In recent years, mobile communication technology has been greatly developed, and various products have been proposed in which a reception function is mounted on a portable small device represented by a wristwatch. In particular, a long wave radio timepiece that receives a time code superimposed on a long wave standard radio wave has been commercialized in a large number of watches and table clocks. This long wave standard radio wave is transmitted in many countries such as German DCF 7 7, American WW V B, British MSF, Chinese BPC, Japanese JJ Y and so on. It has become.

  The frequency of these long-wave standard radio waves is 7 7. 5 KHz, BPC is 68.5 KHz, WWVB and MSF are 60 KHz, JJY's Kyushu station is 60 KHz, and Fukushima station is 40 KHz. The long wave radio clock is tuned to each frequency. Therefore, for example, in order to realize a long wave radio clock that can be used nationwide in Japan, it is necessary to receive radio waves with frequencies of 40 kHz and 60 kHz. There are many applications for such long-wave radio clocks that can be used nationwide.

  When receiving multiple long-wave standard radio waves with different frequencies, the long-wave radio clock uses a crystal filter that matches the standard radio frequency as the filter circuit, but the number of crystal filters is required according to the frequency to be received. There is a growing problem.

For this reason, a proposal has been made to reduce the number of crystal filters and reduce the size of the watch by using a heterodyne receiver capable of receiving a plurality of long-wave standard radio waves having different frequencies with one crystal filter. Yes. (For example, see Patent Document 1 and Patent Document 2)
In addition, a circuit that does not use a crystal filter has been proposed as an IF circuit used in a heterodyne receiver. (For example, see Patent Document 3)

JP 2004-294357 A (page 13, FIG. 1) JP-A-6-125280 (page 6, FIG. 1) Japanese Patent Laid-Open No. 63-242016 (page 7, FIG. 1)

The conventional techniques shown in Patent Document 1 and Patent Document 2 have the following problems.
The heterodyne receiver receives a long-wave standard radio wave, generates a standard radio wave signal, an oscillation circuit that generates a reference signal, and a plurality of local oscillation signals (hereinafter referred to as “local oscillation signals”) based on the reference signal. A local oscillation circuit to be created, a M I X circuit that mixes a local oscillation signal and a standard radio wave signal to create an intermediate signal, and an I F circuit that extracts the intermediate signal and outputs an I F signal (hereinafter referred to as “filter circuit”) And a control circuit that generates time information from the output of the detection circuit, and the intermediate signal generated by the MIX circuit matches the center frequency of the filter circuit. When the filter circuit has a narrow band, the reception sensitivity of the long wave standard radio wave varies greatly depending on the degree of coincidence between the center frequency of the filter circuit and the intermediate signal generated by the MIX circuit.

  The accuracy of the intermediate signal generated by the MIX circuit depends on the accuracy of the reference signal generated by the oscillation circuit, and the local oscillation circuit needs to be adjusted by the individual reference signal.

  In the filter circuit of Patent Document 3, the accuracy of the center frequency needs to be adjusted because the center frequency changes due to variations in capacitors used.

  Patent Document 1 discloses that a heterodyne receiver mixes a local signal generated based on a reference signal and a standard radio signal, and causes sensitivity deterioration due to a frequency shift between an intermediate signal output to a crystal filter and an intermediate frequency of the crystal filter. In order to improve the frequency of the reference signal, the frequency of the reference signal is adjusted. However, if the frequency of the reference signal is changed by the variable capacitance means, there is a problem that the current consumption of the oscillation circuit increases.

  SUMMARY OF THE INVENTION An object of the present invention is to provide an adjustment circuit that can adjust the frequency of a filter circuit with high accuracy while suppressing an increase in current consumption.

In order to achieve the above object, the present invention employs the following configuration.
That is, a local oscillation circuit that inputs a reference signal from the outside and creates a local oscillation signal;
A MIX circuit that mixes a local signal and a received signal to generate an intermediate signal;
A filter circuit that extracts an intermediate signal and generates an IF signal used for detection;
A first adjustment circuit for adjusting the manufacturing variation of the intermediate frequency of the filter circuit;
First storage means for storing adjustment data in the first adjustment circuit;
A second adjustment circuit for adjusting variation of the intermediate signal caused by deviation from the theoretical value of the reference signal;
A first communication circuit for inputting adjustment data in the second adjustment circuit;
The second adjustment circuit is characterized by adjusting the variation of the intermediate signal based on the adjustment data.

  According to the above aspect of the present invention, the reference signal is adjusted by adjusting the center frequency of the filter circuit including the amount of deviation of the center frequency of the filter circuit in the heterodyne receiving circuit and the amount of frequency deviation of the intermediate signal due to the frequency deviation of the reference signal. Therefore, it is possible to prevent an increase in current consumption of the oscillator that outputs the reference signal.

1 is a block diagram of a long wave radio timepiece in Embodiment 1. FIG. 1 is a block diagram of an IF circuit in Embodiment 1. FIG. 2 is a block diagram of a local oscillation circuit in Embodiment 1. FIG. FIG. 3 is a block diagram when a filter circuit is adjusted in the first embodiment. 6 is a flowchart at the time of filter circuit adjustment in Embodiment 1. FIG. FIG. 3 is a block diagram when adjusting a timepiece circuit according to the first exemplary embodiment. FIG. 6 is a flowchart at the time of clock circuit adjustment in the first embodiment. FIG. 3 is a flowchart at the time of reception in the first embodiment. 6 is a block diagram of a long wave radio timepiece in Embodiment 2. FIG. FIG. 10 is a flowchart at the time of reception in the second embodiment. It is a conceptual block diagram of the present invention. It is the figure which showed the filter characteristic change at the time of error adjustment of filter circuit itself. It is a figure which shows the filter characteristic at the time of reception after filter circuit error adjustment.

[Example 1]
Hereinafter, Example 1 will be described with reference to the drawings. In addition, although Example 1 is based on the case where it applies to a timepiece, description and illustration are abbreviate | omitted about the structural parts which are not related to invention, for example, structural parts of timepieces, such as a ground plate, receptacles, and a hand. .

[Description of Overall Configuration of First Embodiment: FIG. 1]
FIG. 1 is a block diagram of a long wave radio timepiece according to the first embodiment.
The overall configuration used for the long wave radio timepiece in Embodiment 1 of the present invention will be described with reference to the block diagram of FIG.

  Reference numeral 100 denotes a long wave radio clock, reference numeral 1 denotes an antenna that receives a long wave standard radio wave, and reference numeral 3 denotes a circuit board (composite circuit) that generates a standard radio signal 17 generated from the antenna 1 as time data and advances the time. 4) is a time display unit for displaying time information of the circuit board.

  The circuit board 3 receives the standard radio signal 17 generated from the antenna 1 and outputs the time data 13, and corrects the time based on the time data 13 generated by the heterodyne reception circuit 2. A clock circuit 6 that performs stepping (timekeeping) is mounted. Detailed configurations of the heterodyne reception circuit 2 and the clock circuit 6 will be described later.

  The circuit board 3 has an antenna terminal 31 to which the reception signal 16 generated from the antenna 1 is input, a display terminal 32 for outputting display contents to the time display unit 4, and a control for transmitting an operation from the outside to the clock circuit 6. A terminal 33 is provided.

  Next, the detailed configuration of the timepiece circuit 6 will be described later.

  Reference numeral 5 denotes an oscillation circuit that generates a reference signal 7 as a time reference. Reference numeral 8 denotes a stepping circuit that inputs a reference signal 7 and performs timekeeping. Reference numeral 11 denotes a clock memory circuit that stores the rate adjustment data 9 of the step circuit 8.

  The oscillation circuit 5 may be an inexpensive CR oscillation circuit as long as it is used only as a reference signal for the heterodyne reception circuit 2, but a crystal oscillation circuit is desirable because it can be shared with a clock oscillation circuit that requires time accuracy. Therefore, the first embodiment will be described using a crystal oscillation circuit.

  The step circuit 8 of the timepiece circuit 6 has a known logical frequency adjustment function, and the rate adjustment data 9 stored in the timepiece storage circuit 11 is adjusted by being supplied to the stepping circuit 8 via the control circuit 15. Has been.

  The clock storage circuit 11 is preferably a memory such as a non-volatile memory that does not lose stored data even when power is not applied.

  A communication circuit 12 outputs frequency data 10 including the rate adjustment data 9 and a control signal 26 including information for controlling the heterodyne reception circuit 2. A data receiving circuit 14 receives the time data 13 generated by the heterodyne receiving circuit 2.

  15 corrects the stepping circuit 8 using the time data 13 received from the data receiving circuit 14 as the current time, and corrects the time to display the current time on the clock display unit 4 based on the current time information from the stepping circuit 8; This is a control circuit that controls the time display function and the data communication through the communication circuit 12.

  Further, as external terminals, a CNT terminal 34 that transmits input from the control terminal 33 to the control circuit 15, a DSP terminal 35 that outputs display contents from the control circuit 15 to the display terminal 32, and a reference from the oscillation circuit 5 to the heterodyne reception circuit 2. CLK_out terminal 36 for outputting signal 7, S_out terminal 37 for outputting control signal 26 from communication circuit 12 to heterodyne reception circuit 2, and D_in terminal 38 for transmitting time data 13 from heterodyne reception circuit 2 to data reception circuit 14. ing.

  Next, the detailed configuration of the heterodyne reception circuit 2 will be described later.

  Reference numeral 18 denotes an amplifier circuit that amplifies the received signal 16 generated from the antenna 1 and outputs a standard radio signal 17. Reference numeral 20 denotes a local oscillation circuit that generates a local oscillation signal 19 from the reference signal 7 of the timepiece circuit 6. Reference numeral 50 denotes a MIX circuit that mixes the local oscillation signal 19 and the standard radio signal 17 to generate an intermediate signal 21. Reference numeral 23 denotes an IF circuit that extracts the IF signal 22 from the intermediate signal 21. Reference numeral 24 denotes a detection circuit that generates time data 13 from the IF signal 22. Reference numeral 25 denotes a communication circuit for a control signal 26 output from the clock circuit 6. Reference numeral 27 denotes a control circuit for controlling the heterodyne reception circuit 2 by the control signal 26.

  Further, as external terminals, an S_in terminal 39 that transmits a control signal 26 output from the clock circuit 6 to the communication circuit 25, a CLK_in terminal 40 that transmits a reference signal 7 output from the clock circuit 6 to the local oscillation circuit 20, and an antenna An ANT_in terminal 41 that transmits the received signal 16 from the terminal 31 to the amplifier circuit 18, a D_out terminal 42 that outputs time data from the detection circuit 24 to the clock circuit 6, and the pseudo intermediate signal 21 are input when adjusting the IF circuit 23. When adjusting the F_in terminal 43 and the IF circuit 23, an F_out terminal 44 for outputting the IF circuit 23 is provided.

  The F_in terminal 43 and the F_out terminal 44 of the heterodyne reception circuit 2 are not provided on the circuit board 3.

  FIG. 2 is a block diagram of the IF circuit according to the first embodiment.

  As shown in FIG. 2, the IF circuit 23 extracts a IF signal 22 that is a specific frequency signal from the intermediate signal 21 generated by the MIX circuit 50, and an adjustment that can adjust the center frequency of the filter circuit 28. The circuit 29 and the adjustment value storage circuit 30 that stores the set value 98 of the adjustment circuit 29 are provided.

  The filter circuit 28 can easily change the center frequency by adopting a switched capacitor filter (SCF) system similar to that of Patent Document 3. The filter circuit 28 according to the first embodiment will be described on the premise that the SCF is employed. However, any method other than the SCF may be employed as long as the center frequency can be changed.

  The filter circuit 28 is configured such that the center frequency can be changed with a certain frequency width by the rank data 99 transmitted from the adjustment circuit 29. In the first embodiment, the target center frequency is 500 Hz.

  The adjustment value storage circuit 30 is preferably a memory such as a nonvolatile memory that does not lose stored data even when power is not applied.

  Next, the local oscillation circuit 20 will be described in detail with reference to FIG.

FIG. 3 is a block diagram of the local oscillation circuit according to the first embodiment.
Reference numeral 201 denotes an oscillation circuit whose frequency can be varied, and generates a local oscillation signal 19.

  202 is a counter that counts the local oscillation signal 19, 205 is a counter that counts the reference signal 7 output from the clock circuit 6 via the CLK_in terminal 40, 203 is a counter 202, a comparison circuit that compares the outputs of the counter 205, 204 Is an oscillation adjustment circuit that adjusts the frequency setting of the oscillation circuit 201.

  The oscillation circuit 201 is configured by a CR oscillation circuit that can easily adjust the frequency, and the frequency can be adjusted by switching an applied voltage, a capacitor capacity to be used, a resistance value, and the like.

  Next, the operation of the local oscillation circuit 20 will be described.

When the frequency of the reference signal 7 is 32768 Hz, the frequency of the long wave standard radio wave to be received is 77.5 KHz of the DCF77 station, and the frequency of the intermediate signal is 500 Hz, the local signal 19 should be 77.5 KHz-500 Hz = 77000 Hz. Ideal.
Therefore, the comparison circuit 203 compares the outputs of the counters 202 and 205 so that the counter 202 becomes 77000 counts when the counter 205 counts 32768. If the count up of the counter 202 is early, the adjustment of the oscillation adjustment circuit 204 is performed. The value is set so that the oscillation circuit 201 is delayed, and when the count up of the counter 205 is early, the adjustment value of the oscillation adjustment circuit 204 is set so that the oscillation circuit 201 is accelerated.

  In the present invention, the DCF 77 station has been described as an example of the receiving station. However, when other long wave standard radio waves are received, the count values of the counters 202 and 205 are changed.

  As described above, the local oscillation signal 19 can be created from the reference signal 7, but the accuracy of the local oscillation signal 19 also varies depending on the accuracy of the reference signal 7.

  Table 1 shows the influence on the intermediate signal with respect to the frequency variation of a general crystal oscillator.

  As shown in Table 1, when the oscillation circuit 5 varies from 32766.2 Hz to 32769.8 Hz, an error of about ± 4.2 Hz occurs with respect to the target frequency 500 Hz of the intermediate signal. Since there is a difference from the center frequency, it is a major factor in reducing the reception sensitivity.

  In the first embodiment, the rate adjustment data 9 is set every 3.05 μS, which is 1/10 the accuracy of 30.5 μS, which is one cycle of the target frequency of the crystal oscillator. Therefore, the intermediate signal 21 changes by 0.1 Hz when the value of the rate adjustment data 9 changes by one. The rate adjustment data 9 is determined in accordance with the frequency of the reference signal shown in Table 1, and the step circuit 8 performs logical frequency adjustment based on the set rate adjustment data 9.

次に、本発明の概念について図１１、１２、１３を用いて説明を行なう。

Next, the concept of the present invention will be described with reference to FIGS.

  FIG. 11 is a conceptual block diagram of the present invention, and blocks having the same functions as those in FIGS.

  As described above, the reception sensitivity of the heterodyne reception circuit 2 varies greatly depending on the degree of coincidence between the center frequency of the filter circuit 28 and the frequency of the intermediate signal 21 generated by the reference signal 7.

  Therefore, in the present invention, the problem is solved by adjusting the center frequency of the filter circuit 28 to the frequency of the intermediate signal 21, and the error adjustment of the filter circuit 28 itself and the adjustment of the filter circuit 28 by the reference signal 7 This is achieved by adjusting in two stages.

  Next, the first stage adjustment will be described.

FIG. 12 is a diagram showing a change in the filter characteristics when the error of the filter circuit 28 itself is adjusted. 210 is a filter characteristic A indicating a filter characteristic before the error adjustment of the filter circuit 28 itself. In the first embodiment, the center frequency of the filter circuit without adjustment is 497 Hz, and 211 is an error adjustment of the filter circuit 28 itself. In this embodiment, the target value of the center frequency of the filter circuit is set to 500 Hz.

  Reference numeral 212 denotes an adjustment width A at the time of error adjustment of the filter circuit 28 itself, and 213 denotes an adjustment width B including the adjustment error A213 corresponding to the frequency error of the reference signal 7.

  As an operation at the time of error adjustment of the filter circuit 28 itself, the target value 500 Hz of the center frequency is output from the outside as a pseudo signal of the intermediate signal 21, and the rank data 99 output from the adjustment circuit 29 is changed to change the filter circuit 28. , The filter characteristic A 210 of the filter circuit 28 is matched with the filter characteristic B 211, and the rank data 99 is stored as the set value 98. Details of the adjustment method will be described later.

  Next, the second stage adjustment will be described.

FIG. 13 is a diagram illustrating filter characteristics when receiving a long wave standard wave after adjusting the filter circuit error. Reference numeral 301 denotes a filter characteristic C in a state where the above adjustment is performed, and reference numeral 302 denotes a filter characteristic D corrected by including the frequency error of the reference signal 7.
300 is an adjustment width C indicating the frequency error corresponding to the reference signal 7 after performing the above adjustment, and the frequency of the intermediate signal 21 can correspond to -4 to +11 Hz with respect to 500 Hz.

  Here, when the frequency of the intermediate signal 21 is shifted to 503 Hz due to the error of the reference signal 7, the frequency of the intermediate signal 21 becomes 503 Hz from the error data of the reference signal 7 measured by the adjustment process of the timepiece circuit 6. The calculated frequency data 10 is sent to the adjustment circuit 29, a value using the set value 98 and the frequency data 10 is sent to the filter circuit 28 as rank data 99, the filter characteristic C301 is changed to the filter characteristic D302, and the frequency of the intermediate signal 21 And the center frequency of the filter circuit 28 are combined to improve reception sensitivity. Details of the adjustment method will be described later.

  Next, a specific adjustment method according to the first embodiment will be described with reference to FIGS. 4, 5, 6, and 7.

  Adjustment of the error of the filter circuit 28 itself due to manufacturing variations of the filter circuit 28 is performed before the heterodyne reception circuit 2 is mounted on the circuit board 3. If the heterodyne receiving circuit 2 is made of a semiconductor such as an IC, it can be adjusted in the wafer state, and can be adjusted to a single circuit by dicing after adjustment, or can be adjusted in the inspection process with a tester or the like. Thus, the cost can be reduced.

  Further, since the heterodyne reception circuit 2 can be performed before being mounted on the circuit board 3, even if the heterodyne reception circuit 2 is a defective product that cannot be adjusted, only the heterodyne reception circuit 2 is rejected as a defective product. It is possible to prevent the circuit board 3 from being wasted by mounting the circuit 2.

  As will be described later, the F_in terminal 43 and the F_out terminal 44 are used for adjustment. However, since the adjustment is performed by the heterodyne reception circuit 2 alone, it is not necessary to connect the F_in terminal 43 and the F_out terminal 44 to the circuit board 3. This can contribute to simplification and miniaturization of the circuit board 3.

  FIG. 4 is a block diagram when adjusting the filter circuit 28, and 400 is a filter circuit adjusting device.

The filter circuit adjustment device 400 includes a signal generator 401 that outputs a pseudo intermediate signal to the F_in terminal 43, and an amplitude measurement device 402 that measures the amplitude of the IF signal output from the filter circuit 28 via the F_out terminal 44. , A control unit 403 that controls the heterodyne reception circuit 2 via the S_in terminal 39.

  As shown in Table 2, the filter circuit 28 of the first embodiment prepares 16 rank data for the adjustment width, and the adjustment width for each rank data is 1 Hz.

  The filter circuit 28 is designed to have a center frequency of 500 Hz when the rank data 99 is set to 7 or 8, and the center frequency can be changed by ± 8 Hz to cope with variations at the time of manufacture.

  The range corresponding to the center frequency described in Table 2 indicates the center frequency when the rank data 99 is 7 or 8, and from the center frequency of the filter circuit 28 measured by the amplitude measuring device 402 via the F_out terminal 44, By setting the rank data 99 corresponding to Table 2, the center frequency of the design value can be set to 500 Hz.

  In the first embodiment, the center frequency adjustment of the filter circuit 28 must take into account the adjustment range of the frequency data 10 calculated from the rate adjustment data described later, and therefore the rank data 99 is in the range from 4 to 11. It is adjusted with.

次に、フィルタ回路調整時の調整方法について図５を用いて説明する。

Next, an adjustment method at the time of filter circuit adjustment will be described with reference to FIG.

  FIG. 5 is a flowchart when the filter circuit is adjusted in the first embodiment.

  The adjustment of the filter circuit 28 starts from STEP 1, the data A and data B, which are variable data used in the calculation in STEP 2, are set to 0, and the rank data 99 for adjusting the center frequency of the filter circuit 28 is set to 3. Set. Subsequently, in STEP 3, the heterodyne reception circuit 2 is set to the adjustment mode of the filter circuit 28 from the control unit 403. In STEP 31, the rank data 99 is transmitted from the control unit 403 to the heterodyne reception circuit 2 to set the center frequency of the filter circuit 28.

  In STEP 4, a pseudo intermediate signal is input from the signal generator 401 to the filter circuit 28 via the F_in 43 terminal. The pseudo intermediate signal is set at the frequency of the intermediate signal in the design of the heterodyne reception circuit 6 and is adjusted at 500 Hz in the first embodiment.

  Next, in STEP 5, the IF signal 22 output from the heterodyne reception circuit 2 via the F_out terminal 44 is measured using the amplitude measuring device 402, and the measured value is stored in the data A which is a variable.

  Next, data A and data B are compared in STEP 6, and if data B is not larger (NO: if the previous measured value is not larger than the current measured value), the process moves to STEP 7 and rank data 99 is reached. The maximum value of 12 is compared. If the rank data 99 is not 12 (NO), the process proceeds to STEP8, the contents of the data A are copied to the data B, and the process proceeds to STEP9. In STEP 9, the rank data 99 is increased by one rank, the adjustment value of the filter circuit 28 is sent as rank data 99 from the control unit 403, and the process proceeds to STEP 5.

  If the rank data 99 is 12 in STEP 7 (YES), the rank data 99 is not adjusted to be greater than 11, so that the process proceeds to STEP 13, an adjustment error occurs, and the adjustment ends in STEP 14.

  Returning, if the data B is larger than the data A in STEP 6 (YES: the previous measured value is larger), the process proceeds to STEP 10 and is compared with the minimum value 4 of the rank data 99. When the rank data 99 is 4, since the peak value of the adjustment has not been detected, the process proceeds to STEP13, an adjustment error occurs, and the adjustment ends at STEP14.

  If the rank data 99 is not 4 in STEP 10 (NO), since the peak value of the adjustment is detected as normal, the process proceeds to STEP 11 and the rank data 99 is set to one rank in order to obtain the peak value rank data 99. DOWN, the process proceeds to STEP 12, rank data 99 is stored in the adjustment value storage circuit 30 as the set value 98, the process proceeds to STEP 14, and the adjustment is completed.

  By performing the above adjustment, the filter circuit 28 can exhibit an ideal filter effect for the intermediate signal 21 as designed.

  Next, a method for adjusting the rate of the oscillation circuit 5 in the timepiece circuit 6 will be described.

  The adjustment of the reference signal 7 is performed in a state where the clock circuit 6 is mounted on the circuit board 3, and the CLK_out terminal 36 and the SW terminal 34 provided on the circuit board 3 are used at the time of adjustment.

  This is because the crystal oscillator used in the crystal oscillation circuit used in this embodiment cannot be built in the IC and is mounted on the circuit board 3 as a separate component. Another reason is that the capacitance of the crystal oscillation circuit changes before and after mounting on the circuit board 3, and the oscillation conditions change.

  Note that the heterodyne reception circuit 2 does not need to be mounted on the circuit board 3 during the rate adjustment.

  Next, an adjustment method when adjusting the timepiece circuit will be described.

  FIG. 6 is a block diagram of the timepiece circuit adjustment in the first embodiment.

  Reference numeral 500 denotes a reference signal adjusting device, which includes a frequency measuring device 501 that measures the frequency of the reference signal 7 output via the CLK_out terminal 36 and a control unit 502 that controls the clock circuit 6 via the SW terminal 34.

  Next, an adjustment method will be described with reference to the flowchart for adjustment in FIG.

  FIG. 7 is a flowchart when the timepiece circuit is adjusted in the first embodiment.

  The adjustment of the reference signal 7 starts from STEP 100. In STEP 101, the control unit 502 sets the adjustment mode of the reference signal 7 to the timepiece circuit 6. In STEP 102, the frequency measuring device 501 measures the frequency of the reference signal 7. Then, the rate adjustment data 9 corresponding to Table 1 is selected from the frequency measurement value of the reference frequency 7 obtained in STEP 103, the rate adjustment data 9 selected in STEP 104 is stored in the timepiece storage circuit 11, and in STEP 105 The adjustment operation is terminated.

  Next, the reception operation of the first embodiment will be described with reference to FIG.

FIG. 8 is a flowchart at the time of reception in the first embodiment.
In the description of the operation, the case where the frequency of the reference signal 7 is 32766.65 Hz, the rate adjustment data 9 is 31, and the setting value 98 that is the adjustment data of the filter circuit 28 is 11 is described.

  Table 3 shows the relationship between the rank data 99 of the filter circuit 28 having the characteristic that the set value 98 of the filter circuit 28 is 11 and the center frequency.

実施例１の受信動作としてはＳＴＥＰ２００より受信動作を開始し、ＳＴＥＰ２０１で時計回路６の時計記憶回路１１より歩度調整データ９を読み出し、表１より歩度データ９に対応した周波数データ１０を算出する。

As the receiving operation of the first embodiment, the receiving operation is started from STEP 200, the rate adjustment data 9 is read from the timepiece storage circuit 11 of the timepiece circuit 6 at STEP 201, and the frequency data 10 corresponding to the rate data 9 is calculated from Table 1.

  In the first embodiment, since the rate adjustment data 9 is 31, the frequency data 10 is 3.

  In STEP 202, the frequency data 10 is sent to the heterodyne reception circuit 2 via the communication circuit 12.

Next, in STEP 203, the set value 98 is read from the adjustment value storage circuit 30, and the calculation of Expression 1 is performed.

Rank data 99 = set value 9−frequency data 10...

As a result of the calculation, the rank data 99 is 8, and the center frequency of the filter circuit 28 is 503 Hz according to Table 3.

  Further, from Table 1, the frequency of the intermediate signal 21 when the rate adjustment data 9 is 31 is 503.1 Hz to 503.3 Hz, and can be adjusted with an accuracy of ± 1 Hz, and the process proceeds to STEP 204 in this setting state. To start receiving longwave standard radio waves.

  In the first embodiment, the relationship between the rate adjustment data 9 and the frequency data 10 is calculated using Table 1. This is a case where the frequency of the received longwave standard radio wave is 77.5 KHz, and the received longwave standard radio wave is obtained. The relationship between the rate adjustment data 9 and the frequency data 10 differs depending on the frequency.

  As an example, Tables 4 and 5 show the relationship between the rate adjustment data 9 and the frequency data 10 when receiving 40 KHz and 60 KHz.

  In the case of a multi-station radio timepiece that receives radio waves of multiple frequencies of 40 KHz, 60 KHz, and 77.5 KHz, a correspondence table corresponding to the frequency of the received radio waves is selected from Tables 1, 4, and 5. In the subsequent processing, the processing as described above is executed.

以上のように、発振回路５が出力する基準信号７の周波数誤差をＩＦ回路２３の中心周波数調整によって補正するため、特許文献１のように発振回路５の周波数調整を行なわず、消費電流の増加を抑え、高精度なフィルタ回路の周波数調整することが出来る。

As described above, since the frequency error of the reference signal 7 output from the oscillation circuit 5 is corrected by adjusting the center frequency of the IF circuit 23, the frequency of the oscillation circuit 5 is not adjusted as in Patent Document 1, and the current consumption increases. The frequency of the filter circuit can be adjusted with high accuracy.

  Further, by adjusting the center frequency of the filter circuit 28 before mounting the circuit board 3, it is not necessary to provide the F_in terminal 43 and the F_out terminal 44 necessary for the adjustment on the circuit board 3, thereby suppressing an increase in the board area.

  Further, the frequency error of the reference signal 7 can be implemented only by adjusting the variation of the heterodyne reception circuit 2 itself by correcting the frequency error of the intermediate signal 21 using the rate adjustment data 9 used for correcting the timing accuracy of the clock circuit 6. become.

[Description of Example 2]
Since the intermediate frequency of the filter circuit 28 used in the IF circuit 23 of the first embodiment is determined by the ratio of the capacitor capacity to be used, if a capacitor whose capacitor capacity ratio does not change with temperature is used, the intermediate frequency of the filter circuit 28 depends on the temperature. Does not have sex.
However, since the oscillation circuit 5 changes the characteristics of the crystal oscillator, resistance, and capacitance depending on the temperature, the frequency of the reference signal 7 changes, causing a frequency shift between the intermediate frequency 21 and the center frequency of the IF circuit 23, and the heterodyne reception circuit. The reception sensitivity of 2 has temperature dependence.

  The second embodiment is an invention in view of the above problems, and will be described with reference to FIGS.

  The overall configuration used for the long wave radio timepiece in Embodiment 2 of the present invention will be described with reference to the block diagram of FIG. Note that blocks having the same functions as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

The clock circuit 603 is a yearly clock circuit with a high rate accuracy of the timepiece, and in order to realize a higher rate accuracy than that of the first embodiment, in addition to the step circuit 8 having a logical frequency adjustment function, a logical frequency adjustment is performed. It has a crystal oscillation circuit 605 having a frequency adjustment function using a capacitor for adjusting accuracy that cannot be adjusted by the function, and a temperature measurement circuit 600 that measures the temperature of the crystal oscillation circuit 605.

  Since the oscillation frequency of the crystal oscillation circuit 605 changes depending on the temperature, the control circuit 15 calculates the rate adjustment amount based on the temperature information from the temperature measurement circuit 600, and adjusts the frequency to the crystal oscillation circuit 605 using a capacitor. The rate accuracy of the watch is increased by outputting the rate data 601 and logical rate data 602 for performing logical frequency adjustment to the step circuit 8.

  The logical rate data 602 is adjusted for a cycle per second with a minimum resolution of every 3.05 μS, which is 1/10 the accuracy of 30.5 μS, which is one cycle of the target frequency of the crystal oscillator.

  Further, the crystal rate data 601 is adjusted by dividing the minimum resolution 3.05 μS of the logical rate data 602 by 16, and the crystal rate is set to 0.190625 μS, which is 1/16 of 3.05 μS, as the minimum resolution. Data 601 is set, and the oscillation frequency of the crystal is directly adjusted.

  As an example, Table 6 shows the relationship between the reference signal 7 and the crystal rate data 601 when the logical rate data 602 is 18.

  The reference signal 7 of each logical rate data 602 has an error of ± 6.24 mHz corresponding to a resolution of 0.190625 μS, and the intervals between the logical rate data 602 are about 0.1 Hz.

As described in Table 6, the frequency of the reference signal 7 changes depending on the switching of the logical rate data 602.
The logical rate data 602 is determined in accordance with the frequency of the reference signal shown in Table 7, and the step circuit 8 performs logical frequency adjustment based on the set logical rate data 602.

このため、温度によって論理歩度データ６０２が１ランク切り替わった場合、基準信号７の周波数が０．１Ｈｚ毎に変化し、中間信号２１の周波数が変化するため、フィルタ回路２８のランクデータ９９が温度に追従して変化しなければ、中間信号２８とフィルタ回路２８の中間周波数との周波数ズレによる感度劣化が発生してしまう。

For this reason, when the logical rate data 602 is switched by one rank depending on the temperature, the frequency of the reference signal 7 changes every 0.1 Hz and the frequency of the intermediate signal 21 changes. Therefore, the rank data 99 of the filter circuit 28 changes to the temperature. If the change does not follow, sensitivity deterioration occurs due to a frequency shift between the intermediate signal 28 and the intermediate frequency of the filter circuit 28.

  Further, as described above, since the crystal oscillation circuit 605 changes the frequency of the reference signal 7 by changing the variable capacitance means based on the crystal rate data 601, the current consumption of the crystal oscillation circuit 605 increases. However, since the frequency range to be changed is as small as 3.05 μS, the current consumption does not increase significantly.

  Next, the receiving operation of the second embodiment will be described with reference to FIG.

  FIG. 10 is a flowchart at the time of reception in the second embodiment.

In describing the operation, the frequency of the reference signal 7 at a temperature of 25 degrees is set to 32766.701 Hz, the logical rate data 602 is set to 31, the set value 98 that is the adjustment data of the filter circuit 28 is set to 11, and the reference signal 7 at the temperature of 40 degrees The case where the frequency is 327699.099 Hz, the logical rate data 602 is 7, and the setting value 98 that is the adjustment data of the filter circuit 28 is 11 will be described as an example.
Table 3 shows the relationship between the rank data 99 and the center frequency of the heterodyne reception circuit 2 having the characteristic that the set value 98 of the filter circuit 28 is 11.

  As the receiving operation of the second embodiment at the temperature of 25 degrees, the receiving operation is started from STEP 300, the temperature data is measured by the temperature measuring circuit 600 of the clock circuit 603 at STEP 301, and the crystal rate data 601 and the logical rate data are read at STEP 302. 602 is calculated, and frequency data 603 corresponding to the logical rate data 602 is calculated from Table 7.

  In the second embodiment, when the logical rate data 602 is 31, the frequency data 603 is 3.

次にＳＴＥＰ３０３にて水晶発振回路６０５と歩進回路８で周波数調整を行ない、ＳＴＥＰ３０４にて周波数データ６０３をヘテロダイン受信回路２へ送り、ＳＴＥＰ３０５にて設定値９８を調整値記憶回路３０より読み出し、式２の計算を行なう。

ランクデータ＝設定値９８−周波数データ６０３・・・・式２

計算の結果としてランクデータ９９は８となり、表３よりフィルタ回路２８の中心周波数は５０３Ｈｚとなる。

Next, at STEP 303, the frequency is adjusted by the crystal oscillation circuit 605 and the stepping circuit 8, and at STEP 304, the frequency data 603 is sent to the heterodyne reception circuit 2, and at STEP 305, the set value 98 is read from the adjustment value storage circuit 30, 2. Calculate 2

Rank data = set value 98−frequency data 603...

As a result of the calculation, the rank data 99 is 8, and from Table 3, the center frequency of the filter circuit 28 is 503 Hz.

  Further, from Table 7, the frequency of the intermediate signal 21 when the logical rate data 602 is 31 is 503.1 Hz and can be adjusted with an accuracy of ± 1 Hz. Start receiving operation.

  Next, the reception operation when the temperature of the watch changes from 25 degrees to 40 degrees will be described.

  In the receiving operation of the second embodiment at a temperature of 40 degrees, when the crystal rate data 601 and the logical rate data 602 are calculated in STEP 302 and the logical rate data 602 is 7, the frequency data 603 is −3, and STEP 305 Then, the set value 98 is read from the adjustment value storage circuit 30 and the calculation of Expression 2 is performed. The rank data 99 is 14, and the center frequency of the filter circuit 28 is 497 Hz from Table 3.

  Further, from Table 7, the frequency of the intermediate signal 21 when the logical rate data 602 is 7 is 497.4 Hz, and it can be adjusted with an accuracy of ± 1 Hz. Start receiving operation.

  As described above, the timepiece circuit 603 according to the second embodiment outputs the crystal rate data 601 for adjusting the frequency by the capacitor to the crystal oscillation circuit 605 and the logical rate data 602 for performing the logical frequency adjustment to the stepping circuit 8 to output the timepiece of the timepiece. By increasing the rate accuracy and sending the logical rate data 602 corresponding to the temperature change to the heterodyne reception circuit 2 and reflecting it in the center frequency adjustment of the filter circuit 28, it is possible to obtain a reception sensitivity characteristic independent of the temperature change.

DESCRIPTION OF SYMBOLS 1 Antenna 2 Heterodyne reception circuit 3 Circuit board 4 Time display part 5 Oscillation circuit 6 Clock circuit 7 Reference signal 8 Step circuit 9 Rate adjustment data 10 Frequency data 11 Clock storage circuit 12 Communication circuit 13 Time data 14 Data reception circuit 15 Control circuit 16 received signal 17 standard radio wave signal 18 amplifying circuit 19 local oscillation signal 20 local oscillation circuit 21 intermediate signal 22 IF signal 23 IF circuit 24 detection circuit 25 communication circuit 27 control circuit 28 filter circuit 29 adjustment circuit 30 adjustment value storage circuit 50 MIX circuit 99 Rank data 100 Long wave radio clock 201 Oscillation circuit 202 Counter 203 Comparison circuit 204 Oscillation adjustment circuit 205 Counter 400 Filter circuit adjustment device 401 Signal generator 402 Amplitude measurement device 403 Control unit 500 Reference signal adjustment device 501 Frequency measurement device 5 02 Control unit

Claims (3)

A local oscillation circuit that inputs a reference signal from outside and creates a local oscillation signal;
A MIX circuit that mixes the local oscillation signal and the received signal to generate an intermediate signal;
A filter circuit for extracting the intermediate signal and generating an IF signal used for detection;
A first adjustment circuit for adjusting a manufacturing variation of an intermediate frequency of the filter circuit;
First storage means for storing adjustment data in the first adjustment circuit;
A second adjustment circuit that adjusts variations of the intermediate signal caused by deviation from a theoretical value of the reference signal;
A first communication circuit for inputting adjustment data in the second adjustment circuit;
The heterodyne reception circuit, wherein the second adjustment circuit adjusts variation of the intermediate signal based on the adjustment data. A heterodyne receiver circuit according to claim 1;
An oscillation circuit capable of outputting an oscillation signal as a reference signal, a frequency adjustment circuit for adjusting the frequency of the oscillation signal, a second storage means for storing adjustment data in the frequency adjustment circuit,
A clock circuit having a second communication circuit for outputting adjustment data of the second storage means;
The heterodyne reception circuit inputs an oscillation signal of the oscillation circuit as the reference signal,
Adjustment data output from the second communication circuit is input from the first communication circuit,
The composite circuit for a radio timepiece, wherein the second adjustment circuit adjusts variation of the intermediate signal based on adjustment data obtained by the first communication circuit. 3. The radio timepiece composite circuit according to claim 2, wherein the heterodyne reception circuit writes the adjustment data to the first storage means by the heterodyne reception circuit alone.

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