JP2016067092A - Driving control device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a driving control device configured so that loss can be suppressed when driving a reverse conducting power device having a transistor structure and a diode structure formed in the same semiconductor substrate.SOLUTION: A current detecting portion 25 obtains a first detection value and a second detection value by detecting detection values responding to flowing currents of a semiconductor element 1B at timing different from each other. A gradient calculating portion 26 calculates a difference between the first detection value and the second detection value obtained by the current detecting portion 25 and calculates the gradient. A threshold generating portion 27 generates a threshold for polarity determination so that the threshold is varied toward a direction of time variation of the detection values, in response to decrease of calculation results by the gradient calculating portion 26. Further, a polarity determining portion 28 compares the generated threshold by the threshold generating portion 27 with the detection values for polarity determination, and a driving portion 29 shuts down/applies gate driving voltages to a semiconductor element 1B according to a result of the polarity determination by the polarity determining portion 28.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a drive control apparatus for a semiconductor element in which an insulated gate transistor structure and a diode structure are formed.

  The insulated gate transistor element and the diode element are formed on the same semiconductor substrate, and the current-carrying electrode (for example, collector and emitter) of the transistor element and the current-carrying electrode (for example, cathode and anode) of the diode element are common electrodes. There are semiconductor elements. This semiconductor element has a characteristic that when a gate driving voltage is applied in a state where a current flows through the diode element, a channel is formed and hole injection is suppressed, so that conduction loss increases. .

  Therefore, during the period when the ON command signal is given, the current flowing through the sense element of the transistor element is compared with the threshold value to determine whether or not the current is flowing through the diode element. It has been proposed to execute drive control in which a gate drive voltage is applied when the voltage is cut off and not flowing (see, for example, Patent Document 1).

JP 2010-118642 A JP 2009-170670 A

  The drive voltage cutoff control is preferably performed when a current is flowing through the diode element. However, when the transistor element and the diode element are formed on the same semiconductor substrate, it is difficult to accurately determine whether the current is flowing in the forward direction of the diode element. This is because there are, for example, a delay error of the feedback circuit when performing feedback control, a feedback detection error, an accuracy error due to variations in semiconductor element structures, and the like.

  In such a case, it is better to set a margin for the threshold value used for polarity determination. However, if a large margin is set for the threshold value, driving is performed even though current flows in the forward direction of the diode structure. The dead zone that cannot cut off the voltage increases. In particular, the current change (di / dt) that flows through the power device changes according to the power supply voltage or load, and conventionally, a dead zone corresponding to the case where the current change becomes the largest according to the fluctuation of the power supply voltage or load is set. The polarity determination threshold value is a constant value.

  An object of the present invention is to provide a drive control device that can reduce loss when driving a reverse conducting power device having a transistor structure and a diode structure formed on the same semiconductor substrate.

  According to a first aspect of the present invention, an insulated gate transistor structure to which a gate drive voltage is applied and a diode structure are formed on the same semiconductor substrate. A drive unit is provided that performs drive control of the reverse conducting power device that is a common electrode, and controls energization of the load.

  The acquisition unit acquires the detection values detected according to the energization current of the reverse conducting power device or the load current as the first detection value and the second detection value while shifting the timing. The gradient calculation unit calculates a difference by calculating a difference between the first detection value and the second detection value acquired by the acquisition unit, and the threshold value generation unit is for polarity determination according to a decrease in the calculation result of the gradient calculation unit. Are generated so as to change the dead band in the direction of narrowing the dead zone.

  Then, the polarity determination unit compares the threshold value generated by the threshold value generation unit with the detected value to determine the polarity, and the drive unit drives the control terminal of the reverse conductive power device according to the polarity determination result of the polarity determination unit. Cut off / apply voltage. For this reason, the threshold value generation unit can generate the threshold value for determining the polarity while changing the detection value gradient in a direction in which the dead zone becomes narrower if the gradient of the detection value decreases. As a result, if the drive unit cuts off / applies the drive voltage to the control terminal of the reverse conducting power device according to the polarity determination result of the polarity determination unit, for example, the time until the normal drive voltage is applied can be delayed. And the time range during which the drive voltage is cut off can be expanded. Therefore, it is not necessary to set a dead zone corresponding to the case where the current change is greatest according to the fluctuation of the power supply voltage or the load as in the conventional case, and the dead zone can be substantially narrowed and the loss can be reduced.

1 is an electrical configuration diagram schematically illustrating a drive control device according to a first embodiment. Equivalent circuit diagram schematically showing the internal structure of a semiconductor device Structural sectional view schematically showing the internal structure of a semiconductor device Illustration of V-I characteristics and conduction loss of diode structure Explanatory diagram showing the relationship between diode current and IGBT current within one cycle Timing chart schematically showing the relationship between drive signal, sense voltage and drive voltage Circuit diagram showing load configuration example Electrical configuration diagram schematically showing a drive control device in a second embodiment Timing chart (1) schematically showing a relationship among a drive signal, a sense voltage, and a drive voltage Timing chart (part 2) schematically showing a relationship among a drive signal, a sense voltage, and a drive voltage Electrical configuration diagram schematically showing a drive control device in a third embodiment Timing chart (1) schematically showing a relationship among a drive signal, a sense voltage, and a drive voltage Timing chart (part 2) schematically showing a relationship among a drive signal, a sense voltage, and a drive voltage Electrical configuration diagram schematically showing the drive control device in the fourth embodiment Electrical configuration diagram schematically showing a drive control apparatus in a fifth embodiment Timing chart schematically showing the relationship between drive signal, sense voltage and drive voltage

In the following description, components having the same or similar functions as those described in the embodiments are given the same reference numerals or similar symbols, and descriptions thereof are omitted as necessary.
(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. The drive control system shown in FIG. 1 drives an inductive load such as a motor, and is used as a power converter. Each of the semiconductor elements 1A and 1B is configured as a reverse conducting power device, and these semiconductor elements 1A and 1B are connected between an output terminal Nt between the high potential side DC power supply line 2 and the low potential side DC power supply line 3. The half-bridge circuit 4 is arranged in series across the circuit.

  The semiconductor elements 1A and 1B have the same structure, and are, for example, reverse conducting IGBTs (RC-IGBTs) in which an insulated gate transistor structure 5 and a diode structure 6 are formed on the same semiconductor substrate. The conducting electrodes (collector, emitter) of the transistor structure 5 and the conducting electrodes (cathode, anode) of the diode structure 6 are common electrodes.

  In addition to this main element, a sense element comprising a transistor structure 5s and a diode structure 6s for passing a minute current proportional to the current flowing through the main element is formed on the semiconductor substrate as shown in FIG. In FIG. 1, the main element and the sense element are simply shown. Sense resistors 7A and 7B are connected between the sense terminals S1 and S2 of the semiconductor elements 1A and 1B, respectively.

  As an example of the semiconductor elements 1A and 1B, FIG. 3 shows an RC-IGBT having a vertical structure. In the RC-IGBT of this embodiment, the transistor structure 5 and the diode structure 6 are provided on the same semiconductor substrate 8. The semiconductor substrate 8 is composed of an n− type silicon substrate.

  A p-type base layer 9 is formed on the top surface portion of the semiconductor substrate 8. A plurality of trenches having a depth that reaches the semiconductor substrate 8 through the base layer 9 are formed in the base layer 9. Polysilicon is buried in the trench, whereby the gate electrode 10 having a trench structure is formed. A gate drive voltage is input to each gate electrode 10 through a common gate wiring 11. The gate electrodes 10 are provided in stripes at equal intervals in one direction along the surface layer portion of the base layer 9. Thereby, the base layer 9 is partitioned into a plurality of first regions 12 and a plurality of second regions 13 that are electrically separated from each other along the one direction. These first regions 12 and second regions 13 are alternately arranged, and the width of the second region 13 is wider than the width of the first region 12.

  In the surface layer portion of the first region 12, an n + -type emitter region 14 is formed adjacent to the gate electrode 10. An emitter electrode 15 is formed on the first region 12. The emitter electrode 15 is connected to the base layer 9 and the emitter region 14 in the first region 12. The first region 12 operates as a channel region of the transistor structure 5 and also operates as an anode region of the diode structure 6. That is, the emitter electrode 15 for the first region 12 becomes the emitter electrode of the transistor structure 5 and the anode electrode of the diode structure 6.

  The second region 13a provided above the collector region 16 (described later) is not connected to any electrode. A second region 13 b provided above the cathode region 17 (described later) is connected to the emitter electrode 15. Accordingly, only the second region 13 b provided above the cathode region 17 in the second region 13 operates as the anode region of the diode structure 6. That is, the emitter electrode 15 becomes an anode electrode of the diode element 6 in the second region 13b.

  In the lower surface layer portion of the semiconductor substrate 8, a p + type collector region 16 is formed corresponding to a range (left side of the broken line) where the second region 13a is formed, and a range where the second region 13b is formed (broken line) N + type cathode region 17 is formed corresponding to the right side of FIG. The collector region 16 and the cathode region 17 are connected to the collector electrode 18. That is, the cathode electrode of the diode structure 6 is in common with the collector electrode 18 of the transistor structure 5. An n-type field stop layer 19 is formed between the semiconductor substrate 8 and the collector region 16 and the cathode region 17.

  In the drive control system shown in FIG. 1, the microcomputer (microcomputer) 21 includes a PWM signal generator 22 that generates the high-side and low-side drive signals FH and FL of the half bridge circuit 4. The drive signals FH and FL both have an active level of “H”, but have a certain dead time between the high side and the low side active level so that both sides become inactive levels (L level: off command level). doing. The drive signals FH and FL are input to the drive ICs 24A and 24B via the photocouplers 23A and 23B, respectively.

  Each of the drive ICs 24A and 24B includes a current detection unit 25, a gradient calculation unit 26, a threshold generation unit 27, a polarity determination unit 28, and a drive unit 29 as an acquisition unit. These drive ICs 24A and 24B have substantially the same configuration, except that the low-side drive IC 24B operates with reference to the potential of the ground 3, whereas the high-side drive IC 24A has a potential at the load connection node Nt. It is a place that operates on the basis of. Therefore, hereinafter, the configuration and connection relationship of the drive IC 24B will be described, and the description of the configuration and connection relationship of the drive IC 24A will be omitted.

  The current detection unit 25 in the drive IC 24B operates as an acquisition unit that acquires the current value flowing through the sense resistor 7B as the first detection value I1 and the second detection value I2 at different timings T1 and T2. The gradient calculation unit 26 calculates the gradient by calculating the difference between the first detection value I1 and the second detection value I2 by the current detection unit 25. The threshold value generation unit 27 generates the polarity determination threshold value so as to change in the time change direction of the first detection value I1 and the second detection value I2 in accordance with a decrease in the calculation result of the gradient calculation unit 26. . The polarity determination unit 28 compares the threshold value generated by the threshold value generation unit 27 with the detected value, and determines whether the current flows through the diode structure 6. The drive unit 29 cuts off or applies the drive voltage to the gate G of the semiconductor element 1B according to the polarity determination result of the polarity determination unit 28. The drive control device 30B is configured by connecting a drive IC 24B and a sense resistor 7B. The drive IC 24A has the same configuration as the drive IC 24B and will not be described here. However, the drive control device 30A is configured by connecting the drive IC 24A and the sense resistor 7A.

  Next, the operation of the drive control device 24B on the low side will be mainly described. Although the operation of the low-side drive control device 30B will be described, the operation of the high-side drive control device 30A is substantially the same. In the semiconductor elements 1A and 1B, when normal gate drive voltages VGH and VGL are applied in a state where a current flows through the diode structure 6, a channel is formed in the first region 12 and hole injection is suppressed. Therefore, as shown in FIG. 4A, the forward voltage Vf of the diode structure 6 in which the forward current flows is increased by ΔVf, and the conduction loss (Vf × If) of the diode structure 6 is increased. Therefore, it is referred to as so-called Vf control in which the normal gate drive voltages VGH and VGL are cut off when it is estimated whether or not a current flows through the diode structure 6 and when it is estimated that a current flows through the diode structure 6. It is good to perform control.

  FIG. 5 schematically shows an energization current during one cycle period of sinusoidal energization of the semiconductor element 1B, for example. The positive direction current shown in FIG. 5 indicates the amount of current flowing through the diode structure 6 from the emitter electrode 15 toward the collector electrode 18.

  In the period shown in FIG. 5, during the “diode current” period of the first half cycle, a current flows from the diode structure 6 in the direction of the load through the output terminal Nt, and the latter half cycle in FIG. During the “IGBT current” period, a current flows through the transistor structure 5 when the drive signal FL becomes the active level “H”. The current flowing through these semiconductor elements 1B changes in a sinusoidal pulse shape so as to prevent the change in the energization current of the load throughout this period.

  The above-described Vf control may be performed by determining with high accuracy whether or not current is flowing through the diode structure 6 during the period when the drive signal FL is at the active level “H”. Ideally, if the current flowing through the diode structure 6 exceeds 0 A, a voltage obtained by cutting off the normal drive voltage VGL applied to the semiconductor element 1B is output to the gate G of the semiconductor element 1B. A normal drive voltage may be output to the gate G of the semiconductor element 1B.

  If it demonstrates with reference to the electric current of the semiconductor element 1B in FIG. 5, when the absolute value of the electric current which flows into the diode structure 6 is a stage larger than predetermined current among the electric current changes of one period which changes in a sine wave pulse shape, It is easy to perform Vf control for cutting off the drive voltage VGL. Even when the absolute value of the current of the transistor structure 5 is larger than the predetermined current, it is easy to control the output of the normal drive voltage VGL.

  During these periods, the current change in the semiconductor element 1B is a period in which the amplitude changes greatly among the one-cycle changes that change in a sine wave pulse shape. Therefore, the current is mainly supplied to the diode structure 6 in the semiconductor element 1B. This is because it is easy to determine whether or not the current flows. In normal Vf control, the application / cutoff of the normal gate drive voltage VGL is set by comparing the value of the current flowing through the sense resistor 7B with the threshold value for polarity determination.

  Conventionally, a margin in consideration of the control delay time must be provided from factors such as current detection and feedback delay time for feedback control based on the detection result. The threshold for determining the polarity is often set to a static constant value depending on the maximum value assuming the maximum value of the degree of change in the current flowing through the sense resistor 7B. At this time, among the changes in one cycle in FIG. 5, for example, when the power supply voltage is controlled to be low, the load inductance is large, etc. Since it can be assured that a current flows through the element 6, so-called Vf control is desired. However, as described above, when the threshold value for polarity determination is set to a static constant value depending on the maximum value of the change in current, so-called Vf control is not performed and the normal gate drive voltage is used as it is. In some cases, VGL is output to the gate G of the semiconductor element 1B. As a result, the conduction loss increases.

  If the normal gate drive voltage VGL is output to the gate G of the semiconductor element 1B, the conduction loss characteristic when the normal gate drive voltage VGL is applied is shown in FIG. 4B as the Vce-Ic characteristic. It deteriorates (see the solid line characteristic P0 of the control dead zone R0 shown in FIG. 4B). In the control dead zone region R0, a channel is formed in the first region 12, so that hole injection is suppressed and conduction loss is deteriorated.

  Therefore, in the present embodiment, in consideration of the above, particularly during a period in which the input drive signal FL is “H”, the gradient calculation unit 26 changes the current flowing through the diode structure 6 of the semiconductor element 1B. The gradient is calculated, the threshold generation unit 27 generates a threshold for polarity determination according to the calculated gradient, the polarity determination unit 28 determines the polarity using this threshold, and the drive unit 29 The conduction loss is reduced by driving the semiconductor element 1B according to the polarity determination result. When the drive unit 29 drives the semiconductor element 1B according to the polarity determination result in this way, for example, when the power supply voltage becomes low according to the load or when the inductance of the load is large, the diode structure 6 In this operating region, the control dead zone R can be narrowed and the conduction loss can be improved (the solid line characteristic P of the control dead zone R shown in FIG. 4B). reference).

  The detailed operation will be described below with reference to FIG. The periods T0 to T8 described in FIG. 6 show the control processing during a certain period in which the effect in FIG. 5 occurs and the change in the signal waveform of each node in an enlarged manner. The phase current shown in FIG. 6 indicates, for example, a load current flowing through an automobile motor or the like. During the period shown in FIG. 6, the phase current continues to decrease when the drive signal FL is at the active level “H”. When the drive signal FH becomes the active level “H” after the dead time period T1, the drive unit 29 applies the ON drive voltage to the semiconductor element 1A, and current is supplied from the power supply to the load through the high-side semiconductor element 1A. As a result, the phase current rises. When the high-side semiconductor element 1A is turned off, the phase current continues to decrease. In FIG. 6, a period T5 indicates a phase current in a so-called zero vector section in which there is no inverter output. In this case, the load is, for example, a three-phase motor 200 (see, for example, FIG. 7). For example, a period during which all the low-side semiconductor elements 1B are on-controlled and all the high-side semiconductor elements 1A are off-controlled, or vice versa (all the low-side is all off and all the high-side is all ON).

  As shown in FIG. 6, when it is determined that the sense voltage VSL is equal to or higher than the threshold voltage VtA during the period when a large current flows through the diode structure 6 of the semiconductor element 1B on the low side, for example, the drive signal FL is Even if the active level is “H”, the normal gate drive voltage VGL is cut off, and 0 V which is an off drive voltage is output (T0 in FIG. 6).

  During this time, the current detection unit 25 acquires the first detection value I1 based on the sense voltage VSL at the first timing, and acquires the second detection value I2 based on the sense voltage VSL at a second timing that is later than the first timing. Then, the gradient calculation unit 26 calculates a subtraction value between the first detection value I1 and the second detection value I2. Thereby, the gradient di / dt shown in FIG. 6 can be calculated, and this gradient di / dt has a value that depends on the degree of decrease in the sense voltage VSL and, in turn, the degree of decrease in the current flowing through the diode structure 6. Therefore, as shown in FIG. 6, as the degree of decrease decreases with the passage of time from period T0 → periods T3 to T4 → periods T6 to T8, the gradient di / dt also decreases. For example, if the values in the periods T0 and T1 in FIG. 6 are dIA, the values in the periods T3 and T4 are dIB, and the values in the periods T6 and T7 are dIC, there is a relationship of dIA> dIB> dIC.

  The threshold generation unit 27 generates a threshold value for polarity determination based on the calculated gradient di / dt of the gradient calculation unit 26 and outputs the threshold value to the polarity determination unit 28. The change in the sense voltage VSL in FIG. 6 includes a threshold for determining the polarity corresponding to the values dIA (periods T0 and T1), dIB (periods T3 and T4), and dIC (periods T6 to T8) of the gradient di / dt. Values VtA, VtB, and VtC are also indicated by broken lines.

  The polarity determination unit 28 compares the threshold values VtA, VtB, and VtC with the sense voltage VSL and cuts off the normal drive voltage VGL until the sense voltage VSL reaches and falls below these threshold values. When the sense voltage VSL falls below these threshold values VtC while FL is at the active level “H”, the normal drive voltage VGL is output (period T7 in FIG. 6).

  As described above, conventionally, since a feedback delay time for feedback control or the like is required, a margin in consideration of a certain control delay time must be provided. For this reason, the conventional threshold value for determining the polarity is assumed to be the maximum value of the degree of change of the current flowing through the sense resistor 7B, and is a static constant value depending on this maximum value (the sense voltage VSL shown in FIG. 6). Threshold value Vt). As a result, for example, in the operation mode in which the current change gradient is low, there is a possibility that the normal gate drive voltage VGL may be output although the current flows through the diode structure 6 (timing t4a in FIG. 6). (Refer to the broken line in the period Ta of T6).

  However, when the configuration of the present embodiment is adopted, the threshold voltages VtA, VtB, and VtC of the sense voltage VSL are gradually lowered, and accordingly, the threshold voltage for polarity determination is also gradually lowered, and the gate drive voltage VGL Can be delayed. As a result, the gate drive voltage VGL can be kept off during the period Ta and the conduction loss can be reduced as compared with the conventional case. It should be noted that the power supply voltage is reduced during low torque operation, but in such a case, small changes in the current gradient di / dt are likely to continue and the threshold for polarity determination can be set low. In such a case, the effect is most improved.

  According to the present embodiment, when the power supply voltage is low and / or when the load inductance is large, the gradient di / dt of the detection values I1 and I2 is reduced, so that the threshold generation unit 27 uses the threshold for polarity determination. The values VtA, VtB, and VtC can be generated by sequentially decreasing. Thereby, it is possible to delay the time until the detection value by the sense voltage VSL reaches the threshold values VtA, VtB, and VtC for polarity determination. For this reason, if the drive unit 29 cuts off / applies the drive voltage to the control terminal of the semiconductor element 1B according to the polarity determination result of the polarity determination unit 28, the time until the normal drive voltage is applied can be delayed. The time range during which the drive voltage VGL is cut off can be expanded. Since an appropriate threshold can be set by sequentially detecting the gradient di / dt, conduction loss can be reduced.

(Second Embodiment)
8 to 10 show a second embodiment. FIG. 8 shows a configuration example of the drive control device 130 on the low side. Since the configuration of the high-side drive control device is the same as that of the low-side drive control device 130, the configuration of the high-side drive control device is not shown. The configuration described in the second embodiment shows a specific example of the functional components described in the first embodiment, and the functionally corresponding components are denoted by the same reference numerals and described. Do.

  In FIG. 8 showing the configuration of the present embodiment, the drive IC 124 includes a control circuit 31, and the control circuit 31 includes a function as the threshold value generation unit 27 described in the above-described embodiment. The current detection unit 25 includes a plurality of sample hold units 40 and 41. These sample and hold units 40 and 41 sample and hold the sense voltage VSL of the sense resistor 7B according to the timing control signal output from the control circuit 31. At this time, the sample and hold units 40 and 41 sample and hold at a plurality of different timings because the timing signals output from the control circuit 31 are different from each other.

  Subtracting circuit 42 is connected to the subsequent stage of these sample and hold units 40 and 41. The subtraction circuit 42 is configured as the gradient calculation unit 26 described in the above embodiment, calculates a difference between output results of the plurality of sample hold units 40 and 41, and outputs the difference to the control circuit 31. The control circuit 31 is configured by a control logic circuit using a delay circuit, for example, and calculates a polarity determination threshold value according to the output result of the subtraction circuit 42. Then, the control circuit 31 outputs this polarity determination threshold value command signal to the polarity determination unit 28. The polarity determination unit 28 includes a variable voltage generation unit 43, a comparator 44, and a latch circuit 45. The variable voltage generation unit 43 changes the output voltage of the variable voltage generation unit 43 according to the polarity determination threshold value command signal input from the control circuit 31.

  The output voltage of the variable voltage generator 43 is input to the inverting input terminal of the comparator 44. The comparator 44 compares the output voltage of the variable voltage generator 43 with the sense voltage VSL and outputs the comparison result to the latch circuit 45. The latch circuit 45 holds the binary output of the comparator 44. The binary holding value of the latch circuit 45 is input to the driving unit 29, and the driving unit 29 drives according to the binary holding value of the latch circuit 45.

  The drive unit 29 outputs the normal gate drive voltage VGL according to the drive signal FL input from the microcomputer 21, but outputs the normal gate drive voltage VGL as it is according to the binary holding value of the latch circuit 45. Or shut off. For example, so-called Vf control is not performed when the output of the latch circuit 45 is “H”, and so-called Vf control is performed when the output of the latch circuit 45 is “L”.

  9 and 10 schematically show timing charts. FIG. 9 shows characteristics when the current gradient is large / small, and FIG. 10 shows a period Tb in which there is a conduction loss reduction effect by cutting off the drive voltage VGL as compared with the conventional example.

  As shown in FIGS. 9 and 10, the plurality of sample and hold units 40 and 41 have a sampling period for sampling the sense voltage VSL to be sampled (Sample period in FIGS. 9 and 10). And an output period (Out period in FIGS. 9 and 10) for holding and outputting the sampling voltage. Therefore, the detection value is output while the operation state is the output period (Out period).

  The control circuit 31 sets a predetermined timing while the plurality of sample hold units 40 and 41 are in the output period (Out period) as the threshold change timing (see timings ta1, tb1, tc1, and td1 in FIG. 9). Then, the comparator 44 sets the timing immediately after the threshold change timings ta1, tb1, tc1, and td1 as the polarity determination timing (timing ta2, tb2, tc2, and td2 in FIG. 9). Then, at the polarity determination timings ta2, tb2, tc2, and td2, the drive unit 29 can refer to the binary hold value of the latch circuit 45 and determine the cutoff / application of the drive voltage VSL as the polarity determination result.

  As shown in the left column of FIG. 9, when the current gradient (absolute value) is large, the gradient di / dt is detected as a gradient value di1 having a relatively high absolute value. At the timing, a threshold value Vt1 for polarity determination corresponding to the gradient value di1 is set as the output voltage of the variable voltage generator 43 (see ta1 and tb1 in FIG. 9). Then, the comparator 44 compares the output voltage of the variable voltage generator 43 with the sense voltage VSL, and stores the comparison result in the latch circuit 45 as a polarity determination result. Then, the drive unit 29 refers to the binary hold value of the latch circuit 45 and determines the cutoff / application of the drive voltage VSL as the polarity determination result.

  On the other hand, as shown in the right column of FIG. 9, when the current gradient (absolute value) is relatively small, the gradient di / dt is detected by the gradient value di2 (<di1) that has a relatively low absolute value. The control circuit 31 sets the polarity determination threshold Vt2 corresponding to the gradient value di2 as the output voltage of the variable voltage generator 43 at the threshold change timing (see tc1 and td1 in FIG. 9). Then, the comparator 44 compares the output voltage of the variable voltage generator 43 with the sense voltage VSL, and stores the comparison result in the latch circuit 45 as a polarity determination result. Then, the drive unit 29 refers to the binary hold value of the latch circuit 45 at the immediately subsequent polarity determination timing, and determines whether the drive voltage VSL is interrupted / applied as the polarity determination result.

  When the comparator 44 stores “L” as the polarity determination result in the latch circuit 45, the drive unit 29 cuts off the normal drive voltage VSL and outputs 0 V according to the output “L” of the latch circuit 45. . Conversely, when the comparator 44 stores “H” as the polarity determination result in the latch circuit 45, the drive unit 29 applies the normal drive voltage VSL as it is according to the output “H” of the latch circuit 45. Output to.

  FIG. 10 shows the change of the sense voltage VSL together with the threshold value for polarity determination. As shown in FIG. 10, even when the sense voltage VSL changes gently, the control circuit 31 changes the output voltage of the variable voltage generation unit 43 to the threshold values VtA, VtB, VtC (gradient) at the threshold change timing. di / dt equivalent). In such a case, the values dIA, dIB, dIC, and dID of the gradient di / dt dynamically change with the passage of time. In the period Tb shown as an example in FIG. 10, the value of the gradient di / dt gradually decreases with the passage of time, the time for cutting off the normal drive voltage VGL can be delayed, and the conduction loss can be reduced (FIG. 6). (Refer to the period Ta shown corresponding to).

  According to the present embodiment, the detection values sampled by the sample hold units 40 and 41 during different periods are held, whereby the polarity determination thresholds VtA, VtB, and VtC corresponding to the gradient di / dt are set. It is set. Also in this embodiment, there exists an effect similar to the above-mentioned embodiment.

(Third embodiment)
11 to 13 show a third embodiment. FIG. 11 shows a configuration example of the low-side drive control device 230 and the drive IC 224. Since the configuration of the high-side drive control device is the same as that of the low-side drive control device 230, the configuration of the high-side drive control device is not shown.

  In the second embodiment, the sense voltage VSL is input to the sample hold unit 41, whereas in the configuration of FIG. 11 illustrating the present embodiment, the input of the sample hold unit 41 is the output of the sample hold unit 40. Is different. Since the other configuration is the same as that of the second embodiment, the corresponding components are denoted by the same reference numerals and description thereof is omitted.

  12 and 13 show timing charts. The sample hold units 40 and 41 have different sampling processing periods (see Sample periods Ty0, Ty, Tz, etc.) for sampling the sense voltage VSL. As shown in FIG. 12, the sample hold unit 41 samples the output Out output from the sample hold unit 40 at a timing during the period Ty, holds this value, and continues to output (see after the period Tz). The sample hold unit 40 samples the value of another sense voltage VSL at a timing during the period Tz, and then holds and outputs this value (see the period Tz2 and thereafter).

  As shown in the left column of FIG. 12, when the current gradient (absolute value) is large, the gradient di / dt is detected by the gradient value di3 having a relatively high absolute value. The threshold value Vt3 for polarity determination according to the gradient value di3 at the timing is set as the output voltage of the variable voltage generator 43 (see ta1, tb1, and tc1 in FIG. 12). Then, the comparator 44 compares the output voltage of the variable voltage generation unit 43 with the sense voltage VSL, stores the comparison result in the latch circuit 45 as a polarity determination result, and the drive unit 29 immediately follows the polarity determination timing. Then, with reference to the binary holding value of the latch circuit 45, the interruption / application of the drive voltage VSL is determined as the polarity determination result.

  On the other hand, as shown in the right column of FIG. 12, when the current gradient (absolute value) is relatively small, the gradient di / dt is detected by a gradient value di4 (<di3) that has a relatively low absolute value. The control circuit 31 sets the polarity determination threshold value Vt4 corresponding to the gradient value di4 as the output voltage of the variable voltage generation unit 43 at the threshold change timing (see td1, te1, and tf1 in FIG. 12). Then, the comparator 44 compares the output voltage of the variable voltage generator 43 with the sense voltage VSL, and stores the comparison result in the latch circuit 45 as a polarity determination result. Then, the drive unit 29 refers to the binary hold value of the latch circuit 45 at the immediately subsequent polarity determination timing, and determines whether the drive voltage VSL is interrupted / applied as the polarity determination result.

  When the comparator 44 stores “L” in the latch circuit 45 as the polarity determination result, the drive unit 29 cuts off the normal drive voltage VSL according to the output “L” of the latch circuit 45 and outputs 0 V. . Conversely, when the comparator 44 stores “H” as the polarity determination result in the latch circuit 45, the drive unit 29 applies the normal drive voltage VSL as it is according to the output “H” of the latch circuit 45. Output to.

  The sample hold units 40 and 41 include the same period as an output period (Out period) for outputting the sense voltage VSL sampled at different timings. Therefore, if the control circuit 31 sets the predetermined timing during the period in which the output period is the same period as the threshold change timing, it can calculate the difference between the detected values by slightly shifting the sampling timing, which is almost the same as in the previous embodiment. A polarity determination result can be obtained.

  FIG. 13 shows the change of the sense voltage VSL together with the threshold value for polarity determination. As shown in FIG. 13, even when the sense voltage VSL changes gently, the control circuit 31 changes the output voltage of the variable voltage generator 43 to the threshold values VtA, VtB, VtC (gradient) at the threshold change timing. di / dt equivalent). In such a case, the values dIA, dIB, dIC, and dID of the gradient di / dt dynamically change with the passage of time. In the period Tb shown in FIG. 13 as an example, the value of the gradient di / dt gradually decreases with the passage of time, the time for cutting off the normal drive voltage VGL can be delayed, and the conduction loss can be reduced (FIG. 13). (See period Ta shown corresponding to 6).

  According to the present embodiment, the sample hold unit 41 samples again the detection value sampled in advance by the sample hold unit 40 at the timing during the period Ty0 (period Ty), and holds the detection value. , Sampling at the timing in the period Tz after the period Ty0 and holding this detection value, thereby setting the threshold values VtA, VtB, VtC, VtD for polarity determination according to the gradient di / dt. ing. Also in this embodiment, there exists an effect similar to the above-mentioned embodiment.

(Fourth embodiment)
FIG. 14 is an explanatory diagram of the fourth embodiment. FIG. 14 shows an example of the configuration of a drive control apparatus that replaces FIG. The fourth embodiment shows a mode in which the current of the load is detected using a current detection means (for example, a hall sensor) other than the above, and is controlled according to the detected value.

  As shown in the configuration example of FIG. 14, a hall sensor 432 is provided at the energization node Nt of the load. The Hall sensor 432 is provided in place of the configuration for detecting current using the sense resistors 7A and 7B shown in the first to third embodiments. Therefore, the transistor structure 5 in the semiconductor elements 101A and 101B that replace the semiconductor elements 1A and 1B of this embodiment is not provided with the sense transistor structure 5s.

  In this embodiment, a control circuit 421 as a drive control device is provided. The control circuit 421 includes a drive signal generation unit 29z that receives the PWM signal generated by the PWM signal generation unit 22 and generates and outputs the drive signals FH and FL. The drive signal generation unit 29z outputs the drive signals FH and FL to the drive units 29A and 29B through the photocouplers 23A and 23B. The drive units 29A and 29B include, for example, a gate drive buffer 33, and the drive signals FH and FL The corresponding gate drive voltages VGH and VGL are output to the semiconductor elements 101A and 101B, respectively, to drive the semiconductor elements 101A and 101B. Thus, even when the current of the load is detected by the Hall sensor 432, substantially the same effect as in the above-described embodiment can be obtained.

(Fifth embodiment)
15 and 16 are explanatory diagrams of the fifth embodiment. FIG. 15 shows a configuration example of the drive control device 430 and the drive IC 424 on the low side. Since the configuration of the high-side drive control device is the same as that of the low-side drive control device 430, the configuration of the high-side drive control device is not shown.

  In the fifth embodiment, a mode including a maximum value holding unit 34 is shown. As shown in the previous embodiment, in FIG. 6, the period T5 indicates a so-called zero vector section in which all of the high-side or low-side semiconductor elements 1A or 1B are turned on and there is no output of the inverter. Phase current change does not occur in principle. In this zero vector section, the phase current does not change even though the active level “H” of the drive signal FL is input to the drive IC 424. Therefore, even if the gradient calculation unit 26 of the above-described embodiment calculates the gradient. The gradient di / dt is almost 0, and as a result, the threshold value for polarity determination also changes greatly. Therefore, in the present embodiment, the maximum value holding unit 34 is provided after the gradient calculating unit 26 of the drive IC 424.

  The maximum value holding unit 34 is a peak hold circuit that holds the maximum value of the gradient calculated by the gradient calculating unit 26 during one control period after receiving the ON command signal at which the drive signal FL becomes the active level “H”. Composed. In this case, as shown in FIG. 16, even when the period T5 that becomes the zero vector with the passage of time is entered, the calculation gradient di / dt of the gradient calculation unit 26 in the immediately preceding period T4 can be held, and during the period T4 It is possible to hold the threshold value for polarity determination set to. As a result, an appropriate threshold value for polarity determination can be set even during the period T5 during the so-called zero vector. In the subsequent period T6, even if the calculated gradient di / dt of the gradient calculating unit 26 is calculated again, if the calculated gradient calculated di / dt has not increased again, the maximum value holding unit 34 is configured to be the gradient calculating unit 26. The calculated gradient di / dt is held.

  In addition, when an off command signal that causes the drive signal FL to become the inactive level “L” is given, the maximum value holding unit 34 resets the held maximum value. Thereby, the maximum value of the threshold value for polarity determination that has been held can be canceled, and appropriate control can be realized. FIG. 16 shows the value of the calculated gradient di / dt of the gradient calculating unit 26 for reference.

(Other embodiments)
In the above-described embodiment, the current detection unit 25 is configured by forming sense elements in the semiconductor elements 1A and 1B and connecting the sense resistors 7A and 7B. Alternatively, a shunt resistor may be provided in series with the semiconductor elements 1A and 1B. The current detector 25 only needs to detect at least the current flowing through the diode element 6.

  The RC-IGBT is not limited to a trench gate type but may be a planar gate type. The semiconductor elements 1A and 1B may be MOS transistors and MOS parasitic diodes. The MOS transistor is not limited to a trench gate type, but may be a planar gate type, an SJ type, or the like. It can be applied when driving a reverse conducting power device.

  In the drawings, 1A, 1B, 101A and 101B are semiconductor elements (reverse conductive power devices), 25 is a current detection unit (acquisition unit), 26 is a gradient calculation unit, 27 is a threshold generation unit, 28 is a polarity determination unit, 29 Denotes a drive unit, 29z denotes a drive signal generation unit, and 31 denotes a control circuit.

Claims (5)

The transistor structure and the diode structure are formed on the same semiconductor substrate, and the conductive electrode of the transistor structure and the current-carrying electrode of the diode structure are used as a common electrode to drive and control a reverse conductive power device having a control terminal. A drive unit (29, 29A, 29B) for controlling energization to
An acquisition unit (25) that acquires the first detection value and the second detection value at different timings for the detection value detected according to the energization current of the reverse conductive power device or the current of the load;
A gradient calculation unit (26) for calculating a gradient by calculating a difference between the first detection value and the second detection value acquired by the acquisition unit;
A threshold value generation unit (27) for generating a threshold value for polarity determination so as to change in a direction of narrowing the dead zone in accordance with a decrease in the calculation result of the gradient calculation unit;
A polarity determination unit (28) for determining the polarity by comparing the detection threshold value generated by the threshold value generation unit with the detection value;
The drive control device, wherein the drive unit cuts off / applies a gate drive voltage to a control terminal of the reverse conductive power device according to a polarity determination result of the polarity determination unit. The acquisition unit
A first sample hold unit (40) that samples the detection value at a first timing, and outputs the first sample hold unit at a second timing after the first timing to obtain the second detection value. A second sample-and-hold unit (41)
2. The drive control apparatus according to claim 1, wherein the first sample hold unit samples the detection value at a third timing after the first timing to obtain the first detection value. The acquisition unit
A first sample hold unit (40) that samples the detection value at a first timing to obtain the first detection value, and the second detection by sampling the detection value at a second timing different from the first timing. The drive control device according to claim 1, further comprising: a second sample hold unit (41) that is a value.   The maximum value holding part (34) which hold | maintains the maximum value of the gradient calculated by the said gradient calculation part during one control period after receiving an ON command signal, The any one of Claims 1-3 characterized by the above-mentioned. The drive control device according to item.   The drive control device according to claim 4, wherein the maximum value holding unit resets the held maximum value when an off command signal is received.

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