JP2016066337A - Information processor, storage device, and information processing system - Google Patents

Abstract

PURPOSE: To provide an information processor capable of determining which of an information processor and a storage device has broken down.CONSTITUTION: In an information processor on and to which a memory module is attachably and detachably mounted and connected, an ECC coding part adds an error correction code to data to generate coded data, and a first error detection part performs error detection and correction processing to the data, and a first abnormality detection part supplies a first abnormality detection signal indicting the presence/absence of an error included in the data to a failure portion determination part. The memory module includes: a second error detection part and a second abnormality detection part, and the second error detection part performs error detection and correction processing to the data separately from the information processor, and the second abnormality detection part supplies a second abnormality detection signal to the failure portion determination part on the basis of the result of the error detection and correction processing. The failure portion determination part determines which of the information processor main body and the memory module has broken down on the basis of the first abnormality detection signal and the second abnormality detection signal.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an information processing device, a storage device, and an information processing system.

  In recent years, with the increase in memory capacity required for information processing, data can be written and read by attaching and connecting a removable memory module such as a DIMM (Dual Inline Memory Module) to the main body such as a motherboard. It has been broken. At that time, in order to improve the reliability of the memory module, error detection and correction processing (ECC: Error Check and Correct) is performed on the data to be written and read to detect a failure of the memory module. (For example, Patent Document 1).

  Such error detection and correction processing is performed by adding error correction code (ECC code) to data to be written and read to generate ECC encoded data and decoding it. The memory module corresponding to the error detection / correction processing has a storage area for ECC encoded data in addition to a storage area for normal data, and the information processing apparatus performs ECC encoding from the storage area of the memory module. Data is read and error detection and correction processing is performed.

JP 2012-198727 A

  However, even when using a memory module that supports error detection and correction processing, the error detection and correction processing is actually performed by the information processing apparatus body, not the memory module. It cannot be determined whether the error occurred in the information processing apparatus main body or in the memory module. Therefore, although it is possible to detect that a failure may have occurred in the information processing device or the memory module, it is not possible to specify whether the failure part is the information processing device main body or the memory module. A separate survey is required to identify the site. Further, since both the information processing apparatus main body and the memory module are in a suspicious failure state until the failure part is specified, there is a problem that neither of them can be used.

  The present invention has been made in view of the above problems, and is an information processing apparatus capable of determining which one of the information processing apparatus and the storage device has failed based on the result of error detection processing on data. The purpose is to provide.

  An information processing apparatus according to the present invention is an information processing apparatus that writes and reads data to and from a storage device that is detachably mounted and connected to the storage device, and writes the data to the storage device and the storage device A control unit that controls reading of data from the storage unit, an encoding unit that generates encoded data by adding an error correction code to the write data to be written to the storage device, and the write data or An error detection unit for performing error detection processing on read data from the storage device; and receiving an error detection processing result in the storage device; and receiving the error detection processing result in the storage device and the error detection unit Failure part determination for determining which of the information processing device or the storage device is failed based on the result of error detection processing Characterized in that it comprises a and.

  In addition, a storage device according to the present invention is a storage device that is detachably attached to an information processing device, stores data supplied from the information processing device, and stores data supplied from the information processing device A storage area; an encoded data storage area that stores encoded data obtained by adding an error correction code to the data; and an error detection unit that performs an error detection process on the data using the encoded data. It is characterized by that.

  An information processing system according to the present invention is an information processing system including an information processing device and a storage device that is detachably attached to the information processing device, and the information processing device includes the storage device. A control unit that controls writing of data to and reading of data from the storage device, an encoding unit that generates encoded data by adding an error correction code to the write data to be written to the storage device, and the encoding A first error detection unit that performs an error detection process on the write data or read data from the storage device using data, and the write based on a result of the error detection process in the first error detection unit A first abnormality detection unit that generates a first abnormality detection signal indicating the presence or absence of an error included in the data or the read data; A failure location determination unit that determines which of the storage devices is faulty, wherein the storage device stores a data storage area for storing the write data supplied from the information processing device, and an error in the write data An encoded data storage area for storing encoded data to which a correction code is added; a second error detection unit that performs error detection processing on the write data or the read data using the encoded data; A second abnormality detection unit that generates a second abnormality detection signal indicating the presence or absence of an error included in the write data or the read data based on the result of the error detection process in the two error detection unit and supplies the second abnormality detection signal to the information processing apparatus And the failure site determination unit based on the first abnormality detection signal and the second abnormality detection signal based on the information processing device or the storage device And judging whether one is faulty.

  According to the present invention, it is possible to determine which of the information processing device and the storage device is out of order based on the result of error detection processing on data.

It is a block diagram which shows the structure of the information processing apparatus and memory module of Example 1 of this invention. It is a figure which shows supply of the data which an information processing apparatus and a memory module perform at the time of data writing. It is a figure which shows the determination table in the failure site | part determination of Example 1. FIG. It is a figure which shows supply of the data which an information processing apparatus and a memory module perform at the time of data reading. 6 is a block diagram illustrating configurations of an information processing apparatus, a memory module, and a socket according to Embodiment 2. FIG. It is a figure which shows the determination table in the failure site | part determination of Example 2. FIG. It is a figure which shows an example of the determination table at the time of combining the failure location determination at the time of data writing and data reading in Example 2. FIG. FIG. 10 is a block diagram illustrating configurations of an information processing apparatus, a memory module, and a socket according to a third embodiment. FIG. 10 is a diagram illustrating data supply performed by the information processing apparatus and the memory module when data is written in the third embodiment. It is a figure which shows the determination table of the failure location determination at the time of the data writing in Example 3. FIG. FIG. 10 is a diagram illustrating data supply performed by the information processing apparatus and the memory module when data is read in the third embodiment. It is a figure which shows the determination table of the failure location determination at the time of the data reading in Example 3. FIG.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram illustrating a configuration of an information processing system including the information processing apparatus 10 and the memory module 20.

  The information processing apparatus 10 includes a control unit 11, an ECC unit 12, and an error collection / memory determination unit 17. A memory module 20 is detachably attached to the information processing apparatus 10 and connected thereto. The information processing apparatus 10 writes and reads data to and from the memory module 20.

  The control unit 11 is a microprocessor including a CPU (Central Processing Unit) and the like, and controls each unit of the information processing apparatus 10. The control unit 11 exchanges data with the memory module 20 via the bus line BL, and controls writing and reading of data to and from the memory module 20.

  The ECC unit 12 includes an ECC encoding unit 13, a first error detection unit 14, a first abnormality detection unit 15, and a failure site determination unit 16.

  The ECC encoding unit 13 performs error correction encoding processing on the data when writing the data to the memory module 20 to generate encoded data CD. The error correction coding process is performed using, for example, a Hamming code.

  The first error detection unit 14 decodes the encoded data CD and performs error detection and correction processing (ECC: Error Check and Correct) on the data. The first error detection unit 14 supplies an error detection signal ES1 indicating the result of error detection to the first abnormality detection unit 15.

  The first abnormality detection unit 15 is a binary (0, 1) indicating whether or not there is an error (hereinafter referred to as data abnormality) included in the data based on the result of the error detection and correction process in the first error detection unit 14. The first abnormality detection signal AS1 is generated and supplied to the failure site determination unit 16.

  The failure part determination unit 16 receives the first abnormality detection signal AS1 from the first abnormality detection unit 15 and receives the second abnormality detection signal AS2 from the second abnormality detection unit 24 of the memory module 20. The failure site determination unit 16 uses a combination of the first abnormality detection signal AS1 and the second abnormality detection signal AS2 to cause a failure of the main body of the information processing apparatus 10 (hereinafter referred to as main body failure) and a failure of the memory module 20 (hereinafter referred to as memory). (Referred to as failure).

  The failure part determination unit 16 supplies a failure part determination signal FS indicating the determination result to the error collection / memory determination unit 17.

  The error collection / memory determination unit 17 accumulates the failure part determination signal FS supplied from the failure part determination unit 16 and stores it as error information EI. The error collection / memory determination unit 17 supplies error information EI to the control unit 11 in response to a request from the control unit 11.

  Further, the error collection / memory determination unit 17 performs a memory determination process for determining whether or not the memory module connected to the information processing apparatus 10 is the memory module 20 according to the present invention.

  The error collection / memory determination unit 17 transmits the memory determination signal JS to the terminal NC1 of the memory module 20, and the memory according to whether or not the return signal RS having the same signal value as the memory determination signal JS is received from the terminal NC2. Judgment processing is performed. The error collection / memory determination unit 17 supplies information indicating the determination result to the control unit 11 as memory information MI.

  The memory module 20 is a storage device composed of a DIMM (Dual Inline Memory Module) or the like, is detachably mounted on the motherboard of the information processing apparatus 10, and is connected to the information processing apparatus 10. The memory module 20 includes a data storage area 21, an encoded data storage area 22, a second error detection unit 23, a second abnormality detection unit 24, and bidirectional buffers 26 and 27.

  The data storage area 21 stores data supplied from the control unit 11. The encoded data storage area 22 stores the encoded data CD generated by the ECC encoding unit 13.

  The second error detection unit 23 decodes the encoded data CD and performs error detection and correction processing on the data. The second error detection unit 23 supplies a second error detection signal ES2 indicating a result of error detection to the second abnormality detection unit 24.

  Based on the second error detection signal ES2 supplied from the second error detection unit 23, the second abnormality detection unit 24 is a binary (0, 1) value indicating an error included in the data, that is, the presence or absence of the data abnormality. (2) The abnormality detection signal AS2 is generated and supplied to the failure site determination unit 16.

  The memory determination signal reply unit 25 is connected to terminals NC1 and NC2 that are not used in a normal DIMM. When the memory judgment signal reply unit 25 receives the memory judgment signal JS from the error collection / memory judgment unit 17 via the terminal NC1, the memory judgment signal reply unit 25 sends the reply signal RS having the same signal value as the received memory judgment signal JS to the terminal NC2. To the error collection / memory determination unit 17.

  The bidirectional buffer 26 supplies data supplied from the information processing apparatus 10 to the data storage area 21 when data is written. Further, the bidirectional buffer 26 supplies the data read from the data storage area 21 to the information processing apparatus 10 when reading data.

  The bidirectional buffer 27 supplies the encoded data CD supplied from the information processing apparatus 10 at the time of data writing to the encoded data storage area 22. The bidirectional buffer 27 supplies the encoded data CD read from the encoded data storage area 22 to the information processing apparatus 10 when reading data.

  Next, operations of the information processing apparatus 10 and the memory module 20 at the time of data writing will be described with reference to FIG. 2 and FIG.

[When writing data]
The control unit 11 supplies the write data ND to the data storage area 21 of the memory module 20. The data storage area 21 stores write data ND. The control unit 11 also supplies the write data ND to the ECC encoding unit 13, the first error detection unit 14, and the second error detection unit 23 of the memory module 20.

  The ECC encoding unit 13 generates encoded data CD based on the write data ND supplied from the control unit 11. The ECC encoder 13 supplies the encoded data CD to the first error detector 14, the encoded data storage area 22 of the memory module 20, and the second error detector 23.

  The first error detection unit 14 decodes the encoded data CD, and performs error detection and correction processing on the write data ND using the decoded data. The first error detection unit 14 supplies a first error detection signal ES1 indicating the error detection result to the first abnormality detection unit 15.

  Based on the first error detection signal ES1, the first anomaly detector 15 detects an error occurring in the write data ND, that is, a binary (0, 1) first anomaly that indicates the presence or absence of data anomaly in the write data ND A signal AS <b> 1 is generated and supplied to the failure site determination unit 16.

  The second error detection unit 23 of the memory module 20 decodes the encoded data CD supplied from the ECC encoding unit 13. The memory module 20 performs error detection and correction processing on the write data ND using the decoded encoded data CD.

  The second error detection unit 23 supplies a second error detection signal ES2 indicating a result of error detection to the second abnormality detection unit 24.

  Based on the second error detection signal ES2, the second abnormality detection unit 24 generates a second (0, 1) second abnormality detection signal AS2 indicating the presence / absence of data abnormality in the write data ND, and a failure part determination unit 16 is supplied.

  Based on the first abnormality detection signal AS1 supplied from the first abnormality detection unit 15 and the second abnormality detection signal AS2 supplied from the second abnormality detection unit 24, the failure site determination unit 16 Determine which is occurring.

  FIG. 3A is a diagram illustrating a determination table for failure site determination performed by the failure site determination unit 16 when data is written.

  The failure part determination unit 16 determines whether or not a main body failure has occurred based on whether the signal value of AS1 is 0 or 1. For example, when AS1 is 0, the failure part determination unit 16 determines that a main body failure has not occurred. When AS1 is 1, the failure part determination unit 16 determines that a main body failure has occurred.

  Further, the failure site determination unit 16 determines whether or not a memory failure has occurred based on whether or not the signal values of AS1 and AS2 are the same. For example, when AS1 and AS2 have the same signal value, the failure site determination unit 16 determines that no memory failure has occurred. When AS1 and AS2 are different signal values, the failure site determination unit 16 determines that a memory failure has occurred.

  Specifically, for example, when AS1 and AS2 are both 0, no data abnormality is detected in either the information processing apparatus 10 or the memory module 20, and therefore the failure part determination unit 16 has neither a main body failure nor a memory failure. Is determined.

  When AS1 is 0 and AS2 is 1, the first abnormality detection unit 15 detects no data abnormality and the second abnormality detection unit 24 detects the data abnormality. It is determined that no memory failure has occurred and no memory failure has occurred.

  When AS1 is 1 and AS2 is 0, since the data abnormality is detected by the first abnormality detection unit 15, the failure part determination unit 16 determines that a main body failure has occurred. On the other hand, since no data abnormality is detected in the second abnormality detection unit 24 where a data abnormality should be detected, the failure part determination unit 16 determines that a memory failure has also occurred.

  When AS1 is 1 and AS2 is 1, since the data abnormality is detected by the first abnormality detection unit 15 and the data abnormality is also detected as it is by the second abnormality detection unit 24, the failure site determination unit 16 It is determined that a main unit failure has occurred and no memory failure has occurred.

  The failure part determination unit 16 supplies a failure part determination signal FS indicating the determination result to the error collection / memory determination unit 17.

  Next, operations of the information processing apparatus 10 and the memory module 20 when reading data will be described with reference to FIGS. 4 and 3B.

[When reading data]
The control unit 11 reads the read data RD from the data storage area 21 of the memory module 20 and supplies the read data RD to the first error detection unit 14 and the second error detection unit 23. Further, the control unit 11 reads out the encoded data CD corresponding to the read data RD from the encoded data storage area 22 and supplies it to the first error detector 14 and the second error detector 23.

  The second error detection unit 23 decodes the encoded data CD and performs error detection and correction processing on the read data RD using the decoded encoded data CD. The second error detection unit 23 supplies a second error detection signal ES2 indicating a result of error detection to the second abnormality detection unit 24.

  Based on the second error detection signal ES2 supplied from the second error detection unit 23, the second abnormality detection unit 24 has a binary value indicating the error included in the read data RD, that is, the presence or absence of data abnormality in the read data RD ( 0, 1) of the second abnormality detection signal AS2 is generated and supplied to the failure site determination unit 16.

  The first error detection unit 14 decodes the encoded data CD read from the encoded data storage area 22, and performs error detection / correction processing on the read data RD using the decoded encoded data CD. .

  The first error detection unit 14 supplies a first error detection signal ES1 indicating the error detection result to the first abnormality detection unit 15.

  Based on the first error detection signal ES1 supplied from the first error detection unit 14, the first abnormality detection unit 15 is a binary (0, 1) first abnormality detection indicating the presence or absence of data abnormality in the read data RD. A signal AS <b> 1 is generated and supplied to the failure site determination unit 16.

  Based on the first abnormality detection signal AS1 supplied from the first abnormality detection unit 15 and the second abnormality detection signal AS2 supplied from the second abnormality detection unit 24, the failure site determination unit 16 Determine which is occurring.

  FIG. 3B is a diagram illustrating a determination table for the determination performed by the failure site determination unit 16 when reading data.

  The failure site determination unit 16 determines whether or not a memory failure has occurred based on whether the signal value of AS2 is 0 or 1. For example, when AS2 is 0, the failure site determination unit 16 determines that no memory failure has occurred. When AS2 is 1, the failure site determination unit 16 determines that a memory failure has occurred.

  Moreover, the failure part determination part 16 determines whether the main body failure has arisen based on whether the signal value of AS1 and AS2 is the same. For example, when AS2 and AS1 have the same signal value, it is determined that no main body failure has occurred. When AS1 and AS2 are different signal values, the failure part determination unit 16 determines that a main body failure has occurred.

  Specifically, for example, when AS1 and AS2 are both 0, no data abnormality is detected in either the memory module 20 or the information processing apparatus 10, and therefore the failure site determination unit 16 has neither a memory failure nor a main body failure. Is determined.

  When AS1 is 0 and AS2 is 1, a data abnormality is not detected by the first abnormality detection unit 15 even though a data abnormality is detected by the second abnormality detection unit 24. 16 determines that both a main body failure and a memory failure have occurred.

  When AS1 is 1 and AS2 is 0, no data abnormality is detected by the second abnormality detection unit 24, and data abnormality is detected by the first abnormality detection unit 15, so that the failure site determination unit 16 stores the memory It is determined that no failure has occurred and a main unit failure has occurred.

  When AS1 is 1 and AS2 is 1, since the data abnormality is detected by the second abnormality detection unit 24 and the abnormality is also detected as it is by the first abnormality detection unit 15, the failure site determination unit 16 stores the memory It is determined that a failure has occurred and no main unit failure has occurred.

  Next, the memory determination operation performed by the error collection / memory determination unit 17 will be described.

[Memory judgment]
The error collection / memory determination unit 17 transmits a memory determination signal JS to the memory module immediately after the information processing apparatus 10 is powered on or immediately after the memory module is connected.

  The error collection / memory determination unit 17 first transmits a memory determination signal JS having a signal value of “0” to the terminal NC 1 of the memory module 20.

  When the error collection / memory determination unit 17 does not receive the return signal RS having the signal value “0” from the terminal NC2, the error collection / memory determination unit 17 determines that the connected memory module is not the memory module 20 according to the present invention. When the reply signal RS having the signal value “0” is received from the terminal NC2, the error collection / memory determination unit 17 further transmits the memory determination signal JS having the signal value “1”.

  When the error collection / memory determination unit 17 does not receive the return signal RS with the signal value “1” from the terminal NC2, the error collection / memory determination unit 17 determines that the connected memory module is not the memory module 20 according to the present invention. When the reply signal RS having the signal value “1” is received from the terminal NC2, the error collection / memory determination unit 17 determines that the connected memory module is the memory module 20 according to the present invention.

  The error collection / memory determination unit 17 supplies memory information MI indicating whether or not the connected memory module is the memory module 20 according to the present invention to the control unit 11.

  When the connected memory module is the memory module 20 according to the present invention, the control unit 11 controls the failure part determination unit 16 to execute a failure part determination process. When the connected memory module is a normal memory module, the control unit 11 controls the failure site determination unit 16 so as not to perform the failure site determination process.

  As described above, the information processing apparatus 10 according to the present invention includes the failure determination unit 16. The failure determination unit 16 receives the first abnormality detection signal AS1 indicating the result of the error detection and correction process in the information processing apparatus 10 and the second abnormality detection signal AS2 indicating the result of the error detection and correction process in the memory module 20. And based on these, the failure part is determined.

  Therefore, based on the result of the error detection and correction process in the information processing apparatus and the result of the error detection and correction process in the memory module, it can be determined whether a main body failure or a memory failure has occurred.

  In addition, the memory module 20 includes a second error detection unit 23 and performs error detection and correction processing separately from the error detection and correction processing performed in the information processing apparatus 10. Therefore, in the information processing apparatus 10, it is possible to determine a failure site based on the result of the error detection and correction process in the information processing apparatus 10 and the result of the error detection and correction process in the memory module 20.

  In addition, the information processing apparatus 10 according to the present invention determines whether or not the connected memory module is the memory module 20 according to the present invention, and determines that the normal memory module is connected. The determination process is not performed. Therefore, when a normal memory module is connected, it can operate as a normal information processing apparatus.

  The error collection / memory determination unit 17 transmits and receives the memory determination signal JS having a signal value of “0” and the reply signal RS, and further sends the memory determination signal JS having a signal value of “1” and the reply signal RS. The memory judgment is performed by transmitting and receiving. Therefore, it is possible to prevent erroneous determination when, for example, a signal having the same signal value is received by accident.

  FIG. 5 is a block diagram illustrating a configuration of the information processing system according to the second embodiment. The information processing apparatus 10 according to the present exemplary embodiment includes a socket 30 that mediates connection between the information processing apparatus 10 and the memory module 20. The configuration other than the socket 30 is the same as that of the first embodiment shown in FIG.

  The socket 30 has, for example, a shape of an insertion port provided on the motherboard of the information processing apparatus 10, and is fitted with the memory module 20 to mediate connection between the information processing apparatus 10 and the memory module 20.

  When the information processing apparatus 10 and the memory module 20 are connected, a connection failure may occur between the information processing apparatus 10 and the memory module 20 due to a fitting abnormality between the memory module 20 and the socket 30. . The connection failure causes an error in data.

  The failure part determination unit 16 in this embodiment determines whether a connection failure has occurred between the information processing apparatus 10 and the memory module 20 in addition to whether a main body failure or a memory failure has occurred. Hereinafter, the determination operation of the failure site determination unit 16 at the time of data writing and data reading will be described.

[When writing data]
The failure site determination unit 16 has a main body failure based on the first abnormality detection signal AS1 supplied from the first abnormality detection unit 15 and the second abnormality detection signal AS2 supplied from the second abnormality detection unit 24. Whether a connection failure or a memory failure has occurred.

  FIG. 6A is a diagram illustrating a determination table for failure site determination performed by the failure site determination unit 16 when data is written.

  The failure part determination unit 16 determines whether or not a main body failure has occurred based on whether the signal value of AS1 is 0 or 1. For example, when AS1 is 0, the failure part determination unit 16 determines that a main body failure has not occurred. When AS1 is 1, the failure part determination unit 16 determines that a main body failure has occurred.

  Further, the failure site determination unit 16 determines whether a connection failure or a memory failure has occurred based on whether the signal values of AS1 and AS2 are the same. For example, when AS1 and AS2 have the same signal value, the failure site determination unit 16 determines that neither a connection failure nor a memory failure has occurred. When AS1 and AS2 are different signal values, the failure site determination unit 16 determines that a connection failure or a memory failure has occurred.

  Specifically, for example, when AS1 and AS2 are both 0, no data abnormality is detected in any of the information processing apparatus 10 and the memory module 20, so the failure site determination unit 16 determines that the main body failure, connection failure, memory It is determined that no failure has occurred.

  When AS1 is 0 and AS2 is 1, the first abnormality detection unit 15 detects no data abnormality and the second abnormality detection unit 24 detects the data abnormality. It is determined that no failure has occurred and a connection failure or memory failure has occurred.

  When AS1 is 1 and AS2 is 0, since the data abnormality is detected by the first abnormality detection unit 15, the failure part determination unit 16 determines that a main body failure has occurred. On the other hand, since the data abnormality is not detected in the second abnormality detection unit 24 where a data abnormality should be originally detected, the failure part determination unit 16 determines that a connection failure or a memory failure has occurred.

  When AS1 is 1 and AS2 is 1, since the data abnormality is detected by the first abnormality detection unit 15 and the data abnormality is also detected as it is by the second abnormality detection unit 24, the failure site determination unit 16 It is determined that a main unit failure has occurred and no connection failure or memory failure has occurred.

[When reading data]
Based on the first abnormality detection signal AS1 supplied from the first abnormality detection unit 15 and the second abnormality detection signal AS2 supplied from the second abnormality detection unit 24, the failure part determination unit 16 determines whether a main body failure or a connection failure has occurred. It is determined whether or not a memory failure has occurred.

  FIG. 6B is a diagram illustrating a determination table for failure site determination performed by the failure site determination unit 16 when reading data.

  The failure site determination unit 16 determines whether or not a memory failure has occurred based on whether the signal value of AS2 is 0 or 1. For example, when AS2 is 0, the failure site determination unit 16 determines that no memory failure has occurred. When AS2 is 1, the failure site determination unit 16 determines that a memory failure has occurred.

  Moreover, the failure part determination part 16 determines whether the main body failure or the connection failure has arisen based on whether the signal value of AS1 and AS2 is the same. For example, when AS2 and AS1 have the same signal value, it is determined that no main body failure or poor connection has occurred. When AS1 and AS2 are different signal values, the failure part determination unit 16 determines that a main body failure or a connection failure has occurred.

  Specifically, for example, when AS1 and AS2 are both 0, no data abnormality is detected in either the memory module 20 or the information processing apparatus 10, and therefore, the failure site determination unit 16 determines any of memory failure, connection failure, and main body failure. It is determined that neither has occurred.

  When AS1 is 0 and AS2 is 1, a data abnormality is not detected by the first abnormality detection unit 15 even though a data abnormality is detected by the second abnormality detection unit 24. No. 16 determines that a memory failure has occurred and a connection failure or main unit failure has also occurred.

  When AS1 is 1 and AS2 is 0, no data abnormality is detected by the second abnormality detection unit 24, and data abnormality is detected by the first abnormality detection unit 15, so that the failure site determination unit 16 stores the memory It is determined that no failure has occurred and a connection failure or a main unit failure has occurred.

  When AS1 is 1 and AS2 is 1, since the data abnormality is detected by the second abnormality detection unit 24 and the abnormality is also detected as it is by the first abnormality detection unit 15, the failure site determination unit 16 stores the memory It is determined that a failure has occurred and no connection failure or main unit failure has occurred.

  As described above, according to the information processing system of this embodiment, it is possible to determine whether a main unit failure, a connection failure, or a memory failure has occurred when data is written. Further, when reading data, it can be determined whether a memory failure has occurred, a connection failure, or a main body failure has occurred.

  In addition, it is possible to further specify the failure part by combining the failure part determination at the time of data writing and the failure part determination at the time of data reading. For example, when AS1 is 0 and AS2 is 1 at the time of data writing, it can be determined that a connection failure or a memory failure has occurred, as shown in FIG. It cannot be determined whether it has occurred.

  However, as shown in FIG. 7, by performing failure determination at the time of data reading, if AS1 is 1 and AS2 is 0 at the time of data reading, a connection failure occurs, and AS1 is 1 and AS2 is 1. It is possible to determine that a memory failure has occurred and identify the failure site.

  FIG. 8 is a block diagram illustrating a configuration of an information processing system including the information processing apparatus 10, the socket 30, and the memory module 20 according to the third embodiment.

  The ECC unit 12 includes an ECC encoding unit 13, a first error detection unit 14, a first abnormality detection unit 15, a failure site determination unit 16, a first parity generation unit 18, and a parity verification unit 19.

  The first parity generation unit 18 is supplied with data (write data ND or read data RD) and encoded data CD, and among these data, the number of data having a signal value “1” included for each predetermined number of bits. In response to this, the first parity data PD1 is generated.

  For example, when the write data ND or the read data RD is composed of 64 bits, the first parity generation unit 18 divides the data into 8 data strings composed of 8 bits, and the number of “1” included in each data string is an odd number. When the number of signal values “1” and “1” is an even number, the signal value “0” is set as a parity bit. The first parity generation unit 18 generates 8-bit first parity data PD1 including the parity bits set in each data string.

  The parity check unit 19 receives supply of the first parity data PD from the first parity generation unit 18 and also receives supply of the second parity data PD2 from the second parity generation unit 28 of the memory module 20. The parity check unit 19 checks whether or not the first parity data PD1 and the second parity data PD2 match for each corresponding bit from the upper bit to the lower bit. The parity check unit 19 generates a parity signal PS with a signal value “0” when the values match for all bits and a mismatch of 1 bit or more, and a failure value determination unit with a signal value “1”. 16 is supplied.

  The failure part determination unit 16 determines the failure of the main body of the information processing apparatus 10, the failure of the memory module 20, the socket 30 and the memory module by the combination of the first abnormality detection signal AS1 and the second abnormality detection signal AS2 and the parity signal PS. 20 is determined whether or not there is a connection failure.

  The memory module 20 includes a data storage area 21, an encoded data storage area 22, a second error detection unit 23, a second abnormality detection unit 24, bidirectional buffers 26 and 27, and a second parity generation unit 28.

  The second parity generation unit 28 is supplied with data (write data ND or read data RD) and encoded data CD, and among these data, the number of data having a signal value “1” included for each predetermined number of bits. In response to this, the second parity data PD2 is generated. At this time, like the first parity generation unit 18, the second parity generation unit 28 divides 64-bit data into, for example, 8 data strings of 8 bits, and the number of “1” included in each data string is When the number is odd, the signal value “1” is set, and when the number of “1” is an even number, the signal value “0” is set as the parity bit to generate the second parity data PD2 of 8 bits.

  Next, operations of the information processing apparatus 10 and the memory module 20 according to the third embodiment at the time of data writing will be described with reference to FIGS. 9 and 10.

[When writing data]
As shown in FIG. 9, the control unit 11 sends the write data ND to the data storage area 21 of the memory module 20, the ECC encoding unit 13, the first error detection unit 14, and the second error detection unit 23 of the memory module 20. At the same time, it is supplied to the first parity generation unit 18 and the second parity generation unit 28.

  The ECC encoding unit 13 generates encoded data CD based on the write data ND, and supplies the encoded data CD to the first error detection unit 14, the encoded data storage area 22 of the memory module 20, and the second error detection unit 23. This is supplied to the first parity generation unit 18 and the second parity generation unit 28.

  The first parity generation unit 18 generates first parity data PD1 based on the write data ND and the encoded data CD, and supplies the first parity data PD1 to the parity verification unit 19. The second parity generation unit 28 generates the second parity data PD2 based on the write data ND and the encoded data CD, and supplies the second parity data PD2 to the parity verification unit 19.

  The parity check unit 19 checks the first parity data PD1 and the second parity data PD2, and supplies the parity signal PS indicating the check result as a binary signal of “0” and “1” to the failure site determination unit 16. .

  The failure part determination unit 16 includes a first abnormality detection signal AS1 supplied from the first abnormality detection unit 15, a second abnormality detection signal AS2 supplied from the second abnormality detection unit 24, and a parity supplied from the parity verification unit 19. Based on the signal PS, it is determined whether there is a main body failure, a memory failure, and a connection failure.

  FIG. 10 is a diagram illustrating a determination table for failure site determination performed by the failure site determination unit 16 when data is written.

  The failure part determination unit 16 determines whether or not a main body failure has occurred based on whether the signal value of AS1 is 0 or 1. For example, when AS1 is 0, the failure part determination unit 16 determines that a main body failure has not occurred. When AS1 is 1, the failure part determination unit 16 determines that a main body failure has occurred.

  The failure site determination unit 16 determines whether a connection failure has occurred based on whether the signal value of the parity signal PS is 0 or 1. For example, when PS is 0, the failure site determination unit 16 determines that no connection failure has occurred. When PS is 1, the failure site determination unit 16 determines that a connection failure has occurred.

  The failure site determination unit 16 determines whether or not a memory failure has occurred based on whether the signal value of PS is 0 or 1 and the signal values of AS1 and AS2. For example, when the PS signal value is 0 and AS1 and AS2 are the same signal value, the failure portion determination unit 16 determines that no memory failure has occurred. On the other hand, when the PS signal value is 0 and AS1 and AS2 are different signal values, the failure part determination unit 16 determines that a memory failure has occurred.

  On the other hand, if the PS signal value is 1, if AS2 is 0 even though a connection failure has occurred, the failure site determination unit 16 determines that a memory failure has occurred. On the other hand, when the signal value of PS is 1 and AS2 is 1, the failure site determination unit 16 determines that no memory failure has occurred.

  According to the above rule, as shown in FIG. 10, the failure site determination unit 16 determines the presence or absence of a main body failure, a memory failure, and a connection failure. In the figure, “◯” indicates that there is no failure or defect in the part, and “X” indicates that there is a failure or defect in the part. As described above, in the configuration including the socket 30 between the information processing apparatus 10 and the memory module 20, it is possible to determine whether or not there is a failure and to specify a failure part when writing data.

  Next, operations of the information processing apparatus 10 and the memory module 20 according to the third embodiment when reading data will be described with reference to FIGS.

[When reading data]
As illustrated in FIG. 11, the control unit 11 supplies the read data RD to the first error detection unit 14 and the second error detection unit 23, and also supplies the read data RD to the first parity generation unit 18 and the second parity generation unit 28. To do. In addition, the control unit 11 reads the encoded data CD corresponding to the read data RD from the encoded data storage area 22, and the first error detection unit 14, the second error detection unit 23, the first parity generation unit 18, and the second This is supplied to the parity generation unit 28.

  The first parity generation unit 18 generates first parity data PD1 based on the read data RD and the encoded data CD, and supplies the first parity data PD1 to the parity verification unit 19. The second parity generation unit 28 generates the second parity data PD2 based on the read data RD and the encoded data CD, and supplies the second parity data PD2 to the parity verification unit 19.

  The parity check unit 19 checks the first parity data PD1 and the second parity data PD2, and supplies the parity signal PS indicating the check result as a binary signal of “0” and “1” to the failure site determination unit 16. .

  The failure part determination unit 16 includes a first abnormality detection signal AS1 supplied from the first abnormality detection unit 15, a second abnormality detection signal AS2 supplied from the second abnormality detection unit 24, and a parity supplied from the parity verification unit 19. Based on the signal PS, it is determined whether there is a main body failure, a memory failure, and a connection failure.

  FIG. 12 is a diagram illustrating a determination table for failure site determination performed by the failure site determination unit 16 when data is read.

  The failure site determination unit 16 determines whether or not a memory failure has occurred based on whether the signal value of AS2 is 0 or 1. For example, when AS2 is 0, the failure site determination unit 16 determines that no memory failure has occurred. When AS2 is 1, the failure site determination unit 16 determines that a memory failure has occurred.

  The failure site determination unit 16 determines whether a connection failure has occurred based on whether the signal value of the parity signal PS is 0 or 1. For example, when PS is 0, the failure site determination unit 16 determines that no connection failure has occurred. When PS is 1, the failure site determination unit 16 determines that a connection failure has occurred.

  The failure site determination unit 16 determines whether or not a main body failure has occurred based on whether the signal value of PS is 0 or 1 and the signal values of AS1 and AS2. For example, when the signal value of PS is 0 and AS1 and AS2 are the same signal value, the failure part determination unit 16 determines that a main body failure has not occurred. On the other hand, when the signal value of PS is 0 and AS1 and AS2 are different signal values, the failure part determination unit 16 determines that a main body failure has occurred.

  On the other hand, when the signal value of PS is 1, if AS1 is 0 even though connection failure has occurred, the failure site determination unit 16 determines that a main body failure has occurred. On the other hand, when the signal value of PS is 1 and AS1 is 1, the failure site determination unit 16 determines that no main body failure has occurred.

  According to the above rule, as shown in FIG. 12, the failure site determination unit 16 determines the presence or absence of a main body failure, a memory failure, and a connection failure. In the figure, “◯” indicates that there is no failure or defect in the part, and “X” indicates that there is a failure or defect in the part. As described above, in the configuration including the socket 30 between the information processing apparatus 10 and the memory module 20, it is possible to determine whether or not there is a failure and to identify a failure part when reading data.

  As described above, according to the information processing system of the present embodiment, at the time of data writing and at the time of data reading, the failure of the information processing apparatus 10, the failure of the memory module 20, and the connection between the socket 30 and the memory module 20, respectively. It is possible to detect the presence or absence of a connection failure between them and determine which one of them is occurring.

  Since the failure of the information processing apparatus 10 or the memory module 20 and the connection failure of the socket 30 and the memory module 20 can be distinguished, for example, when it is determined that only the connection failure occurs, there is no need for repair. Can be determined.

  The embodiment of the present invention is not limited to the above. For example, in the above-described embodiment, the first error detection unit 14 of the ECC unit 12 has been described as performing the error detection and correction process, but only the error detection process may be performed. Further, the error detection processing method is not limited to the Hamming method, and a parity method, a CRC method (Cyclic Redundancy Check), or the like may be used.

  The type of the memory module is not limited to DIMM, and a storage device such as a RIMM (Rambus Inline Memory Module) or SO-DIMM (Small Outline Dual Inline Memory Module) may be used.

  In the above embodiment, the memory module 20 is described as being mounted and connected to the motherboard of the information processing apparatus 10, but the connection method is not limited to mounting on the motherboard. Further, the configuration of the socket 30 is not limited to a shape like an insertion port, and any configuration that can mediate the connection between the information processing apparatus 10 and the memory module 20 may be used. According to the present invention, in an apparatus having a connection unit that mediates connection between an information processing device and a memory module, it is possible to determine whether the cause of an error included in data is before or after the connection unit.

  In the above embodiment, the failure part determination unit 16 is based on the first abnormality detection signal AS1 from the first abnormality detection unit 15 and the second abnormality detection signal AS2 from the second abnormality detection unit 24. The configuration for performing the determination has been described.

  However, the first abnormality detection unit 15 and the second abnormality detection unit 24 are not provided, and the failure site determination unit 16 performs the first error detection signal ES1 from the first error detection unit 14 and the second error detection unit 23 from the second error detection unit 23. The configuration may be such that the failure part is determined based on the error detection signal ES2. In short, any configuration may be used as long as the failure part determination unit 16 determines the failure part based on the result of the error detection and correction process in the information processing apparatus 10 and the result of the error detection and correction process in the memory module 20.

  In the above embodiment, in the memory determination, after the transmission / reception of the signal having the signal value of “0”, the determination is performed by transmitting / receiving the signal having the signal value of “1” to prevent erroneous determination. However, the number of times of signal transmission / reception is not limited to this, and determination may be performed by one transmission / reception, or transmission / reception may be performed three or more times.

  In the third embodiment, the first parity generation unit 18 and the second parity generation unit 28 have the signal values “1” and “1” when the number of “1” included in each data string is an odd number. In the above description, the example in which the first parity data PD1 and the second parity data PD2 are generated by the so-called “even parity” method in which the signal value “0” is set as a parity bit when the number of data is an even number is described. However, the present invention is not limited to this. When the number of “1” included in each data string is an even number, the signal value “1” is set. When the number of “1” is an odd number, the signal value “0” is set as a parity bit. A so-called “odd parity” method may be used. Whichever method is used, the parity data generated by the first parity generation unit 18 and the second parity generation unit 28 may be the same.

  In the above-described embodiment, an example in which the memory module 20 is connected to the information processing apparatus 10 has been described. However, the device to be connected is not limited to the memory module 20, and another detachable device may be connected to the information processing device 10. In short, according to the present invention, it is possible to determine a fault site or a connection failure by detecting a data error that occurs before and after a connection portion between the information processing apparatus 10 and another apparatus.

DESCRIPTION OF SYMBOLS 10 Information processing apparatus 11 Control part 12 ECC part 13 ECC encoding part 14 1st error detection part 15 1st abnormality detection part 16 Failure location determination part 17 Error collection / memory determination part 18 1st parity generation part 19 Parity collation part 20 Memory module 21 Data storage area 22 Encoded data storage area 23 Second error detection unit 24 Second abnormality detection unit 25 Memory determination signal return unit 26, 27 Bidirectional buffer 28 Second parity generation unit 30 Socket NC1, NC2 terminal

Claims (12)

An information processing apparatus that writes and reads data to and from a storage device that is detachably mounted and connected,
A control unit that controls writing of data to the storage device and reading of data from the storage device;
An encoding unit that generates encoded data by adding an error correction code to write data to be written to the storage device;
Using the encoded data, an error detection unit that performs error detection processing on the write data or read data from the storage device;
Either the information processing device or the storage device is received based on the received error detection processing result in the storage device and the error detection processing result in the error detection unit. An information processing apparatus comprising: a failure part determination unit that determines whether or not the device is out of order. A socket connected to the storage device;
The failure part determination unit is configured to determine whether the information processing device has failed, the storage device has failed, or the socket based on the received error detection processing result in the storage device and the error detection processing result in the error detection unit. 2. The information processing apparatus according to claim 1, wherein a determination is made as to whether a connection abnormality between the storage device and the storage device has occurred. Based on the result of the error detection process in the error detection unit, an abnormality detection unit that generates a first abnormality detection signal indicating the presence or absence of an error included in the write data or the read data,
The failure part determination unit receives a second abnormality detection signal indicating the presence or absence of an error included in the write data or the read data in the storage device, and generates a first abnormality detection signal and a second abnormality detection signal. The information processing apparatus according to claim 1, wherein the determination is performed based on the information processing apparatus. A socket connected to the storage device;
Parity data generated based on the write data or the read data and the encoded data in the information processing device, and based on the write data or the read data and the encoded data in the storage device A parity collation unit that collates the generated parity data and determines whether or not they match,
With
The failure part determination unit is configured to detect a failure of the information processing device based on the received error detection processing result in the storage device, the error detection processing result in the error detection unit, and the verification result of the parity verification unit. The information processing apparatus according to claim 1, wherein a determination is made as to which of the failure of the storage device and the connection abnormality between the socket and the storage device has occurred. Based on the result of the error detection process in the error detection unit, an abnormality detection unit that generates a first abnormality detection signal indicating the presence or absence of an error included in the write data or the read data;
A parity generator that generates first parity data based on the write data or the read data and the encoded data;
With
The parity check unit receives second parity data generated based on the write data or the read data and the encoded data in the storage device, and checks the first parity data and the second parity data. And generating a parity signal indicating whether the first parity data and the second parity data match,
The failure part determination unit receives a second abnormality detection signal indicating whether there is an error included in the write data or the read data in the storage device, and receives the first abnormality detection signal, the second abnormality detection signal, and the The information processing apparatus according to claim 4, wherein the determination is performed based on a parity signal. A storage device that is detachably attached to the information processing device and stores data supplied from the information processing device,
A data storage area for storing data supplied from the information processing apparatus;
An encoded data storage area for storing encoded data obtained by adding an error correction code to the data;
A storage device comprising: an error detection unit that performs error detection processing on the data using the encoded data.   The apparatus according to claim 1, further comprising: an abnormality detection unit that generates an abnormality detection signal indicating the presence / absence of an error included in the data based on a result of an error detection process in the error detection unit and supplies the abnormality detection signal to the information processing apparatus. 6. The storage device according to 6.   The storage device according to claim 6, further comprising a parity generation unit that generates parity data based on the data and the encoded data and supplies the parity data to the information processing device. An information processing system including an information processing device and a storage device that is detachably attached to and connected to the information processing device,
The information processing apparatus includes:
A control unit that controls writing of data to the storage device and reading of data from the storage device;
An encoding unit that generates encoded data by adding an error correction code to write data to be written to the storage device;
A first error detection unit that performs an error detection process on the write data or read data from the storage device using the encoded data;
A first abnormality detection unit that generates a first abnormality detection signal indicating the presence or absence of an error included in the write data or the read data based on a result of the error detection process in the first error detection unit;
A failure site determination unit that determines which of the information processing device or the storage device is faulty,
The storage device
A data storage area for storing the write data supplied from the information processing apparatus;
An encoded data storage area for storing encoded data obtained by adding an error correction code to the write data;
A second error detection unit that performs an error detection process on the write data or the read data using the encoded data;
Based on the result of error detection processing in the second error detection unit, a second abnormality detection signal indicating the presence or absence of an error included in the write data or the read data is generated and supplied to the information processing apparatus A detection unit;
The information processing system, wherein the failure part determination unit determines which of the information processing device or the storage device is in failure based on the first abnormality detection signal and the second abnormality detection signal. . The information processing apparatus includes a socket connected to the storage device,
The failure part determination unit is configured to detect either a failure of the information processing device, a failure of the storage device, or a connection failure between the socket and the storage device based on the first abnormality detection signal and the second abnormality detection signal. The information processing system according to claim 9, wherein it is determined whether or not an error has occurred. The information processing apparatus includes:
A socket connected to the storage device;
A first parity generation unit that generates first parity data based on the write data or the read data and the encoded data;
A parity verification unit that performs data verification based on the first parity data;
With
The storage device
A second parity generation unit that generates second parity data based on the write data or the read data and the encoded data;
The parity verification unit receives the second parity data, compares the first parity data and the second parity data, and supplies a parity signal indicating a verification result to the failure site determination unit;
The failure part determination unit is configured to determine whether the information processing device has failed, the storage device has failed, and the socket and the storage device have a failure based on the first abnormality detection signal, the second abnormality detection signal, and the parity signal. The information processing system according to claim 9, wherein any one of the connection abnormalities is determined. The information processing apparatus includes a memory determination unit that transmits a memory determination signal for determining whether or not the storage device is connected to a predetermined terminal of the storage device,
The storage device includes a reply unit that is connected to the predetermined terminal, receives the memory judgment signal, and transmits a reply signal having the same signal value as the memory judgment signal to the memory judgment unit,
The memory determination unit determines whether the storage device is connected based on whether the return signal having the same signal value as the determination signal is received from the predetermined terminal. The information processing system according to any one of claims 9 to 11.

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