JP2016058652A - Manufacturing method of semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor memory by which, when etching an upper film, a film at a lower side of the film can be prevented from being retracted.SOLUTION: On a sidewall and a bottom face of a groove 60, a first sacrifice film 61 is formed and inside of the first sacrifice film, a second sacrifice film 62 is formed. While leaving a bottom of the first sacrifice film between the bottom face of the groove and the second sacrifice film, the first sacrifice film formed on the sidewall of the groove is removed. The second sacrifice film on the bottom of the first sacrifice film is removed. On the sidewall of the groove, an insulation film is formed so as to cover the bottom of the first sacrifice film. The insulation film on the bottom of the first sacrifice film is removed, the bottom of the first sacrifice film is exposed, the exposed bottom of the first sacrifice film is removed by isotropic etching, and a laminated film is exposed on the bottom face of the groove. Inside of the insulation film, a conductive film is formed in contact with a channel film 20 of the laminated film that is formed in a recess.SELECTED DRAWING: Figure 9

Description

  Embodiments described herein relate generally to a method for manufacturing a semiconductor memory device.

  A memory hole is formed in a stacked body in which a plurality of electrode layers functioning as control gates in a memory cell are stacked via an insulating layer, and a silicon body serving as a channel is provided on the side wall of the memory hole via a charge storage film. A memory device having a three-dimensional structure has been proposed.

  In the process of such a three-dimensional memory device, a technique for anisotropically etching the etching target film on the thin film while protecting the thin film under the etching target film may be required.

JP 2007-266143 A

  Embodiments of the present invention provide a method for manufacturing a semiconductor memory device that can suppress the receding of a film below the upper film when the upper film is etched.

  According to the embodiment, a method for manufacturing a semiconductor memory device includes: stacking a plurality of first layers and a plurality of second layers each provided between the plurality of first layers on a conductive layer. Forming. According to the embodiment, the method of manufacturing a semiconductor memory device includes a recess extending in the main surface direction of the conductive layer in the conductive layer, and a hole penetrating the stacked body and leading to the recess in the stacked body. Forming. According to the embodiment, the method for manufacturing a semiconductor memory device includes a step of forming a stacked film including a charge storage film and a channel film on the side wall of the hole and the inner wall of the recess. According to the embodiment, the method for manufacturing a semiconductor memory device includes a step of forming a groove that penetrates the stacked body and reaches the stacked film formed in the recess. According to the embodiment, the method of manufacturing a semiconductor memory device includes a step of forming a first sacrificial film on the side wall and the bottom surface of the groove. According to the embodiment, the method for manufacturing a semiconductor memory device includes a step of forming a second sacrificial film inside the first sacrificial film. According to the embodiment, in the method of manufacturing a semiconductor memory device, the bottom of the first sacrificial film between the bottom surface of the groove and the second sacrificial film is left, and the semiconductor memory device is formed on the side wall of the groove. A step of removing the first sacrificial film; According to the embodiment, the method for manufacturing a semiconductor memory device includes a step of removing the second sacrificial film on the bottom portion of the first sacrificial film. According to the embodiment, in the method of manufacturing a semiconductor memory device, after the second sacrificial film is removed, an insulating film is formed on the side wall of the groove so as to cover the bottom of the first sacrificial film. Have According to the embodiment, the method of manufacturing a semiconductor memory device includes a step of removing the insulating film on the bottom portion of the first sacrificial film and exposing the bottom portion of the first sacrificial film. According to the embodiment, the method of manufacturing a semiconductor memory device includes a step of removing the exposed bottom portion of the first sacrificial film by isotropic etching to expose the stacked film on a bottom surface of the groove. According to the embodiment, the method for manufacturing a semiconductor memory device includes a step of forming a conductive film in contact with the channel film of the stacked film formed in the concave portion inside the insulating film.

1 is a schematic perspective view of a semiconductor memory device according to an embodiment. 1 is a schematic cross-sectional view of a semiconductor memory device according to an embodiment. 1 is a schematic cross-sectional view of a semiconductor memory device according to an embodiment. FIG. 5 is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor memory device according to the embodiment. FIG. 5 is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor memory device according to the embodiment. FIG. 5 is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor memory device according to the embodiment. FIG. 5 is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor memory device according to the embodiment. FIG. 5 is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor memory device according to the embodiment. FIG. 5 is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor memory device according to the embodiment. FIG. 5 is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor memory device according to the embodiment. FIG. 5 is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor memory device according to the embodiment. FIG. 5 is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor memory device according to the embodiment. FIG. 5 is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor memory device according to the embodiment. FIG. 5 is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor memory device according to the embodiment. FIG. 5 is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor memory device according to the embodiment. FIG. 5 is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor memory device according to the embodiment. FIG. 5 is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor memory device according to the embodiment.

  Hereinafter, embodiments will be described with reference to the drawings. In addition, the same code | symbol is attached | subjected to the same element in each drawing.

  FIG. 1 is a schematic perspective view of a memory cell array 1 in the semiconductor memory device of the embodiment. In FIG. 1, the illustration of the insulating layer is omitted for easy understanding of the drawing.

  In FIG. 1, two directions that are parallel to the main surface of the substrate 10 and are orthogonal to each other are defined as an X direction (first direction) and a Y direction (second direction). The direction orthogonal to the Z direction (third direction, stacking direction).

FIG. 2 is a schematic cross-sectional view of the memory cell array 1.
The memory cell array 1 has a plurality of columnar portions CL as shown in FIG. 1, but FIG. 2 shows only one columnar portion CL, for example.

  A back gate BG is provided on the substrate 10 via an insulating layer 41. The back gate BG is a conductive layer. For example, the back gate BG is a silicon layer containing silicon as a main component, and the silicon layer is doped with an impurity (for example, boron) for imparting conductivity.

  A source-side selection gate (lower gate layer) SGS is provided on the back gate BG via an insulating layer 42.

  On the source-side selection gate SGS, a stacked body 15 including a plurality of electrode layers (first layers) WL and a plurality of insulating layers (second layers) 40 is provided via an insulating layer 43. The electrode layers WL and the insulating layers 40 are alternately stacked.

  On the uppermost electrode layer WL, a drain-side selection gate (upper gate layer) SGD is provided via an insulating layer 40. An insulating layer 44 is provided on the drain side select gate SGD.

  The source side selection gate SGS, the drain side selection gate SGD, and the electrode layer WL are, for example, silicon layers containing silicon as a main component, and the silicon layer is doped with, for example, boron as an impurity for imparting conductivity. Has been. Alternatively, the source side selection gate SGS, the drain side selection gate SGD, and the electrode layer WL may include metal silicide. Alternatively, the source side selection gate SGS, the drain side selection gate SGD, and the electrode layer WL are metal layers (for example, a layer mainly containing tungsten).

  Corresponding to the columns of the columnar portions CL arranged in the Y direction, the drain side select gates SGD are separated into a plurality in the Y direction. Each drain-side selection gate SGD extends in the X direction.

  A plurality of bit lines BL (metal films) are provided on the drain side select gate SGD as shown in FIG. Corresponding to the columns of the columnar portions CL arranged in the X direction, the bit lines BL are separated into a plurality in the X direction. Each bit line BL extends in the Y direction.

  A plurality of columnar portions CL pass through the insulating layer 44, the drain side select gate SGD, the stacked body 15, the insulating layer 43, the source side select gate SGS, and the insulating layer 42. The columnar portion CL extends in the stacking direction (Z direction) of the stacked body 15. The columnar portion CL is formed, for example, in a cylindrical or elliptical column shape.

  Further, the source layer SL penetrates the insulating layer 44, the drain side select gate SGD, the stacked body 15, the insulating layer 43, the source side select gate SGS, and the insulating layer 42. The source layer SL extends in the stacking direction (Z direction) of the stacked body 15.

  The lower end of the columnar part CL and the lower end of the source layer SL reach the back gate BG and are connected to a connecting part JP provided in the back gate BG.

  The source layer SL includes a metal (for example, tungsten). An insulating film 63 is provided on the side wall of the source layer SL. The insulating film 63 is provided between the source layer SL and the electrode layer WL, between the source layer SL and the source side selection gate SGS, between the source layer SL and the drain side selection gate SGD, and between the source layer SL and the back gate BG. Between.

  FIG. 3 is an enlarged schematic cross-sectional view of a part of the columnar part CL.

  As will be described later, the columnar portion CL is formed in the memory hole 53 shown in FIG. The memory hole 53 communicates with a recess 51 formed in the back gate BG and extending in the main surface direction (XY direction) of the back gate BG. As shown in FIG. 7B, the channel film 20 is provided in the memory hole 53 and the recess 51. The channel film 20 is a silicon film containing silicon as a main component, for example. The channel film 20 is substantially free of impurities.

  The channel film 20 in the memory hole 53 is formed in a cylindrical shape extending in the stacking direction of the stacked body 15. The upper end portion of the channel film 20 penetrates the drain side select gate SGD and is connected to the bit line BL shown in FIG.

  The channel film 20 is also provided in the back gate BG along the inner wall of the recess 51. A memory film 30 is provided between the side wall of the memory hole 53 and the channel film 20 and between the inner wall of the recess 51 and the channel film 20.

  As shown in FIG. 3, the memory film 30 includes a block insulating film 35, a charge storage film 32, and a tunnel insulating film 31. The memory film 30 formed on the side wall of the memory hole 53 is formed in a cylindrical shape extending in the stacking direction of the stacked body 15.

  Between the electrode layer WL and the channel film 20, a block insulating film 35, a charge storage film 32, and a tunnel insulating film 31 are provided in this order from the electrode layer WL side. The block insulating film 35 is in contact with the electrode layer WL, the tunnel insulating film 31 is in contact with the channel film 20, and the charge storage film 32 is provided between the block insulating film 35 and the tunnel insulating film 31.

  The memory film 30 surrounds the outer peripheral surface of the channel film 20. The electrode layer WL surrounds the outer peripheral surface of the channel film 20 with the memory film 30 interposed therebetween. A core insulating film 50 is provided inside the channel film 20.

  The electrode layer WL functions as a control gate of the memory cell. The charge storage film 32 functions as a data storage layer that stores charges injected from the channel film 20. A memory cell having a vertical transistor structure in which the control gate surrounds the periphery of the channel film 20 is formed at the intersection between the channel film 20 and each electrode layer WL.

  The semiconductor memory device according to the embodiment is a nonvolatile semiconductor memory device that can electrically and freely erase and write data and can retain stored contents even when the power is turned off.

  The memory cell is, for example, a charge trap type memory cell. The charge storage film 32 has a large number of trap sites for trapping charges, and includes, for example, a silicon nitride film.

  The tunnel insulating film 31 serves as a potential barrier when charge is injected from the channel film 20 into the charge storage film 32 or when the charge stored in the charge storage film 32 diffuses into the channel film 20. The tunnel insulating film 31 includes, for example, a silicon oxide film. As the tunnel insulating film 31, a laminated film (ONO film) having a structure in which a silicon nitride film is sandwiched between a pair of silicon oxide films may be used. When an ONO film is used as the tunnel insulating film 31, an erasing operation can be performed with a lower electric field than a single layer of a silicon oxide film.

  The block insulating film 35 prevents the charges stored in the charge storage film 32 from diffusing into the electrode layer WL. The block insulating film 35 includes a cap film 34 provided in contact with the electrode layer WL, and a block film 33 provided between the cap film 34 and the charge storage film 32.

  The block film 33 is, for example, a silicon oxide film. The cap film 34 is a film having a dielectric constant higher than that of the silicon oxide film, and is, for example, a silicon nitride film, an aluminum oxide film, a hafnium oxide film, an yttrium oxide film, or the like. By providing such a cap film 34 in contact with the electrode layer WL, back tunnel electrons injected from the electrode layer WL at the time of erasing can be suppressed.

  As shown in FIG. 1, a drain side select transistor STD is provided at the upper end of the columnar part CL, and a source side select transistor STS is provided at the lower end.

  The memory cell, the drain side select transistor STD, and the source side select transistor STS are vertical transistors in which current flows in the stacking direction (Z direction) of the stacked body 15.

  The drain side select gate SGD functions as a gate electrode (control gate) of the drain side select transistor STD. Between the drain side select gate SGD and the channel film 20, an insulating film functioning as a gate insulating film of the drain side select transistor STD is provided.

  The source side select gate SGS functions as a gate electrode (control gate) of the source side select transistor STS. An insulating film functioning as a gate insulating film of the source side select transistor STS is provided between the source side select gate SGS and the channel film 20.

  Between the drain side select transistor STD and the source side select transistor STS, there are provided a plurality of memory cells using the electrode layer WL of each layer as a control gate. The plurality of memory cells, the drain side select transistor STD, and the source side select transistor STS are connected in series through the channel body 20 to constitute one memory string MS. By arranging a plurality of memory strings MS in the X direction and the Y direction, a plurality of memory cells are three-dimensionally provided in the X direction, the Y direction, and the Z direction.

  As shown in FIG. 2, the channel film 20 is provided integrally with the columnar part CL and the connecting part JP. The memory film 30 is provided integrally with the columnar part CL and the connecting part JP. A memory film 30 is provided between the channel film 20 provided in the connecting portion JP and the back gate BG.

  The lower end of the source layer SL is in contact with the channel film 20 provided in the connecting portion JP. The connecting portion JP is provided with a back gate transistor BGT whose back gate BG is a control gate. By applying an appropriate potential to the back gate BG and turning on the back gate transistor BGT, the channel film 20 of the columnar part CL is electrically connected to the source layer SL via the channel film 20 of the coupling part JP. The The upper end of the channel film 20 is connected to the bit line BL shown in FIG. The upper end of the source layer SL is connected to an upper layer wiring (not shown).

  Next, with reference to FIGS. 4A to 17B, a method for manufacturing the semiconductor memory device of the embodiment will be described.

  As shown in FIG. 4A, a conductive layer BGa is formed on the substrate 10 with an insulating layer 41 interposed therebetween. The substrate 10 is, for example, a semiconductor substrate and a silicon substrate. The conductive layer BGa is, for example, a silicon layer doped with impurities.

  A recess 51 is formed in the conductive layer BGa as shown in FIG. 4B, and a sacrificial film 52 is embedded in the recess 51 as shown in FIG. The sacrificial film 52 is, for example, a silicon nitride film. A portion where the sacrificial film 52 (concave portion) is formed becomes a connection portion JP of the memory string MS.

  A conductive layer BGb is formed on the conductive layer BGa as shown in FIG. The sacrificial film 52 is covered with the conductive layer BGb. The conductive layer BGb is the same material as the conductive layer BGa, and the conductive layer BGa and the conductive layer BGb constitute a back gate BG.

  As shown in FIG. 6A, an insulating layer 42 is formed on the back gate BG. On the insulating layer 42, a source-side selection gate SGS is formed. An insulating layer 43 is formed on the source side select gate SGS.

  On the insulating layer 43, the stacked body 15 including a plurality of electrode layers (first layers) WL and a plurality of insulating layers (second layers) 40 is formed. On the insulating layer 43, the electrode layers WL and the insulating layers 40 are alternately formed. The process of alternately forming the electrode layers WL and the insulating layers 40 is repeated a plurality of times. An insulating layer 40 is provided between the electrode layer WL and the electrode layer WL. The number of stacked electrode layers WL and insulating layers 40 is not limited to the number of layers shown in the drawing.

  On the uppermost electrode layer WL, the drain side select gate SGD is formed via the insulating layer 40. An insulating layer 44 is formed on the drain side select gate SGD.

  As shown in FIG. 6B, the memory hole 53 is formed in the stacked body 100 on the back gate BG. A memory hole 53 is formed by an RIE (Reactive Ion Etching) method using a mask layer (not shown) formed on the stacked body 100.

  The memory hole 53 passes through the stacked body 100 and also passes through the back gate BG on the sacrificial film 52 to reach the sacrificial film 52.

  Next, the sacrificial film 52 is removed by isotropic etching through the memory hole 53. As a result, as shown in FIG. 7A, a recess 51 formed in the back gate BG appears. The recess 51 extends in the main surface direction of the conductive layer BGa and the conductive layer BGb constituting the back gate BG and is connected to the memory hole 53.

  A memory film 30 is formed on the side wall of the memory hole 53 and the inner wall of the recess 51 as shown in FIG. A channel film 20 is formed inside the memory film 30. A core insulating film 50 is formed in the cavity inside the channel film 20 as shown in FIG.

  The stacked film including the memory film 30, the channel film 20, and the core insulating film 50 formed in the memory hole 53 forms the columnar portion CL. The stacked film including the memory film 30, the channel film 20, and the core insulating film 50 formed in the recess 51 forms the connection portion JP. The connecting portion JP is formed in the back gate BG. A memory film 30 is formed on the outermost side of the connecting portion JP, and the memory film 30 is in contact with the back gate BG.

  The memory film 30, the channel film 20, and the core insulating film 50 deposited on the upper surface of the stacked body 100 are removed.

  Next, as shown in FIG. 8B, the groove 60 is formed in the stacked body 100. The groove 60 is formed by the RIE method using a mask layer (not shown) formed on the stacked body 100. The trench 60 penetrates the stacked body 100 and further passes through the back gate BG above the coupling portion JP and reaches the memory film 30 of the coupling portion JP.

  FIG. 9A shows an enlarged cross section of a portion where the groove 60 is formed.

  The groove 60 extends in a direction penetrating the paper surface. The memory film 30 of the connecting portion JP is exposed on the bottom surface of the groove 60.

  As shown in FIG. 9B, a first sacrificial film 61 is formed on the side wall and the bottom surface of the groove 60. The first sacrificial film 61 is a film made of a different material from the stacked body 100, the memory film 30, and the channel film 20. As the first sacrificial film 61, for example, an organic film is conformally formed along the side wall and the bottom surface of the groove 60 by a CVD (Chemical Vapor Deposition) method. A cavity remains inside the first sacrificial film 61.

  A second sacrificial film 62 is formed inside the first sacrificial film 61. The second sacrificial film 62 is a film made of a material different from that of the first sacrificial film 61. As the second sacrificial film 62, for example, an SOG (spin on glass) film containing silicon oxide is embedded inside the first sacrificial film 61 by a coating method.

  The second sacrificial film 62 deposited on the first sacrificial film 61 on the upper surface of the stacked body 100 is etched back and removed by the RIE method. As a result, the first sacrificial film 61 is exposed as shown in FIG.

  Next, the first sacrificial film 61 is etched back by the RIE method. Thereby, the first sacrificial film 61 formed on the upper surface of the stacked body 100 and on the side wall of the groove 60 is removed as shown in FIG. During this RIE, the second sacrificial film 62 serves as a mask, and the bottom 61 a of the first sacrificial film 61 between the bottom surface of the trench 60 and the second sacrificial film 62 remains.

  In addition, by etching back the first sacrificial film 61 by, for example, RIE using oxygen plasma, a sufficient selection ratio with respect to the memory film 30 exposed on the bottom surface of the groove 60 can be secured, so The memory film 30 and the channel film 20 are not lost by overetching.

  Next, the second sacrificial film 62 on the bottom 61a of the first sacrificial film 61 is removed. The second sacrificial film 62, which is an SOG film, is removed by, for example, a wet etching method using hydrofluoric acid. As shown in FIG. 11A, the bottom portion 61 a of the first sacrificial film 61 remains on the bottom surface of the groove 60.

  When the insulating layers 40, 42, 43, 44 of the stacked body 100 include silicon oxide, the end portions of the insulating layers 40, 42, 43, 44 on the side wall side of the groove 60 when the second sacrificial film 62 is wet etched. May go back a little.

  After removing the second sacrificial film 62, an insulating film 63 is formed in the trench 60 as shown in FIG. The insulating film 63 is a film made of a different material from the first sacrificial film 61. As the insulating film 63, for example, a silicon oxide film is conformally formed by the CVD method so as to cover the bottom portion 61 a of the first sacrificial film 61 along the side wall of the groove 60. A cavity is left inside the insulating film 63. The side surface and the upper surface of the bottom portion 61 a of the first sacrificial film 61 are covered with the insulating film 63.

  Next, the insulating film 63 is etched back by the RIE method. The insulating film 63 on the bottom 61a of the first sacrificial film 61 is removed as shown in FIG. The insulating film 63 deposited on the upper surface of the stacked body 100 is also removed.

  By etching back the insulating film 63, the bottom 61a of the first sacrificial film 61 is exposed. Next, the bottom portion 61a of the first sacrificial film 61 is removed by, for example, an ashing method using oxygen plasma. Thereby, as shown in FIG. 12B, the memory film 30 of the connecting portion JP is exposed on the bottom surface of the groove 60.

  Here, as a reference example, for example, after the trench 60 is formed, the first sacrificial film 61 and the second sacrificial film 62 are not formed, and the insulating film 63 is formed conformally in the trench 60. The problem is concerned.

  In order to prevent a short circuit between the source layer SL formed in the trench 60 and the electrode layer WL in a later step, the insulation film 63 on the bottom surface of the trench 60 is formed by RIE while leaving the insulation film 63 on the side wall of the trench 60. A process for removing the channel film 20 to be connected to the source layer SL on the bottom surface of the groove 60 is required.

  The thickness of the memory film 30 of the connecting portion JP under the groove 60 is expected to be about 20 to 30 nm, for example, and the thickness of the channel film 20 under the memory film 30 is expected to be even thinner, for example, 20 nm or less.

  In such a thin film, the channel film 20 disappears due to over-etching of the insulating film 63 on the bottom surface of the groove 60 during RIE, and the source film SL cannot be contacted, or the channel film 20 becomes very thin and the source There is a concern that the contact resistance with the layer SL may increase.

  As the bit density is increased, the aspect ratio of the cavity inside the insulating film 63 is increased as the number of electrode layers WL is increased and the width of the groove 60 is reduced. It is difficult to etch a film under such a high aspect ratio cavity with high controllability by the RIE method.

  On the other hand, according to the embodiment, the bottom 61a of the first sacrificial film 61 is removed by isotropic etching instead of anisotropic etching such as RIE. For this reason, even when the aspect ratio of the cavity inside the insulating film 63 is high, excessive etching of the channel film 20 under the bottom 61a of the first sacrificial film 61 can be suppressed. As a result, sufficient contact between the source layer SL formed in the subsequent process and the channel film 20 of the connecting portion JP can be secured, and a decrease in contact resistance between the source layer SL and the channel film 20 can be prevented.

  After removing the bottom 61a of the first sacrificial film 61 to expose the memory film 30 on the bottom surface of the groove 60, the memory film 30 exposed on the bottom surface of the groove 60 is removed by RIE. At this time, there is no thick insulating film on the memory film 30 exposed on the bottom surface of the groove 60. That is, an etching process that exposes the memory film 30 while completely removing the thick insulating film is unnecessary, and overetching of the thin memory film 30 and the thin channel film 20 under the etching process, which is likely to occur in such an etching process, is not necessary. Can be suppressed. As shown in FIG. 13A, an opening 30a reaching the channel film 20 is formed under the cavity inside the insulating film 63 in the trench 60, and the channel film 20 is exposed.

  Thereafter, the source layer SL is formed in the cavity inside the insulating film 63. As shown in FIG. 13B, the source layer SL is in contact with the channel film 20 of the connecting portion JP. Therefore, the channel film 20 of the columnar part CL is connected to the source layer SL via the channel film 20 of the connecting part JP.

  The first sacrificial film 61 is not limited to an organic film, and for example, a silicon film can be used. When the first sacrificial film 61 is a silicon film, the selectivity with respect to the memory film 30 can be secured by using plasma of chlorine or bromine gas in the process of FIG. In the step of FIG. 12B, the bottom portion 61a of the first sacrificial film 61, which is a silicon film, can be removed by isotropic etching by using an organic alkali solution.

  Next, FIG. 14A to FIG. 17B are schematic cross-sectional views showing another method for manufacturing the semiconductor memory device of the embodiment.

  The process proceeds to the step shown in FIG. Then, the groove 60 is formed. After the groove 60 is formed or when the groove 60 is formed, the memory film 30 of the connecting portion JP is removed and the channel film 20 is exposed on the bottom surface of the groove 60 as shown in FIG.

  Thereafter, the same process as in the above embodiment using the first sacrificial film 61 and the second sacrificial film 62 is performed.

  That is, the first sacrificial film 61 is formed on the side wall and the bottom surface of the groove 60 as shown in FIG. As the first sacrificial film 61, for example, an organic film is conformally formed along the side wall and the bottom surface of the groove 60 by a CVD method. A cavity remains inside the first sacrificial film 61.

  A second sacrificial film 62 is formed inside the first sacrificial film 61. As the second sacrificial film 62, for example, an SOG film containing silicon oxide is embedded inside the first sacrificial film 61 by a coating method.

  The second sacrificial film 62 deposited on the first sacrificial film 61 on the upper surface of the stacked body 100 is etched back and removed by the RIE method. As a result, as shown in FIG. 15A, the first sacrificial film 61 is exposed.

  Next, the first sacrificial film 61 is etched back by the RIE method. Thereby, the first sacrificial film 61 formed on the upper surface of the stacked body 100 and on the side wall of the groove 60 is removed as shown in FIG. During this RIE, the second sacrificial film 62 serves as a mask, and the bottom 61 a of the first sacrificial film 61 between the bottom surface of the trench 60 and the second sacrificial film 62 remains.

  Next, the second sacrificial film 62 on the bottom 61a of the first sacrificial film 61 is removed. The second sacrificial film 62, which is an SOG film, is removed by, for example, a wet etching method using hydrofluoric acid. As shown in FIG. 16A, the bottom 61 a of the first sacrificial film 61 remains on the bottom surface of the groove 60.

  After removing the second sacrificial film 62, an insulating film 63 is formed in the trench 60 as shown in FIG. As the insulating film 63, for example, a silicon oxide film is conformally formed by the CVD method so as to cover the bottom portion 61 a of the first sacrificial film 61 along the side wall of the groove 60. A cavity is left inside the insulating film 63. The side surface and the upper surface of the bottom portion 61 a of the first sacrificial film 61 are covered with the insulating film 63.

  Next, the insulating film 63 is etched back by the RIE method. The insulating film 63 on the bottom 61a of the first sacrificial film 61 is removed as shown in FIG. The insulating film 63 deposited on the upper surface of the stacked body 100 is also removed.

  By etching back the insulating film 63, the bottom 61a of the first sacrificial film 61 is exposed. Next, the bottom 61a of the first sacrificial film 61 is removed by, for example, an ashing method using oxygen plasma. As a result, as shown in FIG. 17B, the channel film 20 of the connecting portion JP is exposed on the bottom surface of the groove 60.

  Also in this embodiment, the bottom 61a of the first sacrificial film 61 is removed by isotropic etching instead of anisotropic etching such as RIE. For this reason, even when the aspect ratio of the cavity inside the insulating film 63 is high, excessive etching of the channel film 20 under the bottom 61a of the first sacrificial film 61 can be suppressed. As a result, sufficient contact between the source layer SL formed in the subsequent process and the channel film 20 of the connecting portion JP can be secured, and a decrease in contact resistance between the source layer SL and the channel film 20 can be prevented.

  The silicon oxide film formed on the upper surface of the channel film 20 by ashing when the bottom 61a of the first sacrificial film 61 is removed may be removed by chemical treatment. Thereafter, the source layer SL is formed in the cavity inside the insulating film 63. As shown in FIG. 17B, the source layer SL is in contact with the channel film 20 of the connecting portion JP. Therefore, the channel film 20 of the columnar part CL is connected to the source layer SL via the channel film 20 of the connecting part JP.

  According to the embodiment described above, the insulating film 63 in a portion where the source layer SL and the channel film 20 are in contact with each other is completely removed while protecting the channel film 20 of the connecting portion JP under the groove 60. Contact failure between the SL and the channel film 20 can be prevented.

  In forming the stacked body 100, the stacked body 100 is formed by alternately stacking first layers (for example, silicon nitride films) and second layers (for example, silicon oxide films) of different materials from the first layers. May be. Thereafter, the first layer is removed by etching through a hole or slit that penetrates the stacked body 100, and a conductive layer (for example, a metal layer) that becomes the electrode layer WL, the selection gates SGD, and SGS in the space from which the first layer is removed. Can also be formed.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 10 ... Substrate, 20 ... Channel film, 30 ... Memory film, 32 ... Charge storage film, 40 ... Insulating layer, 51 ... Recess, 60 ... Groove, 61 ... First sacrificial film, 62 ... Second sacrificial film, 63 ... Insulation Film, WL ... electrode layer, SL ... source layer, CL ... columnar portion, JP ... connecting portion

Claims (5)

Forming a laminated body having a plurality of first layers and a plurality of second layers each provided between the plurality of first layers on a conductive layer;
Forming a recess extending in the main surface direction of the conductive layer in the conductive layer, and forming a hole in the stacked body that penetrates the stacked body and communicates with the recessed portion;
Forming a stacked film including a charge storage film and a channel film on the side wall of the hole and the inner wall of the recess;
Forming a groove that penetrates the laminated body and reaches the laminated film formed in the recess;
Forming a first sacrificial film on the side wall and bottom surface of the groove;
Forming a second sacrificial film inside the first sacrificial film;
Removing the first sacrificial film formed on the side wall of the groove, leaving the bottom of the first sacrificial film between the bottom surface of the groove and the second sacrificial film;
Removing the second sacrificial film on the bottom of the first sacrificial film;
Forming an insulating film on a sidewall of the groove so as to cover the bottom of the first sacrificial film after removing the second sacrificial film;
Removing the insulating film on the bottom of the first sacrificial film to expose the bottom of the first sacrificial film;
Removing the exposed bottom portion of the first sacrificial film by isotropic etching to expose the laminated film on the bottom surface of the groove;
Forming a conductive film in contact with the channel film of the stacked film formed in the concave portion inside the insulating film;
A method for manufacturing a semiconductor memory device comprising: The first sacrificial film is formed in the groove without exposing the channel film formed in the recess on the bottom surface of the groove,
The method of manufacturing a semiconductor memory device according to claim 1, wherein after removing the bottom portion of the first sacrificial film, the channel film formed in the recess is exposed on the bottom surface of the groove.   The method of manufacturing a semiconductor memory device according to claim 1, wherein the first sacrificial film is formed in the groove after exposing the channel film formed in the recess on the bottom surface of the groove. The first sacrificial film is an organic film or a silicon film;
The first sacrificial film formed on the sidewall of the trench is removed by RIE (Reactive Ion Etching) method,
The method of manufacturing a semiconductor memory device according to claim 1, wherein the bottom portion of the first sacrificial film on the bottom surface of the groove is removed by an ashing method or a wet etching method.   5. The method of manufacturing a semiconductor memory device according to claim 1, wherein the second sacrificial film on the bottom of the first sacrificial film is removed by a wet etching method.

Images