JP2016046445A - Semiconductor device and semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a semiconductor device manufacturing method, which can reduce a width of a mesa part without performing fine patterning thereby to achieve a low loss.SOLUTION: A semiconductor device comprises: a mesa part 1a between adjacent trenches 2, which projects from an interface between an interlayer insulation film 8 and an emitter electrode 9 to the emitter electrode 9 side; a p type base area 5 provided in the mesa part 1a between the adjacent trenches 2; and an ntype emitter area 6 and a ptype contact area 7, which are provided inside the p-type base area 5. The p type base area 5, the ntype emitter area 6 and the ptype contact area 7 are provided in areas of the mesa part 1a, respectively, each including a portion which projects from an interface between the interlayer insulation film 8 and the emitter electrode 9 to the emitter electrode 9 side. The emitter electrode 9 contacts the ntype emitter area 6 and the ptype contact area 7 at a portion of the mesa part 1a, which projects from the interface between the interlayer insulation film 8 and the emitter electrode 9 to the emitter electrode 9 side.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  Examples of power semiconductor devices include IGBTs (insulated gate field effect transistors) having a withstand voltage class of 400 V, 600 V, 1200 V, 1700 V, 3300 V, or higher. In power semiconductor devices, IGBTs are used in power conversion devices such as converter-inverters. This power semiconductor device is required to have low loss, high efficiency, high withstand capability, and low cost. The structure of a conventional power semiconductor device will be described below by taking a trench IGBT as an example. FIG. 32 is a cross-sectional view showing the structure of the active portion of a conventional trench IGBT. FIG. 33 is an enlarged sectional view showing the structure on the emitter side of FIG.

As shown in FIGS. 32 and 33, the conventional trench IGBT has a trench type MOS gate (insulated gate made of metal-oxide film-semiconductor) structure on the front surface side of an n ⁻ type semiconductor substrate. Specifically, a trench 102 is provided on the front surface side of an n ⁻ type semiconductor substrate to be the n ⁻ type drift layer 101, and a gate electrode 104 is embedded in the trench 102 via a gate insulating film 103. It is. A p-type base region 105 is provided in a mesa portion between adjacent trenches 102. In the p-type base region 105, an n-type inversion layer (channel) is formed near the boundary with the gate insulating film 103 when a gate voltage is applied. In the p-type base region 105, an n ⁺ -type emitter region 106 and a p ⁺ -type contact region 107 are selectively provided.

The n ⁺ -type emitter region 106 is provided so as to be in contact with the gate insulating film 103 provided along the sidewall of the trench 102. The p ⁺ -type contact region 107 is provided at a substantially central portion between adjacent trenches 102 so as not to contact the channel formed in the vicinity of the boundary between the p-type base region 105 and the gate insulating film 103 when a gate voltage is applied. ing. The p ⁺ -type contact region 107 has a function of maintaining a latch-up resistance. The interlayer insulating film 108 covering the front surface of the n ⁻ type semiconductor substrate has a contact hole that penetrates the interlayer insulating film 108 in the depth direction and exposes the n ⁺ type emitter region 106 and the p ⁺ type contact region 107. Is provided.

Emitter electrode 109 is provided on interlayer insulating film 108 and is in contact with n ⁺ -type emitter region 106 and p ⁺ -type contact region 107 through a contact hole. Patterning for forming each region, trench and contact hole constituting the MOS gate structure is performed by photolithography. Among these, the patterning for forming the contact hole has the narrowest width of the portion removed by etching, which limits the miniaturization of the patterning. An n-type field stop layer 110 and a p-type collector layer 111 are provided on the back side of the n ⁻ type semiconductor substrate. The collector electrode 112 is in contact with the p-type collector layer 111.

In order to reduce the power loss of the IGBT, it is effective to increase the carrier injection efficiency on the emitter side and decrease the carrier injection efficiency on the collector side. In order to increase the carrier injection efficiency of the emitter of the trench IGBT, the width (mesa width) Ln of the mesa portion provided with the n ⁺ -type emitter region 106 is narrowed to increase the injection enhancement (IE) effect. It is effective to make it. However, in this case, it is difficult to make contact between the emitter electrode 109 and the silicon portion (n ⁺ -type emitter region 106 and p ⁺ -type contact region 107).

Specifically, the reason why it is difficult to make contact between the emitter electrode 109 and the silicon portion is that fine patterning is necessary to form a contact hole with the narrowest etching width, and in this way It is difficult to bury the emitter electrode 109 made of aluminum (Al) in a narrow contact hole. In the conventional trench IGBT, the p ⁺ -type contact region 107 is formed by ion implantation and heat treatment. Due to the diffusion of impurities in the lateral direction (direction perpendicular to the depth direction) during this heat treatment, the p ⁺ -type contact region 107 is formed to extend laterally to a position in contact with the channel, and the latch-up resistance is reduced. There is.

As a device that solves such a problem, as shown in FIG. 34, a second trench 112 is provided at a depth shallower than the p-type base region 105 in the mesa between adjacent trenches (gate trenches) 102. An apparatus in which a p ⁺ -type contact region (trench contact) 117 is provided along the inner wall of the trench 112 has been proposed (see, for example, Patent Documents 1 to 3 below). FIG. 34 is a cross-sectional view showing another example of the structure on the emitter side of the active portion of a conventional trench IGBT. In the following Patent Documents 1 to 3, since the dose of ion implantation can be reduced when forming the p ⁺ -type contact region 117 at a predetermined depth from the front surface of the substrate by ion implantation, the lateral direction of impurities Diffusion is suppressed and the latch-up resistance is improved.

As a method of forming a p ⁺ type contact region along the inner wall of the trench provided in the mesa between adjacent gate trenches, a shallow trench is dug to a depth to form the p ⁺ type contact region, oblique implantation, vapor phase A method of injecting impurities using a diffusion method or a solid phase diffusion method has been proposed (see, for example, Patent Document 4 below). As another device having a configuration in which the carrier injection efficiency on the emitter side is increased, the upper surface of the gate is located above the upper surface of the p-channel region, the interlayer insulating film is in the trench, and the upper surface is from the opening of the trench. A device is proposed in which the source electrode, the n ⁺ -type source region, and the p ⁺ -type body region are electrically connected to each other at the sidewall of the trench (see, for example, Patent Document 5 below). .

JP 2009-076762 A JP 2011-204808 A JP 2012-174989 A JP 2003-017699 A Japanese Patent Laying-Open No. 2005-045123

  However, as described above, in the trench IGBT, it is necessary to narrow the width of the mesa portion in order to reduce power loss. Accordingly, it is necessary to reduce the width of the contact hole. However, as described above, when a narrow contact hole that selectively exposes the mesa portion is formed by fine patterning, the contact between the emitter electrode and the silicon portion is reduced. It becomes difficult to make ohmic contact. In the above Patent Documents 1 to 3, a device that structurally solves the problem that it becomes difficult to make ohmic contact between the emitter electrode and the silicon portion when narrowing the width of the mesa portion in order to reduce power loss. Not proposed.

  In order to solve the above-described problems caused by the prior art, the present invention can reduce the width of the mesa portion without performing fine patterning, and can reduce the loss. It aims to provide a method.

  In order to solve the above-described problems and achieve the object of the present invention, a semiconductor device according to the present invention has the following characteristics. A plurality of trenches are provided on the front surface of the first conductivity type semiconductor substrate. A first insulating film is provided inside the trench along the inner wall of the trench. A gate electrode is provided inside the first insulating film inside the trench. A first semiconductor region of a second conductivity type facing the gate electrode is provided in the mesa portion between the adjacent trenches through the first insulating film provided along the side wall of the trench. A second semiconductor region of a first conductivity type is provided inside the first semiconductor region. A second insulating film is provided on the gate electrode inside the trench. A first electrode in contact with the first semiconductor region and the second semiconductor region is provided. A second conductivity type semiconductor layer is provided on the back surface of the semiconductor substrate. A second electrode in contact with the second conductivity type semiconductor layer is provided. An end portion of the mesa portion on the first electrode side protrudes from the interface between the second insulating film and the first electrode toward the first electrode side. The first electrode is in contact with the entire surface of the protruding portion of the mesa portion and is connected to the first semiconductor region and the second semiconductor region.

  In the semiconductor device according to the present invention, in the above-described invention, when the width of the mesa portion is 3.0 μm or less, the width of the mesa portion is Lm, and the width of the gate electrode is Lg, Lm / (Lg + Lm) <0.5 is satisfied.

  In the semiconductor device according to the present invention, in the above-described invention, a thickness of a portion of the mesa portion protruding from the interface between the second insulating film and the gate electrode toward the first electrode is 0.1 μm. It is the above.

  In the semiconductor device according to the present invention as set forth in the invention described above, the depth of the trench is 3.0 μm or more.

  In the semiconductor device according to the present invention as set forth in the invention described above, the depth of the first semiconductor region is shallower on the center side of the mesa portion than on the side surface side of the mesa portion.

  The semiconductor device according to the present invention is characterized in that, in the above-described invention, a plurality of the gate electrodes electrically insulated by the second insulating film are provided inside the trench.

  The semiconductor device according to the present invention is characterized in that, in the above-described invention, at least one of the plurality of gate electrodes has a different potential from the other gate electrodes.

  The semiconductor device according to the present invention is characterized in that, in the above-described invention, the plurality of trenches are arranged in a stripe shape.

  In the semiconductor device according to the present invention, in the above-described invention, the first semiconductor region and the second semiconductor region are orthogonal to a direction in which the trench extends in a stripe shape in a protruding portion of the mesa portion. It is characterized by being repeatedly arranged alternately.

  In the semiconductor device according to the present invention as set forth in the invention described above, the first insulating film is made of an insulating film having a dielectric constant higher than that of the oxide film.

  In the semiconductor device according to the present invention, in the above-described invention, the first insulating film has an oxide film along a bottom surface and a side wall, and at least a part of a portion provided along the side wall is made of an oxide film. Is also made of an insulating film having a high dielectric constant.

  In the semiconductor device according to the present invention, in the above-described invention, the first insulating film includes an oxide film along a bottom surface and a side surface, and at least a part of a portion provided along the bottom surface is formed from the oxide film. Is also made of an insulating film having a low dielectric constant.

  In the semiconductor device according to the present invention as set forth in the invention described above, the first insulating film has a thickness at least part of a portion provided along the bottom surface of the trench along the sidewall of the trench. It is characterized by being thicker than the thickness of the part.

  The semiconductor device according to the present invention further includes a second semiconductor region of a second conductivity type provided in a surface layer of the semiconductor substrate exposed at a bottom surface of the trench in the above-described invention. And

  In order to solve the above-described problems and achieve the object of the present invention, a semiconductor device manufacturing method according to the present invention has the following characteristics. First, a first step of selectively forming a first film on the front surface of a first conductivity type semiconductor substrate is performed. Next, a second step of forming a second film on the front surface of the semiconductor substrate and the first film is performed. Next, a third step of leaving a portion of the second film on the front surface of the semiconductor substrate in contact with the side surface of the first film with a predetermined width is performed. Next, a fourth step of removing the first film is performed. Next, a fifth step of forming a plurality of trenches on the front surface of the semiconductor substrate using the second film as a mask is performed. Next, a sixth step of forming a first insulating film in the trench along the inner wall of the trench is performed. Next, a seventh step of forming a gate electrode inside the first insulating film inside the trench is performed. Next, a second conductive type first semiconductor region is formed in a mesa portion between adjacent trenches so as to face the gate electrode through the first insulating film provided along the sidewall of the trench. The 8th process to form is performed. Next, a ninth step of forming a second semiconductor region of the first conductivity type inside the first semiconductor region is performed. Next, a tenth step of forming a second insulating film on the gate electrode by heat treatment is performed. Next, an eleventh step of forming a first electrode in contact with the first semiconductor region and the second semiconductor region is performed. Next, a twelfth step of forming a second conductivity type semiconductor layer on the back surface of the semiconductor substrate is performed. Next, a thirteenth step of forming a second electrode in contact with the second conductivity type semiconductor layer is performed. In the third step, the second film is etched to leave a portion of the second film that remains on the side surface of the first film without being etched. In the seventh step, the gate electrode is formed so that the surface of the gate electrode is positioned below the surface of the mesa portion. In the eighth step, the first semiconductor region is formed in a region including the protruding portion of the mesa portion. In the ninth step, the second semiconductor region is formed in a region including the protruding portion of the mesa portion. In the eleventh step, the first electrode in contact with the entire surface of the protruding portion of the mesa portion is formed.

  The method for manufacturing a semiconductor device according to the present invention further has the following characteristics in the above-described invention. In the seventh step, first, a deposition step for depositing the gate electrode is performed. Next, a polishing process for polishing the gate electrode is performed. Next, an etching process for etching the gate electrode is performed. Then, the thickness of the gate electrode is reduced by the polishing step and the etching step so that the surface of the gate electrode is positioned below the surface of the mesa portion.

  In the method of manufacturing a semiconductor device according to the present invention, in the above-described invention, in the polishing step, a portion of the gate electrode above the surface of the second film is polished using the second film as a polishing stopper. It is characterized by that.

  The method for manufacturing a semiconductor device according to the present invention is characterized in that, in the above-described invention, in the etching step, the gate electrode is etched using the second film as a mask.

  In order to solve the above-described problems and achieve the object of the present invention, a semiconductor device manufacturing method according to the present invention has the following characteristics. First, a first step of forming a plurality of trenches on the front surface of a first conductivity type semiconductor substrate is performed. Next, a second step of forming a first insulating film in the trench along the inner wall of the trench is performed. Next, a third step of forming a gate electrode inside the first insulating film inside the trench is performed. Next, a second conductive type first semiconductor region is formed in a mesa portion between adjacent trenches so as to face the gate electrode through the first insulating film provided along the sidewall of the trench. The 4th process to form is performed. Next, a fifth step of forming a second semiconductor region of the first conductivity type inside the first semiconductor region is performed. Next, a sixth step of forming a second insulating film on the gate electrode by heat treatment is performed. Next, a seventh step of forming a first electrode in contact with the first semiconductor region and the second semiconductor region is performed. Next, an eighth step of forming a second conductivity type semiconductor layer on the back surface of the semiconductor substrate is performed. Next, a ninth step of forming a second electrode in contact with the second conductivity type semiconductor layer is performed. In the third step, the gate electrode is formed such that the surface of the gate electrode is positioned below the surface of the mesa portion. In the fourth step, by introducing a second conductivity type impurity from the sidewall of the trench by using an ion implantation method or a plasma doping method, the first semiconductor region is formed in a region including the protruding portion of the mesa portion. Form. In the fifth step, the second semiconductor region is formed in a region including the protruding portion of the mesa portion by introducing a first conductivity type impurity from the sidewall of the trench using an ion implantation method or a plasma doping method. Form. In the seventh step, the first electrode in contact with the entire surface of the protruding portion of the mesa portion is formed.

  In the method for manufacturing a semiconductor device according to the present invention, in the above-described invention, when the ion implantation method is used in the fourth step and the fifth step, 10 ° or more with respect to the front surface of the semiconductor substrate. A second conductivity type impurity is introduced into the side wall of the trench from an oblique direction of 80 ° or less.

  The method for manufacturing a semiconductor device according to the present invention further has the following characteristics in the above-described invention. In the fourth step, when an ion implantation method is used, two ion implantation steps are performed. Specifically, first, the second conductivity type impurity is applied to the side wall of the trench forming one side surface of the mesa portion from an oblique direction of 10 ° to 80 ° with respect to the front surface of the semiconductor substrate. A first ion implantation step for ion implantation is performed. Next, a second conductivity type impurity is ion-implanted into a side wall of the trench forming the other side surface of the mesa portion from an oblique direction of −80 ° to −10 ° with respect to the front surface of the semiconductor substrate. A second ion implantation step is performed.

  In the semiconductor device manufacturing method according to the present invention, in the above-described invention, the first semiconductor region and the second semiconductor region are activated by heat treatment after the fifth step and before the sixth step. A heat treatment step, wherein the heat treatment step is performed at 800 ° C. to 1100 ° C. for 1 second or less.

  In the semiconductor device manufacturing method according to the present invention, spike heat annealing or flash lamp annealing is performed as the heat treatment in the heat treatment step.

  According to the method of manufacturing a semiconductor device according to the present invention, in the above-described invention, the first insulating film is locally oxidized by heat treatment after the first insulating film is formed and before the gate electrode is formed. A step of making a thickness of a part of the first insulating film thicker than a thickness of the other part of the first insulating film is performed.

  According to the above-described invention, the mesa portion between adjacent trenches protrudes from the interface between the second insulating film and the first electrode toward the first electrode, thereby selectively exposing the upper surface of the mesa portion. It can be set as the structure which does not provide. Therefore, a trench type semiconductor device can be manufactured (manufactured) without performing the finest patterning for forming a narrow contact hole among a plurality of times of patterning by photolithography. For this reason, even when the width of the mesa portion is narrowed to increase the IE effect, the ohmic contact between the first electrode and the silicon portion can be reliably obtained.

  According to the semiconductor device and the manufacturing method of the semiconductor device according to the present invention, the mesa portion can be narrowed without performing fine patterning, and the loss can be reduced.

2 is a cross-sectional view showing a structure of an active portion of the semiconductor device according to the first embodiment; FIG. It is sectional drawing which expands and shows the structure of the mesa part by the side of the board | substrate front surface of FIG. FIG. 6 is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the first embodiment; It is a characteristic view which shows the relationship between the ON voltage and turn-off loss of the semiconductor device concerning Embodiment 1 of this invention. FIG. 6 is a perspective view showing a structure of a main part of a semiconductor device according to a second embodiment. FIG. 6 is a cross-sectional view showing a state during the manufacture of the semiconductor device according to the second embodiment; FIG. 6 is a cross-sectional view showing a state during the manufacture of the semiconductor device according to the second embodiment; FIG. 6 is a cross-sectional view showing a structure of a main part of a semiconductor device according to a third embodiment. FIG. 9 is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the third embodiment; FIG. 9 is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the third embodiment; FIG. 9 is a cross-sectional view showing a structure of a main part of another example of a semiconductor device according to a fourth embodiment; FIG. 9 is a cross-sectional view showing a structure of a main part of a semiconductor device according to a fifth embodiment. FIG. 10 is a cross-sectional view showing a structure of a main part of a semiconductor device according to a sixth embodiment. FIG. 10 is a cross-sectional view showing a structure of a main part of a semiconductor device according to a seventh embodiment. FIG. 10 is a cross-sectional view showing a structure of a main part of a semiconductor device according to an eighth embodiment. FIG. 10 is a sectional view showing a state in the middle of manufacturing the semiconductor device according to the ninth embodiment; FIG. 10 is a sectional view showing a state in the middle of manufacturing the semiconductor device according to the ninth embodiment; It is sectional drawing which shows the structure of the active part of the conventional trench type IGBT. It is sectional drawing which expands and shows the structure by the side of the emitter of FIG. It is sectional drawing which shows another example of the structure by the side of the emitter of the active part of the conventional trench type IGBT.

  Exemplary embodiments of a semiconductor device and a method for manufacturing the semiconductor device according to the present invention will be explained below in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that electrons or holes are majority carriers in layers and regions with n or p, respectively. Further, + and − attached to n and p mean that the impurity concentration is higher and lower than that of the layer or region where it is not attached. Note that, in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted.

(Embodiment 1)
The structure of the semiconductor device according to the first embodiment will be described by taking a trench IGBT as an example. FIG. 1 is a cross-sectional view illustrating the structure of the active portion of the semiconductor device according to the first embodiment. FIG. 2 is an enlarged cross-sectional view showing the structure of the mesa portion on the front side of the substrate in FIG. The active portion is a region through which current flows when in an on state, and is a region responsible for current driving of the semiconductor device. As shown in FIG. 1, in the semiconductor device according to the first embodiment, the mesa portion 1a between adjacent trenches 2 is formed from the interface between the interlayer insulating film (second insulating film) 8 and the emitter electrode (first electrode) 9. A trench type MOS gate structure is provided which protrudes toward the emitter electrode 9 side. No contact hole by fine patterning is provided in the interlayer insulating film 8 on the mesa portion 1a, and the entire surface of the mesa portion 1a on the front side of the substrate (hereinafter referred to as the upper surface) is in contact with the emitter electrode 9. ing. Further, a portion (side surface) of the mesa portion 1 a exposed on the side wall of the trench 2 is also in contact with the emitter electrode 9.

Specifically, a trench 2 is provided on the front surface side of the n ⁻ type semiconductor substrate that becomes the n ⁻ type drift layer 1. The depth D of the trench 2 is preferably 3.0 μm or more, for example, in order to set an n ⁺ -type emitter region (second semiconductor region) 6 and a p ⁺ -type contact region 7 described later to a predetermined depth. The depth D of the trench 2 is a depth from the upper surface of the mesa portion 1 a to the bottom surface of the trench 2. Inside the trench 2, a gate insulating film (first insulating film) 3 made of, for example, an oxide film (SiO ₂ ) is provided along the inner wall of the trench 2, and polysilicon (Poly−) is formed inside the gate insulating film 3. A gate electrode 4 made of Si) is embedded. In addition, an interlayer insulating film 8 made of, for example, an oxide film (SiO ₂ ) is provided on the gate electrode 4 inside the trench 2.

  A mesa portion 1 a between adjacent trenches 2 protrudes from the interface between the interlayer insulating film 8 and the emitter electrode 9 toward the emitter electrode 9. A p-type base region (first semiconductor region) 5 is provided in the mesa portion 1 a between the adjacent trenches 2. The p-type base region 5 is provided in a region including a portion of the mesa portion 1 a that protrudes from the interface between the interlayer insulating film 8 and the emitter electrode 9 toward the emitter electrode 9. The p-type base region 5 is a region where an n-type inversion layer (channel) is formed in the vicinity of the boundary with the gate insulating film 3 provided on the sidewall of the trench 2 when a gate voltage is applied.

  The width of mesa portion 1a between adjacent trenches 2 (distance between adjacent trenches 2 (mesa width)) Lm is, for example, 3.0 μm or less, and preferably satisfies the following formula (1). The reason is that by reducing the width Lm of the mesa portion 1a to the extent that the following expression (1) is satisfied, the carrier injection efficiency on the emitter side can be increased by the IE effect, and the on-voltage can be reduced. is there. In the following formula (1), Lg is the width of the trench 2 (the width in the direction in which the trenches 2 are arranged (that is, the lateral direction in FIG. 1)).

  Lm / (Lg + Lm) <0.5 (1)

Inside the p-type base region 5, an n ⁺ -type emitter region 6 and a p ⁺ -type contact region 7 are selectively provided. The n ⁺ -type emitter region 6 and the p ⁺ -type contact region 7 are each provided in a region including a portion of the mesa portion 1a that protrudes from the interface between the interlayer insulating film 8 and the emitter electrode 9 toward the emitter electrode 9 side. . The n ⁺ -type emitter region 6 is disposed on the side of the trench 2 of the mesa portion 1 a and is in contact with the gate insulating film 3 provided along the side wall of the trench 2. The depth of the n ⁺ -type emitter region 6 is preferably shallower than the depth of the p ⁺ -type contact region 7. This is because a latch-up phenomenon caused by a parasitic pnpn thyristor can be prevented.

The p ⁺ -type contact region 7 is arranged at substantially the center between the adjacent trenches 2 so as not to contact the channel formed in the vicinity of the boundary between the p-type base region 5 and the gate insulating film 3 when a gate voltage is applied. ing. The p ⁺ -type contact region 7 has a function of maintaining a latch-up resistance. The emitter electrode 9 is provided on the entire surface of the substrate in the active portion, and an n ⁺ -type emitter is formed at a portion of the mesa portion 1a protruding from the interface between the interlayer insulating film 8 and the emitter electrode 9 toward the emitter electrode 9 side. It is in contact with region 6 and p ⁺ -type contact region 7. That is, emitter electrode 9 is in contact with n ⁺ -type emitter region 6 and p ⁺ -type contact region 7 on the upper surface of mesa portion 1a. The emitter electrode 9 is buried in a portion on the interlayer insulating film 8 inside the trench 2 and is in contact with the n ⁺ -type emitter region 6 on the side wall of the trench 2.

The thickness of the portion of the silicon (Si) portion (mesa portion 1a) between the trenches 2 that protrudes from the interface between the interlayer insulating film 8 and the emitter electrode 9 toward the emitter electrode 9 (ie, the interlayer insulation from the upper surface of the mesa portion 1a) The distance Z) to the interface between the film 8 and the emitter electrode 9 is preferably 0.1 μm or more, for example. This is because the contact resistance between the n ⁺ -type emitter region 6 and the emitter electrode 9 can be reduced. An n-type field stop layer 10 is provided on the front surface layer of the n ⁻ -type semiconductor substrate. Further, a p-type collector layer (second conductivity type semiconductor layer) 11 is provided on the surface layer on the back surface of the n ⁻ type semiconductor substrate at a position shallower than the n-type field stop layer 10 from the back surface of the substrate. The collector electrode (second electrode) 12 is in contact with the p-type collector layer 11.

Next, a method for manufacturing the semiconductor device according to the first embodiment will be described. 3 to 17 are cross-sectional views illustrating a state in the process of manufacturing the semiconductor device according to the first embodiment. 3 to 17 show the mesa portion 1a on the front side of the substrate in an enlarged manner (the same applies to FIGS. 19 to 31). First, as shown in FIG. 3, n ^- -type drift layer 1 and comprising for example n ^- prepared -type silicon substrate, for example, by heat treatment at water vapor (H ₂ O), in an atmosphere, n ^- type silicon substrate main An initial oxide film (SiO ₂ : first film) 21 is formed on the surface. Next, as shown in FIG. 4, after a resist is applied on the initial oxide film 21 to form a resist film 22, the resist film 22 is patterned into a predetermined pattern by photolithography.

Next, the initial oxide film 21 is etched using the resist film 22 as a mask, leaving the initial oxide film 21 in a portion corresponding to the formation region of the trench 2 and exposing the front surface of the substrate. At this time, the formation region of another trench 2 adjacent to the formation region of one trench 2 covered with the initial oxide film 21 is exposed without being covered with the initial oxide film 21. Next, after removing the resist film 22, for example, a nitride film (SiN: second film) 23 is deposited on the exposed substrate front surface and the initial oxide film 21. Next, as shown in FIG. 5, the nitride film 23 is etched, and a portion (side wall) left on the side surface of the initial oxide film 21 without being etched is left as a mask for trench etching described later. (Sidewall process). As a result, a nitride film 23 having a predetermined width in contact with the side surface of the initial oxide film 21 is formed on the n ⁻ type silicon substrate.

  The width of the nitride film 23 that remains on the side surface of the initial oxide film 21 without being etched is preferably, for example, 0.005 μm or more and less than 3.0 μm. The width of the nitride film 23 is the width of the silicon portion (mesa width Lm) that is left as the mesa portion 1a between the adjacent trenches 2 when the trench 2 is formed in a later step. Next, as shown in FIG. 6, the initial oxide film 21 is removed by photolithography and etching. As described above, the nitride film 23 serves as a mask for trench etching in the formation region of the adjacent trench 2 with the nitride film 23 interposed therebetween. For this reason, when forming three or more trenches 2 arranged in stripes, for example, the formation region of the trench 2 covered with the initial oxide film 21 and the trench exposed without being covered with the initial oxide film 21. The initial oxide film 21 may be patterned so that the two formation regions are alternately arranged.

Next, as shown in FIG. 7, etching 51 is performed using the remaining portion of nitride film 23 as a mask, and trench 2 having a depth D of about 0.01 μm or more and less than 7.0 μm is formed on the front surface of the n ⁻ -type silicon substrate. Form. As a result, the portion immediately below the nitride film 23 of the n ⁻ type silicon substrate remains as the mesa portion 1a. The etching 51 for forming the trench 2 may be dry etching or anisotropic etching such as wet etching using KOH (potassium hydroxide) or TMAH (tetramethylammonium hydride). Next, as shown in FIG. 8, the substrate front surface and the inner wall of the trench 2 are thermally oxidized by heat treatment, and an oxide film that becomes the gate insulating film 3 with a thickness of about 0.001 μm to 0.2 μm. (SiO ₂ ) is formed.

Next, as shown in FIG. 9, a polysilicon layer to be the gate electrode 4 is deposited so as to be embedded in the trench 2. Next, as shown in FIG. 10, CMP (chemical mechanical polishing) 52 is performed using the nitride film 23 as a polishing stopper to reduce the thickness of the gate electrode 4. Next, as shown in FIG. 11, using the nitride film 23 as a mask, the gate electrode 4 is etched 53 until the upper surface of the gate electrode 4 is lower than the upper surface of the mesa portion 1a by about 0.005 μm to 3.5 μm. To do. Next, as shown in FIG. 12, the gate electrode 4 is thermally oxidized by heat treatment, and has a thickness of, for example, about 0.002 μm to 3.5 μm so as to be thicker than the gate insulating film 3. An oxide film (SiO ₂ ) to be the interlayer insulating film 8 is formed.

  Next, a p-type impurity such as boron (B) is first ion-implanted (oblique ions) at predetermined implantation angles θ11 and θ12 with respect to the front surface of the substrate through the gate insulating film 3 above the mesa portion 1a. 24), and the p-type base region 5 is formed over the entire upper portion of the mesa portion 1a. The first ion implantation 24 includes, for example, an implantation angle θ11 of about 10 ° to 80 ° with respect to the substrate front surface, and an implantation angle of about −80 ° to −10 ° with respect to the substrate front surface. A total of two oblique ion implantations at θ12 may be used. By forming the p-type base region 5 by two oblique ion implantations at implantation angles θ11 and θ12 that are symmetric with respect to the mesa portion 1a, the depth of the p-type base region 5 can be set to the side surface side of the mesa portion 1a. It becomes shallower on the center side of the mesa portion 1a than on the side wall side of the trench 2. Thereby, the IE effect can be increased. Alternatively, the p-type base region 5 may be formed on the entire upper portion of the mesa portion 1a by introducing impurities such as boron from the sidewall of the trench 2 by plasma doping.

Next, as shown in FIG. 13, a p-type impurity such as boron is introduced into the second ion at a predetermined implantation angle θ21, θ22 with respect to the front surface of the substrate through the gate insulating film 3 above the mesa portion 1a. Implantation (oblique ion implantation) 25 is performed, and ap ⁺ -type contact region 7 is selectively formed inside the p-type base region 5. In this second ion implantation 25, for example, the first ion implantation 24 has an acceleration energy higher than that of the first ion implantation 24 for forming the p-type base region 5 and the implantation angles θ21, θ22 with respect to the front surface of the substrate. The implantation angle is larger than the implantation angles θ11 and θ12 with respect to the front surface of the substrate.

Next, as shown in FIG. 14, an n-type impurity such as arsenic (As), for example, is implanted at a predetermined implantation angle θ31, θ32 with respect to the front surface of the substrate through the gate insulating film 3 above the mesa portion 1a. A third ion implantation (oblique ion implantation) 26 is performed to selectively form an n ⁺ -type emitter region 6 inside the p-type base region 5. In this third ion implantation 26, for example, the acceleration energy is lower than that of the first ion implantation 24, and the implantation angles θ31 and θ32 with respect to the substrate front surface are set to the implantation angle θ11 with respect to the substrate front surface of the first ion implantation 24. , Θ12.

Next, as shown in FIG. 15, for example, heat treatment is performed at a temperature of about 800 ° C. to about 1100 ° C. to activate each impurity region formed in the mesa portion 1 a. In order to suppress the diffusion of impurities, the heat treatment for activating the impurities is performed, for example, by rapid annealing (RTA: Rapid Thermal Anneal) or Spike RTA (spike RTA: rapid rise in temperature within 1 second). After that, it is preferable to perform annealing (annealing for lowering the temperature without holding at a predetermined annealing temperature) or flash lamp annealing. Next, the nitride film 23 is removed by etching. Next, as shown in FIG. 16, etching is performed so that the interlayer insulating film 8 remains on the gate electrode 4, and the gate insulating film 3 covering the portion of the mesa portion 1a protruding on the interlayer insulating film 8 is removed. . As a result, the n ⁺ -type emitter region 6 and the p ⁺ -type contact region 7 of the mesa portion 1a are exposed.

Next, as shown in FIG. 17, for example, an aluminum (Al) electrode serving as the emitter electrode 9 is deposited (formed) so as to fill the trench 2 on the front surface of the substrate. As a result, an ohmic contact is formed between the emitter electrode 9 and a portion of the mesa portion 1a protruding on the interlayer insulating film 8 (that is, the n ⁺ -type emitter region 6 and the p ⁺ -type contact region 7). Thereafter, n-type field stop layer 10, p-type collector layer 11 and collector electrode 12 are formed on the back side of the substrate by a general method, thereby completing the trench IGBT shown in FIG.

In the IGBT structure of the present invention described above, the mesa portion 1a protrudes from the interface between the interlayer insulating film 8 and the emitter electrode 9 to the emitter electrode 9 side, so that the n ⁻ type drift layer 1 (n ⁻ of the mesa portion 1a). The thickness of the drift layer 1 from the boundary with the p-type base region 5 to the lower part of the mesa is reduced and the IE effect is reduced. However, the mesa can be improved to the extent that the IE effect can be improved more than the reduction of the IE effect. The width Lm of the part 1a can be reduced. FIG. 18 is a characteristic diagram showing the relationship between the on-voltage and the turn-off loss of the semiconductor device according to the first embodiment of the present invention. As shown in FIG. 18, the IGBT structure of the present invention can improve the trade-off of the on-voltage (Von) -turn-off loss (Eoff), which is an index of the power loss of the IGBT, as compared with the prior art.

As described above, according to the first embodiment, the upper surface of the mesa portion is selectively formed by projecting the mesa portion between adjacent trenches from the interface between the interlayer insulating film and the emitter electrode to the emitter electrode side. The contact hole exposed to the surface may not be provided. For this reason, a trench IGBT can be manufactured (manufactured) without performing the finest patterning for forming a narrow contact hole among a plurality of patterning processes by photolithography in the manufacturing process of the trench IGBT. it can. For this reason, even when the width of the mesa portion is narrowed to increase the IE effect, an ohmic contact between the emitter electrode and the silicon portion (n ⁺ -type emitter region and p ⁺ -type contact region) can be reliably obtained. . Therefore, a low-loss trench IGBT can be provided.

In addition, according to the first embodiment, the mesa portion that becomes a fine pattern next to the contact hole is formed using the insulating film formed on the side wall of the initial oxide film by using the sidewall process as a mask. Fine patterning for forming a mesa portion is not required. Therefore, a narrow mesa portion can be formed with high accuracy, and a low-loss trench IGBT can be manufactured. Further, according to the first embodiment, the oblique ion implantation is performed on the sidewall of the trench to form the p ⁺ -type contact region in the mesa portion between the adjacent trenches. Therefore, the acceleration energy and the dose amount of the oblique ion implantation are reduced. controlled, and to activate the p ⁺ -type contact region by fast thermal treatment at high temperature, it is possible to form the p ⁺ -type contact region of predetermined width in the central portion of the mesa portion. As a result, it is possible to prevent a reduction in latch-up resistance caused by lateral diffusion of impurities.

(Embodiment 2)
Next, the structure of the semiconductor device according to the second embodiment will be described. FIG. 19 is a perspective view of the structure of the main part of the semiconductor device according to the second embodiment. The semiconductor device according to the second embodiment is different from the semiconductor device according to the first embodiment in that the mesa portion 1a extends in a stripe shape (the depth direction in FIG. 19) and the n ⁺ -type emitter region 16 and p. ^This is a point having an IGBT structure in which ⁺ -type contact regions 17 are alternately and repeatedly arranged. That is, both n ⁺ -type emitter region 16 and p ⁺ -type contact region 17 are in contact with gate insulating film 3 provided along the sidewall of trench 2. Emitter electrode 9 is in contact with n ⁺ -type emitter region 16 and p ⁺ -type contact region 17 on the upper surface of mesa portion 1 a, and is in contact with n ⁺ -type emitter region 16 and p ⁺ -type contact region 17 on the side wall of trench 2.

Next, a method for manufacturing the semiconductor device according to the second embodiment will be described. 20 and 21 are cross-sectional views illustrating a state during the manufacture of the semiconductor device according to the second embodiment. First, the process up to forming the p-type base region 5 over the entire upper portion of the mesa portion 1a is performed by the same manufacturing process as in the first embodiment (FIGS. 3 to 12). Next, the nitride film 23 is removed by etching. Next, as shown in FIG. 20, a p-type impurity such as boron is introduced from the side wall of the trench 2 into the upper portion of the mesa portion 1a over the gate insulating film 3 by, for example, plasma doping or by ion implantation. By introducing a p-type impurity such as boron at an implantation angle of 7 ° with respect to the front surface, a p ⁺ -type contact region 17 is formed inside the p-type base region 5 over the entire upper portion of the mesa portion 1a. .

Next, as shown in FIG. 21, a resist film 27 is formed by applying a resist to the entire front surface of the substrate. Next, the resist film 27 is patterned by photolithography to expose a region where the n ⁺ -type emitter region 6 is formed. At this time, the pattern of the resist film 27 is a pattern extending in a stripe shape in a direction orthogonal to the direction in which the trench 2 extends in a stripe shape. Next, using the resist film 27 as a mask, an n-type impurity such as arsenic is introduced from the sidewall of the trench 2 by, for example, plasma doping over the gate insulating film 3 on the mesa portion 1a, or by ion implantation. By introducing an n-type impurity such as arsenic at an implantation angle of 7 ° with respect to the front surface, an n ⁺ -type emitter region 16 is selectively formed above the mesa portion 1a. At this time, the n ⁺ -type emitter region 16 is formed by reversing the p ⁺ -type contact region 17 already formed in the upper part of the mesa portion 1a with n-type impurities and inverting it to the n-type. After that, the step of activating the impurity region formed in the mesa portion 1a is performed by the same manufacturing process as in the first embodiment, thereby completing the trench type IGBT shown in FIG.

As described above, according to the second embodiment, the same effect as in the first embodiment can be obtained. Further, according to the second embodiment, an increase in the on-voltage can be suppressed by alternately arranging the n ⁺ -type emitter regions and the p ⁺ -type contact regions in the direction in which the mesa portions extend in a stripe shape. In addition, since the area of the p ⁺ -type contact region can be reduced, the saturation current can be reduced, and the short-circuit tolerance can be improved.

(Embodiment 3)
Next, the structure of the semiconductor device according to the third embodiment will be described. FIG. 22 is a cross-sectional view illustrating the structure of the main part of the semiconductor device according to the third embodiment. The semiconductor device according to the third embodiment is different from the semiconductor device according to the first embodiment in that two gate electrodes 14 electrically insulated by an interlayer insulating film 18 are provided inside the trench 2. Specifically, the gate electrode 14 is provided on the opposite side wall of the trench 2 along the side wall. Each gate electrode 14 is opposed to the mesa portion 1a (p-type base region 5 and n ⁺ -type emitter region 6) with the gate insulating film 3 interposed therebetween. In the trench 2, an interlayer insulating film 18 is embedded on the surface of the gate electrode 14 and between the two gate electrodes 14.

  Next, a method for manufacturing the semiconductor device according to the third embodiment will be described. 23 and 24 are cross-sectional views illustrating a state in the middle of manufacturing the semiconductor device according to the third embodiment. First, the manufacturing process similar to that of the first embodiment is performed until the polysilicon layer that becomes the gate electrode 14 embedded in the trench 2 is removed until the upper surface thereof is below the upper surface of the mesa portion 1a. (FIGS. 3-11). Next, as shown in FIG. 23, a sidewall 28 such as a nitride film is formed on the gate electrode 14 along the side surface of the mesa portion 1a.

  Next, as shown in FIG. 24, the gate electrode 14 is etched using the sidewall 28 as a mask, leaving a portion of the gate electrode 14 immediately below the sidewall 28. Thereby, the two gate electrodes 14 can be formed inside the trench 2 without using fine patterning. Next, an oxide film to be an interlayer insulating film 18 is formed on the gate electrode 14 so as to be embedded between the two gate electrodes by heat treatment. The method for forming the interlayer insulating film 18 is the same as in the first embodiment. Then, the trench type IGBT shown in FIG. 22 is completed by performing the process after forming the impurity region (p-type base region 5 and the like) in the mesa portion 1a by the same manufacturing process as in the first embodiment.

  As described above, according to the third embodiment, the same effect as in the first embodiment can be obtained. Further, according to the third embodiment, since the area where the gate insulating film and the gate electrode are in contact with each other along the bottom surface of the trench is reduced, the gain is multiplied by the mirror effect and functions as the input capacitance. The gate-collector capacitance can be reduced. Thereby, switching characteristics can be improved.

(Embodiment 4)
Next, the structure of the semiconductor device according to the fourth embodiment will be described with reference to FIGS. The semiconductor device according to the fourth embodiment is different from the semiconductor device according to the first embodiment in that the material of the gate insulating film 3 is higher in dielectric constant than the silicon oxide film instead of the silicon oxide film (SiO ₂ ). A high dielectric constant (High-K) material is used. Examples of the High-K material include hafnium oxide (HfO ₂ ), hafnium silicate (HfSiO), lanthanum oxide (La ₂ O ₃ ), lanthanum aluminate (LaAlO ₃ ), and cerium oxide (CeO ₂ ). In general, an IGBT can collect a large amount of electrons in a channel by thinning a gate insulating film, and can increase an electric driving force. However, it is difficult to ensure a gate breakdown voltage by thinning the gate insulating film. . Therefore, in the fourth embodiment, a High-K material is used as the material of the gate insulating film 3. In this way, by using a High-K material as the material of the gate insulating film 3, a large amount of electrons can be collected in the channel without reducing the thickness of the gate insulating film 3, so that the electric driving force can be increased. it can. Further, since the thickness of the gate insulating film 3 is not reduced, a gate breakdown voltage can be ensured.

  The manufacturing method of the semiconductor device according to the fourth embodiment is the same as the manufacturing method of the semiconductor device according to the first embodiment. Instead of the heat treatment step for forming the gate insulating film 3, the High-K that becomes the gate insulating film 3 A step of depositing a film may be performed.

  Further, when the gate insulating film 3 is replaced with an oxide film and a High-K film is used, the gate-collector capacitance increases and the switching characteristics deteriorate. Therefore, a part of the gate insulating film 3 made of an oxide film may be replaced with a High-K film made of a High-K material instead of the silicon oxide film. FIG. 25 is a cross-sectional view illustrating a structure of a main part of another example of the semiconductor device according to the fourth embodiment. Specifically, as shown in FIG. 25, a portion of the gate insulating film along the bottom surface of the trench 2 is a silicon oxide film 31, and at least a portion of the portion along the sidewall of the trench 2 is a high-K film 32. And FIG. 25 shows a case where the entire portion of the gate insulating film along the sidewall of the trench 2 is the High-K film 32. Thus, the mirror effect can be suppressed by using the silicon oxide film 31 instead of the High-K material as the portion of the gate insulating film immediately below the gate electrode 4 (on the collector electrode 12 side).

  Another example of the manufacturing method of the semiconductor device according to the fourth embodiment is the same as the manufacturing method of the semiconductor device according to the first embodiment except that a trench is used instead of the heat treatment step for forming a gate insulating film made of only an oxide film. After forming the High-K film 32 on the side walls of the second layer, a step of forming the silicon oxide film 31 on the bottom surface of the trench 2 by heat treatment may be performed. Specifically, when forming the gate insulating film composed of the silicon oxide film 31 and the High-K film 32, first, the High-K film 32 is deposited along the inner wall of the trench 2, and then the High side is formed on the sidewall of the trench 2. For example, anisotropic dry etching is performed so that the -K film 32 remains. Next, a silicon oxide film 31 is formed on the bottom surface of the trench 2 by heat treatment.

  As described above, according to the fourth embodiment, the same effect as in the first embodiment can be obtained. Further, according to the fourth embodiment, the whole or part of the gate insulating film is a High-K film, so that the electric driving force can be increased while maintaining the gate breakdown voltage.

(Embodiment 5)
Next, the structure of the semiconductor device according to the fifth embodiment will be described. FIG. 26 is a cross-sectional view illustrating the structure of the main part of the semiconductor device according to the fifth embodiment. The semiconductor device according to the fifth embodiment differs from the semiconductor device according to the first embodiment in that the thickness of at least a part of the portion of the gate insulating film 3 along the bottom surface of the trench 2 is increased. is there. Specifically, as shown in FIG. 26, at least a part of the portion of the gate insulating film 3 along the bottom surface of the trench 2 is locally oxidized (LOCOS) thicker than other portions of the gate insulating film 3. ) A film 33 is formed. The other part of the gate insulating film 3 is a part of the gate insulating film 3 along the side wall of the trench 2 and a part of the gate insulating film 3 other than the LOCOS film 33 along the bottom surface of the trench 2. . By providing the LOCOS film 33 in this way, the gate-collector capacitance can be reduced, so that the switching characteristics can be improved.

  The manufacturing method of the semiconductor device according to the fifth embodiment is the same as the manufacturing method of the semiconductor device according to the first embodiment, after forming the gate insulating film 3 and before depositing the polysilicon layer to be the gate electrode 4. A part of the portion of the gate insulating film 3 along the bottom of the trench 2 may be formed into the LOCOS film 33 by a simple LOCOS method.

  As described above, according to the fifth embodiment, the same effect as in the first embodiment can be obtained.

(Embodiment 6)
Next, the structure of the semiconductor device according to the sixth embodiment will be described. FIG. 27 is a cross-sectional view illustrating the structure of the main part of the semiconductor device according to the sixth embodiment. The semiconductor device according to the sixth embodiment is different from the semiconductor device according to the first embodiment in that a part of the gate insulating film made of a silicon oxide film (SiO ₂ ) is replaced with a silicon oxide film rather than a silicon oxide film. A low-K film made of a low dielectric constant (Low-K) material having a low dielectric constant is used. The Low-K material is, for example, silicon dioxide containing silicon (SiOC, SiOCH). Specifically, as shown in FIG. 27, a portion of the gate insulating film 3 along the bottom surface of the trench 2 is a Low-K film 34, and a portion along the sidewall of the trench 2 is a silicon oxide film 35. As described above, the portion of the gate insulating film immediately below the gate electrode 4 is not the oxide film but the Low-K film 34, so that the gate-collector capacitance can be reduced as in the fifth embodiment.

  The semiconductor device manufacturing method according to the fifth embodiment is the same as the semiconductor device manufacturing method according to the first embodiment, except that a heat treatment step for forming a gate insulating film made only of an oxide film is performed on the sidewall of the trench 2. After the silicon oxide film 35 is formed, a step of forming the Low-K film 34 on the bottom surface of the trench 2 may be performed. Specifically, when forming a gate insulating film composed of the Low-K film 34 and the silicon oxide film 35, first, the silicon oxide film 35 is formed on the inner wall of the trench 2 by heat treatment. Next, a portion of the silicon oxide film 35 along the bottom surface of the trench 2 is removed by photolithography to expose the bottom surface of the trench 2. Next, a Low-K film 34 is deposited on the bottom surface of the trench 2.

  As described above, according to the sixth embodiment, the same effects as in the first and fifth embodiments can be obtained.

(Embodiment 7)
Next, the structure of the semiconductor device according to the seventh embodiment will be described. FIG. 28 is a cross-sectional view illustrating the structure of the main part of the semiconductor device according to the seventh embodiment. The semiconductor device according to the seventh embodiment is different from the semiconductor device according to the third embodiment in that the gate electrode is provided at the boundary between the bottom of the trench 2 inside the n ⁻ type drift layer 1 via the gate insulating film 3. 14 is that a p-type region 19 is provided so as to face at least a part of 14. Specifically, as shown in FIG. 28, the p-type region 19 is provided from directly below the gate electrode 14 on one side wall side of the trench 2 to directly below the gate electrode 14 on the other side wall side of the trench 2, The gate electrode 14 and the interlayer insulating film 18 are opposed to each other through the gate insulating film 3. By providing the p-type region 19 in this way, a depletion layer extends in the n ⁻ -type drift layer 1, so that a desired breakdown voltage can be ensured.

  The manufacturing method of the semiconductor device according to the seventh embodiment is the same as the manufacturing method of the semiconductor device according to the third embodiment, after the formation of the gate insulating film 3 and before the deposition of the polysilicon layer that becomes the gate electrode 14. The step of forming the p-type region 19 in the surface layer at the bottom of the substrate may be performed. As a method of forming the p-type region 19, for example, a p-type impurity such as an implantation angle boron of about 0 ° to 7 ° with respect to the bottom surface of the trench 2 is ionized through the gate insulating film 3 on the bottom surface of the trench 2. Just inject.

  As described above, according to the seventh embodiment, the same effects as in the first and third embodiments can be obtained.

(Embodiment 8)
Next, the structure of the semiconductor device according to the eighth embodiment will be described. FIG. 29 is a cross-sectional view illustrating the structure of the main part of the semiconductor device according to the eighth embodiment. The semiconductor device according to the eighth embodiment is different from the semiconductor device according to the third embodiment in that two gate electrodes (hereinafter referred to as first gate electrodes) 14 provided along the opposite side walls of the trench 2 respectively. A plurality of second gate electrodes 41 are further provided therebetween. That is, at least three gate electrodes that are electrically insulated by the interlayer insulating film 18 are provided inside the trench 2. An interlayer insulating film 18 is buried between the first gate electrode 14 and the second gate electrode 41 and between the adjacent second gate electrodes 41.

  For example, the first and second gate electrodes 14 and 41 are arranged at predetermined intervals in a direction orthogonal to the direction in which the trench 2 extends in a stripe shape (the depth direction on the paper), and extend in a stripe shape in the direction in which the trench 2 extends in a stripe shape ing. The first gate electrode 14 contributes to gate control. The second gate electrode 41 may have a potential different from that of the first gate electrode 14. Specifically, by setting the second gate electrode 41 to a floating potential from the potential of the first gate electrode 14 to the potential of the emitter electrode 9, the second gate electrode 41 functions as a field plate and the breakdown voltage is improved. . Further, by setting the second gate electrode 41 to the same potential as the emitter electrode 9, it is possible to improve the turn-on di / dt controllability.

  The manufacturing method of the semiconductor device according to the eighth embodiment is the same as the manufacturing method of the semiconductor device according to the first embodiment, wherein the polysilicon layer deposited inside the trench 2 is etched to form two first gate electrodes 14. In the process, the polysilicon layer may be patterned so that one or more second gate electrodes 41 may be formed in addition to the two first gate electrodes 14.

  As described above, according to the eighth embodiment, the same effect as in the third embodiment can be obtained.

(Embodiment 9)
Next, a method for manufacturing a semiconductor device according to the ninth embodiment will be described. 30 and 31 are cross-sectional views illustrating a state in the middle of manufacturing the semiconductor device according to the ninth embodiment. The semiconductor device manufacturing method according to the ninth embodiment is different from the semiconductor device manufacturing method according to the first embodiment in that the surface of the substrate front surface is formed before the trench 2 is formed on the substrate front surface side. The p-type base region 15 is formed in the layer. In the ninth embodiment, the first ion implantation for forming the p-type base region 15 is performed at an implantation angle that is substantially perpendicular to the front surface of the substrate, for example. When the implantation angle of the first ion implantation is substantially perpendicular to the front surface of the substrate, the depth of the p-type base region 15 from the upper surface of the mesa portion 1a is the central portion side and the side surface side of the mesa portion 1a. Both are approximately equal.

Specifically, first, as shown in FIG. 30, n ^- -type drift layer 1 and comprising for example n ^- prepared -type silicon substrate, for example by ion implantation of boron, n ^- type silicon substrate on the front surface A p-type base region 15 is formed in the surface layer. Next, as shown in FIG. 31, etching 54 is performed using the nitride film 23 formed on the front surface of the substrate as a mask, penetrating the p-type base region 15 from the front surface of the substrate, and the n ⁻ type drift layer 1. A trench 2 reaching to is formed. As a result, the p-type base region 15 remains in the mesa portion 1 a between the adjacent trenches 2. Thereafter, the steps after forming the p ⁺ -type contact region 7 in the mesa portion 1a by oblique ion implantation (second ion implantation) are performed by the same manufacturing process as in the first embodiment, so that the trench IGBT shown in FIG. Complete.

  As described above, according to the ninth embodiment, the same effect as in the first embodiment can be obtained.

  As described above, the present invention can be variously changed. In each of the above-described embodiments, for example, the dimensions and surface concentration of each part are variously set according to required specifications. In the above-described second to sixth and ninth embodiments, the case where the present invention is applied to the IGBT structure of the first embodiment has been described as an example, but the same applies to the case where the present invention is applied to the IGBT structure of other embodiments. There is an effect. Further, in the above-described seventh and eighth embodiments, the case where the present invention is applied to the IGBT structure of the third embodiment has been described as an example, but the same effect can be obtained even when the present invention is applied to the IGBT structure of other embodiments. Play. In each embodiment, the first conductivity type is n-type and the second conductivity type is p-type. However, in the present invention, the first conductivity type is p-type and the second conductivity type is n-type. It holds.

  As described above, the semiconductor device and the method for manufacturing the semiconductor device according to the present invention are useful for power conversion devices such as inverters, power supply devices such as various industrial machines, and power semiconductor devices used for automobile igniters. is there.

1 n ⁻ type drift layer 1 a mesa 2 trench 3 gate insulating film 4 gate electrode 5 p type base region 6 n ⁺ type emitter region 7 p ⁺ type contact region 8 interlayer insulating film 9 emitter electrode 10 n type field stop layer 11 p Type collector layer 12 collector electrode Lg width of trench Lm width of mesa portion

Claims (25)

A plurality of trenches provided on the front surface of the first conductivity type semiconductor substrate;
A first insulating film provided inside the trench along the inner wall of the trench;
A gate electrode provided inside the first insulating film inside the trench;
A first semiconductor region of a second conductivity type provided in a mesa portion between adjacent trenches and facing the gate electrode through the first insulating film provided along a side wall of the trench;
A second semiconductor region of a first conductivity type provided inside the first semiconductor region;
A second insulating film provided on the gate electrode inside the trench;
A first electrode in contact with the first semiconductor region and the second semiconductor region;
A second conductivity type semiconductor layer provided on the back surface of the semiconductor substrate;
A second electrode in contact with the second conductivity type semiconductor layer;
With
An end of the mesa portion on the first electrode side protrudes from the interface between the second insulating film and the first electrode to the first electrode side,
The first electrode is in contact with the entire surface of the protruding portion of the mesa portion and is connected to the first semiconductor region and the second semiconductor region. The mesa portion has a width of 3.0 μm or less,
2. The semiconductor device according to claim 1, wherein Lm / (Lg + Lm) <0.5 is satisfied when the width of the mesa portion is Lm and the width of the gate electrode is Lg.   3. The thickness of a portion of the mesa portion protruding from the interface between the second insulating film and the gate electrode toward the first electrode is 0.1 μm or more. Semiconductor device.   The depth of the said trench is 3.0 micrometers or more, The semiconductor device as described in any one of Claims 1-3 characterized by the above-mentioned.   5. The semiconductor device according to claim 1, wherein a depth of the first semiconductor region is shallower on a central portion side of the mesa portion than on a side surface side of the mesa portion.   The semiconductor device according to claim 1, wherein a plurality of the gate electrodes that are electrically insulated by the second insulating film are provided inside the trench.   The semiconductor device according to claim 6, wherein at least one of the plurality of gate electrodes has a potential different from that of the other gate electrodes.   The semiconductor device according to claim 1, wherein the plurality of trenches are arranged in a stripe shape.   The first semiconductor region and the second semiconductor region are alternately and repeatedly arranged in a direction perpendicular to a direction in which the trench extends in a stripe shape in a protruding portion of the mesa portion. 8. The semiconductor device according to 8.   The semiconductor device according to claim 1, wherein the first insulating film is an insulating film having a dielectric constant higher than that of an oxide film.   The first insulating film has an oxide film along a bottom surface and a side wall, and at least a part of a portion provided along the side wall is made of an insulating film having a dielectric constant higher than that of the oxide film. Item 10. The semiconductor device according to any one of Items 1 to 9.   The first insulating film includes an oxide film along a bottom surface and a side surface, and at least a part of a portion provided along the bottom surface is formed of an insulating film having a dielectric constant lower than that of the oxide film. Item 10. The semiconductor device according to any one of Items 1 to 9.   2. The first insulating film according to claim 1, wherein a thickness of at least a part of a portion provided along a bottom surface of the trench is larger than a thickness of a portion provided along a side wall of the trench. The semiconductor device as described in any one of -9.   14. The semiconductor device according to claim 1, further comprising a third semiconductor region of a second conductivity type provided in a surface layer of a portion of the semiconductor substrate exposed at a bottom surface of the trench. Semiconductor device. A first step of selectively forming a first film on a front surface of a first conductivity type semiconductor substrate;
A second step of forming a second film on the front surface of the semiconductor substrate and the first film;
A third step of leaving a portion of the second film on the front surface of the semiconductor substrate in contact with a side surface of the first film with a predetermined width;
A fourth step of removing the first film after the third step;
After the fourth step, a fifth step of forming a plurality of trenches on the front surface of the semiconductor substrate using the second film as a mask;
A sixth step of forming a first insulating film in the trench along the inner wall of the trench;
A seventh step of forming a gate electrode inside the first insulating film inside the trench;
Forming a second conductive type first semiconductor region in a mesa between adjacent trenches so as to face the gate electrode through the first insulating film provided along the sidewall of the trench; 8 steps,
A ninth step of forming a second semiconductor region of the first conductivity type inside the first semiconductor region;
A tenth step of forming a second insulating film on the gate electrode by heat treatment;
After the tenth step, an eleventh step of forming a first electrode in contact with the first semiconductor region and the second semiconductor region;
After the eleventh step, a twelfth step of forming a second conductivity type semiconductor layer on the back surface of the semiconductor substrate;
A thirteenth step of forming a second electrode in contact with the second conductivity type semiconductor layer;
Including
In the third step, the second film is etched, leaving a portion of the second film that remains on the side surface of the first film without being etched,
In the seventh step, the gate electrode is formed such that the surface of the gate electrode is positioned below the surface of the mesa portion,
In the eighth step, the first semiconductor region is formed in a region including a protruding portion of the mesa portion,
In the ninth step, the second semiconductor region is formed in a region including a protruding portion of the mesa portion,
In the eleventh step, the first electrode in contact with the entire surface of the protruding portion of the mesa portion is formed. The seventh step includes
A deposition step of depositing the gate electrode;
A polishing step of polishing the gate electrode;
An etching step of etching the gate electrode after the polishing step,
16. The semiconductor device according to claim 15, wherein the thickness of the gate electrode is reduced by the polishing step and the etching step so that the surface of the gate electrode is positioned below the surface of the mesa portion. Manufacturing method.   17. The method of manufacturing a semiconductor device according to claim 16, wherein, in the polishing step, a portion of the gate electrode above the surface of the second film is polished using the second film as a polishing stopper.   18. The method of manufacturing a semiconductor device according to claim 16, wherein in the etching step, the gate electrode is etched using the second film as a mask. A first step of forming a plurality of trenches on a front surface of a first conductivity type semiconductor substrate;
A second step of forming a first insulating film in the trench along the inner wall of the trench;
A third step of forming a gate electrode inside the first insulating film inside the trench;
Forming a second conductive type first semiconductor region in a mesa between adjacent trenches so as to face the gate electrode through the first insulating film provided along the sidewall of the trench; 4 steps,
A fifth step of forming a second semiconductor region of the first conductivity type inside the first semiconductor region;
A sixth step of forming a second insulating film on the gate electrode by heat treatment;
After the sixth step, a seventh step of forming a first electrode in contact with the first semiconductor region and the second semiconductor region;
After the seventh step, an eighth step of forming a second conductivity type semiconductor layer on the back surface of the semiconductor substrate;
A ninth step of forming a second electrode in contact with the second conductivity type semiconductor layer;
Including
In the third step, the gate electrode is formed so that the surface of the gate electrode is positioned below the surface of the mesa portion,
In the fourth step, by introducing a second conductivity type impurity from the sidewall of the trench by using an ion implantation method or a plasma doping method, the first semiconductor region is formed in a region including the protruding portion of the mesa portion. Forming,
In the fifth step, the second semiconductor region is formed in a region including the protruding portion of the mesa portion by introducing a first conductivity type impurity from the sidewall of the trench using an ion implantation method or a plasma doping method. Forming,
In the seventh step, the first electrode in contact with the entire surface of the protruding portion of the mesa portion is formed. In the fourth step and the fifth step,
When using ion implantation,
The semiconductor device manufacturing method according to claim 19, wherein a second conductivity type impurity is introduced into a sidewall of the trench from an oblique direction of 10 ° to 80 ° with respect to the front surface of the semiconductor substrate. Method. The fourth step includes
When using ion implantation,
First ion implantation for ion-implanting a second conductivity type impurity into a side wall of the trench forming one side surface of the mesa portion from an oblique direction of 10 ° to 80 ° with respect to the front surface of the semiconductor substrate Process,
A second conductivity type impurity is ion-implanted into the side wall of the trench forming the other side surface of the mesa portion from a diagonal direction of −80 ° to −10 ° with respect to the front surface of the semiconductor substrate. 21. The method of manufacturing a semiconductor device according to claim 20, further comprising two ion implantation steps including an ion implantation step. After the fifth step, before the sixth step, further includes a heat treatment step of activating the first semiconductor region and the second semiconductor region by heat treatment,
The method for manufacturing a semiconductor device according to any one of claims 19 to 21, wherein in the heat treatment step, a heat treatment is performed at a temperature of 800 ° C to 1100 ° C within 1 second.   23. The method of manufacturing a semiconductor device according to claim 22, wherein in the heat treatment step, spike high-speed annealing or flash lamp annealing is performed as the heat treatment.   After the sixth step and before the seventh step, the first insulating film is locally oxidized by a heat treatment, and the thickness of a part of the first insulating film is changed to another thickness of the first insulating film. The method for manufacturing a semiconductor device according to claim 15, further comprising a step of making the thickness thicker than a thickness of the portion.   After the second step and before the third step, the first insulating film is locally oxidized by a heat treatment, and the thickness of a part of the first insulating film is changed to another thickness of the first insulating film. 24. The method of manufacturing a semiconductor device according to claim 19, further comprising a step of making the thickness thicker than a thickness of the portion.

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