JP2016039626A - Semiconductor device, power source supply control circuit and power source supply control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption.SOLUTION: A processing circuit 2 performs processing which is based on signals supplied from a signal supply source 5 at a plurality of different timings. A switch SW1 switches the on-off of a power source of the processing circuit 2. A clock signal generation circuit 3 generates a clock signal. On receipt of the signal from the signal supply source 5, a control circuit 4 controls the switch SW1 so as to turn on the power source in synchronization with the clock signal independently of a reception timing of the signal, and thereby, reduces the number of times of turning on the power source.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device, a power supply control circuit, and a power supply control method.

  A sensor network in which a plurality of sensors are networked wirelessly is known. In the sensor network, various data detected by the sensors are transmitted as sensor signals to the management device via the relay device.

In order to save power on the relay device side, there is a technique for turning on and off the power in synchronization with a sensor that repeats a sleep state and an active state.
In the wireless communication system, there is a technique in which the relay station performs an event-driven operation that starts its own activation when a connection request from a wireless terminal is detected.

JP 2010-206724 A JP 2009-246508 A

  For example, in order to save power, a device that receives a signal from a signal supply source such as a sensor turns on the power of a circuit that performs processing based on the signal triggered by the reception, and the circuit performs processing based on the signal. It is conceivable to turn off the power after the operation.

  However, when the number of receptions of signals supplied at various timings, such as sensor signals, increases, the frequency of turning on (and turning off) the power increases, and charging and discharging are repeated many times in circuits included in the apparatus. As a result, power consumption increases.

  According to one aspect of the invention, a processing circuit that performs processing based on signals supplied from a signal supply source at a plurality of different timings, a switch that switches on and off the power of the processing circuit, and clock signal generation that generates a clock signal There is provided a semiconductor device comprising: a circuit; and a control circuit that controls the switch so as to turn on the power supply in synchronization with the clock signal regardless of the reception timing of the signal when the signal is received. The

  According to another aspect of the invention, a clock signal generation circuit that generates a clock signal and a power source for a processing circuit that performs processing based on the signal when receiving signals supplied from the signal supply source at a plurality of different timings And a control circuit that turns on in synchronization with the clock signal regardless of the reception timing of the signal.

  According to another aspect of the invention, when the clock signal generation circuit generates a clock signal and the control circuit receives signals supplied from the signal supply source at a plurality of different timings, the processing based on the signal is performed. A power supply control method is provided in which the power of a processing circuit to be performed is turned on in synchronization with the clock signal regardless of the reception timing of the signal.

  According to the disclosed semiconductor device, power supply control circuit, and power supply control method, power consumption can be reduced.

It is a figure which shows an example of the semiconductor device of 1st Embodiment. It is a figure which shows an example of the semiconductor device of 2nd Embodiment. It is a figure which shows an example of a control circuit. It is a timing chart which shows operation | movement of an example of a control signal generation part. 6 is a timing chart illustrating an example of a method for controlling the power supply of a processing circuit using a semiconductor device. It is a figure which shows the comparative example of a semiconductor device. It is a timing chart which shows an example of the power supply control method of the processing circuit by the semiconductor device of a comparative example. It is a figure which shows an example of the semiconductor device of 3rd Embodiment. It is a figure which shows an example of a control part. It is a figure which shows the example of a setting of a priority flag. It is a figure which shows an example of write-in data. It is a figure explaining an example of operation | movement of CAM and a down counter at the time of RE state. It is a figure which shows an example of the data of the sensor signal read from a memory | storage part and output to a processing circuit in the RE state. 12 is a timing chart illustrating an example of signals of respective parts of the semiconductor device according to the third embodiment during a write operation. 12 is a timing chart illustrating an example of signals of respective parts of the semiconductor device according to the third embodiment during a read operation; It is a flowchart which shows the flow of an example process at the time of write-in operation | movement. It is a flowchart which shows the flow of an example at the time of read-out operation | movement. It is a figure which shows an example of the control part in the semiconductor device of 4th Embodiment. It is a figure which shows the example of a setting of an interrupt flag. It is a figure which shows an example of write-in data. It is a figure explaining an example of operation | movement of CAM and a down counter at the time of RE state. It is a figure which shows an example of the data of the sensor signal read from a memory | storage part and output to a processing circuit in the RE state. 10 is a timing chart illustrating an example of signals of respective parts of a semiconductor device according to a fourth embodiment during a write operation. 12 is a timing chart illustrating an example of signals of respective parts of the semiconductor device according to the fourth embodiment during a read operation; It is a flowchart which shows the flow of an example process at the time of write-in operation | movement. It is a flowchart which shows the flow of an example at the time of read-out operation | movement.

Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a diagram illustrating an example of the semiconductor device according to the first embodiment.

  The semiconductor device 1 includes a processing circuit 2, a switch SW1, a clock signal generation circuit 3, and a control circuit 4. The clock signal generation circuit 3 and the control circuit 4 function as a power supply control circuit 1 a that controls power supply to the processing circuit 2.

  The processing circuit 2 performs processing based on signals (hereinafter referred to as sensor signals) supplied from a signal supply source (hereinafter referred to as sensors) 5 at a plurality of different timings. For example, when the semiconductor device 1 is used as a relay device in a sensor network, the processing circuit 2 performs a process of transferring a sensor signal to another device.

  The switch SW1 is connected between the power supply and the processing circuit 2, and switches the power supply of the processing circuit 2 on and off. The switch SW1 switches on / off the power supply of the processing circuit 2 based on a switch control signal output from the control circuit 4.

  The clock signal generation circuit 3 generates a clock signal. For example, the control circuit 4 obtains the reception frequency from the number of receptions of the sensor signal in a predetermined period in advance, and sends the clock signal to the clock signal generation circuit 3 so that the frequency of turning on the processing circuit 2 is less than the reception frequency. The period may be set.

  The control circuit 4 controls on / off of the switch SW1. In the semiconductor device 1 of the present embodiment, when the control circuit 4 receives the sensor signal, the control circuit 4 switches so as to turn on the processing circuit 2 in synchronization with the clock signal regardless of the reception timing of the sensor signal. SW1 is controlled. For example, the control circuit 4 generates a switch control signal synchronized with the clock signal, and controls the switch SW1 with the switch control signal.

(Operation example of semiconductor device)
Hereinafter, an operation example of the semiconductor device 1 will be described.
A timing chart showing an example of a power supply control method of the processing circuit 13 by the semiconductor device 1 is shown on the lower side of FIG. The timing chart shows examples of clock signals, sensor signals, and switch control signals. When the switch control signal is “1”, the switch SW1 is turned on and the processing circuit 2 is turned on.

  In the example of FIG. 1, it is shown that sensor signals are output at timings t1 and t2. Even if the control circuit 4 receives the sensor signal at timings t1 and t2, the control circuit 4 does not set the switch control signal to “1” but maintains “0”. As a result, the switch SW1 remains off, and the processing circuit 2 maintains the off state.

  At timing t3, the clock signal rises to “1”. The control circuit 4 raises the switch control signal to “1” in synchronization with the rise of the clock signal. As a result, the switch SW1 is turned on and the processing circuit 2 is turned on. When the power is on, the processing circuit 2 performs processing based on the sensor signal output twice at timings t1 and t2.

  In addition, although illustration is abbreviate | omitted in FIG. 1, a sensor signal is memorize | stored in the memory | storage part (refer FIG. 2) mentioned later. The storage unit can store the sensor signal even when the processing circuit 2 is turned off even when the processing circuit 2 is turned off. Therefore, when the power supply is turned on, the processing circuit 2 performs processing based on the sensor signal stored in the storage unit.

  When the switch control signal falls to “0” at timing t4, the switch SW1 is turned off and the processing circuit 2 is turned off. Note that the pulse width of the switch control signal is appropriately set according to the length of processing based on the sensor signal, for example.

The sensor signal is output again at timings t5, t6, and t7, but the switch control signal remains “0”.
When the clock signal rises to “1” at timing t8, the control circuit 4 raises the switch control signal to “1” in synchronization with the rise of the clock signal. As a result, the switch SW1 is turned on and the processing circuit 2 is turned on. When the power is on, the processing circuit 2 performs processing based on the sensor signal output three times at timings t5 to t7.

  As described above, when the semiconductor device 1 receives the sensor signal from the power source of the processing circuit 2 that performs processing based on the sensor signal supplied from the sensor 5 at various timings, instead of the reception timing of the sensor signal, Turns on in synchronization with the internally generated clock signal. Therefore, the processing circuit 2 is not turned on each time a sensor signal is output, and the number of times the processing circuit 2 is turned on (and off) can be reduced. Thereby, the power consumption accompanying charging / discharging in the processing circuit 2 that occurs when the power supply of the processing circuit 2 is switched on and off can be reduced, and the power consumption of the semiconductor device 1 can be reduced.

(Second Embodiment)
FIG. 2 is a diagram illustrating an example of a semiconductor device according to the second embodiment.
The semiconductor device 10 includes reception units 11A, 11B, and 11C, a storage unit 12, a processing circuit 13, a switch SW2, a clock signal generation circuit 14, and a control circuit 15. The clock signal generation circuit 14 and the control circuit 15 function as a power supply control circuit 10 a that controls power supply to the processing circuit 13.

  Each of the receiving units 11A to 11C receives sensor signals transmitted wirelessly from the sensors 5A, 5B, and 5C outside the semiconductor device 10, performs demodulation processing, A / D (Analog / Digital) conversion processing, and the like. The data is output to the storage unit 12 and the control circuit 15.

  The receiving units 11A to 11C may be a single circuit instead of a plurality, and sensor signals from the sensors 5A to 5C after processing may be divided and supplied to the storage unit 12 and the control circuit 15.

  The storage unit 12 holds sensor signals (hereinafter referred to as sensor signals A, B, and C) processed by the receiving units 11A, 11B, and 11C. The storage unit 12 is also in the on state when the processing circuit 13 is in the off state.

  When the power supply is turned on, the processing circuit 13 performs processing based on the sensor signals A to C held in the storage unit 12 using power supplied from the power supply via the switch SW2. For example, when the semiconductor device 10 is used as a relay device in a sensor network, the processing circuit 13 performs processing for transferring the sensor signals A to C to other devices. Further, when the semiconductor device 10 is used as a management device in a sensor network, the processing circuit 13 uses information represented by sensor signals A to C (for example, environmental information such as temperature and humidity, and sensors 5A to 5C are humans). If it is attached to a heart rate, pulse, etc.). The processing circuit 13 may perform processing for transmitting the analysis result or the like to another device.

The switch SW2 is connected between the power supply and the processing circuit 13, and switches on / off the power supply of the processing circuit 13 based on a switch control signal supplied from the control circuit 15.
The clock signal generation circuit 14 generates a clock signal. The period of the clock signal is appropriately set so that, for example, the frequency with which the processing circuit 13 is turned on is less than the frequency with which the sensors 5A to 5C output the sensor signals A to C. For example, the control circuit 15 obtains the reception frequency from the number of receptions of the sensor signals A to C in a certain period in advance, and the clock signal generation circuit 14 so that the frequency of turning on the processing circuit 2 is less than the reception frequency. The period of the clock signal may be set to. Further, since the larger the capacity of the storage unit 12 is, the more sensor signals A to C can be held, the cycle of the clock signal may be longer.

  Note that a clock signal generation circuit (not shown) in the processing circuit 13 may be used as the clock signal generation circuit 14 when it is desired to synchronize the power-on timing of the processing circuit 13 with the internal clock of the processing circuit 13. Further, the clock signal generation circuit 14 may divide the internal clock signal of the processing circuit 13 and output it as the clock signal CK.

  When the control circuit 15 receives at least one of the sensor signals A to C, the control circuit 15 turns on the processing circuit 13 in synchronization with a clock signal CK, which will be described later, regardless of the reception timing of the sensor signals A to C. The switch SW2 is controlled by the switch control signal.

  In addition, the control circuit 15 switches so that the power of the processing circuit 13 is turned off when there is no output of the sensor signals A, B, and C during one cycle immediately before the transition timing of the clock signal CK described later. SW2 is controlled.

The sensors 5A to 5C are located outside the semiconductor device 10 and communicate with the semiconductor device 10 wirelessly. The number of sensors is not particularly limited to this number.
(Example of control circuit)
Hereinafter, an example of the control circuit 15 will be described.

FIG. 3 is a diagram illustrating an example of the control circuit.
The control circuit 15 includes a delay circuit 16, a waveform shaping circuit 17, control signal generation units 18A, 18B, and 18C, and an OR circuit 19.

The delay circuit 16 delays the clock signal CK and outputs the delayed clock signal CKd to the waveform shaping circuit 17 and the control signal generators 18A to 18C.
The waveform shaping circuit 17 shapes the waveform by adjusting the duty ratio of the delayed clock signal CKd output from the delay circuit 16, further delays the shaped waveform, and outputs the delayed waveform to the control signal generators 18A to 18C. .

  Based on the sensor signal A input from the reception unit 11A, the clock signal CK, the delayed clock signal CKd, and the output of the waveform shaping circuit 17, the control signal generation unit 18A performs an OR circuit on the signal “1” or “0”. 19 output.

  Based on the sensor signal B input from the receiving unit 11B, the clock signal CK, the delayed clock signal CKd, and the output of the waveform shaping circuit 17, the control signal generation unit 18B performs an OR circuit on the signal “1” or “0”. 19 output.

  Based on the sensor signal C input from the receiving unit 11C, the clock signal CK, the delayed clock signal CKd, and the output of the waveform shaping circuit 17, the control signal generating unit 18C performs an OR circuit on the signal “1” or “0”. 19 output.

The OR circuit 19 performs an OR operation on the signals output from the control signal generators 18A to 18C, and outputs the OR operation result to the switch SW2 as a switch control signal.
Hereinafter, an example of the control signal generators 18A to 18C will be described using the control signal generator 18A. The other control signal generators 18B and 18C can be realized by a similar circuit.

The control signal generator 18A includes an FF (flip flop) 20, an inverter circuit 21, a NOR circuit 22, an FF 23, a clocked inverter circuit 24, and a NOR circuit 25.
The FF 20 is a set / reset type FF, the set terminal S is connected to the receiving unit 11A, the reset terminal R is connected to the output of the waveform shaping circuit 17, and the output terminal Q is connected to the input of the inverter circuit 21. ing.

The inverter circuit 21 inverts the value output from the FF 20 and outputs the result to the NOR circuit 22.
The NOR circuit 22 performs a NOR operation on the value output from the inverter circuit 21 and the clock signal CK, and outputs the operation result to the FF 23.

  The FF 23 is a set / reset type FF, the set terminal S is connected to the output of the NOR circuit 22, the reset terminal R is connected to the output of the delay circuit 16, and the output terminal Q is an input of the clocked inverter circuit 24. It is connected to the.

  The clocked inverter circuit 24 includes an inverter circuit 26 and transistors T1, T2, T3, and T4. The clocked inverter circuit 24 is activated when the input clock signal CK is “1”.

The inverter circuit 26 inverts the value of the clock signal CK and outputs it to the gate of the transistor T1.
The transistors T1 and T2 are p-channel transistors, and the transistors T3 and T4 are n-channel transistors.

  The gate of the transistor T1 is connected to the output of the inverter circuit 26, the gate of the transistor T4 is connected to the output of the clock signal generation circuit 14, and the gates of the transistors T2 and T3 are connected to the output terminal Q of the FF23.

  One input / output terminal (source) of the transistor T1 is connected to a power source, and the other input / output terminal (drain) of the transistor T1 and one input / output terminal (source) of the transistor T2 are connected. The other input / output terminal (drain) of the transistor T2 and one input / output terminal (drain) of the transistor T3 are connected to each other, and further connected to the input of the NOR circuit 25. The other input / output terminal (source) of the transistor T3 is connected to one input / output terminal (drain) of the transistor T4, and the other input / output terminal (source) of the transistor T4 is grounded.

  The NOR circuit 25 performs a NOR operation on the value output from the clocked inverter circuit 24 and the delayed clock signal CKd output from the delay circuit 16 and outputs the operation result to the OR circuit 19.

(Operation example of control signal generator)
Hereinafter, an operation example of the control signal generation unit 18A will be described.
FIG. 4 is a timing chart illustrating an example of the operation of the control signal generation unit.

  FIG. 4 shows an example of the clock signal CK, the delayed clock signal CKd, the output of the waveform shaping circuit 17, the sensor signal A, the output of the FF 20, the output of the NOR circuit 22, the output of the FF 23, and the output of the NOR circuit 25. ing.

It is assumed that the output of the clocked inverter circuit 24 is “1” immediately before the timing t10.
In the example of FIG. 4, the sensor signal A that repeats “1” and “0” at a predetermined cycle is output at timing t10. When the sensor signal A rises to “1”, the output of the FF 20 also rises to “1”. Further, the output of the inverter circuit 26 falls to “0” in response to “1” of the output of the FF 20. At this time, since the clock signal CK is “0”, the output of the NOR circuit 22 rises to “1”. Further, in response to the output “1” of the NOR circuit 22, the output of the FF 23 also rises to “1”. At this time, the transistor T2 of the clocked inverter circuit 24 is turned off and the transistor T3 is turned on, but the transistor T4 remains off, so that the output of the clocked inverter circuit 24 is in a floating state, and the previous value “1” is set. Hold. Therefore, the output of the NOR circuit 25 remains “0”.

  When the clock signal CK rises to “1” at timing t11, the output of the NOR circuit 22 falls to “0”. Furthermore, since the clocked inverter circuit 24 is activated, “0” obtained by inverting the output “1” of the FF 23 is input to the NOR circuit 25. At this time, since the delayed clock signal CKd is “0”, the output of the NOR circuit 25 rises to “1”. As a result, “1” is output from the control signal generator 18 </ b> A to the OR circuit 19.

  When the delayed clock signal CKd rises to “1” at timing t12, the FF 23 is reset and the output of the FF 23 falls to “0”. As a result, the output of the clocked inverter circuit 24 becomes “1”, and the output of the NOR circuit 25 falls to “0”. Therefore, “0” is output to the OR circuit 19 from the control signal generator 18A.

When the output of the waveform shaping circuit 17 rises to “1” at timing t13, the FF 20 is reset and the output of the FF 20 falls to “0”.
When the output of the waveform shaping circuit 17 falls to “0” at timing t14, the reset of the FF 20 is released.

At timing t15, the clock signal CK falls to “0”. As a result, the clocked inverter circuit 24 is deactivated.
When the delayed clock signal CKd falls to “0” at timing t16, the reset of the FF 23 is released.

  At the next rising timing t17 of the clock signal CK, there is no output of the sensor signal A during the immediately preceding cycle (timing t11 to t16). Therefore, the outputs of the FFs 20 and 23 remain “0”. When the clock signal CK becomes “1”, the clocked inverter circuit 24 becomes active, performs an inverting operation, and outputs “1”. As a result, the output of the NOR circuit 25 remains “0”, and the output from the control signal generator 18A to the OR circuit 19 remains “0”.

As described above, when there is no output from the sensor signal A during one cycle immediately before the clock signal CK, the output from the control signal generator 18A to the OR circuit 19 is “0”.
Note that the sensor signal A may be output again between the fall of the output of the NOR circuit 25 to “0” (timing t12) and the fall of the output of the FF 20 to “0” (timing t13). is there. In such a case, even if the sensor signal A is captured by the FF 20, the output of the waveform shaping circuit 17 becomes “1” at the timing t 13, so that the FF 20 is reset and the output of the FF 20 falls to “0”. . Therefore, even when the clock signal CK rises next time, the output of the NOR circuit 25 (the output of the control signal generator 18A) does not become “1”. At this time, if the outputs of the other control signal generators 18B and 18C are also “0”, the switch control signal output from the OR circuit 19 remains “0”, and the power supply of the processing circuit 13 is not turned on. .

  However, even in such a case, the sensor signal A output at this time is held in the storage unit 12, and the held sensor signal A is then sent to the sensor signals A˜ at another timing. Processing is performed when the power of the processing circuit 13 is turned on due to the occurrence of C.

  The operation as described above is similarly performed for the control signal generation units 18B and 18C. The OR circuit 19 sets the switch control signal to “1” when any one of the outputs of the control signal generators 18A to 18C becomes “1”.

(Operation example of semiconductor device)
Hereinafter, an operation example of the semiconductor device 10 will be described.
FIG. 5 is a timing chart illustrating an example of a power supply control method for a processing circuit using a semiconductor device. The timing chart shows examples of clock signals, sensor signals, and switch control signals.

  When the switch control signal is “1”, the switch SW2 is turned on, and the processing circuit 13 is turned on. In FIG. 4, the sensor signal A is a signal that repeats “1” and “0”. However, in FIG. 5, the illustration is simplified and is simply expressed as a signal “1”.

  In the example shown in FIG. 5, sensor signals A and C are output at timings t20 and t21. At this time, each input of the OR circuit 19 is maintained at “0” by the operation of the control circuit 15 described above, so that the switch control signal output from the OR circuit 19 remains “0”. Thereby, the power supply of the processing circuit 13 is maintained in the off state, and the sensor signals A and C are stored in the storage unit 12.

  At timing t22, the clock signal CK rises to “1”. Since the sensor signals A and C are output during one cycle immediately before the transition timing of the clock signal CK, “1” is ORed from the control signal generators 18A and 18C by the operation of the control circuit 15 described above. It is output to the circuit 19. Therefore, the switch control signal becomes “1”, and the power supply of the processing circuit 13 is turned on.

Thereby, the processing circuit 13 reads the sensor signals A and C stored in the storage unit 12 and performs processing based on the sensor signals A and C.
When the switch control signal becomes “0” at timing t23, the processing circuit 13 is turned off.

  When the clock signal CK rises to “1” again at the timing t24, the sensor signals A to C are not output during one cycle (timing t22 to t24) immediately before the transition timing of the clock signal CK. Therefore, the outputs from the control signal generators 18A to 18C to the OR circuit 19 are all “0”. As a result, the switch control signal remains “0”, and the power of the processing circuit 13 remains off.

  As described above, when there is no output of the sensor signals A to C from the sensors 5A to 5C during one cycle immediately before the transition timing of the clock signal CK, even if the clock signal CK rises to “1”, the processing circuit The switch SW2 is controlled so that the power supply 13 is turned off.

  The sensor signal A is output at timing t25, the sensor signal B is output at timings t26 and t27, and the sensor signal C is output at timing t28. At this time, each input of the OR circuit 19 is maintained at “0” by the operation of the control circuit 15 described above, so that the switch control signal output from the OR circuit 19 remains “0”. Thereby, the power supply of the processing circuit 13 is maintained in the OFF state, and the sensor signals A, B, and C are stored in the storage unit 12.

  At timing t29, the clock signal CK rises to “1”. Since the sensor signals A, B, and C are output during one cycle immediately before the transition timing of the clock signal CK, the operation of the control circuit 15 causes the control signal generators 18A, 18B, and 18C to “ 1 ″ is output to the OR circuit 19. Therefore, the switch control signal becomes “1”, and the power supply of the processing circuit 13 is turned on.

Thereby, the processing circuit 13 reads the sensor signals A to C stored in the storage unit 12 and performs processing based on the sensor signals A to C.
Hereinafter, before describing the effects of the semiconductor device 10 of the present embodiment, an example of an event-driven semiconductor device that turns on the power whenever a sensor signal is received will be described as a comparative example.

(Comparative example)
FIG. 6 is a diagram illustrating a comparative example of a semiconductor device.
The semiconductor device 30 includes receiving units 31A, 31B, and 31C, a processing circuit 32, an OR circuit 33, and a switch SW3.

  The receiving units 31A, 31B, and 31C receive sensor signals wirelessly transmitted from the sensors 5A, 5B, and 5C outside the semiconductor device 30, respectively, perform demodulation processing, A / D conversion processing, and the like, and perform processing circuit 32. And output to the OR circuit 33.

  Similar to the processing circuit 13 of the second embodiment, when the power is turned on, the processing circuit 32 is output from the receiving units 31A, 31B, and 31C using power supplied from the power supply via the switch SW3. Processing based on the sensor signals A to C is performed.

The OR circuit 33 performs an OR operation on the sensor signals A to C output from the receiving units 31A, 31B, and 31C, and outputs the operation result to the switch SW3 as a switch control signal.
The switch SW3 is connected between the power supply and the processing circuit 32, and switches the power supply of the processing circuit 32 on and off. The switch SW3 switches on / off the power supply of the processing circuit 32 based on, for example, a switch control signal supplied from the OR circuit 33.

(Operation example of comparative example)
Hereinafter, an operation example of the semiconductor device 30 will be described.
FIG. 7 is a timing chart illustrating an example of a power supply control method for a processing circuit using a semiconductor device of a comparative example. The timing chart shows an example of sensor signals and switch control signals.

  In the example shown in FIG. 7, the sensor signal A is output at timing t30. The sensor signal A is input to the OR circuit 33, the switch control signal becomes “1”, and the processing circuit 32 is turned on. Thereby, the processing circuit 32 performs processing based on the sensor signal A. Note that the switch control signal transitions to “0” after maintaining “1” for a predetermined period even when the output of the sensor signal A is stopped by a delay circuit or the like, for example.

  At timing t31, the sensor signal C is output. The sensor signal C is input to the OR circuit 33, the switch control signal becomes “1”, and the processing circuit 32 is turned on. Thereby, the processing circuit 32 performs processing based on the sensor signal C.

  At timing t32, the sensor signal A is output. The sensor signal A is input to the OR circuit 33, the switch control signal becomes “1”, and the processing circuit 32 is turned on. Thereby, the processing circuit 32 performs processing based on the sensor signal A.

  At timing t33, the sensor signal B is output. This sensor signal B is input to the OR circuit 33, the switch control signal becomes “1”, and the processing circuit 32 is turned on. Thereby, the processing circuit 32 performs processing based on the sensor signal B.

Hereinafter, similarly, each time the sensor signals A to C are output, the switch control signal becomes “1”, and the power supply of the processing circuit 32 is turned on.
In such a semiconductor device 30, the processing circuit 32 is turned on and off each time the sensor signals A to C are received. Therefore, in the semiconductor device 30, the more frequently the sensor signals A to C are received, the more frequently the processing circuit 32 is turned on and off. When the frequency of switching on / off of the power supply of the processing circuit 32 increases, the power consumption accompanying charging / discharging in the processing circuit 32 increases, and the power consumption of the semiconductor device 30 increases.

  On the other hand, in the semiconductor device 10 according to the second embodiment, even when there are a plurality of sensors and sensor signals are supplied at various timings from each of the sensors, it is not synchronized with the reception timing of the sensor signals but synchronized with an internally generated clock signal. Then, the processing circuit 13 is turned on. Therefore, even if the number of sensors increases or the frequency at which the sensor signals A to C are output increases, an increase in the number of times the processing circuit 13 is turned on (and off) can be suppressed. As a result, power consumption associated with charging / discharging in the processing circuit 13 caused by turning on / off the power supply of the processing circuit 13 can be reduced, and the power consumption of the semiconductor device 10 can be reduced.

  Further, in the semiconductor device 10 of the second embodiment, the power of the processing circuit 13 is turned off when the sensor signals A to C are not received during one cycle immediately before the transition timing of the clock signal CK. The switch SW2 is controlled. Thereby, the power consumption of the semiconductor device 10 can be further reduced.

(Third embodiment)
FIG. 8 is a diagram illustrating an example of the semiconductor device according to the third embodiment. The same elements as those shown in FIG. 2 are denoted by the same reference numerals, and the description thereof is omitted.

The semiconductor device 10b includes reception units 11A, 11B, and 11C, a storage unit 12, a control unit 12a, a processing circuit 13, a switch SW2, a clock signal generation circuit 14, and a control circuit 15.
When the switch control signal supplied from the control circuit 15 is “0” and the power of the processing circuit 13 is turned off, the storage unit 12 is processed by the receiving units 11A to 11C based on the control of the control unit 12a. Hold signals A-C. In addition, when the switch control signal supplied from the control circuit 15 is “1” and the processing circuit 13 is turned on, the storage unit 12 stores the sensor signals A to C held based on the control of the control unit 12a. A part is output to the processing circuit 13. The storage unit 12 is a storage device having a plurality of input terminals, for example, a RAM (Random Access Memory) having a plurality of input terminals. In the following, for the sake of explanation, it is assumed that the storage unit 12 has 16 word lines that are designated by a 4-bit address.

  When the switch control signal supplied from the control circuit 15 is “0”, the control unit 12a puts the storage unit 12 in a WE (Write Enable) state, and sends the sensor signal A supplied to the reception units 11A to 11C to the storage unit 12. Hold ~ C. Further, when the switch control signal is “1”, the control unit 12a sets the storage unit 12 to an RE (Read Enable) state, and converts some of the sensor signals A to C held in the storage unit 12 to the sensors 5A to 5A. It is designated based on the priority of 5C and is read from the storage unit 12 and processed by the processing circuit 13. For example, in the sensors 5A to 5C, the higher the priority, the higher the priority.

(Example of control unit)
FIG. 9 is a diagram illustrating an example of the control unit.
The control unit 12a includes processing units 40A, 40B, and 40C, an OR circuit 41, buffers 42 and 43, an up counter 44, a register 45, a subtractor 46, a comparator 47, an up counter 48, a down counter 49, a CAM (Content Addressable Memory). ) 50.

  When the sensor signal A is input from the receiving unit 11A, the processing unit 40A generates a priority flag for the sensor signal A and outputs the priority flag to the CAM 50. Further, the processing unit 40A outputs a signal that becomes “1” to the OR circuit 41 when the sensor signal A is input. In addition, the processing unit 40A converts the signals that are sequentially input bit by bit of the sensor signal A into parallel data, and outputs the parallel data to the storage unit 12.

  When the sensor signal B is input from the receiving unit 11B, the processing unit 40B generates a priority flag for the sensor signal B and outputs the priority flag to the CAM 50. Further, the processing unit 40B outputs a signal that becomes “1” to the OR circuit 41 when the sensor signal B is input. In addition, the processing unit 40B converts the signals that are sequentially input bit by bit of the sensor signal B into parallel data and outputs the parallel data to the storage unit 12.

  When the sensor signal C is input from the receiving unit 11C, the processing unit 40C generates a priority flag for the sensor signal C and outputs the priority flag to the CAM 50. Further, the processing unit 40C outputs a signal that becomes “1” to the OR circuit 41 when the sensor signal C is input. In addition, the processing unit 40C converts signals that are sequentially input bit by bit of the sensor signal C into parallel data and outputs the parallel data to the storage unit 12.

Hereinafter, a circuit example of the processing unit 40A will be described. The other processing units 40B and 40C can be realized by a similar circuit.
The processing unit 40A includes a flag generator 51, an OR circuit 52, and a serial / parallel circuit 53.

  When the sensor signal A is input from the receiver 11A, the flag generator 51 outputs a priority flag of the sensor signal A to the OR circuit 52 and the CAM 50. The priority flag is represented by a 2-bit signal, for example. The priority flag is preset in the flag generator 51 by the outside (computer not shown) based on the above priority.

FIG. 10 is a diagram illustrating an example of setting priority flags.
FIG. 10 shows an example in which priorities are set by the sensors 5A to 5C. The priority flag indicates that the higher the value, the higher the priority.

  That is, the priority flag is set to “01” for the sensor 5A, “10” for the sensor 5B, and “11” for the sensor 5C. FIG. 10 shows an example of priority determination for each priority flag value. In the example of FIG. 10, the sensor 5A with the priority flag “01” has a low priority, the sensor signal A may be discarded without being processed, and the sensor 5B with the priority flag “10” has a priority of Although low, it is desirable to process sensor signal B. Further, it is desirable to process the sensor signal B of the sensor 5C having the priority flag “11” with the highest priority.

Returning to the description of FIG.
The OR circuit 52 performs an OR operation on the 2-bit signal of the priority flag supplied from the flag generator 51 and outputs the operation result to the OR circuit 41. When the sensor signal A is supplied to the processing unit 40A, the flag generator 51 outputs a priority flag “01” in which at least one bit of the 2-bit signal is “1” to the OR circuit 52. The circuit 52 outputs a signal that becomes “1” to the OR circuit 41.

The serial / parallel circuit 53 converts the signal that is input bit by bit of the sensor signal A from the receiving unit 11 </ b> A into parallel data, and outputs the parallel data to the storage unit 12.
The OR circuit 41 performs an OR operation on signals supplied from the processing units 40A, 40B, and 40C (for example, the OR circuit 52 of the processing unit 40A). The OR circuit 41 outputs the OR operation result as a write clock signal (hereinafter simply referred to as a clock signal CKw).

The buffer 42 delays the clock signal CKw and outputs it to the up counter 44.
The buffer 43 delays the clock signal CKw and outputs it to the storage unit 12. The delay amount in the buffer 42 is larger than the delay amount in the buffer 43.

  The up counter 44 is a 4-bit counter, for example, and increments the counter value from “0000” in synchronization with the rise of the signal supplied from the buffer 42. Further, the up counter 44 outputs the counter value as a write address to the CAM 50 and the storage unit 12. Further, when the switch control signal supplied from the control circuit 15 becomes “1” (RE state), the up counter 44 resets the held counter value to “0000”.

  For example, the register 45 holds an upper limit value of the data amount (hereinafter referred to as the number of data) of the sensor signals A to C processed by the processing circuit 13 during a certain period. This upper limit value held in the register 45 is preset by a computer or the like (not shown).

The subtractor 46 subtracts 1 from the value held in the register 45 and outputs the result to the comparator 47.
The comparator 47 compares the output value of the subtractor 46 with the counter value of the up counter 48. The comparator 47 outputs a reset signal that becomes “1” when the counter value of the up counter 48 exceeds the output value of the subtractor 46.

  The up counter 48 increments the counter value in synchronization with the rising edge of the Up signal supplied from the CAM 50. The up-counter 48 resets the counter value when the reset signal output from the comparator 47 becomes “1”.

  The down counter 49 is a 6-bit counter, for example. When the switch control signal supplied from the control circuit 15 becomes “1” (RE state), the down counter 49 outputs a 6-bit counter value in synchronization with the Read clock signal (hereinafter simply referred to as a clock signal) CKr. . When the down counter 49 receives a Down signal that is “1” supplied from the CAM 50, the down counter 49 decrements the counter value to be output. When the down counter 49 receives a reset signal that is “1” supplied from the comparator 47, the down counter 49 resets the counter value to the initial value (“111111”). As the clock signal CKr, for example, the clock signal CK supplied from the clock signal generation circuit 14 (see FIG. 8) can be used.

The CAM 50 includes storage units 50a and 50b.
When the switch control signal is “0” (WE state), the storage unit 50a is a 2-bit signal supplied from the processing units 40A to 40C to the address specified by the Write address in synchronization with the clock signal CKw. A certain priority flag is stored.

In the storage unit 50b, 4-bit data indicating an address is stored in advance. The 4-bit data is used as a read address to be described later.
When the switch control signal becomes “1” (RE state), the CAM 50 compares the 6-bit counter value of the down counter 49 with the data stored in the storage units 50a and 50b. In the CAM 50, the most significant bit (MSB) and the least significant bit (LSB) of the 6-bit counter value are stored in the storage unit 50b and the most significant bit of the 2-bit data stored in the storage unit 50a, respectively. The comparison is performed so as to correspond to the least significant bit of the existing 4-bit data.

  When the counter value of the down counter 49 matches the 6-bit data stored in the storage units 50a and 50b, the CAM 50 stores the lower order stored in the storage unit 50b among the matching 6-bit data. 4-bit data is output as a Read address. At this time, the CAM 50 outputs an Up signal that becomes “1”.

Further, the CAM 50 outputs a Down signal that becomes “1” every time the counter value of the down counter 49 is compared with the 6-bit data stored in the storage units 50a and 50b.
The above is the circuit example of the control unit 12a.

  When the switch control signal is “0” (WE state), the storage unit 12 synchronizes with the clock signal CKw and outputs the sensor signals A to C supplied from the processing units 40A to 40C to the address specified by the Write address. Remember C. In addition, when the switch control signal is “1” (RE state), the storage unit 12 receives the read address output from the CAM 50 and outputs the stored data of the sensor signals A to C to the processing circuit 13. .

(Example of write operation)
When the switch control signal is “0”, the WE state is entered and a write operation is performed.
FIG. 11 is a diagram illustrating an example of write data.

  FIG. 11 shows an example of the priority flag stored in the storage unit 50 a of the CAM 50 and the data of the sensor signals A to C stored in the storage unit 12. The address of the storage unit 12 where the data of the sensor signals A to C is stored and the address of the storage unit 50a where the priority flags of the sensor signals A to C are stored are the same.

  The write address is incremented sequentially from “0000” by the up counter 44 every time the control unit 12 a receives the sensor signals A to C, and is supplied to the CAM 50 (storage unit 50 a) and the storage unit 12. Therefore, the data of the sensor signals A to C are written in order from the address “0000” of the storage unit 12 in the order of supply to the control unit 12a. In addition, a priority flag having a value corresponding to the priority of the sensors 5A to 5C that output the sensor signals A to C is sequentially written from the address “0000” of the storage unit 50a.

(Read operation example)
When the switch control signal is “1”, the RE state is entered and a read operation is performed.
FIG. 12 is a diagram for explaining an example of the operation of the CAM and the down counter in the RE state.

FIG. 12 shows the 2-bit data of the priority flag stored in the storage unit 50a and the 4-bit data stored in the storage unit 50b in advance in the WE state.
During the read operation, the CAM 50 compares the counter value of the down counter 49 with the 6-bit data stored in the storage units 50a and 50b.

  First, 6-bit data combining the 2-bit data of the priority flag stored at the address “1111” of the storage unit 50a and the 4-bit data “1111” stored in the storage unit 50b, and the counter value “ 111111 "is compared.

  In the example of FIG. 12, since the priority flag stored in the address “1111” of the storage unit 50a is “10”, it does not match the counter value “111111” of the down counter 49. The CAM 50 outputs a Down signal that becomes “1”.

When the down counter 49 receives the Down signal which becomes “1”, the counter value is decremented and “111110” is output to the CAM 50.
Next, the CAM 50 includes 6-bit data obtained by combining the 2-bit data of the priority flag stored at the address “1110” of the storage unit 50a and the 4-bit data “1110” of the storage unit 50b, and the counter value “111110”. To compare.

  In the example of FIG. 12, since the priority flag stored in the address “1110” of the storage unit 50a is “11”, it matches the counter value “111110” of the down counter 49. Therefore, the CAM 50 outputs the 4-bit data “1110” in the storage unit 50 b to the storage unit 12 as a Read address, and further outputs an Up signal that becomes “1” to the up counter 48. Further, the CAM 50 outputs a Down signal that becomes “1” to the down counter 49 after the comparison. As a result, the sensor signal data stored in the address “1110” of the storage unit 12 is read and supplied to the processing circuit 13.

  When the same processing is repeated and the counter value of the up counter 48 exceeds the output value of the subtractor 46, a reset signal that is “1” is output by the comparator 47, and the counter value of the down counter 49 is set to “111111”. Reset. Further, the counter value of the up counter 48 is reset to “0”.

FIG. 13 is a diagram illustrating an example of sensor signal data read from the storage unit and output to the processing circuit in the RE state.
In FIG. 13, the data of the sensor signals A to C are arranged in the order in which they are processed by the processing circuit 13. In the example of FIG. 13, the upper limit value of the number of data of the sensor signals A to C processed by the processing circuit 13 stored in the register 45 is “4”.

  Through the above-described reading process, the data of the sensor signals A to C are read in the descending order of the 2-bit data value of the priority flag as shown in FIG. That is, among the sensors 5A to 5C, the data of the sensor signal C of the sensor 5C having a higher priority is preferentially processed.

  In addition, for example, for a plurality of data supplied from the same sensor, the value of the 2-bit data of the priority flag is the same, so in the storage unit 12, the data stored at the larger value is preferential. Is read out. That is, the data supplied to the control unit 12a is preferentially read from the later data. This is because new data is more valuable than old data.

  For example, among the plurality of data of the sensor signal B, the data “dddddddd” stored in the address “0011” is read from the storage unit 12 before the data “bbbbbbbbb” stored in the address “0001”. And processed by the processing circuit 13.

  Further, in the example of FIG. 13, since the upper limit value “4” of the number of data of the sensor signals A to C processed by the processing circuit 13 is two, two of the three sensor signals A (address “0100”, “0000”). The data stored in “” is not read from the storage unit 12. That is, two of the three sensor signals A are not processed by the processing circuit 13.

Hereinafter, an example of a signal of each part of the semiconductor device 10b during the write operation and the read operation will be described using a timing chart.
(An example of a signal of each part of the semiconductor device 10b during the write operation)
FIG. 14 is a timing chart illustrating an example of signals of respective parts of the semiconductor device according to the third embodiment during the write operation.

  FIG. 14 shows an example of the switch control signal, the sensor signals A to C, the output of the flag generators of the processing units 40A to 40C, the clock signal CKw, and the output (Write address) of the up counter 44. . Further, FIG. 14 shows an example of write data (2-bit data indicating a priority flag) to the storage unit 50a of the CAM 50 and write data to the storage unit 12.

  When the switch control signal falls from “1” to “0” at timing t40, the control unit 12a enters the WE state. All data in the storage unit 50a is reset to “0” at this timing.

  At timing t41, a sensor signal A that repeats “1” and “0” in a predetermined cycle is output (in the example of FIG. 14, 4-bit data “1111” is shown). When the sensor signal A rises to “1”, the flag generator 51 of the processing unit 40A generates a priority flag that is “01”. Further, by generating the priority flag, the clock signal CKw rises to “1”.

  The rising edge of the clock signal CKw is transmitted to the storage unit 12 before the up counter 44. Since the initial value of the write address output from the up counter 44 is “0000”, the storage unit 12 stores the data of the sensor signal A that is converted into parallel data by the serial / parallel circuit 53 of the processing unit 40A at the address “0000”. “1111” is stored. Further, when the rising edge of the clock signal CKw is transmitted to the up counter 44, the counter value is incremented, and the next write address “0001” is generated. When the sensor signal A becomes “0” for a predetermined period, the output of the flag generator 51 of the processing unit 40A becomes “00”, and the clock signal CKw falls to “0”.

  Similar processing is performed when the sensor signal B that is 4-bit data “1011” is output (timing t42) and when the sensor signal C that is 4-bit data “1101” is output (timing t43). Is called. The same processing is performed when the sensor signal A that is “1001” is output (timing t44).

  At timing t45, the switch control signal rises from “0” to “1”. Thereby, the control part 12a will be in RE state. At this time, the up counter 44 is reset, and the write address becomes “0000”.

(An example of a signal of each part of the semiconductor device 10b during the read operation)
FIG. 15 is a timing chart illustrating an example of signals of respective parts of the semiconductor device according to the third embodiment during a read operation.

  FIG. 15 shows an example of the switch control signal, the output of the down counter 49, the Up signal, the output of the up counter 48, the Read address, and the reset signal. In the following, it is assumed that “4” (the value output by the subtractor 46 is “3”) is set in the register 45 as the upper limit value of the number of data of the sensor signals A to C processed by the processing circuit 13. explain.

At timing t50, the switch control signal rises from “0” to “1”. Thereby, the control part 12a will be in RE state.
When the switch control signal rises to “1”, the down counter 49 outputs “111111” which is the initial value of the counter value at timing t51. Then, the CAM 50 compares the output “111111” of the down counter 49 with the 6-bit data stored in the storage units 50a and 50b. In the example of FIG. 15, since they do not match, the CAM 50 outputs a Down signal that becomes “1” to the down counter 49 after the comparison while maintaining the Up signal at “0”.

  Upon receiving the Down signal that becomes “1”, the down counter 49 decrements the counter value at timing t52, outputs “111110”, and the CAM 50 uses the 6-bit data stored in the storage units 50a and 50b. A comparison is made. Also at this time, since the output “111110” of the down counter 49 and the 6-bit data in the storage units 50a and 50b do not match, the Up signal is maintained at “0”. Then, a Down signal that becomes “1” is output to the down counter 49, and the down counter 49 decrements the counter value.

Similar processing is performed at timing t53.
In the example of FIG. 15, when the output of the down counter 49 becomes “110010” at the timing t54, it matches the data in the storage units 50a and 50b. At this time, the CAM 50 outputs the 4-bit data “0010” in the storage unit 50b to the storage unit 12 as a Read address. The CAM 50 raises the Up signal to “1”. In response to the rising edge of the Up signal, the up counter 48 increments the counter value and outputs “001”. Further, the CAM 50 outputs a Down signal that becomes “1” to the down counter 49 after the comparison.

  FIG. 15 shows an example in which the output of the down counter 49 and the data in the storage units 50a and 50b coincide with each other three times (timing t55, t56, t57). When the Up signal rises to “1” at timing t57, the output of the up counter 48 becomes “100” (decimal number “4”). At this time, since the output of the up counter 48 exceeds the output value “3” of the subtractor 46, the reset signal rises to “1” by the comparator 47 (timing t58). When the reset signal rises to “1”, the output of the down counter 49 is reset to “111111” and the output of the up counter 48 is reset to “000”.

At timing t59, the switch control signal falls from “1” to “0”. Thereby, the control part 12a will be in a WE state.
Incidentally, the processing of the control unit 12a as described above can also be realized by software. In this case, the function of the control unit 12a is realized by a processor (CPU (Central Processing Unit) or the like) executing a program stored in a ROM (Read Only Memory) or the like, for example. Hereinafter, control in the case of being executed by software will be described.

First, the write operation will be described.
(Example of writing operation by software)
FIG. 16 is a flowchart illustrating an exemplary process flow during a write operation.

  First, the control part 12a determines whether it is a WE state (step S1). For example, if the switch control signal supplied from the control circuit 15 is “0”, the control unit 12a determines that the state is the WE state, and if the switch control signal supplied from the control circuit 15 is “1”, It is determined that the state is not the WE state (the RE state). When it is determined that the state is the WE state, the control unit 12a executes the processes of steps S2A, S2B, and S2C. On the other hand, when determining that the state is not the WE state, the control unit 12a ends the process and performs a reading operation.

  The processes of steps S2A to S2C are processes performed for each of the sensor signals A to C, respectively. Below, the process of step S2A which is a process with respect to the sensor signal A is demonstrated to an example.

  First, the control unit 12a determines whether or not the sensor signal A has been received (step S3). When determining that the sensor signal A has been received, the control unit 12a performs the process of step S4. On the other hand, when it determines with the control part 12a not receiving the sensor signal A, it returns to the process of step S1.

  Next, the control unit 12a reads and acquires the priority flag 60A of the sensor signal A from, for example, the storage unit 12 (step S4). The priority flags 60A, 60B, and 60C are stored in the storage unit 12, for example. The values of the priority flags 60A, 60B, and 60C (for example, 2-bit data as described above) are set for each sensor based on the priorities of the sensors 5A to 5C.

  Thereafter, the control unit 12a creates table data 61 including data of the sensor signals A to C and priority flags 60A to 60C of the sensor signals A to C (step S5). For example, the table data 61 as shown in FIG. 11 is created. The created table data 61 is stored in the storage unit 12, for example.

The controller 12a assigns addresses in ascending order from “0000” to the data of the sensor signals A to C to the controller 12a in the order of supply to the controller 12a.
Then, the control unit 12a writes the data of the sensor signals A to C to the address of the storage unit 12 specified by the table data 61 (Step S6).

After the process of step S6 is complete | finished, the control part 12a repeats the process from step S1.
Next, the reading operation will be described.

(Example of read operation by software)
FIG. 17 is a flowchart showing an exemplary flow during a read operation.
First, the control unit 12a determines whether or not the RE state is set (step S10). For example, if the switch control signal supplied from the control circuit 15 is “1”, the control unit 12a determines that the state is the RE state, and if the switch control signal supplied from the control circuit 15 is “0”, It is determined that the state is not the RE state (WE state). When it is determined that the controller 12a is in the RE state, the controller 12a executes the process of step S11. On the other hand, when determining that the controller 12a is not in the RE state, the controller 12a ends the process and performs the writing operation.

  Next, the control part 12a sorts the table data 61 (refer FIG. 16), and produces the sort data 62 (step S11). For example, the sort data 62 as shown in FIG. 13 is created.

  As shown in FIG. 13, the control unit 12a sorts the data of the sensor signals A to C so that the one with the larger value of the 2-bit data of the priority flag is higher. In addition, the control unit 12a sorts a plurality of pieces of data having the same priority flag so that data having a larger address, that is, data supplied later in time is higher.

Thereafter, the control unit 12a reads the data of the sensor signals A to C from the storage unit 12 in the sort order based on the sort data 62, and outputs the data to the processing circuit 13 (step S12).
Further, the control unit 12a determines whether or not the number of data of the sensor signals A to C read from the storage unit 12 by the process of step S12 has reached the upper limit value 63 processed by the processing circuit 13 (step S13). The upper limit value 63 is stored in the storage unit 12, for example, and the value is set in advance from the outside. When it is determined that the number of data of the read sensor signals A to C is smaller than the upper limit value 63, the control unit 12a repeatedly performs the process from step S12. On the other hand, when it is determined that the number of data of the read sensor signals A to C has reached the upper limit value 63, the control unit 12a ends the process.

  For example, when the upper limit value 63 is set to “4”, the two data (“eeeeeeee” and “aaaaaaaaa”) of the sensor signal A shown in FIG. It is not processed by the processing circuit 13.

  As described above, according to the semiconductor device 10b of the present embodiment, the same effect as that of the semiconductor device 10 of the second embodiment can be obtained and the data processed by the processing circuit 13 is limited. Power consumption can be further reduced.

(Fourth embodiment)
FIG. 18 is a diagram illustrating an example of a control unit in the semiconductor device according to the fourth embodiment. In addition, the same code | symbol is attached | subjected to the element same as the element shown in FIG. 9, and the description is abbreviate | omitted.

FIG. 18 shows the control unit 12b of the semiconductor device 10c according to the fourth embodiment.
When the switch control signal supplied from the control circuit 15 is “0”, the control unit 12b sets the storage unit 12 to the WE state and holds the sensor signals A to C supplied to the reception units 11A to 11C in the storage unit 12. Let The control unit 12b sets the RE state when the switch control signal supplied from the control circuit 15 is “1”, and uses part of the sensor signals A to C held in the storage unit 12 as a priority flag. It is designated based on the interrupt flag and is read from the storage unit 12 and processed by the processing circuit 13. The interrupt flag will be described later.

  The control unit 12b includes processing units 40A1, 40B1, and 40C1, an OR circuit 41, buffers 42 and 43, an up counter 44, a register 45, a subtractor 46, a comparator 47, an up counter 48, a down counter 49a, and a CAM 50c.

Hereinafter, an example of the processing unit 40A1 will be described, but the processing units 40B1 and 40C1 are the same as the processing unit 40A1.
The processing unit 40A1 has substantially the same function as the processing unit 40A shown in FIG. 9, but when the sensor signal A is input from the receiving unit 11A, in addition to the priority flag described above, an interrupt flag is generated, Output to CAM 50c.

  Similar to the processing unit 40A, the processing unit 40A1 includes a flag generator 51a, an OR circuit 52a, and a serial / parallel circuit 53. However, unlike the flag generator 51 of the processing unit 40A, when the sensor signal A is input from the receiving unit 11A, the flag generator 51a sets an interrupt flag in addition to the priority flag of the sensor signal A to the OR circuit 52a. Output to CAM 50c.

  Similar to the third embodiment, the priority flag is represented by, for example, a 2-bit signal, and is set in advance in the flag generator 51a by an external device (not shown) based on the above-described priority. Also in the fourth embodiment, as in the third embodiment, the sensors 5A to 5C have higher priority in the order, and the priority flags of the sensor signals A to C are “01” and “ It is assumed that “10” and “11” are set.

  The interrupt flag is represented by a 1-bit signal, for example, and is assigned to each of the sensors 5A to 5C. Even in the case of sensor data with a low priority, if the interrupt flag assigned to the sensor is “1”, for example, the sensor data is read from the storage unit 12 at least once. Then, the processing circuit 13 performs processing (hereinafter referred to as interrupt processing).

FIG. 19 is a diagram illustrating an example of setting an interrupt flag.
As described above, since the sensor 5A has a low priority and the sensor signal A may be discarded without being processed (see FIG. 10), no interrupt processing is required, and no interrupt processing is performed on the sensor 5A. Is assigned an interrupt flag “0”.

  On the other hand, the sensor 5B has a low priority, but it is desirable to process the sensor signal B. Therefore, it is desirable to perform interrupt processing, and an interrupt flag “1” indicating that interrupt processing is performed is provided to the sensor 5B. Assigned.

Further, since the sensor 5C has the highest priority, the sensor signal C is processed without performing interrupt processing. Therefore, an interrupt flag “0” is assigned.
Returning to the description of FIG.

  The OR circuit 52a performs an OR operation on a 3-bit signal based on the 2-bit signal of the priority flag supplied from the flag generator 51a and the 1-bit signal of the interrupt flag, and outputs the OR operation result to the OR circuit 41. Output. When the sensor signal A is supplied to the processing unit 40A1, a 3-bit signal in which at least one bit is “1” among the 3-bit signals based on the interrupt flag and the priority flag is sent to the OR circuit 52a by the flag generator 51a. Is output. Therefore, when the sensor signal A is supplied to the processing unit 40A1, the OR circuit 52a outputs a signal that becomes “1” to the OR circuit 41.

The serial / parallel circuit 53 converts the signal that is input bit by bit of the sensor signal A from the receiving unit 11 </ b> A into parallel data, and outputs the parallel data to the storage unit 12.
Unlike the down counter 49 shown in FIG. 9, the down counter 49a is, for example, a 7-bit counter. When the switch control signal supplied from the control circuit 15 becomes “1” (RE state), the down counter 49a outputs 7-bit data (initial value “1111111”) to the CAM 50c in synchronization with the clock signal CKr. Further, when the down counter 49a receives the Down signal that becomes “1” from the CAM 50c, the down counter 49a decrements the counter value to be output.

  Further, when receiving the reset 2 signal that becomes “1” from the CAM 50 c, the down counter 49 a resets the counter value to “0111111”. When the down counter 49a receives a Down signal that becomes “1” from the CAM 50c, the down counter 49a outputs a counter value decremented from “0111111” after reset.

When the down counter 49 a receives a reset signal that is “1” from the comparator 47, the down counter 49 a resets the counter value to the initial value (“1111111”).
Hereinafter, in order to distinguish from the reset signal output from the comparator 47, the reset signal output from the CAM 50c is referred to as a reset 2 signal.

The CAM 50c includes a storage unit 50d and a storage unit 50b.
When the switch control signal is “0” (WE state), the storage unit 50d synchronizes with the clock signal CKw, and the priority flag and interrupt supplied from the processing units 40A1 to 40C1 to the address specified by the Write address. A 3-bit signal by a flag is stored. At this time, the storage unit 50d stores the 3-bit signal such that the most significant bit is a 1-bit signal of the interrupt flag and the lower 2 bits of the 3-bit signal are a 2-bit signal of the interrupt flag.

In the storage unit 50b, 4-bit data indicating an address is stored in advance. The 4-bit data is used as a read address to be described later.
When the switch control signal becomes “1” (RE state), the CAM 50c compares the 7-bit counter value of the down counter 49a with the data stored in the storage units 50d and 50b. In the CAM 50c, the most significant bit (MSB) and the least significant bit (LSB) of the 7-bit counter value are stored in the most significant bit of the 3-bit data stored in the storage unit 50d and the storage unit 50b, respectively. The comparison is performed so as to correspond to the least significant bit of the 4-bit data.

  Then, when the counter value of the down counter 49a matches the 7-bit data stored in the storage units 50d and 50b, the CAM 50c, among the matched 7-bit data, stores the lower order stored in the storage unit 50b. 4-bit data is output as a Read address. At this time, the CAM 50c outputs a reset 2 signal that becomes “1” to the down counter 49a.

  The CAM 50c outputs a Down signal that becomes “1” every time the 7-bit counter value of the down counter 49a is compared with the 7-bit data stored in the storage units 50d and 50b.

(Example of write operation)
When the switch control signal is “0”, the WE state is entered and a write operation is performed.
FIG. 20 is a diagram illustrating an example of write data.

  FIG. 20 shows an example of the priority flag and the interrupt flag stored in the storage unit 50d of the CAM 50c and the data of the sensor signals A to C stored in the storage unit 12. The address of the storage unit 12 where the data of the sensor signals A to C is stored is the same as the address of the storage unit 50d where the priority flags and interrupt flags of the sensor signals A to C are stored.

  The write address is incremented sequentially from “0000” by the up counter 44 every time the control unit 12 b receives the sensor signals A to C, and is supplied to the CAM 50 (storage unit 50 d) and the storage unit 12. Therefore, the data of the sensor signals A to C are written in order from the address “0000” of the storage unit 12 in the order of supply to the control unit 12b. Further, the priority flag and the interrupt flag assigned to the sensors 5A to 5C that output the sensor signals A to C are sequentially written from the address “0000” of the storage unit 50d.

(Read operation example)
When the switch control signal is “1”, the RE state is entered and a read operation is performed.
FIG. 21 is a diagram for explaining an example of the operation of the CAM and the down counter in the RE state.

  FIG. 21 shows the 3-bit data by the interrupt flag and the priority flag stored in the storage unit 50d and the 4-bit data stored in the storage unit 50b in advance in the WE state.

During the read operation, the CAM 50c compares the counter value of the down counter 49a with the 7-bit data stored in the storage units 50d and 50b.
First, 7-bit data combining the 3-bit data by the interrupt flag and the priority flag stored in the address “1111” of the storage unit 50d and the 4-bit data “1111” stored in the storage unit 50b; The counter value “1111111” is compared.

  In the example of FIG. 21, since the 3-bit data by the interrupt flag and the priority flag stored at the address “1111” of the storage unit 50d is “011”, it does not match the counter value “1111111” of the down counter 49a. . The CAM 50c outputs a Down signal that becomes “1”.

  Thereafter, when the counter value is decremented and the counter value becomes “1101011”, the interrupt flag and the priority flag stored in the address “1011” of the storage unit 50d are “110” in the example of FIG. Therefore, it matches the counter value. Therefore, the CAM 50c outputs the 4-bit data “1011” of the storage unit 50b to the storage unit 12 as a Read address, and further outputs an Up signal that becomes “1” and a reset 2 signal. As a result, the sensor signal data stored in the address “1011” of the storage unit 12 is read and supplied to the processing circuit 13.

The counter value of the down counter 49a is reset to “0111111” by the reset 2 signal. Then, the same comparison process is repeated.
When the counter value of the up counter 48 exceeds the output value of the subtractor 46, the comparator 47 outputs a reset signal that becomes “1”, and the counter value of the down counter 49a is reset to “1111111”. Further, the counter value of the up counter 48 is reset to “0”.

FIG. 22 is a diagram illustrating an example of sensor signal data read from the storage unit and output to the processing circuit in the RE state.
In FIG. 22, the data of the sensor signals A to C are arranged in the order in which they are processed by the processing circuit 13. In the example of FIG. 22, the upper limit value of the number of data of the sensor signals A to C processed by the processing circuit 13 stored in the register 45 is “4”.

  By the above-described reading process, first, the data (“dddddddd”) of the sensor signal B having the larger address among the two data of the sensor signal B having the interrupt flag “1” is read, and the processing circuit 13 It is processed. On the other hand, the data with the smaller address (“bbbbbbbb”) is not read and is not processed by the processing circuit 13.

  Thereafter, the sensor signal of the sensor having the large 2-bit data value of the priority flag is preferentially read from the storage unit 12 and processed by the processing circuit 13. That is, among the sensors 5A and 5C, the data of the sensor signal C of the sensor 5C having a higher priority is processed with priority.

  In addition, for example, for a plurality of data supplied from the same sensor, the value of the 2-bit data of the priority flag is the same, so that the value is large in the storage unit 12 as in the third embodiment. Data stored at the address is read preferentially.

  For example, among the plurality of data of the sensor signal C, the data “jjjjjjjj” stored at the address “1001” is read from the storage unit 12 before the data “iiiiiiiii” stored at the address “1000”. And processed by the processing circuit 13.

  Further, in the example of FIG. 22, since the upper limit value of the number of data of the sensor signals A to C processed by the processing circuit 13 is “4”, the two data of the sensor signal C are not read from the storage unit 12. Further, the three data of the sensor signal A are not read from the storage unit 12. That is, the two data of the sensor signal C and the three data of the sensor signal A are not processed by the processing circuit 13.

Hereinafter, an example of a signal of each part of the semiconductor device 10c during the write operation will be described with reference to a timing chart.
(An example of a signal of each part of the semiconductor device 10c during the write operation)
FIG. 23 is a timing chart illustrating an example of signals of respective parts of the semiconductor device according to the fourth embodiment during a write operation.

  FIG. 23 shows an example of the switch control signal, sensor signals A to C, the output of the flag generators of the processing units 40A1 to 40C1, the clock signal CKw, and the output (Write address) of the up counter 44. . Further, FIG. 23 shows an example of write data (3-bit data indicating an interrupt flag and a priority flag) to the storage unit 50d of the CAM 50c and write data to the storage unit 12.

  When the switch control signal falls from “1” to “0” at timing t60, the control unit 12b enters the WE state. All data in the storage unit 50d is reset to “0” at this timing.

  At timing t61, a sensor signal A that repeats “1” and “0” at a predetermined cycle is output (in the example of FIG. 23, 4-bit data “1111” is shown). When the sensor signal A rises to “1”, the flag generator 51 of the processing unit 40A1 generates an interrupt flag that is “0” and a priority flag that is “01”. Further, the generation of the interrupt flag and the priority flag causes the clock signal CKw to rise.

  The rising edge of the clock signal CKw is transmitted to the storage unit 12 before the up counter 44. Since the initial value of the write address output from the up counter 44 is “0000”, the storage unit 12 stores the data of the sensor signal A converted into parallel data by the serial / parallel circuit 53 of the processing unit 40A1 at the address “0000”. “1111” is stored. Further, when the rising edge of the clock signal CKw is transmitted to the up counter 44, the counter value is incremented, and the next write address “0001” is generated. When the sensor signal A becomes “0” for a predetermined period, the output of the flag generator 51a of the processing unit 40A1 becomes “000” and the clock signal CKw falls to “0”.

  Similar processing is performed when the sensor signal B that is 4-bit data “1011” is output (timing t62) and when the sensor signal C that is 4-bit data “1101” is output (timing t63). Is called. The same processing is performed when the sensor signal A that is “1001” is output (timing t64).

  At timing t65, the switch control signal rises from “0” to “1”. Thereby, the control part 12b will be in RE state. At this time, the up counter 44 is reset, and the write address becomes “0000”.

(An example of a signal of each part of the semiconductor device 10c during the read operation)
FIG. 24 is a timing chart illustrating an example of signals of respective parts of the semiconductor device according to the fourth embodiment during a read operation.

  FIG. 24 shows an example of the switch control signal, the output of the down counter 49a, the reset 2 signal, the Up signal, the output of the up counter 48, the Read address, and the reset signal. In the following, it is assumed that “4” (the value output by the subtractor 46 is “3”) is set in the register 45 as the upper limit value of the number of data of the sensor signals A to C processed by the processing circuit 13. explain.

At timing t70, the switch control signal rises from “0” to “1”. Thereby, the control part 12b will be in RE state.
When the switch control signal rises to “1”, the down counter 49a outputs “1111111” which is the initial value of the counter value at timing t71. Then, the CAM 50c compares the output “1111111” of the down counter 49a with the 7-bit data stored in the storage units 50d and 50b. In the example of FIG. 24, since they do not match, the CAM 50c outputs a Down signal that becomes “1” to the down counter 49a after the comparison while maintaining the Up signal at “0”.

  The down counter 49a that has received the Down signal that is “1” decrements the counter value at timing t72, outputs “1111110”, and the CAM 50c determines whether the 7-bit data stored in the storage units 50d and 50b A comparison is made. Also at this time, since the output “1111110” of the down counter 49a does not match the 7-bit data in the storage units 50d and 50b, the Up signal remains “0”. Then, a Down signal that becomes “1” is output to the down counter 49, and the down counter 49 decrements the counter value.

Similar processing is performed at timing t73.
In the example of FIG. 24, when the output of the down counter 49a becomes “1100011” at the timing t74, it matches the data in the storage units 50d and 50b. At this time, the CAM 50c outputs the 4-bit data “0011” in the storage unit 50b to the storage unit 12 as a Read address. The CAM 50c raises the reset 2 signal and the Up signal to “1”. In response to the rising edge of the Up signal, the up counter 48 increments the counter value and outputs “001”.

  Upon receiving the reset 2 signal that becomes “1”, the down counter 49a outputs the reset counter value “0111111” at timing t75. Then, the CAM 50c again compares the 7-bit data stored in the storage units 50d and 50b. At this time, since the counter value “0111111” of the down counter 49a and the 7-bit data in the storage units 50d and 50b do not match, the CAM 50c keeps the Up signal at “0” and becomes Down after being compared to “1”. The signal is output to the down counter 49a.

  The down counter 49a that has received the Down signal of “1” outputs the counter value “0111110” decremented from “0111111” at timing t76, and the 7-bit data stored in the storage units 50d and 50b by the CAM 50c. Is compared. Also at this time, since the output “0111110” of the down counter 49a does not match the 7-bit data in the storage units 50d and 50b, the Up signal remains “0”. Then, a Down signal that becomes “1” is output to the down counter 49a, and the down counter 49a decrements the counter value.

Similar processing is performed at timing t77.
Thereafter, in the example of FIG. 24, an example is shown in which the output of the down counter 49a and the data in the storage units 50d and 50b coincide with each other three times (timing t78, t79, t80). When the Up signal rises to “1” at timing t80, the output of the up counter 48 becomes “100” (decimal number “4”). At this time, since the output of the up counter 48 exceeds the output value “3” of the subtractor 46, the reset signal rises to “1” by the comparator 47 (timing t81). When the reset signal rises to “1”, the output of the down counter 49a is reset to “1111111” and the output of the up counter 48 is reset to “000”.

At timing t82, the switch control signal falls from “1” to “0”. Thereby, the control part 12b will be in a WE state.
By the way, like the control part 12a in 3rd Embodiment, the above processes of the control part 12b can also be implement | achieved by software. In this case, the function of the control unit 12b is realized by a processor, for example. Hereinafter, control in the case of being executed by software will be described.

First, the write operation will be described.
(Example of writing operation by software)
FIG. 25 is a flowchart illustrating an exemplary process flow during a write operation.

  First, the control part 12b determines whether it is a WE state (step S20). The control unit 12b determines whether or not the state is the WE state according to whether the switch control signal is “0” or “1”, similarly to the process of step S1 illustrated in FIG. When it determines with the control part 12b being a WE state, it performs the process of step S21A, S21B, S21C. On the other hand, when determining that the state is not the WE state, the control unit 12b ends the process and performs a reading operation.

  The processing of steps S21A to S21C is processing performed for each of the sensor signals A to C. Hereinafter, the process of step S21A, which is a process for the sensor signal A, will be described as an example.

  First, the controller 12b determines whether or not the sensor signal A has been received (step S22). When it determines with the control part 12b having received the sensor signal A, it performs the process of step S23. On the other hand, when it determines with the control part 12b not receiving the sensor signal A, it returns to the process of step S20.

  Next, the control unit 12b reads and acquires the interrupt flag 70A and the priority flag 71A of the sensor signal A from, for example, the storage unit 12 (step S23). The interrupt flags 70A, 70B, and 70C and the priority flags 71A, 71B, and 71C are stored in the storage unit 12, for example.

Similarly to the processing in step S23, the interrupt flags 70B and 70C and priority flags 71B and 71C of the sensor signals B and C are also acquired.
Thereafter, the control unit 12b creates table data 72 including the data of the sensor signals A to C and the interrupt flags 70A to 70C and priority flags 71A to 71C of the sensor signals A to C (step S24). For example, the table data 72 as shown in FIG. 20 is created. The created table data 72 is stored in the storage unit 12, for example.

The controller 12b assigns addresses in ascending order from “0000” to the data of the sensor signals A to C to the controller 12b in the order of supply to the controller 12b.
Then, the control unit 12b writes the data of the sensor signals A to C to the address of the storage unit 12 specified by the table data 61 (Step S25).

After the process of step S25 is complete | finished, the control part 12b performs the process from step S20 repeatedly.
Next, the reading operation will be described.

(Example of read operation by software)
FIG. 26 is a flowchart showing an exemplary flow during a read operation.
First, the control unit 12b determines whether or not it is in the RE state (step S30). The control unit 12b determines whether or not the state is the RE state according to whether the switch control signal is “0” or “1”, similarly to the process of step S10 illustrated in FIG. When it is determined that the controller 12b is in the RE state, the controller 12b executes the process of step S31. On the other hand, when determining that the controller 12b is not in the RE state, the controller 12b ends the processing and performs the writing operation.

  Next, the control part 12b sorts the table data 72 (refer FIG. 25), and produces the sort data 73 (step S31). For example, the sort data 73 as shown in FIG. 22 is created.

  The control unit 12b first sorts the data of the sensor signal B with the interrupt flag “1” so that the data is higher, and for the data of the plurality of sensor signals B with the interrupt flag “1”. , Sort the one with the larger address so that it is higher. Further, the control unit 12b sorts the sensor signals A and C for which the interrupt flag is “0” so that the one with the larger value of the 2-bit data of the priority flag is higher. In addition, the control unit 12b sorts a plurality of pieces of data having the same priority flag so that data having a larger address is higher.

  Thereafter, the control unit 12b reads the data of the sensor signal in the highest row where the interrupt flag is “1” from the storage unit 12, and outputs the data to the processing circuit 13 (step S32). In the example of FIG. 22, the data “dddddddd” of the sensor signal B in the uppermost row where the interrupt flag is “1” is read from the storage unit 12 and output to the processing circuit 13.

  Thereafter, the control unit 12b selects data of the highest sensor signal whose interrupt flag is “0” in the sort data 73 (step S33). In the example of FIG. 22, the data of the sensor signal C is selected.

  And the control part 12b reads the data of sensor signal AC in the sort data 73 from the memory | storage part 12 in the sort order from the data selected by the process of step S33, and outputs it to the processing circuit 13 (step S34).

  In addition, the control unit 12b determines whether or not the number of data of the sensor signals A to C read from the storage unit 12 by the processing of steps S32 and S34 has reached the upper limit value 74 processed by the processing circuit 13 (step S35). ). The upper limit value 74 is stored in the storage unit 12, for example, and the value is set in advance from the outside. When it is determined that the number of data of the read sensor signals A to C is smaller than the upper limit value 74, the control unit 12b repeatedly performs the processing from step S34. On the other hand, when it is determined that the number of data of the read sensor signals A to C has reached the upper limit 74, the control unit 12b ends the process.

  For example, when the upper limit 74 is set to “4”, the two data (“ggggggggg” and “cccccccc”) of the sensor signal C shown in FIG. It is not processed by the processing circuit 13. Further, the three data (“ffffffff”, “eeeeeeee”, and “aaaaaaaaa”) of the sensor signal A are not read from the storage unit 12 and are not processed by the processing circuit 13.

  According to the semiconductor device 10c as described above, the same effect as that of the semiconductor device 10b of the third embodiment can be obtained, and even a sensor signal of a sensor having a low priority is processed once. It is possible to prevent the sensor signal of a sensor having a low degree from being completely ignored.

As described above, one aspect of the semiconductor device of the present invention has been described based on the embodiment, but these are merely examples, and the present invention is not limited to the above description.
For example, in the above description, the sensor is used as an example of the signal supply source. However, the present invention is not limited to this, and a wireless terminal device or the like may be used.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 1a Power supply control circuit 2 Processing circuit 3 Clock signal generation circuit 4 Control circuit 5 Signal supply source (sensor)
SW1 switch

Claims (9)

A processing circuit for performing processing based on signals supplied at a plurality of different timings from a signal supply source;
A switch for switching on and off the power of the processing circuit;
A clock signal generation circuit for generating a clock signal;
A control circuit that controls the switch so as to turn on the power supply in synchronization with the clock signal regardless of the reception timing of the signal when the signal is received;
A semiconductor device comprising:   The signal supply source is a plurality of sensors, and the control circuit receives the signal from at least one of the plurality of sensors, and the power supply is synchronized with the clock signal regardless of the reception timing. The semiconductor device according to claim 1, wherein the switch is controlled to turn on.   3. The storage device according to claim 1, further comprising: a storage unit that holds the signal, wherein the processing circuit performs processing based on the signal held in the storage unit when the power is turned on. Semiconductor device.   When the signal from the signal supply source is not received during one cycle of the clock signal immediately before the transition timing of the clock signal, the control circuit is configured to turn off the power supply in synchronization with the transition timing. 4. The semiconductor device according to claim 1, wherein the switch is controlled. A control unit for controlling the storage unit;
When the power is turned on, the control unit designates a part of the signal held in the storage unit based on the priority of the signal supply source, reads the signal from the storage unit, and causes the processing circuit to process the signal. The semiconductor device according to claim 3.   When the power is turned on, the control unit processes at least once the priority of the signal supply source or the signal from the signal supply source for a part of the signal held in the storage unit The semiconductor device according to claim 5, wherein the semiconductor device is designated based on information indicating whether or not to read from the storage unit, and causes the processing circuit to process.   When the first signal is supplied from the same signal supply source and then the second signal is supplied, the control unit reads the second signal from the storage unit preferentially. The semiconductor device according to claim 5 or 6. A clock signal generation circuit for generating a clock signal;
Control that turns on the power of a processing circuit that performs processing based on the signal in synchronization with the clock signal, regardless of the reception timing of the signal, when receiving signals supplied from the signal supply source at a plurality of different timings Circuit,
A power supply control circuit comprising: A clock signal generation circuit generates a clock signal,
When the control circuit receives a signal supplied from the signal supply source at a plurality of different timings, the power of the processing circuit that performs processing based on the signal is synchronized with the clock signal regardless of the reception timing of the signal. Turn on,
The power supply control method characterized by the above-mentioned.

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