JP2016039482A - Iq mismatch correction method and transmission/reception device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a selection from being restricted in combining a baseband circuit to an RF front circuit.SOLUTION: A monitor RF signal of IQ mismatch is generated within the RF front circuit and by performing frequency conversion and delay processing on the monitor RF signal, a transmission monitor I signal and a transmission monitor Q signal are generated. A transmission-side phase error of the transmission monitor I signal and the transmission monitor Q signal is detected. On the basis of a phase difference between a signal that is obtained by adding the transmission monitor I signal and the transmission monitor Q signal, and the transmission monitor I signal or the transmission monitor Q signal, a transmission-side amplitude error of the transmission monitor I signal and the transmission monitor Q signal is detected. A phase shift amount of a phase shifter in a transmission circuit is controlled on the basis of the transmission-side phase error, and a phase difference between a transmission I local signal and a transmission Q local signal is corrected. A gain of an amplifier in the transmission circuit is controlled on the basis of the transmission-side amplitude error, and a gain difference between the transmission monitor I signal and the transmission monitor Q signal is corrected.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an IQ mismatch correction method and a transmission / reception apparatus capable of IQ mismatch correction.

  In the transmission / reception apparatus, the direct conversion method is adopted from the viewpoint of low power consumption, low cost, and the like. The direct conversion method converts the baseband signal into an RF signal by one frequency conversion on the transmitting side, and performs the inverse conversion on the receiving side, and is a homodyne method that does not have an intermediate frequency signal like the superheterodyne method. It is. This eliminates the need for a filter for removing the RF signal and local frequency signal required for the superheterodyne method, and has the advantage of realizing low current consumption and low cost.

  In the direct conversion method, in order to avoid the influence of image interference, a quadrature detection circuit is used so that the transmission apparatus has a transmission I channel baseband signal (hereinafter referred to as a transmission I signal) and a transmission Q channel base that are orthogonal to each other. A band signal (hereinafter referred to as a transmission Q signal) is defined by a transmission I channel local frequency signal (hereinafter referred to as a transmission I local signal) and a transmission Q channel local frequency signal (hereinafter referred to as a transmission Q local signal) in an orthogonal relationship. The frequency is converted into two transmission RF signals, added, and transmitted from the antenna as one transmission RF signal.

  Also, in the receiving apparatus, the received RF signal input to the antenna is orthogonally related to a received I channel local frequency signal (hereinafter referred to as a received I local signal) and a received Q channel local frequency signal (hereinafter referred to as a received Q local signal). Is converted into a reception I channel baseband signal (hereinafter referred to as a reception I signal) and a reception Q channel baseband signal (hereinafter referred to as a reception Q signal) that are orthogonal to each other. In the receiving apparatus, the original data is extracted by digitally demodulating the received I signal and the received Q signal.

  However, in the direct conversion method, if there is an error in the orthogonality between the I signal and the Q signal, an image signal is generated in the side wave of the desired signal, which satisfies the SNR (Signal to Noise Ratio) required for demodulation. Communication quality is greatly deteriorated. Therefore, IQ mismatch correction is indispensable in the direct conversion method.

FIG. 8 is a conceptual diagram of EVM (Error Vector Magnetude) in an example of QPSK modulation. If there is a phase error or an amplitude error in the I signal and the Q signal, the symbol moves to, for example, a dem point that is out of the normal ref point. The EMV and SNR described above can be calculated by equations (1) and (2).

  In addition, the minimum necessary SNR for the modulation scheme can be obtained by Shannon's theorem. The results for each modulation method are shown in FIG. If the modulation scheme is known, the circuit must be designed so that the transmitting apparatus satisfies the EVM value and the receiving apparatus satisfies the SNR value.

  If there is an error between the I signal and the Q signal, the spectrum of the image signal is generated in the RF signal and the baseband signal, and the SNR is further deteriorated. For example, an SRR (Spurious Rejection Ratio) required for communication by 16QAM modulation needs to be −33 dBc or more, and in order to obtain a desired SRR, a gain error is within 0.2 dB and a phase error is within 2 deg. Need to design. Depending on the circuit, if there is a DC offset of about 10 mV, the IQ mismatch cannot satisfy the desired value, so that the IQ mismatch correction is essential in the direct conversion type transmission / reception device (Non-patent Document 1). .

  Therefore, conventionally, for example, as shown in FIG. 10, in the digital baseband circuit 210 of the baseband circuit 200, the IQ signal oscillation circuit 213 generates the monitor I signal and the monitor Q signal and inputs them to the RF front circuit 100. An error between the reception monitor I signal and the reception monitor Q signal output from the RF front circuit 100 is processed by the FFT circuit 211 and the arithmetic circuit 212 to generate a correction signal. Then, this correction signal is input to the transmitter circuit 111 of the RF front circuit 100, the amplifier of the reception circuit 112, and the phase shifter. The phase and amplitude were corrected.

Supisa Lerstaveesin, and Bang-Sup Song "A Complex Image Rejection Circuit With Sign Detection Only", IEEE Journal of Solid-state Circuits, Vol.41, No.12, December 2006

  However, in this method, IQ mismatch correction is performed by the RF front circuit 100 using the correction signal generated by the baseband circuit 200, and the RF front circuit 100 and the baseband circuit 200 must be in a paired relationship. For this reason, from the viewpoint of versatility, there is a problem that options for combining the baseband circuit 200 with the RF front circuit 100 are significantly hindered.

  An object of the present invention is to generate an IQ mismatch correction signal only on the RF front circuit side so that the selection of a combination of baseband circuits with respect to the RF front circuit is not limited, and transmission / reception is performed. Is to provide a device.

  In order to achieve the above object, the invention according to claim 1 inputs a transmission I signal and a transmission Q signal that are orthogonal to each other, performs quadrature modulation with the transmission I local signal and the transmission Q local signal, and adds them. In the IQ mismatch correction method of a transmission / reception apparatus including a transmission circuit that transmits as a transmission RF signal, a monitor RF signal is generated by inputting the internally generated monitor I signal and the monitor Q signal to the transmission circuit, performing quadrature modulation, and adding them Then, the monitor RF signal is frequency-converted to the frequency of the baseband signal to generate one of the transmission monitor I signal and the transmission monitor Q signal, and the generated one of the signals is subjected to delay processing to generate the transmission monitor. The other of the I signal and the transmission monitor signal Q is generated, and a transmission side phase error between the transmission monitor I signal and the transmission monitor Q signal is detected, and the transmission Based on the phase difference between the signal obtained by adding the Nita I signal and the transmission monitor Q signal and the transmission monitor I signal or the transmission monitor Q signal, a transmission-side amplitude error between the transmission monitor I signal and the transmission monitor Q signal is detected. And controlling the phase shift amount of the phase shifter of the transmission circuit based on the transmission side phase error to correct the phase difference between the transmission I local signal and the transmission Q local signal, and based on the transmission side amplitude error A gain difference between the transmission I signal and the transmission Q signal is corrected by controlling an amplifier of a transmission circuit.

  According to a second aspect of the present invention, the transmission circuit according to the first aspect, in which the IQ mismatch is corrected, and the received RF signal received from the transmission circuit are orthogonally demodulated by the received I local signal and the received Q local signal. In the IQ mismatch correction method of a transmission / reception apparatus comprising a receiving circuit that separates an I signal and a received Q signal, the monitor I signal and the monitor Q signal are input to the transmitting circuit in which an IQ mismatch is corrected, and The transmission RF signal is output from the transmission circuit, the transmission RF signal is received by the reception circuit, and the reception monitor I signal and the reception monitor Q signal are orthogonally demodulated by the reception I local signal and the reception Q local signal. And generating a reception-side phase error between the reception monitor I signal and the reception monitor Q signal, and generating the reception monitor I signal and the reception monitor Q signal. Based on the phase difference between the calculated signal and the reception monitor I signal or the reception monitor Q signal, a reception side amplitude error between the reception monitor I signal and the reception monitor Q signal is detected, and based on the reception side phase error, The phase shift amount of the phase shifter of the receiving circuit is controlled to correct the phase difference between the received I local signal and the received Q local signal, and the gain of the amplifier of the receiving circuit is controlled based on the receiving side amplitude error. A gain difference between the received I signal and the received Q signal is corrected.

  According to a third aspect of the present invention, there is provided a transmission circuit for inputting a transmission I signal and a transmission Q signal which are orthogonal to each other, performing quadrature modulation with the transmission I local signal and the transmission Q local signal, adding them, and transmitting as a transmission RF signal A monitor signal oscillation circuit for generating a monitor I signal and a monitor Q signal, and the monitor I signal and the monitor Q signal output from the monitor signal oscillation circuit are input to the transmission circuit to perform orthogonal modulation And then frequency-converting the added monitor RF signal to generate one of the transmission monitor I signal and the transmission monitor Q signal, and the one signal output from the frequency conversion circuit A delay circuit that delays to generate the other of the transmission monitor I signal and the transmission monitor Q signal; and the transmission monitor I signal and the transmission monitor Q signal. A phase difference is detected to generate a transmission-side first phase error signal, and a phase difference between a signal obtained by adding the transmission monitor I signal and the transmission monitor Q signal and the transmission monitor I signal or the transmission monitor Q signal is detected. A phase detection circuit for generating a transmission-side second phase error signal, and a phase shift amount of the phase shifter of the transmission circuit is controlled based on the transmission-side first phase error signal obtained by the phase detection circuit. A phase difference between the transmission I local signal and the transmission Q local signal is corrected, and a transmission side amplitude error between the transmission I signal and the transmission Q signal is obtained based on the transmission side second phase error signal obtained by the phase detection circuit. And a correction control circuit that obtains a signal and controls the gain of the amplifier of the transmission circuit based on the transmission-side amplitude error signal to correct the gain of the transmission I signal and the transmission Q signal.

  According to a fourth aspect of the present invention, in the transmission / reception apparatus including the transmission circuit according to claim 3 and the reception circuit corrected for IQ mismatch, the reception circuit corrects the IQ mismatch output from the transmission circuit. The received monitor RF signal is input and quadrature demodulated with the received I local signal and the received Q local signal to generate a received monitor I signal and a received monitor Q signal, and the phase detection circuit further includes the received monitor Detecting a phase difference between the I signal and the reception monitor Q signal to generate a reception-side first phase error signal, and adding the reception monitor I signal and the reception monitor Q signal to the reception monitor I signal or A phase difference from the reception monitor Q signal is detected to generate a reception-side second phase error signal, and the correction control circuit further includes the reception-side first phase error signal obtained by the phase detection circuit. Based on the phase error signal, the phase shift amount of the phase shifter of the reception circuit is controlled to correct the phase difference between the reception I local signal and the reception Q local signal, and the reception side obtained by the phase detection circuit is corrected. A reception-side amplitude error signal of the reception I signal and the reception Q signal is obtained based on a two-phase error signal, and a gain of an amplifier of the reception circuit is controlled based on the reception-side amplitude error signal, so that the reception I signal and the reception signal are received. The gain of the Q signal is corrected.

  According to a fifth aspect of the present invention, in the transmission / reception device according to the third aspect, the correction control circuit includes a first table indicating a relationship between the transmission-side second phase error and the transmission-side amplitude error. And

  According to a sixth aspect of the present invention, in the transmission / reception device according to the fourth aspect, the correction control circuit includes a first table indicating a relationship between the transmission-side second phase error and the transmission-side amplitude error, and the reception side. And a second table showing a relationship between the second phase error and the reception-side amplitude error.

  According to a seventh aspect of the present invention, in the transmission / reception device according to the third aspect, the phase detection circuit includes an adder that adds the transmission monitor I signal and the transmission monitor Q signal at a first timing, and a second timing. The transmission monitor I signal and the transmission monitor Q signal are multiplied to generate the transmission-side first phase error signal, and at the first timing, the output of the adder and the transmission monitor I signal or the transmission monitor Q signal And a quadrature detection circuit for generating the transmission-side second phase difference signal.

  The invention according to claim 8 is the transmitter / receiver according to claim 4, wherein the adder of the phase detection circuit further adds the reception monitor I signal and the reception monitor Q signal at a third timing, The quadrature detection circuit of the phase detection circuit further multiplies the reception monitor I signal and the reception monitor Q signal at a fourth timing to generate the reception-side first phase error signal, and the addition at the third timing. And the reception monitor I signal or the reception monitor Q signal is multiplied to generate the reception-side second phase difference signal.

  According to the present invention, the IQ mismatch of the transmission circuit and the reception circuit can be corrected regardless of the baseband circuit, so that the options for combining the baseband circuit with the RF front circuit including the transmission circuit and the reception circuit are increased. There are advantages. In addition, since the amplitude error between the I signal and the Q signal can be obtained based on the phase comparison between the I signal and the Q signal and the I signal or the Q signal, no special circuit for detecting the amplitude error is required. There are advantages.

It is a block diagram of the transmission / reception apparatus of the Example of this invention. FIG. 2 is a circuit diagram of a quadrature detection circuit and an addition circuit of the phase detection circuit of the transmission / reception apparatus of FIG. FIG. 2 is a circuit diagram of a quadrature detection circuit and an addition circuit of the phase detection circuit of the transmission / reception apparatus of FIG. 1. FIG. 2 is a circuit diagram of a monitor signal oscillation circuit of the transmission / reception device of FIG. 1. It is a flowchart of correction | amendment of IQ mismatch of the transmission circuit of the transmission / reception apparatus of FIG. It is a flowchart of correction | amendment of IQ mismatch of the receiving circuit of the transmission / reception apparatus of FIG. It is explanatory drawing of the amplitude error detection of two signals. It is a signal arrangement | positioning figure of QPSK. It is a figure which shows the relationship between a modulation system, reception side SNR, and transmission side EVM. It is a block diagram of the conventional transmission / reception apparatus.

<Principle of IQ mismatch detection>
In the present invention, phase error detection in IQ mismatch detection and phase error detection for amplitude error detection are performed by one Gilbert cell type quadrature detection circuit. Since this quadrature detection circuit has sensitivity only to the phase difference, when an amplitude error is detected, the amplitude difference is converted into a phase difference by adding the I signal and the Q signal, and the I signal reference (or Q signal reference) An amplitude error is detected from the phase difference. Then, a phase correction signal is generated based on the obtained phase error, an amplitude correction signal is generated based on the obtained amplitude error, and the phase and gain of the transmission circuit and the phase and gain of the reception circuit are individually determined by these correction signals. to correct.

として、直交検波回路で両者を乗算することで

で得られる。 To detect the phase error φe in the I and Q signals,

By multiplying both by the quadrature detection circuit

It is obtained by.

  Therefore, if an unnecessary second harmonic component (2ωt) is removed from the phase error signal of Equation (4) through a low-pass filter, a DC component (cos φe / 2) corresponding to the phase error φe can be obtained. A DC component is used as a phase correction signal.

  On the other hand, for the amplitude error, the I signal and the Q signal are added, the phase difference is detected by comparing the phase of the added signal and the I signal (or Q signal), and the amplitude error is detected based on the phase difference. Can do.

となるので、Ｉ信号とＱ信号を加算すると、

が得られる。 Here, if the amplitude of the I signal is A, the amplitude of the Q signal is B, and there is no phase difference,

Therefore, when I signal and Q signal are added,

Is obtained.

  For example, the quadrature detection circuit used in the phase error detection is used for phase comparison with the addition signal obtained in this way, using the I signal as a reference. Then, the amplitude difference (= A / B) can be acquired from the obtained phase difference.

  For example, for simplification, when the amplitude is B = 0.5A, ωt = θ, and the addition signal Asinθ + Bcosθ is shown as a waveform, when the horizontal axis is the phase and the vertical axis is the amplitude, FIG. As shown. At this time, at the zero cross point where the magnitude (corresponding to the amplitude) is zero, the waveform of the addition signal Asin θ + Bcos θ is delayed by 26.56 degrees with respect to the waveform of Asin θ.

  Further, when the amplitude is B = A and the addition signal Asinθ + Bcosθ is shown in a waveform, it is as shown in FIG. 7B. At this time, at the zero cross point, the waveform of the addition signal Asinθ + Bcosθ is delayed by 45 degrees with respect to the waveform of Asinθ.

  Therefore, when the ratio of the amplitudes A and B is made different to obtain the phase difference of the addition signal Asinθ + Bcosθ with respect to Asinθ at the zero crossing point, the phase difference with respect to the ratio of the amplitudes A and B has a characteristic as shown in FIG. Indicates. Therefore, if the characteristics shown in FIG. 7 (c) are created in a table in advance, or if an expression indicating the characteristic curve of FIG. 7 (c) is obtained, based on the phase difference detected by the quadrature detection circuit, The amplitude difference (B / A) can be obtained. Therefore, if the amplitude A is set in advance, the amplitude B can be obtained.

  As described above, since the amplitude error can be detected based on the phase error, a common quadrature detection circuit can be used for the phase error detection and the phase error detection for amplitude error detection. A circuit becomes unnecessary. In addition, since phase error detection for amplitude error detection compares two signals at the zero cross point of the waveform, even if there is a frequency drift or distortion in the waveform of the two input signals, the accuracy of phase difference detection is greatly affected. I do not receive it. For this reason, the required accuracy for the monitor I signal and the monitor Q signal described later can be relaxed.

<Example>
FIG. 1 shows an RF front circuit 100 of a transceiver apparatus according to an embodiment of the present invention. In FIG. 1, reference numeral 110 denotes a modulation / demodulation circuit, which includes a transmission circuit 111, a reception circuit 112, an envelope detection circuit (frequency conversion circuit) 113 that detects an envelope of a transmission signal and converts the frequency into a baseband signal, and a single-phase signal. A single-phase / differential conversion circuit 114 that generates a differential signal, a delay circuit 115 that delays an output signal of the single-phase / differential conversion circuit 114 by π / 2, and a transmission signal of the transmission circuit 111 directly to the reception circuit 112 A switch SW0 for inputting is provided.

The transmission circuit 111 includes an amplifier AMP1 that amplifies differential signals I ⁺ and I ⁻ of a transmission I signal input from a baseband circuit (not shown), and a transmission Q signal input from a baseband circuit (not shown). The amplifier AMP2 that amplifies the differential signals Q ⁺ and Q ⁻ , the mixer circuit MIX1 that modulates the transmission I signal by the transmission I local signal oscillated by the local oscillator OSC1, and the phase of the transmission I local signal oscillated by the local oscillator OSC1 A mixer circuit MIX2 that modulates the transmission Q signal by a transmission Q local signal phase-shifted by π / 2 by the device PS1, and an antenna ANT1 that emits an addition signal of the transmission RF signal output from the mixer circuits MIX1 and MIX2.

The reception circuit 112 demodulates the output signal of the amplifier AMP3 and AMP4 that amplifies the reception RF signal input from the antenna ANT2 and the output signal of the amplifier AMP3 by the reception I local signal oscillated by the local oscillator OSC2. ^+, I ^- and mixer circuit MIX3 taking out, received and demodulated by the receiving Q local signal phase-shifted by [pi / 2 the received I local signal oscillated by the local oscillator OSC2 output signal by the phase shifter PS1 of the amplifier AMP4 Q And a mixer circuit MIX4 for extracting differential signals Q ⁺ and Q ^{− of the} signal.

A phase detection circuit 120 removes high-frequency components from the quadrature detection circuit 121, the addition circuit 122 including adders 122a and 122b that add the I signal and the Q signal, and the output signal (phase difference signal) of the quadrature detection circuit 121. A switching control circuit 124 that switches the low-pass filter 123 and the quadrature detection circuit 121 to one for phase difference detection and one for amplitude difference detection is provided. Wherein the adder 122a adds the ^{Q +} signal of the ^{I +} signal and Q signal of the I signal, the adder 122b is, I of the I signal ^- the signal ^- Q of the signal and the Q signal to add.

  Reference numeral 130 denotes a correction control circuit which takes in the output signal of the low-pass filter 123 and generates a phase correction signal and an amplitude correction signal for the transmission circuit 111 and also generates a phase correction signal and an amplitude correction signal for the reception circuit 112. . Specifically, when a phase difference signal indicating a phase error arrives from the quadrature detection circuit 121 via the low-pass filter 123, this is used as a phase correction signal to shift the phase shifter PS1 of the transmission circuit 111 or the phase shift of the reception circuit 112. Output to the PS2 and adjust the amount of phase shift. When a phase difference signal indicating an amplitude error arrives from the quadrature detection circuit 121 via the low-pass filter 123, an amplitude error signal is generated corresponding to the signal, and this is used as an amplitude correction signal to transmit the transmission circuit 111. To the amplifier AMP2 on the Q signal side or the amplifier AMP4 on the Q signal side of the receiving circuit 112 to adjust the gains thereof. In this correction control circuit 130, a low-speed signal from which a high-frequency signal has been removed by the low-pass filter 123 is handled. Therefore, when performing digital processing here, a low-speed A / D converter can be used.

Reference numeral 140 denotes a monitor signal oscillation circuit that generates a monitor I signal and a monitor Q signal in the form of differential signals I ⁺ , I ⁻ , Q ⁺ , Q ⁻ , and three operational amplifiers OP1 to OP3 connected in cascade in the same phase. And an operational amplifier OP4 in which the input side is cascaded in the opposite phase to the output side of the operational amplifier OP3 and the output side is cascaded in the same phase to the input side of the operational amplifier OP1. Then, differential signals I ⁺ and I ^{− of the} monitor I signal are extracted from the output side of the operational amplifier OP2, and differential signals Q ⁺ and Q ^{− of the} monitor Q signal are extracted from the output side of the operational amplifier OP4.

A first switch circuit 150 includes four switches SW1 to SW4. The switch SW1 selects one of the Q ⁺ signal output from the reception circuit 112 and the Q ⁺ signal output from the single-phase / differential conversion circuit 114. The switch SW2 selects one of the Q ^- signal output from the receiving circuit 112 and the Q ^- signal output from the single-phase / differential conversion circuit 114. The switch SW3 selects one of the I ⁻ signal output from the receiving circuit 112 and the I ⁻ signal output from the delay circuit 140. The switch SW4 selects one of the I ⁺ signal output from the receiving circuit 112 and the I ⁺ signal output from the single-phase / differential conversion circuit 114.

A second switch circuit 160 includes four switches SW5 to SW8. The switches SW5 and SW6 connect the differential signals I ⁺ and I ⁻ of the monitor I signal to the differential signal line of the transmission I signal on the input side of the transmission circuit 111. The switches SW7 and SW8 connect the differential signals Q ⁺ and Q ⁻ of the monitor Q signal to the differential signal line of the transmission Q signal on the input side of the transmission circuit 111.

  FIG. 2 shows a specific example of the quadrature detection circuit 121 and the addition circuit 122. The quadrature detection circuit 121 includes a Gilbert cell circuit 121a, an output circuit 121b, and a current / voltage conversion circuit 121c.

  The Gilbert cell circuit 121a includes NMOS transistors MN1 to MN8, PMOS transistors MP1 and MP2, and current sources I1 and I2. The sources of the transistors MN1 and MN2 are commonly connected to the drains of the transistors MN5 and MN7, and the sources of the transistors MN3 and MN4 are commonly connected to the drains of the transistors MN6 and MN8. The sources of the transistors MN5 and MN6 are connected to the current source I1, and the sources of the transistors MN7 and MN8 are commonly connected to the current source I2. The gate and drain of the transistor MP1 are commonly connected to the drains of the transistors MN1 and MN3, and the gate and drain of the transistor MP2 are commonly connected to the drains of the transistors MN2 and MN4.

Then, the gate of the transistor MN1, MN4 is normal signal ^{I +} inputs of the I signal, to the gate of the transistor MN2, MN3 are inverted signal I of the I signal ^- to the input. The gate of transistor MN5 forward signal Q ⁺ is input Q signal, to the gate of transistor MN5 inverted signal Q of the Q signal ^- to the input. Further, the gate of the transistor MN7 is inverted signal I of the I signal ^- inverted signal Q and Q signals ^- entered signal obtained by adding by the adder 122a, the gate of the transistor MN8 is a normal signal I ⁺ of the I signal A signal obtained by adding the normal rotation signal Q ⁺ of the Q signal by the adder 121a is input.

  In the Gilbert cell circuit 121, when the phase error is detected, the current source I1 is operated by the switching control circuit 124, and the current source I2 is not operated. Thereby, the transistors MN5 and MN6 operate and the transistors MN7 and MN8 are turned off. Then, multiplication of the I signal and the Q signal, that is, the calculation of the above-described equation (4) is performed, and the calculation result is output to the output circuit 121b.

  On the other hand, when the amplitude error is detected, the current source I1 is deactivated by the switching control circuit 124, and the current source I2 is activated. As a result, the transistors MN5 and MN6 are turned off, and the transistors MN7 and MN8 operate. Then, the sum signal of the I signal and the Q signal represented by the above equation (6) and the reference I signal are multiplied to obtain a signal indicating the phase difference between the two, and the calculation result is the output circuit 121b. Is output.

  Thus, in the common Gilbert cell circuit 121, the phase error detection and the amplitude error detection phase error detection for the I signal and the Q signal are performed, so that the relative offset can be eliminated and the error detection can be performed with high accuracy. Can be realized.

  The output circuit 121b includes a PMOS transistor MP3 whose gate is controlled by the drain voltage of the transistor MP1 of the Gilbert cell circuit 121a, a PMOS transistor MP4 whose gate is controlled by the drain voltage of the transistor MP2, and NMOS transistors MN9 and MN10. And a mirror circuit. Then, a current corresponding to the difference between the drain voltage of the transistor MP1 and the drain voltage of the transistor MP2 of the Gilbert cell circuit 121a is output.

  The current / voltage conversion circuit 121c includes an operational amplifier OP5, a voltage source E1 that applies a reference voltage to the normal input terminal of the operational amplifier OP5, and a feedback resistor R1 connected between the inverting input terminal and the output terminal of the operational amplifier OP5. And a feedback capacitor C1, and converts the input current signal into a voltage signal and outputs it to the low-pass filter 123.

  FIG. 3 shows a modification of the quadrature detection circuit 121 and the addition circuit 122 described in FIG. In the adder circuit 122, the adder 122b includes resistors R2 and R3, and the adder 122a includes resistors R4 and R5. In the Gilbert cell circuit 121a, the transistors MP1 and MP2 as loads are replaced with resistors R6 and R7. The output circuit 121b is configured by a circuit including a resistor R8, PMOS transistors MP5, MP6, and MP7 constituting a current mirror circuit, and a common mode feedback circuit 121b1. The common mode feedback circuit 121b1 includes resistors R9 and R10, NMOS transistors MN11 and MN12, and an operational amplifier OP6. By applying the voltage of the power source E1 of the current / voltage conversion circuit 121c to the normal input terminal of the operational amplifier OP6, the common mode feedback circuit 121b1 The voltage of the output terminal P1 of the output circuit 121b is held at a voltage corresponding to the voltage of the power supply E1, and a DC offset is prevented from occurring there. In the output circuit 121b described in FIG. 2, a DC offset is generated at the output terminal P1, but this is avoided here. In the current / voltage conversion circuit 121c, a resistor R11 is added.

  FIG. 4 shows a specific example of the monitor signal oscillation circuit 140. Since the operational amplifiers OP1 to OP4 all have the same circuit and the same layout configuration, the operational amplifier OP1 will be described as a representative. The operational amplifier OP1 includes NMOS transistors MN21 to MN24, PMOS transistors MP21 and MP22, resistors R21 to R26, capacitors C21 and C22, and current sources I21 to I23. Transistors MN21 and MN22, resistors R21 and R22, and current source I21 form a differential circuit. The transistors MP21 and MN23, resistors R23 and R24, and the capacitor C21 constitute a load circuit on the normal output side, and the transistors MP22 and MN24, resistors R25 and R26, and the capacitor C22 constitute a load circuit on the inverted output side.

In this monitor signal oscillation circuit 140, all the operational amplifiers OP1 to OP4 have the same circuit and the same layout configuration, so that a highly accurate four-phase signal (I ⁺ = 0, I ⁻ = 2π, Q ⁺ = π, Q ⁻ = 3π / 4) can be taken out. And by making the constants of the resistors R23 to R26 and the capacitors C21 and C22 adjustable, it is possible to increase the degree of freedom in setting the gain, voltage amplitude, and harmonics of the four-phase signal.

<Transmission circuit IQ mismatch correction>
Next, the correction operation in the IQ mismatch correction circuit of the present invention will be described. FIG. 5 is a flowchart showing the IQ mismatch correction operation of the transmission circuit. First, the switch SW0 in the circuit of FIG. 1 is turned off (step S1), the switches SW1 and SW2 select the Q signals Q ⁺ and Q ⁻ output from the single-phase / differential conversion circuit 114, and the switches SW3 and SW4 are delayed. The I signals I ⁺ and I ⁻ output from the circuit 115 are switched to the selection side. Further, by turning on the switches SW5 to SW8, the transmission monitor I signals I ⁺ and I ⁻ and the transmission monitor Q signals Q ⁺ and Q ⁻ generated by the monitor signal oscillation circuit 140 are input to the transmission circuit 111.

As a result, the monitor I signals I ⁺ and I ⁻ and the monitor Q signals Q ⁺ and Q ⁻ generated by the monitor signal oscillation circuit 140 are input to the transmission circuit 111 of the modulation / demodulation circuit 110, and are orthogonally modulated to become a transmission RF signal. The envelope detection unit 113 converts the frequency from the RF signal to the baseband signal, and the single-phase / differential conversion unit 114 becomes the differential transmission monitor I signals I ⁺ and I ⁻ . The switches SW1 and SW2 switch the phase detection circuit 120 to the phase detection circuit 120. input. The transmission monitor I signals I ⁺ and I ⁻ output from the single-phase / differential converter 114 are delayed by π / 2 in the delay circuit 115 to become transmission monitor Q signals Q ⁺ and Q ⁻ , and the switch SW3 , SW4 to the phase detection circuit 120 (step S2).

  At this time, in the phase detection circuit 120, the current source I1 of the quadrature detection circuit 121 is operated by the switching control circuit 124, and the phase difference between the transmission monitor I signal and the transmission monitor Q signal affected by the transmission circuit 111 is detected. (Step S3), and a signal indicating the phase error of the transmission monitor Q signal is output from the low-pass filter 123 to the correction control circuit 130.

  The correction control circuit 130 takes in a signal indicating the phase error of the transmission monitor Q signal and determines whether or not the value is within the set range (allowable range) (step S4). If it is not within the set range, it is then compared to determine whether the phase of the transmission monitor Q signal is delayed or advanced from the set range (step S5). Then, when the transmission monitor Q signal is delayed, the phase shift amount of the phase shifter PS1 of the transmission circuit 111 is advanced by one stage so that the phase is advanced (step S6). If the transmission monitor Q signal is advanced, the phase shift amount of the phase shifter PS1 of the transmission circuit 111 is delayed by one stage so that the phase is delayed (step S7).

  Thereafter, the transmission monitor I signal and the transmission monitor Q signal are taken again (step S2), and when the phase error component of the transmission monitor Q signal is not within the set range, the same operation is repeated in steps S3 to S7. .

  If it is determined in step S4 that the phase error of the transmission monitor Q signal is within the set range, the process proceeds to amplitude detection (step S8). At this time, in the phase detection circuit 120, the switching control circuit 124 switches so that the current source I2 of the quadrature detection circuit 121 operates. Thereby, the phase difference between the signal obtained by adding the transmission monitor I signal and the transmission monitor Q signal and the transmission monitor I signal is detected, and a signal indicating the phase difference is output from the low-pass filter 123 to the correction control circuit 130.

  At this time, the correction control circuit 130 takes in a signal indicating this phase difference and generates amplitude error components of the transmission monitor I signal and the transmission monitor Q signal by the above-described method (FIG. 7). Then, it is determined whether or not the value of the amplitude error component (corresponding to B / A in FIG. 7) is within the setting range (within the allowable range) (step S9). If it is not within the set range, then it is compared and determined whether the amplitude of the transmission monitor Q signal is larger or smaller than the set range with respect to the amplitude of the transmission monitor I signal (step S10). When the amplitude of the transmission monitor Q signal is small, the gain of the amplifier AMP2 of the transmission circuit 111 is adjusted to be increased by one stage so that the amplitude is increased (step S11). On the contrary, when the amplitude of the transmission monitor Q signal is large, the gain of the amplifier AMP2 is adjusted to be lowered by one stage so that the amplitude becomes small (step S12).

  Thereafter, the transmission monitor I signal and the transmission monitor Q signal are taken again (step S13), and when the amplitude error component is not within the set range, the same operation is repeated in steps S9 to S13.

  If it is determined in step S9 that the amplitude error component is within the set range, the process proceeds to steps S14 and S15. If it is determined in step S15 that the phase difference is not within the set range, step S14 is performed. Returning to S5, if determined to be within the set range, the phase shift adjustment of the phase shifter PS1 and the gain adjustment of the amplifier AMP2 of the transmission circuit 111 are finished. Thereby, the IQ mismatch correction of the transmission circuit 111 is completed.

<Receiving circuit IQ mismatch correction>
FIG. 6 is a flowchart showing the IQ mismatch correction operation of the receiving circuit 112. At this time, it is assumed that the mismatch correction of the transmission circuit 111 has been completed. That is, it is assumed that the transmission circuit 111 has no IQ mismatch.

Here, the switch SW0 in the circuit of FIG. 1 is turned on (step S21). Further, the switches SW1 and SW2 select the reception monitor Q signals Q ⁺ and Q ⁻ output from the reception circuit 112, and the switches SW3 and SW4 select the reception monitor I signals I ⁺ and I ⁻ output from the reception circuit 112. Can be switched to. Further, by turning on the switches SW5 to SW8, the monitor I signals I ⁺ and I ⁻ and the monitor Q signals Q ⁺ and Q ⁻ generated by the monitor signal oscillation circuit 140 are input to the transmission circuit 111.

As a result, the monitor I signals I ⁺ , I ⁻ and the monitor Q signals Q ⁺ , Q ⁻ generated by the monitor signal oscillation circuit 140 are input to the transmission circuit 111 in which the IQ mismatch of the modulation / demodulation circuit 110 is corrected and quadrature modulated. The received RF signal is input to the receiving circuit 112 via the switch SW0 as a received RF signal, and is orthogonally demodulated to receive monitor I signals I ⁺ , I ⁻ and receive monitor Q signals Q ⁺ , Q ⁻ , and the switch SW1 Are input to the phase detection circuit 120 through .about.W4 (step S22).

  At this time, in the phase detection circuit 120, the switching control circuit 124 operates the current source I1 of the quadrature detection circuit 121, and the phase difference between the reception monitor I signal and the reception monitor Q signal is detected (step S23). A signal indicating the phase error of the reception monitor Q signal is output from the low-pass filter 123 to the correction control circuit 130.

  The correction control circuit 130 takes in a signal indicating the phase error of the reception monitor Q signal and determines whether or not the value is within the set range (within the allowable range) (step S24). If it is not within the set range, it is then compared to determine whether the phase of the reception monitor Q signal is delayed or advanced from the set range (step S25). Then, when the reception monitor Q signal is delayed, the phase shift amount of the phase shifter PS2 of the reception circuit 112 is advanced by one stage so that the phase is advanced (step S26). If the reception monitor Q signal is advanced, the phase shift amount of the phase shifter PS3 of the reception circuit 112 is delayed by one stage so that the phase is delayed (step S27).

  Thereafter, the reception monitor I signal and the reception monitor Q signal are taken again (step S22), and when the phase error component of the reception monitor Q signal is not within the set range, the same operation is repeated in steps S23 to S27. .

  If it is determined in step S24 that the phase error of the reception monitor Q signal is within the set range, the process proceeds to amplitude detection (step S28). At this time, in the phase detection circuit 120, the switching control circuit 124 switches so that the current source I2 of the quadrature detection circuit 121 operates. Thereby, the phase difference between the signal obtained by adding the reception monitor I signal and the reception monitor Q signal and the reception monitor I signal is detected, and a signal indicating the phase difference is output from the low-pass filter 123 to the correction control circuit 130.

  At this time, the correction control circuit 130 takes in a signal indicating this phase difference and generates amplitude error components of the reception monitor I signal and the reception monitor Q signal by the above-described method (FIG. 7). Then, it is determined whether or not the value of the amplitude error component (corresponding to B / A in FIG. 7) is within the setting range (within the allowable range) (step S29). If it is not within the set range, then it is determined whether the amplitude of the reception monitor Q signal is larger or smaller than the set range with respect to the amplitude of the reception monitor I signal (step S30). Then, when the amplitude of the reception monitor Q signal is small, the gain of the amplifier AMP3 of the reception circuit 112 is adjusted to be increased by one stage so that the amplitude becomes large (step S31). On the contrary, when the amplitude of the reception monitor Q signal is large, the gain of the amplifier AMP4 is adjusted to be lowered by one stage so that the amplitude becomes small (step S32).

  Thereafter, the reception monitor I signal and the reception monitor Q signal are taken again (step S33), and when the amplitude error component is not within the set range, the same operation is repeated in steps S29 to S33.

  If it is determined in step S29 that the amplitude error component is within the set range, the process proceeds to steps S34 and S35. If it is determined in step S35 that the phase difference is not within the set range, step S34 is performed. Returning to S25, if determined to be within the set range, the phase shift adjustment of the phase shifter PS2 and the gain adjustment of the amplifier AMP4 of the reception circuit 112 are finished. Thereby, the IQ mismatch correction of the receiving circuit 112 is completed.

  In the above-described embodiment, the envelope detector (frequency conversion circuit) 113 extracts the transmission monitor I signal from the received RF signal. However, the transmission monitor Q signal is extracted instead of the transmission monitor I signal. May be. At this time, the transmission I signal is extracted from the delay circuit 115. Therefore, it is necessary to replace the switches SW1 and SW3 and to replace the switches SW2 and SW4.

100: RF front circuit 110: Transmission / reception circuit, 111: Transmission circuit, 112: Reception circuit 120: Phase detection circuit, 121: Quadrature detection circuit, 121a: Gilbert cell circuit, 121b: Output circuit, 121c: Current / voltage conversion circuit, 122: addition circuit 130: correction control circuit 140: monitor signal oscillation circuit 150: first switch circuit 160: second switch circuit 200: baseband circuit 210: digital baseband circuit 211: FFT circuit 212: arithmetic circuit 213: IQ signal oscillation circuit

Claims (8)

IQ mismatch of a transmission / reception apparatus including a transmission circuit that inputs a transmission I signal and a transmission Q signal that are orthogonal to each other, adds after performing quadrature modulation with the transmission I local signal and the transmission Q local signal, and transmits as a transmission RF signal In the correction method,
An internally generated monitor I signal and monitor Q signal are input to the transmission circuit and orthogonally modulated and then added to generate a monitor RF signal,
The monitor RF signal is frequency converted to the frequency of the baseband signal to generate one signal of a transmission monitor I signal and a transmission monitor Q signal, and the generated one signal is subjected to delay processing to generate the transmission monitor I signal. And the other of the transmission monitor Q signal,
Detecting a transmission-side phase error between the transmission monitor I signal and the transmission monitor Q signal;
Based on a phase difference between a signal obtained by adding the transmission monitor I signal and the transmission monitor Q signal and the transmission monitor I signal or the transmission monitor Q signal, a transmission-side amplitude error between the transmission monitor I signal and the transmission monitor Q signal. Detect
A phase shift amount of a phase shifter of the transmission circuit is controlled based on the transmission side phase error to correct a phase difference between the transmission I local signal and the transmission Q local signal, and the transmission circuit is based on the transmission side amplitude error. A gain difference between the transmission I signal and the transmission Q signal is controlled by controlling the amplifier of
An IQ mismatch correction method for a transmission / reception device. 2. The transmission circuit according to claim 1, wherein the IQ mismatch is corrected, and the reception RF signal received from the transmission circuit is orthogonally demodulated by the reception I local signal and the reception Q local signal and separated into a reception I signal and a reception Q signal. An IQ mismatch correction method for a transmission / reception device comprising:
The monitor I signal and the monitor Q signal are input to the transmission circuit in which IQ mismatch is corrected, the transmission RF signal is output from the transmission circuit, the transmission RF signal is received by the reception circuit, and the reception The reception monitor I signal and the reception monitor Q signal are generated by performing orthogonal demodulation with the I local signal and the reception Q local signal,
Detecting a reception-side phase error between the reception monitor I signal and the reception monitor Q signal;
Based on the phase difference between the signal obtained by adding the reception monitor I signal and the reception monitor Q signal and the reception monitor I signal or the reception monitor Q signal, a reception-side amplitude error between the reception monitor I signal and the reception monitor Q signal. Detect
A phase shift amount of a phase shifter of the reception circuit is controlled based on the reception side phase error to correct a phase difference between the reception I local signal and the reception Q local signal, and the reception circuit is based on the reception side amplitude error. A gain difference between the received I signal and the received Q signal is controlled by controlling a gain of the amplifier;
An IQ mismatch correction method for a transmission / reception device. In a transmission / reception apparatus including a transmission circuit that inputs a transmission I signal and a transmission Q signal that are orthogonal to each other, adds after performing quadrature modulation with the transmission I local signal and the transmission Q local signal, and transmits as a transmission RF signal.
A monitor signal oscillation circuit for generating a monitor I signal and a monitor Q signal;
The monitor I signal output from the monitor signal oscillation circuit and the monitor Q signal are input to the transmission circuit and quadrature modulated and then added to the monitor RF signal, and the frequency is converted to transmit the monitor I signal and the transmission. A frequency conversion circuit for generating one of the monitor Q signals;
A delay circuit that delays the one signal output from the frequency conversion circuit to generate the other of the transmission monitor I signal and the transmission monitor Q signal;
A transmission side first phase error signal is generated by detecting a phase difference between the transmission monitor I signal and the transmission monitor Q signal, and a signal obtained by adding the transmission monitor I signal and the transmission monitor Q signal to the transmission monitor A phase detection circuit that detects a phase difference from the I signal or the transmission monitor Q signal and generates a transmission-side second phase error signal;
Based on the first phase error signal on the transmission side obtained by the phase detection circuit, the phase shift amount of the phase shifter of the transmission circuit is controlled to correct the phase difference between the transmission I local signal and the transmission Q local signal. A transmission side amplitude error signal of the transmission I signal and the transmission Q signal is obtained based on the transmission side second phase error signal obtained by the phase detection circuit, and an amplifier of the transmission circuit is obtained based on the transmission side amplitude error signal. A correction control circuit for controlling the gain of the transmission I signal and the transmission Q signal by controlling the gain of the transmission I signal,
A transmission / reception apparatus comprising: In the transmission / reception apparatus comprising the transmission circuit according to claim 3 and the reception circuit corrected for IQ mismatch,
The reception circuit receives the monitor RF signal corrected from the IQ mismatch output from the transmission circuit, performs quadrature demodulation with the reception I local signal and the reception Q local signal, and receives the reception monitor I signal and the reception monitor Q signal. Produces
The phase detection circuit further detects a phase difference between the reception monitor I signal and the reception monitor Q signal to generate a reception-side first phase error signal, and also receives the reception monitor I signal and the reception monitor Q signal. , And the reception monitor I signal or the reception monitor Q signal is detected to generate a reception-side second phase error signal,
The correction control circuit further controls the amount of phase shift of the phase shifter of the receiving circuit based on the first phase error signal on the receiving side obtained by the phase detecting circuit, and the received I local signal and the received Q A phase difference between local signals is corrected, a reception side amplitude error signal between the reception I signal and the reception Q signal is obtained based on the reception side second phase error signal obtained by the phase detection circuit, and the reception side amplitude error is obtained. Controlling the gain of the amplifier of the receiving circuit based on the signal to correct the gain of the received I signal and the received Q signal;
A transmitting / receiving apparatus characterized by the above. The transmission / reception apparatus according to claim 3,
The transmission / reception apparatus, wherein the correction control circuit includes a first table indicating a relationship between the transmission-side second phase error and the transmission-side amplitude error. The transmission / reception apparatus according to claim 4,
The correction control circuit includes a first table indicating a relationship between the transmission-side second phase error and the transmission-side amplitude error, and a second table indicating a relationship between the reception-side second phase error and the reception-side amplitude error. A transmission / reception device comprising: The transmission / reception apparatus according to claim 3,
The phase detection circuit includes an adder that adds the transmission monitor I signal and the transmission monitor Q signal at a first timing, and multiplies the transmission monitor I signal and the transmission monitor Q signal at a second timing. A quadrature detection circuit that generates a first phase error signal and multiplies the output of the adder by the transmission monitor I signal or the transmission monitor Q signal at the first timing to generate the transmission-side second phase difference signal. And a transmission / reception apparatus comprising: The transmission / reception apparatus according to claim 4,
The adder of the phase detection circuit further adds the reception monitor I signal and the reception monitor Q signal at a third timing,
The quadrature detection circuit of the phase detection circuit further generates the reception-side first phase error signal by multiplying the reception monitor I signal and the reception monitor Q signal at a fourth timing, and at the third timing, Multiplying the output of the adder and the reception monitor I signal or the reception monitor Q signal to generate the reception-side second phase difference signal;
A transmitting / receiving apparatus characterized by the above.

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