JP2016038550A - Method for designing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To create an accurate resist model and an etching model.SOLUTION: A method for designing a semiconductor device includes: a step (S12) of creating a resist simulation model by measuring a feature of a resist pattern; a step (S14) of forming a model pattern by etching a work piece by using the resist pattern as a mask; a step (S17) of identifying a height position of a resist pattern having a pattern size nearer to the model pattern by using the resist simulation model; a step (S18) of creating a resist model by associating a pattern size of the resist pattern at the identified height position with the size of a photomask; and a step (S19) of creating an etching model by associating the pattern size of the resist pattern at the identified height position with the size of the model pattern.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a method for designing a semiconductor device, and more particularly to a method for generating a resist model and an etching model.

  In designing a semiconductor device, circuit data is first created by circuit design, and then layout data is created by performing layout design based on the circuit data. However, even if a photomask having a mask pattern according to the layout data is manufactured, the resist pattern obtained by exposure does not match the mask pattern, and a predetermined deformation occurs. Further, when etching is performed on the film to be processed using the deformed resist pattern, the obtained etching pattern does not match the resist pattern, and further deformation occurs. In order to obtain an etching pattern having a desired shape, it is necessary to perform correction called optical proximity correction (OPC) on the mask pattern. In addition to lithography, it is called process proximity effect correction (PPC: Process Proximity Correction) in the sense of correcting shape / dimension shifts in other processes such as etching and film formation. In some cases, OPC and PPC are used separately, but here, the technique of correcting the mask dimension to obtain a desired dimension on the wafer is called OPC: optical proximity effect correction.

  In the optical proximity effect correction, it is necessary to reversely calculate a resist pattern from an etching pattern having a target shape, and further to reversely calculate a mask pattern from the resist pattern. In order to realize this, information indicating the correlation between the mask pattern and the resist pattern and information indicating the correlation between the resist pattern and the etching pattern are required. The former information is called a resist model, and the latter information is called an etching model.

  The resist model is composed of data indicating what resist pattern having a predetermined shape and size can be obtained by a mask pattern having a predetermined shape and size. Similarly, the etching model is constituted by data indicating what etching pattern having a predetermined shape and size can be obtained by a resist pattern having a predetermined shape and size.

3D Resist Profile Modeling for OPC Applications, Optical Microlithography XXVI, edited by Will Conley, Proc. Of SPIE Vol. 8683, 868318, March 2013, 8683_43.pdf

  However, in the conventional resist model and etching model, the height position for specifying the size of the resist pattern is fixed at the bottom position (the lower surface position of the resist pattern), so a correct correlation may be obtained depending on the actual shape of the resist pattern. Couldn't get.

  Non-Patent Document 1 describes a method for evaluating the size at a height of 30% of the film thickness of a resist pattern. However, a technique for predicting disconnection after etching using a contour of the resist pattern film thickness is shown. When the contrast of the light intensity is low and the resist shape deteriorates significantly, a good correlation is obtained between the thickness of the resist remaining film and the disconnection of the etching. Therefore, the contour is adjusted with a specific film thickness (height from the substrate). By calculating, it can be predicted whether or not disconnection will occur after etching. However, the relationship between the contour due to the film thickness and the dimension after etching has not been shown. When the contrast of light intensity is low and the resist film is reduced, it is possible to predict disconnection after etching by considering the progress of the resist surface in the height direction in etching. (If the amount of the resist remaining film is less than the amount of progress in the vertical direction of the resist surface in the etching time, the wire breaks after etching.) On the other hand, when the contrast of light intensity is very high and a rectangular resist shape is obtained, Considering the progress in the lateral direction of the resist surface, the dimension after etching can be predicted. When the resist shape has a taper, the resist contour and the resist bottom contour for predicting the disconnection after the etching cannot always obtain the correct correlation between the resist dimension and the post-etching dimension.

  The method of designing a semiconductor device according to the present invention includes a step of forming a photoresist on a film to be processed formed on a semiconductor substrate, and exposing and removing the photoresist using a photomask, thereby leaving the remaining photoresist. Forming a resist pattern comprising: forming a resist simulation model by measuring the shape of the resist pattern; and etching the workpiece using the resist pattern as a mask, thereby remaining the object to be processed. Forming a model pattern made of a processed film; using the resist simulation model; specifying a height position of the resist pattern before etching having a pattern size close to the model pattern; and specifying the specified height The resist pattern at the position By associating the pattern size of the pattern and the size of the photomask, by associating the step of creating a resist model, and the pattern size of the resist pattern at the specified height position and the size of the model pattern, And a step of creating an etching model.

  According to the present invention, since the pattern size at the optimum height position of the resist pattern is evaluated, it is possible to generate more accurate resist model and etching model.

It is a flowchart for demonstrating the production | generation method of mask data. It is a flowchart for demonstrating in detail step S3 in 1st Embodiment. It is sectional drawing which shows the device structure obtained by step S10. 5 is a cross-sectional view for explaining a step of exposing the photoresist 3 using the photomask 4. FIG. It is sectional drawing which shows the device structure obtained by step S11. 5 is a cross-sectional view for explaining the shape of a resist pattern 5. FIG. It is an example of the relationship between the height position and size of the resist pattern 5 shown by the resist simulation model. It is sectional drawing which shows the device structure obtained by step S14. It is a graph which shows an example of a temporary etching model. (A) is sectional drawing which shows the cross-sectional shape of resist pattern 5A, 5B in different exposure conditions (condition A and condition B), (b) is model pattern 6A, 6B patterned using resist pattern 5A, 5B. It is sectional drawing which shows the cross-sectional shape. It is a graph which shows the relationship between the space width of the resist pattern 5, and the shift amount for every height position H1-H4. It is a graph which shows an example of a resist model. It is a flowchart for demonstrating in detail step S3 in 2nd Embodiment.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a flowchart for explaining a mask data generation method. The mask data is data indicating the position and shape of a mask pattern (photomask opening) formed on the photomask.

  First, circuit data is generated by designing a circuit for realizing a desired function (step S1), and then layout data is generated by designing a layout based on the circuit data (step S2). Layout data is data indicating the position and shape of a film to be processed to be formed on a semiconductor substrate. As already described, the layout data cannot be used as it is as mask data. In order to process the layout data into mask data, OPC processing (step S4) for performing optical proximity effect correction is required. The OPC process is performed using layout data, a resist model, and an etching model. The resist model and the etching model are created in the model creation process (step S3). Details of the model creation process will be described later.

  In the OPC process, mask data is generated by arranging an optical proximity correction pattern (OPC pattern) in layout data. Next, the mask data obtained in step S4 is verified to check whether the mask rule is satisfied (step S5). As a result, if it is determined that there is a portion that does not satisfy the mask rule, the process returns to step S4 and the OPC pattern is rearranged.

  If it is determined in step S5 that the mask rule is satisfied, a simulation pattern is calculated from the light intensity distribution during the exposure process by lithography simulation for the mask data after the OPC pattern is arranged (step S6). The simulation pattern is a predicted shape of the device pattern by lithography simulation. Thereafter, the position and size of the simulation pattern are checked, and the expected completion size and formation margin of the device pattern are verified to determine whether the obtained device pattern is appropriate (step S7).

  If it is determined in step S7 that it is outside the allowable range, the process returns to step S4 and the OPC pattern is rearranged. On the other hand, if it is determined in step S7 that it is within the allowable range, the arrangement of the OPC pattern so far is completed and the obtained mask data is output (step S8).

  The above is a rough flow for generating mask data. Next, the model creation in step S3 will be described in detail.

  As described above, a resist model and an etching model are created in step S3. The resist model is information indicating the correlation between the mask pattern and the resist pattern, and the etching model is information indicating the correlation between the resist pattern and the etching pattern.

  FIG. 2 is a flowchart for explaining step S3 in the first embodiment in more detail.

  As shown in FIG. 2, step S3 in the first embodiment is composed of 10 steps including steps S10 to S19. In addition, FIGS. 3 to 12 show an image of processing performed in several steps and graphs for explanation.

  First, as shown in FIG. 3, a film to be processed 2 is formed on a semiconductor substrate 1, and a photoresist 3 is formed on the surface of the film to be processed 2 (step S10). It is necessary to use the same film 2 and photoresist 3 as those used in the actual mass production process.

  Next, as shown in FIG. 4, the photoresist 3 is exposed using the photomask 4, thereby forming the resist pattern 5 shown in FIG. 5 (step S11). The photoresist 3 may be a positive type or a negative type. In either case, the resist pattern 5 is formed by removing an uncured portion. Although only two resist patterns 5 having the same shape are shown in FIG. 5, in practice, a large number of resist patterns 5 having different sizes and shapes are formed. Then, the size of the formed resist pattern 5 is measured.

  In the measurement of the resist pattern 5, it is necessary to actually measure the size of the resist pattern 5 at different height positions. This is because the actual cross-sectional shape of the resist pattern 5 is not a perfect rectangle, but is a substantially trapezoid having a taper as shown in FIG. 6, and the size varies depending on the height position. In the measurement of the resist pattern 5, it is necessary to measure not only the size of each resist pattern 5 but also the space width between adjacent resist patterns 5. This is because the shape and size of the resist pattern 5 vary greatly depending on the space width.

  Next, a resist simulation model is created based on the shape, size, and space width of the resist pattern 5 measured in step S11 (step S12). The resist simulation model is a correlation model indicating the relationship between the height position and size of the resist pattern 5.

  FIG. 7 is an example of the relationship between the height position and size of the resist pattern 5 indicated by the resist simulation model. The height position of the resist pattern 5 is defined by the distance in the vertical direction with respect to the bottom of the resist pattern 5, that is, the interface position with the film 2 to be processed. Reference numerals A and B shown in FIG. 7 are resist simulation models different from each other. Even when the photoresist 3 having the same shape is used, the resist simulation model changes when exposure conditions in photolithography are different. . In the example shown in FIG. 7, all the resist simulation models have the same size at the bottom position (the lower surface position of the resist pattern 5), but the resist simulation model in the condition B is more preferable than the resist simulation model in the condition A. Since the size change according to the height position of the resist pattern 5 is large, it can be seen that the size difference increases as the position increases.

  By using such a resist simulation model, the size of the resist pattern 5 at an arbitrary height position can be specified. FIG. 7 shows that in the resist simulation model of condition A, the size of the resist pattern 5 at the height position Ha is Xa.

  Next, the size at a plurality of height positions of the resist pattern 5 is calculated based on the resist simulation model (step S13). As an example, assuming that the resist height H relative to the bottom of the resist pattern 5 is 100, as shown in FIG. 6, the resist pattern dimension (M1) at the resist bottom (H1 = 0) and H2 = 25 The resist pattern dimension (M2), the resist pattern dimension (M3) at H3 = 50, and the resist pattern dimension (M4) at H4 = 75 are calculated.

  Next, the film to be processed 2 is patterned by actually performing dry etching using the resist pattern 5. Thereby, as shown in FIG. 8, the model pattern 6 which consists of the to-be-processed film | membrane 2 which remains is formed (step S14). Then, the size of the formed model pattern 6 is measured.

  Next, a temporary etching model is created by associating the actually measured size of the model pattern 6 with the size of the resist pattern 5 for each height position (step S15). In the above example, since the resist pattern 5 is divided into four in the height direction, the size of the resist pattern 5 corresponding to each of the height positions H1 to H4 and the model pattern 6 are also generated for the generated temporary etching model. The size is related. That is, four temporary etching models are generated.

  FIG. 9 is a graph showing an example of a temporary etching model.

  In the graph shown in FIG. 9, the horizontal axis is the size of the resist pattern 5, the vertical axis is the size of the model pattern 6, and the measured values are plotted. Since the measurement value of the resist pattern 5 includes errors depending on the measurement height, the result of calibration so that these errors are minimized is displayed as an approximate curve. In this example, since a temporary etching model is generated for each of the height positions H1 to H4 of the resist pattern 5, there are four approximate curves.

  Next, the size of the four resist patterns 5 is calculated from the size of the model pattern 6 using the four temporary etching models (step S16). The calculated size of the resist pattern 5 indicates the size of the resist pattern 5 at each of the height positions H1 to H4.

  Next, an optimum resist pattern is selected from the calculated four resist patterns (step S17). The optimum resist pattern is selected by selecting a resist pattern having the smallest “shift amount”. The shift amount is a half value of the difference between the size of the resist pattern 5 and the size of the model pattern 6. Here, the shift amount will be described with reference to the drawings.

  FIG. 10A is a cross-sectional view showing the cross-sectional shapes of the resist patterns 5A and 5B under different exposure conditions (condition A and condition B), and FIG. 10B is a model patterned using the resist patterns 5A and 5B. It is sectional drawing which shows the cross-sectional shape of pattern 6A, 6B.

  As shown in FIG. 10A, a resist pattern 5A according to condition A and a resist pattern 5B according to condition B are formed on the surface of the film 2 to be processed on the semiconductor substrate 1. The resist height position Ha and the size Xa shown in FIG. 10A correspond to the height position Ha and the size Xa shown in FIG. 7, respectively. In this example, the bottom dimension XAb of the resist pattern 5A and the bottom dimension XBb of the resist pattern 5B are the same value.

  When dry etching is performed using such resist patterns 5A and 5B, as shown in FIG. 10B, the portion of the film 2 to be processed that is not covered with the resist patterns 5A and 5B is removed, and the remaining film to be processed is removed. Model patterns 6A and 6B are formed by the processed film 2. Here, since the resist patterns 5A and 5B as masks have different shapes, the model patterns 6A and 6B to be formed have different sizes. The half value of the difference between the size of the resist patterns 5A and 5B and the size of the model patterns 6A and 6B is defined as the shift amount.

  That is, when the size of the model pattern 6A formed using the resist pattern 5A is YAb, the shift amount X1 of the model pattern 6A is X1 = (XAb−YAb) / 2. Similarly, if the size of the model pattern 6B formed using the resist pattern 5B is YBb, the shift amount X2 of the model pattern 6B is X2 = (XBb−YBb) / 2. As shown in FIG. 10A, compared to the resist pattern 5A, the resist pattern 5B has a tapered shape in which the size greatly decreases as the height position increases. For this reason, the shift amount X2 of the model pattern 6B formed using the resist pattern 5B is larger than the shift amount X1 of the model pattern 6A formed using the resist pattern 5A.

  10A and 10B, the shift amount related to the bottom positions of the resist patterns 5A and 5B has been described. However, the shift amount differs depending on the height positions of the resist patterns 5A and 5B. In step S17, a shift amount for each height position is calculated, and an optimum resist pattern is selected based on the calculated shift amount.

  FIG. 11 is a graph showing the relationship between the space width of the resist pattern 5 and the shift amount for each of the height positions H1 to H4.

  The values shown in FIG. 11 are the root mean square (RMS) of the calculated values obtained by calculating the shift amount for each of the height positions H1 to H4 for the plurality of resist patterns 5. In the example shown in FIG. 11, since the shift amount at the height position H3 is the smallest, the height position H3 is selected as the optimum height position of the resist pattern 5.

  Then, a resist model is created using the size of the resist pattern 5 at the selected height position (step S18). Further, an etching model is created using the created resist model (step S19).

  FIG. 12 is a graph showing an example of a resist model.

  In the graph shown in FIG. 12, the horizontal axis is the design dimension of the pattern in the layout design, and the vertical axis is the measurement value of the resist pattern 5. Each measurement value is plotted. FIG. 12 shows an approximate curve similar to that in FIG. 9, and OPC processing in layout design is performed based on this approximate curve. Here, since one resist model is selected based on the optimal height position of the resist pattern 5, there is only one approximate curve.

  As described above, in the first embodiment, the optimum height position of the resist pattern 5 is selected, and the resist model and the etching model are generated based on this. Thereby, it is possible to improve the placement accuracy of the OPC pattern. In the first embodiment, one value of the height H (H1 to H4) is used. However, an average value can be used for a certain width ΔH (ΔH1 to ΔH4) at the height H. . In the OPC model, averaging in the height direction, which is a contour calculation, is a commonly used technique. For example, the vertical averaging method is often used when it is desired to take into account the vertical diffusion of the acid in the chemically amplified resist and the variation in focus. Here, averaging is performed within a certain range in the sense that the effective dimension of the resist pattern that actually worked as an etching mask is used from the start to the end of etching.

  Next, a second embodiment will be described.

  FIG. 13 is a flowchart for explaining step S3 in the second embodiment in more detail.

  As shown in FIG. 13, step S3 in the second embodiment is configured by 10 steps including steps S20 to S29. Of these steps, steps S20 to S23 are the same as steps S10 to S13 shown in FIG. Next, a resist model is created for each height position from the size for each height position of the resist pattern 5 obtained in step S23 (step S24). In the above example, since the sizes M1 to M4 are calculated for the four height positions H1 to H4, four resist models are created.

  Step S25 is the same as step S14 described above, and the film to be processed 2 is patterned by actually performing dry etching using the resist pattern 5. Then, the size of the formed model pattern 6 is measured.

  Next, an etching model for each height position is created from the actually measured size of the model pattern 6 and the four resist models generated in step S24 (step S26). In this example, since four height positions H1 to H4 are defined, four etching models are created for one height position.

  Further, for each of the sizes M1 to M4 corresponding to the height positions H1 to H4, a virtual mask pattern at each height position is calculated using four resist models having different height positions (step S27). Here, since four virtual mask patterns are calculated for each of four height positions, a total of 16 virtual mask patterns are calculated. The virtual mask pattern is a virtual pattern used in the next step S28 and is different from an actual mask pattern.

  Next, one virtual mask pattern (optimum virtual mask pattern) having the smallest dimensional shift RMS in the 16 calculated virtual mask patterns and the model pattern is selected (step S28). Then, the resist model and the etching model for which the optimum virtual mask pattern is calculated are selected as models used for the OPC pattern arrangement (step S29).

  As described above, in the second embodiment, after creating 16 virtual mask patterns based on the models (resist model and etching model) created for each resist height, the optimum virtual mask pattern is selected. ing. The resist model and the etching model, which are the basis for calculating the optimum virtual mask pattern, are both optimum models in which the dimensional shift from the model pattern is the smallest. Therefore, according to the second embodiment, there is an effect of further improving the OPC pattern placement accuracy as compared with the first embodiment in which the optimum model is only the resist model.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Processed film 3 Photoresist 4 Photomask 5, 5A, 5B Resist pattern 6, 6A, 6B Model pattern H1-H4 Height position M1-M4, Xa Size X1, X2 Shift amount XAb, XBb Bottom dimension

Claims (6)

Forming a photoresist on a film to be processed formed on a semiconductor substrate;
Forming a resist pattern comprising the remaining photoresist by exposing and removing the photoresist using a photomask; and
Creating a resist simulation model by measuring the shape of the resist pattern;
Etching the workpiece with the resist pattern as a mask to form a model pattern made of the remaining workpiece film; and
Identifying the height position of the resist pattern before etching having a pattern size close to the model pattern using the resist simulation model;
Creating a resist model by associating the pattern size of the resist pattern at the specified height position with the size of the photomask;
And a step of creating an etching model by associating a pattern size of the resist pattern at the specified height position with a size of the model pattern.   2. The method of designing a semiconductor device according to claim 1, wherein the resist simulation model includes information indicating a relationship between a height position of the resist pattern and a pattern size.   The step of specifying the height position includes calculating a pattern size at a plurality of height positions of the resist pattern using the resist simulation model, and selecting one pattern size from the calculated pattern sizes. The method for designing a semiconductor device according to claim 2, further comprising a selecting step.   4. The method of designing a semiconductor device according to claim 3, wherein the selecting step selects a pattern size closest to the model pattern from the calculated pattern sizes.   5. The semiconductor device according to claim 1, further comprising a step of associating a plurality of pattern sizes at different height positions of the resist pattern before etching with the size of the photomask. 6. Design method. Determining circuit data by circuit design; and
Generating layout data by performing layout design based on the circuit data;
The design of a semiconductor device according to claim 1, further comprising a step of performing optical proximity effect correction on the layout data using the resist model and the etching model. Method.

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