JP2016035978A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that efficiently protects a signal line from noise in a memory area where a plurality of memory cells are formed.SOLUTION: A semiconductor device comprises: a plurality of memory cells; a first power line for supplying a substantially constant first power supply voltage to one ends of the plurality of memory cells; a first signal line that propagates a first signal of a substantially constant potential; and a first shield wiring that extends adjacently to the first signal line, and that is supplied with the first power supply voltage from the first power line.SELECTED DRAWING: Figure 8

Description

  The present invention relates to a semiconductor device. In particular, the present invention relates to a semiconductor device having shield wiring.

  In recent years, various internal power supply voltages have been generated and used in semiconductor memories in order to achieve high-speed operation and low power consumption. A circuit that generates an internal power supply voltage requires a signal indicating a reference potential.

  Patent Document 1 discloses that a low-potential-side power supply VSS applied from the outside is supplied to a shield wiring of a wiring that transmits an internal reference potential VBREF.

Japanese Patent Application Laid-Open No. 07-106517

  The disclosure of the above prior art document is incorporated herein by reference. The following analysis was made by the present inventors.

  In a dynamic random access memory (DRAM), which is one of the typical semiconductor memories, different power supply voltages are used for circuits arranged in a memory area where a large number of memory elements are arranged and circuits outside the memory area. May be used. Since the memory area is large, a plurality of power generation circuits that generate power supply voltages used in the memory area are distributed and arranged at various locations in the memory area.

  Since each of the plurality of power generation circuits requires a reference voltage signal, it is necessary to route a reference voltage signal line for supplying the reference voltage signal to each power generation circuit in the memory area. Therefore, it is desired to efficiently protect the reference voltage signal line from noise in the memory area. In addition to the reference voltage signal line, other signals (for example, bias signals) that are routed within the memory area and need to be held at a substantially constant level are the same as the reference voltage signal. The configuration of is desired.

  According to a first aspect of the present invention, a plurality of memory cells, a first power supply line for supplying a substantially constant first power supply voltage to one end of the plurality of memory cells, and a substantially constant potential A first signal line that propagates the first signal and a shield wiring that extends adjacent to the first signal line, and the first power supply voltage is supplied from the first power supply line. There is provided a semiconductor device including a first shield wiring.

  According to one aspect of the present invention, a semiconductor device that contributes to efficiently protecting a signal line from noise in a memory area is provided.

1 is a block diagram illustrating an example of a schematic configuration of a semiconductor memory according to a first embodiment. It is a plane schematic diagram which shows an example of the chip layout of a semiconductor memory. It is an example of the enlarged view of the area | region A enclosed with the dotted line of FIG. It is a figure which shows an example of the circuit structure of a cell array. It is a figure which shows an example of the cross-sectional schematic diagram of a memory cell. It is a figure which shows an example of the circuit diagram of a 2nd power generation circuit. It is a figure which shows an example of the circuit diagram of an antifuse circuit. It is a figure which shows an example of the layout on a cell array. It is a figure which shows an example of another layout on a cell array. It is a figure which shows an example of another layout on a cell array. It is a plane schematic diagram which shows an example of another chip layout of a semiconductor memory. It is a plane schematic diagram which shows an example of another chip layout of a semiconductor memory.

  First, an outline of one embodiment will be described. Note that the reference numerals of the drawings attached to the outline are attached to the respective elements for convenience as an example for facilitating understanding, and the description of the outline is not intended to be any limitation.

  A semiconductor device according to an embodiment has a configuration in which a reference voltage signal and a bias signal routed through a memory area are more effectively shielded from noise.

  When the reference voltage signal line routed in the memory area is shielded by the low-potential side power supply voltage VSS used in the memory area, each circuit in the memory area operates frequently, and the memory area low The potential-side power supply voltage VSS may frequently fluctuate. As a result, noise may be superimposed on the reference voltage signal.

  On the other hand, it is also possible to shield the reference voltage signal line routed in the memory area by using the low-potential side power supply voltage VSS used in the circuit outside the memory area. For example, the low potential side power supply voltage VSS of the reference voltage generating circuit is relatively stable. However, in this case, it is necessary to draw unnecessary power lines into the memory area, and the wiring width of the shield wiring cannot be increased, and the resistance value of the shield wiring becomes high. As a result, the shielding effect of the shield wiring may be reduced.

  The semiconductor device according to an embodiment uses a plate voltage VPLT which is a potential of one electrode of a DRAM memory cell as a potential of a shield wiring for a reference voltage signal or a bias signal. The plate voltage VPLT is supplied to the memory cell via a plate-like electrode (plate electrode) covering the cell array. Therefore, the plate electrode has a large capacity. Therefore, it is almost impossible to change the plate voltage VPLT even when the circuit in the memory area operates. In addition, a large number of power supply lines for supplying power to the plate electrodes are originally arranged in the memory area. Therefore, the configuration of the semiconductor device according to the embodiment using the plate voltage VPLT for the shield wiring for the reference voltage signal or the like can more effectively shield the reference voltage signal and the bias signal routed through the memory area from noise. it can.

  In the description of the present specification and claims, “constant voltage” and “constant potential” mean “substantially constant voltage” and “substantially constant potential”.

[First Embodiment]
A first embodiment will be described with reference to the drawings.

  FIG. 1 is a block diagram illustrating an example of a schematic configuration of a semiconductor memory 1 according to the first embodiment. In addition, in each drawing, the same code | symbol is attached | subjected to the same component and the description is abbreviate | omitted.

  The semiconductor memory 1 has a peripheral circuit area 100 and a memory area 200.

  The semiconductor memory 1 includes an input terminal that receives an input signal INPUT supplied to the semiconductor memory 1 from the outside. The input signal INPUT includes a clock, an address, a command, data, and the like. However, in FIG. 1, these signals are collectively shown as one input signal INPUT for simplification.

  The semiconductor memory 1 includes an output terminal that outputs an output signal OUTPUT to the outside. The output signal OUTPUT includes data, a data strobe signal, and the like. Similarly to the input signal INPUT, the output signal is simply expressed as one output signal OUTPUT.

  The semiconductor memory 1 includes a power supply terminal that receives power supplies VDD and VSS from the outside.

  The access control circuit 11 is a circuit for accessing the memory area 200. The access control circuit 11 includes circuits such as a command decoder, an address buffer, a clock generation circuit, and a data input / output circuit.

  The access control circuit 11 generates an array control signal ACTL according to an input signal INPUT supplied from the outside, and supplies it to the in-array control circuit 21. The access control circuit 11 receives the array output signal AOUT from the intra-array control circuit 21.

  The array control signal ACTL includes, for example, various internal operation signals such as an act signal, a read signal, and a write signal, an internal clock signal, an internal address signal of a row address and a column address, write data, and the like. The array output signal AOUT includes data (read data) read from the memory cells included in the memory area 200 and the like.

  The access control circuit 11 generates a fuse control signal AFCTL1 and supplies it to the fuse control circuit 12.

  The fuse control circuit 12 generates a fuse control signal AFCTL2 and a bias control signal BIASCTL in response to the fuse control signal AFCTL1. The fuse control signal AFCTL2 is supplied to an antifuse (AF) circuit 22. The bias control signal BIASCTL is supplied to the bias generation circuit 13.

  The bias generation circuit 13 generates a bias signal BIAS according to the bias control signal BIASCTL. The bias signal BIAS is supplied to the antifuse circuit 22.

  The bias signal BIAS is a signal held at substantially the same voltage. Therefore, the bias signal BIAS is one of signals to be shielded from noise in the embodiment.

  The reference voltage generation circuit 14 is a circuit that generates a reference voltage signal that serves as a reference for various internal power supply voltages. FIG. 1 illustrates two reference voltage signals, ie, a plate voltage reference signal VPLTR and an array power supply voltage reference signal VARYR among a plurality of reference voltage signals. In addition to the above two reference voltage signals, the reference voltage generation circuit 14 is a reference voltage signal that serves as a reference for various internal power supply voltages used inside the semiconductor memory 1, such as a peripheral circuit internal power supply voltage reference signal VPERIR. Is generated.

  The reference voltage generation circuit 14 includes, for example, a band gap reference voltage circuit and a resistance circuit.

  The reference voltage generation circuit 14 supplies the generated plate voltage reference signal VPLTR to the first power supply generation circuit 15. The reference voltage generation circuit 14 supplies the generated array power supply voltage reference signal VARYR to the second power supply generation circuit 23 in the memory area 200.

  Here, the plate voltage reference signal VPLTR and the array power supply voltage reference signal VARYR are each maintained at a substantially constant potential. In the embodiment, the plate voltage reference signal VPLTR is substantially half the voltage of the array power supply voltage reference signal VARYR.

  The first power supply generation circuit 15 generates a plate voltage VPLT according to the plate voltage reference signal VPLTR. The first power supply generation circuit 15 maintains the potential of the plate voltage VPLT so as to be substantially equal to the potential of the plate voltage reference signal VPLTR. Accordingly, the plate voltage VPLT maintains a substantially constant potential. Specifically, the first power supply generation circuit 15 generates the plate voltage VPLT by stepping down the external power supply VDD.

  The first power supply generation circuit 15 supplies a plate voltage VPLT to the plate electrodes in the memory area 200. Although details will be described later, the plate electrode is an electrode that supplies a plate voltage VPLT to one end of a memory cell (MC) included in the memory area 200.

  The in-array control circuit 21 controls the operation in the memory cell area according to the array control signal ACTL from the access control circuit 11 and supplies the array control signal AOUT to the access control circuit 11. Details of the memory cell area will be described later. The intra-array control circuit 21 includes, for example, a row decoder (X decoder), a column decoder (Y decoder), a main amplifier, a write amplifier, and the like. The in-array control circuit 21 operates with the in-array power supply voltage VARY generated according to the array power supply voltage reference signal VARYR.

  The in-array control circuit 21 supplies a cell array control signal CACTL to a circuit (not shown in FIG. 1; for example, a sub word driver, a sense amplifier, etc.) arranged in the memory cell area. A circuit arranged in the memory cell area controls the word line WL and the bit line BL according to the cell array control signal CACTL to access the memory cell. The circuit arranged in the memory cell area responds to the array control circuit 21 using the cell array output signal CAOUT.

  The antifuse circuit 22 is a circuit that holds a defective address. The anti-fuse circuit 22 stores a defective address in accordance with the fuse control signal AFCTL2 supplied from the fuse control circuit 12. The anti-fuse circuit 22 loads the stored defective address in response to the fuse control signal AFCTL2, and supplies it to the in-array control circuit 21 as a fuse-out signal AFOUT.

  The antifuse circuit 22 receives the bias signal BIAS from the bias generation circuit 13.

  The second power supply generation circuit 23 generates an in-array power supply voltage VARY in response to the array power supply voltage reference signal VARYR and supplies it to the in-array control circuit 21. Second power supply generation circuit 23 maintains the potential of in-array power supply voltage VARY so as to be substantially equal to the potential of array power supply voltage reference signal VARYR. Therefore, the in-array power supply voltage VARY maintains a substantially constant potential. Specifically, the second power supply generation circuit 23 generates the in-array power supply voltage VARY by stepping down the external power supply VDD.

  FIG. 2 is a schematic plan view showing an example of the chip layout of the semiconductor memory 1. The memory area 200 shown in FIG. 1 is laid out as two memory areas 201 and 202.

  The peripheral circuit area 100 is laid out between two memory areas 201 and 202 at the center of the chip. The peripheral circuit area 100 includes a power supply system circuit area 101. Referring to FIG. 1, a bias generation circuit 13, a reference voltage generation circuit 14, and a first power generation circuit 15 are arranged in the power supply system circuit area 101.

  Each of the two memory areas 201 and 202 is divided into four. Each of the divided four parts has four memory cell areas 300a to 300d and one array control area 301.

  In each memory cell area 300, a cell array, a sense amplifier, and a sub word driver are arranged.

  In the array control area 301, the in-array control circuit 21, the antifuse circuit 22 and the second power supply generation circuit 23 shown in FIG.

  The plate voltage VPLT is supplied from the power supply system circuit area 101 to each memory cell area 300.

  The array power supply voltage reference signal VARYR is supplied from the power supply system circuit area 101 to the second power supply generation circuit 23 in the array control area 301. The bias signal BIAS is supplied from the power supply system circuit area 101 to the antifuse circuit 22 in the array control area 301.

  FIG. 3 is an example of an enlarged view of a region A (a part of the memory cell area 300 and the array control area 301) surrounded by a dotted line in FIG.

  In the memory cell area 300, a plurality of cell arrays 31, a plurality of sense amplifier arrays (SAA) 32, and a plurality of sub word driver arrays (SWDA) 33 are arranged.

  The cell array 31 includes a plurality of memory cells. The sense amplifier array 32 includes a plurality of sense amplifiers. The sub word driver array 33 includes a plurality of sub word drivers.

  The sense amplifier array 32 is arranged in the X direction so as to sandwich the corresponding cell array 31. The sub word driver arrays 33 are arranged in the Y direction so as to sandwich the corresponding cell array 31.

  In the memory cell area 300, an area where the area where the sub word driver array 33 is arranged and the area where the sense amplifier array 32 is arranged (hereinafter referred to as a cross area XA) is formed. In the cross area XA, a power circuit of a sense amplifier and the like are arranged.

  In the memory cell area 300, an X decoder (XDEC) 34 and a Y decoder (YDEC) 35 included in the array control area 301 are arranged adjacent to each other. A power system circuit (for example, the second power generation circuit 23) included in the array control area 301 is disposed in the in-array power generation circuit area 302 adjacent to the Y decoder 35.

  The anti-fuse circuit 22 included in the array control area 301 is arranged in a fuse circuit area 303 adjacent to the in-array power generation circuit area 302.

  In the memory area 200, a signal line for propagating the array power supply voltage reference signal VARYR and a signal line for propagating the bias signal BIAS are wired. A signal line that propagates the array power supply voltage reference signal VARYR connects the reference voltage generation circuit 14 and the second power supply generation circuit 23. A signal line that propagates the bias signal BIAS connects the bias generation circuit 13 and the antifuse circuit 22.

  Each of the signal lines for transmitting the array power supply voltage reference signal VARYR and the bias signal BIAS is sandwiched between shield wirings. Each shield wiring extends along the signal line while adjacent to the signal line for transmitting the array power supply voltage reference signal VARYR and the bias signal BIAS.

  A plate voltage VPLT is supplied to the shield wiring. That is, the shield wiring also functions as a part of the mesh structure of the power supply line that supplies the plate voltage VPLT (refer to FIGS. 8 and 9 for details).

  In FIG. 3, the broken line indicates the second aluminum (AL) wiring, and the solid line indicates the third aluminum wiring. Details of the multilayer wiring structure of the semiconductor memory 1 will be described later (see FIGS. 5, 8, and 9). Referring to FIG. 3, the signal line extending in the Y direction (array power supply voltage reference signal VARYR and bias signal BIAS) and its shield wiring are wired by aluminum wiring of the second wiring layer. The signal lines extending in the X direction (the array power supply voltage reference signal VARYR and the bias signal BIAS) and the shield wiring thereof are wired by the aluminum wiring of the third wiring layer.

  FIG. 4 is a diagram illustrating an example of a circuit configuration of the cell array 31. In the cell array 31, a plurality of memory cells are two-dimensionally arranged. Each of the plurality of memory cells included in the cell array 31 includes a cell transistor 41 and a cell capacitor (capacitance element) 42.

  The gate of the cell transistor 41 is connected to a sub word driver (SWD) 43 through a sub word line SWL. One of the source and the train of the cell transistor 41 is connected to a sense amplifier (SA) 44 via the bit line BL. The other of the source and drain of the cell transistor 41 is connected to one end of the cell capacitor 42, and the other end of the cell capacitor 42 is connected to a power supply line that supplies the plate voltage VPLT.

  FIG. 5 is a diagram illustrating an example of a schematic cross-sectional view of a memory cell. The memory cell includes a cell transistor 41, a cell capacitor 42, and a multi-level wiring layer.

  One diffusion layer (one of the source and the drain) forming the cell transistor 41 is connected to the bit line BL. The other diffusion layer (the other of the source and the drain) is connected to the cell capacitor 42. The gate of the cell transistor 41 is used as a sub word line SWL.

  The cell capacitor 42 includes an upper electrode 51, a capacitor insulating film 52, and a lower electrode 53.

The lower electrode 53 is formed of a conductor containing titanium (Ti), for example, and is connected to the other diffusion layer of the cell transistor 41. As the capacitor insulating film 52, for example, a dielectric film containing aluminum oxide Al ₂ O ₃ or zirconium oxide ZrO ₂ can be used. The upper electrode 51 is formed of a conductor containing titanium (Ti), for example, and is connected to the plate electrode 54. The materials constituting the upper electrode 51, the capacitor insulating film 52, and the lower electrode 53 are merely examples, and these may be composed of other materials.

  The multilayer wiring structure includes a plate electrode 54 and aluminum wirings 1AL to 3AL of first to third wiring layers.

  The plate electrode 54 is formed of a conductor containing tungsten (W), for example.

  The layers of the multilayer wiring structure are electrically connected through through holes 55a to 55c. The above multilayer wiring structure is an example, and the number of wiring layers and the substances constituting each wiring layer can be changed as appropriate.

  FIG. 6 is a diagram illustrating an example of a circuit diagram of the second power supply generation circuit 23. The second power generation circuit 23 includes an amplifier 61, a current source circuit 62, and a P channel type MOS transistor 63. As the current source circuit 62, for example, a MOS transistor or a resistance element can be used.

  The amplifier 61 compares the potential at the contact between the current source circuit 62 and the P-channel MOS transistor 63, that is, the output node, with the potential of the array power supply voltage reference signal VARYR, and compares the potential of the array power supply voltage reference signal VARYR with The gate voltage of P channel type MOS transistor 63 is controlled so that the potentials of the output nodes are equal.

  The first power generation circuit 15 can also be realized by a circuit configuration similar to that of the second power generation circuit 23.

  FIG. 7 is a diagram illustrating an example of a circuit diagram of the antifuse circuit 22. The antifuse circuit 22 includes a load circuit 71 and a latch circuit 72.

  The load circuit 71 includes an antifuse element. The anti-fuse element is insulated in the initial state, and is subjected to dielectric breakdown when a high voltage is applied between both terminals to be in a conductive state.

  The load circuit 71 includes a switch for connecting the antifuse element and the latch circuit 72. The switch is controlled to be turned on / off by a fuse control signal AFCTL2. When loading the state of the antifuse element, the load circuit 71 uses the switch to connect the latch circuit 72, the antifuse element, and a power supply line to which a predetermined potential is supplied.

  The latch circuit 72 includes P-channel MOS transistors 73 to 76, an N-channel MOS transistor 77, and an inverter circuit 78.

  The latch circuit 72 reads data held by the antifuse element in accordance with the potential of the sense node AFBL, and holds the read data by the latch circuit including the inverter circuit 78.

  The latch circuit 72 outputs data held by the antifuse element as a fuse-out signal AFOUT.

  P-channel MOS transistor 73 operates as a precharge transistor for precharging sense node AFBL to a predetermined potential. P-channel MOS transistor 73 is controlled by fuse control signal AFCTL2.

  P-channel MOS transistor 75 operates as a bias transistor that controls the amount of sense current flowing through sense node AFBL. P-channel MOS transistor 75 receives bias signal BIAS at the gate, and causes a sense current to flow through sense node AFBL in accordance with bias signal BIAS.

  FIG. 8 is a diagram showing an example of the layout on the cell array 31. As described above, the cell array 31 is surrounded by the sense amplifier array 32 and the sub word driver array 33.

  A plurality of plate electrodes 54 are formed above the cell array 31 so as to cover each cell array 31. The plate electrode 54 is disposed between power lines 81 and 82 described later and a plurality of memory cells. The plate electrode 54 is an electrode formed in a plate shape. That is, each plate electrode 54 is formed so as to cover the corresponding cell array 31 continuously. Due to such a shape of the plate electrode 54, the plate electrode 54 has a large wiring capacity. This wiring capacitance contributes to the stabilization of the plate voltage VPLT.

  A plate voltage VPLT is supplied to the plate electrode 54 from the first power supply generation circuit 15 included in the peripheral circuit area 100. Power supply lines for supplying the plate voltage VPLT are formed in the first to third wiring layers. Specifically, the power supply line 81 is wired using the aluminum wiring 2AL of the second wiring layer, and the power supply line 82 is wired using the aluminum wiring 3AL of the third wiring layer. The power supply line 81 and the power supply line 82 of different layers are connected by the through hole 55c, thereby forming a grid-like power supply line for supplying the plate voltage VPLT. The power supply line 81 is connected to the power supply line 83 wired by the first-layer aluminum wiring 1AL through the through hole 55b. The power supply line 83 is electrically connected to the plate electrode 54 through the through hole 55a.

  As described above, the power supply line that transmits the plate voltage VPLT includes the power supply line 81 that extends the second wiring layer in the Y direction and the power supply line 82 that extends the third wiring layer in the X direction. . In other words, the power supply lines that transmit the plate voltage VPLT are wired in a grid pattern above the cell array 31. As a result, the resistance value of the power supply line that transmits the plate voltage VPLT is kept low on the cell array 31 and also in the memory area 200.

  The array power supply voltage reference signal VARYR generated by the reference voltage generation circuit 14 is supplied to the second power supply generation circuit 23 across the memory area 200. In FIG. 8, the signal line 84 for transmitting the array power supply voltage reference signal VARYR is extended and wired in the X direction.

  On the cell array 31 (on the memory area 200), two shield wirings 85 are wired so as to sandwich the signal line 84 therebetween. Each of the shield wiring 85 and the signal line 84 is wired so as to pass over the plate electrode 54.

  The two shield wires 85 are connected to power supply lines 81 and 82 that transmit the plate voltage VPLT. As a result, the plate voltage VPLT is supplied to the shield wiring 85. In FIG. 8, two shield wirings 85 and a power supply line 81 are connected by a through hole 55c.

  The two shield wires 85 function as shield wires for the array power supply voltage reference signal VARYR. Further, the two shield wirings 85 constitute a part of the power supply line formed in a lattice shape for transmitting the plate voltage VPLT described above. As a result, the resistance values of the two shield wires 85 are kept low in the memory area 200.

  Since the two shield wirings 85 are connected to the plate electrode 54, the wiring capacity of the shield wiring 85 is high, and the array power supply voltage reference signal VARYR can be more effectively protected from noise.

  In FIG. 8, in a region where the power line 81 of the second wiring layer and the power line 82 of the third wiring layer intersect, both power lines are connected by two through holes 55c. Further, in a region where the power supply line 81 and the shield wiring 85 of the third wiring layer intersect, the power supply line 81 and the shield wiring 85 are connected through one through hole 55c. The number of through holes 55c for connecting the power supply lines and signal lines is not limited to one or two, but it is preferable that the number of through holes is large from the viewpoint of reducing the wiring resistance.

  On the memory area 200, not only the power supply lines 81 and 82 for transmitting the plate voltage VPLT but also other power supply lines and signal lines are provided. Specifically, the main word lines MWL connected to the sub word drivers included in the sub word driver array 33 are wired so as to extend in the Y direction. Further, the power supply lines for transmitting the external power supplies VDD and VSS are wired so as to extend in the X direction and the Y direction.

  Further, in addition to the wiring shown in FIG. 8, other power supply lines, input / output lines (IO lines) for transferring data, and the like are also arranged on the memory area 200. In FIG. In order to simplify the explanation, illustration of these wirings is omitted.

  FIG. 9 is a diagram illustrating an example of another layout on the cell array 31. As shown in FIG. 9, by arranging the two shield wirings 85 so as to sandwich the signal line 86 for transmitting the bias signal BIAS, the bias signal BIAS can be protected from noise in the same manner as the array power supply voltage reference signal VARYR.

<Modification>
As described above, in the first embodiment, the configuration in which each of the array power supply voltage reference signal VARYR and the bias signal BIAS is individually sandwiched by the shield wiring 85 has been described. However, the circuit layout of the memory area 200 and the layout of the signal lines described in the first embodiment are merely examples, and various modifications can be made.

  For example, as shown in FIG. 10, a signal line 84 for transmitting the array power supply voltage reference signal VARYR and a signal line 86 for transmitting the bias signal BIAS are disposed adjacent to each other, and these signal lines are sandwiched between two shield wirings 85. It may be a configuration.

  Alternatively, instead of the chip arrangement (chip layout) shown in FIG. 2, a chip arrangement as shown in FIG. 11 or FIG. 12 may be used. In the chip arrangement shown in FIG. 11, the peripheral circuit area 100 is formed at both ends and the center of the chip, and the power system circuit area 101 is formed in the peripheral circuit area 100 at the end of the chip. In the chip arrangement shown in FIG. 12, the peripheral circuit area 100 is formed at both ends and the center of the chip, and the power system circuit area 101 is formed in the peripheral circuit area 100 at the center of the chip. The present disclosure can also be applied to the semiconductor memory 1 having the chip layout as shown in FIGS.

  The first embodiment has been described by taking the DRAM as an example of the semiconductor memory 1. However, the present disclosure can be applied to various semiconductor memories having a plate electrode in a cell array that is maintained at a substantially constant voltage. . For example, the present disclosure can be applied to a semiconductor memory such as a dielectric memory.

  The disclosure of the cited patent document is incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. In addition, various combinations or selections of various disclosed elements (including each element in each claim, each element in each embodiment or example, each element in each drawing, etc.) within the scope of the entire disclosure of the present invention. Is possible. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea. In particular, with respect to the numerical ranges described in this document, any numerical value or small range included in the range should be construed as being specifically described even if there is no specific description.

DESCRIPTION OF SYMBOLS 1 Semiconductor memory 11 Access control circuit 12 Fuse control circuit 13 Bias generation circuit 14 Reference voltage generation circuit 15 1st power supply generation circuit 21 In-array control circuit 22 Antifuse circuit 23 2nd power supply generation circuit 31 Cell array 32 Sense amplifier array 33 Sub-word driver array 34 X-decoder 35 Y-decoder 41 Cell transistor 42 Cell capacitor 43 Sub-word driver 44 Sense amplifier 51 Upper electrode 52 Capacitor insulating film 53 Lower electrode 54 Plate electrodes 55a-55c Through-hole 61 Amplifier 62 Current source circuits 63, 73-76 P-channel MOS transistor 71 Load circuit 72 Latch circuit 77 N-channel MOS transistor 78 Inverter circuits 81-83 Power supply lines 84, 86 Signal line 85 Shield wiring 100 Road area 101 Power supply circuit area 200, 201, 202 Memory area 300, 300a to 300d Memory cell area 301 Array control area 302 In-array power generation circuit area 303 Fuse circuit area

Claims (17)

A plurality of memory cells;
A first power supply line for supplying a substantially constant first power supply voltage to one end of the plurality of memory cells;
A first signal line that propagates a first signal having a substantially constant potential;
A shield wiring extending adjacent to the first signal line, the first shield wiring being supplied with the first power supply voltage from the first power supply line;
Including a semiconductor device. A reference voltage generating circuit for generating first and second reference voltage signals;
A first power generation circuit for generating the first power supply voltage in response to the first reference voltage signal;
A second power supply generation circuit for generating a second power supply voltage in response to the second reference voltage signal;
A memory cell area in which the plurality of memory cells are formed;
A first control circuit that controls the operation of the memory cell area and operates at the second power supply voltage;
The semiconductor device according to claim 1, comprising:   The semiconductor device according to claim 2, wherein the first power supply voltage is substantially a half voltage of the second power supply voltage.   The semiconductor device according to claim 2, wherein the first signal is the second reference voltage signal, and the first signal line connects the reference voltage generation circuit and the second power supply generation circuit. The memory cell area includes a cell array in which the plurality of memory cells are two-dimensionally arranged and arranged,
The semiconductor device according to claim 2, further comprising a plate electrode formed to cover the cell array and disposed between the first power supply line and the plurality of memory cells.   The semiconductor device according to claim 5, wherein each of the first signal line and the first shield wiring passes over the plate electrode. An antifuse element;
A latch circuit for latching data held by the antifuse element;
A bias generation circuit for supplying a bias signal to the latch circuit,
2. The semiconductor device according to claim 1, wherein the first signal is the bias signal, and the first signal line connects the bias generation circuit and the latch circuit.   A shield wiring disposed adjacent to the first signal line, the shield wiring disposed on the opposite side of the first signal line from the first power line; The semiconductor device according to claim 1, further comprising a second shield wiring to which one power supply voltage is supplied.   2. The semiconductor according to claim 1, wherein each of the plurality of memory cells includes a cell transistor and a capacitive element having one electrode connected to the cell transistor and the other electrode connected to the first power supply line. apparatus. A signal line that propagates a second signal having a substantially constant potential, is disposed on the opposite side of the first signal line with respect to the first signal line, and is adjacent to the first signal line. A second signal line;
A shield wiring disposed adjacent to the second signal line, the shield wiring disposed on a side opposite to the first shield line with respect to the first and second signal lines, and the first power line A second shield wiring to which the first power supply voltage is supplied;
The semiconductor device according to claim 1, further comprising:   The first power line includes a second power line that extends the first wiring layer in the first direction, and a third power that extends the second wiring layer in a second direction orthogonal to the first direction. The semiconductor device according to claim 1, comprising a power line.   The second power line and the third power line are electrically connected by a plurality of through holes formed between the first wiring layer and the second wiring layer. Semiconductor device.   The semiconductor device according to claim 2, further comprising a second control circuit that controls an operation of the first control circuit in accordance with a signal supplied from the outside. First and second memory areas each having at least a plurality of the memory cell areas,
A peripheral circuit area including a power system circuit area where at least the reference voltage generation circuit and the first power generation circuit are disposed;
A semiconductor device according to claim 2.   The semiconductor device according to claim 14, wherein the peripheral circuit area is formed between the first and second memory areas in a central portion of the chip. The peripheral circuit area is formed at both ends and the center of the chip,
15. The semiconductor device according to claim 14, wherein the power supply system circuit area is formed in the peripheral circuit area formed at an end portion of a chip. The peripheral circuit area is formed at both ends and the center of the chip,
The semiconductor device according to claim 14, wherein the power supply system circuit area is formed in the peripheral circuit area formed in a center portion of a chip.

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