JP2016029753A - Imaging apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an imaging element of a simple configuration having a digital gamma curve and also to provide an imaging apparatus.SOLUTION: In a CMOS image sensor equipped with an AD conversion part using a lamp wave and a converter for each column, the counting of N output and S output is performed separately, and the clock frequency of an AD conversion counter is made high on the low brightness side and made low on the high brightness side within a period of S output count.SELECTED DRAWING: Figure 3

Description

  The present invention includes an AD conversion circuit for each column, the AD conversion circuit compares the output value for each column and the reference voltage of the ramp waveform, and counts the time until the magnitude relationship between the two is inverted, The present invention relates to an image sensor that performs conversion into a digital value and an image pickup apparatus that uses the image sensor.

  Imaging devices that convert light into electrical signals are used in various devices such as digital video cameras, digital still cameras, and facsimiles. An imaging device is an example of a main electronic component mounted on a digital still camera and a digital video camera.

  As a representative example of the image pickup device, a charge coupled device (CCD) type image pickup device and a complementary metal-oxide semiconductor (CMOS) type image pickup device are known. Among these, the CMOS type image sensor performs AD conversion on an electrical signal read from a plurality of pixels arranged in a matrix by an AD (Analog Digital) conversion unit, and outputs the AD signal to the outside.

  FIG. 7 is an example of a gamma curve relating to the output of the image sensor. Usually, the RAW signal, which is a signal before image processing of the image sensor, has a characteristic proportional to the amount of incident light.

  In order to obtain a wide dynamic range with a short bit length when converting the RAW signal into an image such as JPEG, a method using a gamma curve is generally known. Further, in the CMOS type image pickup device, the black current signal value varies due to the variation in the dark current component for each pixel. Therefore, in the RAW signal, the black level is not set to 0, but floats about several percent with respect to the dynamic range. As a specific example, 32 is set to the black level for the output value of the RAW signal from 0 to 1023 in the full range.

  Referring to FIG. 7, the region A represents the black level, and the region B and the region C represent the gamma curve. The JPEG output in the area A where the input signal is below the black level is blacked out and does not affect the image quality even if the effective bit length is short. In the region B, since the change amount of the JPEG output is large with respect to the change amount of the input signal, the bit length is long and the image quality is deteriorated unless the gradation is high. In the area C, the JPEG output hardly changes with respect to the change amount of the input signal. Therefore, the effective bit length is short and the image quality is not affected even if the gradation is low.

  In an image display device, when displaying a RAW signal having the same bit length, a method for optimizing a luminance step by changing a driving condition and realizing a display recognized as a high gradation has been proposed (Patent Document 1). ). In addition, in an imaging apparatus, a method is generally known in which N output and S output are individually detected and a signal component is extracted therefrom (Patent Document 2).

  When the above concept is applied to an imaging apparatus, the relationship between the amount of light incident on the imaging element and the output of the imaging element is as shown in FIG. FIG. 8A shows the relationship between the amount of incident light and the S output of the image sensor. The S output includes a signal component and a noise component, and the output value at the point O corresponds to the noise component. In this example, the noise component of the image sensor A varies as 50 LSB, and the noise component of the image sensor B varies as 100 LSB.

  In the conventional example, the frequency switching point of ADCLK is determined in one place, and the image sensor A and the image sensor B are commonly switched at 200 LSB. In this case, with respect to the incident light amount, the switching point of the gradation is set with the point D for the image sensor A and the point D for the image sensor B, and with different incident light amounts for the respective image sensors. As described above, in FIG. 8A, the ADCLK frequency is delayed in the middle, so that the gradation on the high luminance side can be reduced and the dynamic range can be expanded with the same bit length.

Japanese Patent No. 4012118 JP 2009-159271 A

  However, in FIG. 8A, the S output of the image sensor is affected by the variation in the N output between the image sensors, and the gradation switching point is shifted like point A and point B. There are challenges. In addition, there is a problem that a difference in the amount of saturated incident light appears as in points C and D. FIG. 8B shows the relationship between the amount of incident light and the signal component of the image sensor (S output-N output).

  Here, the point O ′ is a point where the amount of incident light is zero, and corresponds to a point where the signal component of the image sensor is zero. Since the signal component of the image sensor is proportional to the amount of incident light, the S output and the N output of the image sensor A and the image sensor B coincide at the point O ′. Here, if there is a difference in the N output between the image pickup devices, the incident light quantity and the S output-N output characteristic curve vary. Specifically, the positions of the bending point D ′ of the image sensor A and the bending point C ′ of the image sensor B are shifted.

  In such a case, it is necessary to correct the variation in signal value with respect to the amount of incident light in accordance with the characteristics of the element. For this reason, it is necessary to provide correction data for each imaging apparatus for correcting variations in counter frequency switching points. Further, when similar N output variations occur between the columns of the pixel array or between the unit pixels, it is necessary to have correction data in the imaging apparatus for these as well. For this reason, the imaging device using the imaging element does not have a simple configuration.

  An object of the present invention is to provide an image pickup device and an image pickup apparatus with a simple configuration having a digital gamma curve for expanding the dynamic range.

  In order to achieve the above object, an imaging apparatus according to the present invention is a CMOS image sensor provided with an AD conversion unit using a ramp wave and a comparator for each column, and separately counts N output and S output, and outputs S output. In the count period, the clock frequency of the AD conversion counter is high on the low luminance side and low on the high luminance side.

  According to the present invention, the AD converter circuit is provided for each column, and the AD converter circuit compares the output value for each column with the reference voltage of the ramp waveform, and counts the time until the magnitude relationship between the two is inverted. Thus, in an image sensor that performs conversion into a digital value and an image pickup apparatus that uses the image sensor, it is possible to provide an optimum gradation without adjustment between individuals and to realize an expansion of the dynamic range.

1 is a diagram showing a configuration of an image pickup apparatus equipped with an image pickup element according to Embodiment 1 of the present invention. 1 is a diagram showing a configuration of an image sensor according to Embodiment 1 of the present invention. The figure which shows the structure of the counter part which concerns on Embodiment 1 of this invention, and a frequency division part. 4 is a timing chart showing an AD conversion operation according to the first embodiment of the present invention. The figure which shows the incident light quantity and output signal characteristic which concern on Embodiment 1, 2 of this invention. The figure which shows the structure of the counter part and frequency divider which concern on Embodiment 2 of this invention. FIG. 4 is a diagram illustrating an example of a gamma curve relating to an output of an image sensor. The figure which shows the relationship between the incident light quantity to the conventional image sensor, and the output of an image sensor.

  Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.

[First Embodiment]
First, each part will be described with reference to FIGS. FIG. 1 is a block diagram showing a configuration of an imaging apparatus according to Embodiment 1 of the present invention. In FIG. 1, reference numeral 1001 denotes an optical system that includes a zoom lens, a diaphragm mechanism, and the like disposed in a lens barrel (not shown) and forms a subject image on a light receiving portion of a CMOS image sensor. Each mechanism of the optical system 1001 performs control such as autofocus by mechanically driving each part under the control of a CPU 1004 described later.

  Reference numeral 1002 denotes an image capturing unit that captures an image of a subject using a CMOS image sensor. The CMOS image sensor performs processing such as OB (optical black) clamping and AD conversion, and generates and outputs a digital imaging signal. The imaging unit 1002 outputs an imaging signal to the DSP 1007. Reference numeral 1004 denotes a CPU that controls the entire system. The CPU 1004 sends an instruction to each unit of the imaging apparatus using a ROM 1005 and a RAM 1006 described later. Reference numeral 1005 denotes a ROM for storing information such as firmware for driving the imaging apparatus.

  Reference numeral 1006 denotes a RAM for temporarily storing control information of the imaging apparatus. Reference numeral 1007 denotes a DSP. The DSP 1007 performs various kinds of signal processing on the imaging signal from the imaging unit 1002 to generate a still image or moving image video signal (for example, a YUV signal) in a predetermined format. Reference numeral 1008 denotes an external interface. The external interface 1008 is provided with various encoders and D / A converters, and exchanges various control signals and data with external elements (in this example, the display 1012, the memory medium 1009, and the operation panel 1011).

  Reference numeral 1012 denotes a display that displays a captured image incorporated in the imaging apparatus. In addition to the display device incorporated in the imaging device, it is of course possible to transmit the image data to an external display device for display. Reference numeral 1009 denotes a memory medium that can appropriately store images taken on various memory cards and the like. Reference numeral 1010 denotes a memory medium controller that can replace the memory medium 1009. As the memory medium 1009, in addition to various memory cards, a disk medium using magnetism or light can be used.

  Reference numeral 1011 denotes an operation panel provided with input keys for the user to give various instructions when performing a shooting operation with the imaging apparatus. The CPU 1004 monitors an input signal from the operation panel 1011 and executes various operation controls based on the input content.

  FIG. 2 is a block diagram showing the configuration of the image sensor according to Embodiment 1 of the present invention. The image sensor shown in FIG. 2 is a CMOS type image sensor, and will be described later, a pixel array 2001, a vertical scanning unit 2002, an output signal line 2015, an AD conversion unit 2003, a reference voltage generation unit 2004, and a horizontal scanning unit. 2005, a horizontal output line 2006, and a timing control unit 2007.

  Reference numeral 2001 denotes a pixel array including a plurality of unit pixels 2008 arranged in a matrix. Reference numeral 2002 denotes a vertical scanning unit that performs vertical scanning for sequentially selecting rows of unit pixels 2008. Reference numeral 2003 denotes an AD converter that converts signal voltages output to a plurality of column signal lines into digital signals at the same time. The AD conversion unit 2003 includes a plurality of AD conversion circuits 2013 provided for each column signal line to be described later. Reference numeral 2004 denotes a reference voltage generator that generates a reference voltage RAMP. The reference voltage RAMP is supplied from the reference voltage generation unit 2004 to the comparator 2009 provided in each column.

  Reference numeral 2005 denotes a horizontal scanning unit that performs horizontal scanning for sequentially selecting columns of unit pixels 2008. Reference numeral 2006 denotes a horizontal output line for outputting the digital signal converted by the AD conversion unit 2003 to the outside. Reference numeral 2007 denotes a timing control unit that controls operation timings of the vertical scanning unit 2002, the AD conversion unit 2003, the reference voltage generation unit 2004, and the horizontal scanning unit 2005. A timing control clock MCLK is supplied from the CPU 1004 to the timing control unit 2007.

  Further, the timing controller 2007 outputs a clock ADCLK for operating the up / down counter 2011 and a signal Down select for switching between the up count and the down count. Reference numeral 2008 denotes a unit pixel that converts received light into a signal voltage and outputs the converted signal voltage to a column signal line provided for each column. Reference numeral 2009 denotes a comparator that compares which of the voltage of the output signal line 2015 and the reference voltage (ramp signal) RAMP is larger.

  A frequency divider 2010 receives ADCLK and supplies a plurality of types of clocks divided to the up / down counter 2011. Reference numeral 2011 denotes an up / down counter that counts a count value using a clock supplied from the frequency divider 2010. 2012 is a memory for holding the count value of the up / down counter 2011. 2013 is an AD conversion circuit provided in each column. The AD conversion circuit 2013 includes a comparator 2009, a frequency divider 2010, and an up / down counter 2011. Reference numeral 2015 denotes an output signal line that outputs the output of the unit pixel 2008 to the AD conversion unit 2003 as a voltage.

  FIG. 3 is a diagram showing a configuration of the AD conversion unit 2003 according to Embodiment 1 of the present invention. Reference numerals 3001a to 3001c denote frequency division flip-flops. When ADCLK does not enter any of the frequency division flip-flops, the clock supplied to the up / down counter 2011 is ADCLK itself. When ADCLK enters 3001c, the clock supplied to the up / down counter 2011 has a frequency half that of ADCLK. When ADCLK enters 3001b, the clock supplied to the up / down counter 2011 has a frequency that is 1/4 of ADCLK.

  When ADCLK enters 3001a, the clock supplied to the up / down counter 2011 has a frequency of 1/8 of ADCLK. 3002a to 3002j are count flip-flops. In addition, the figure is abbreviate | omitted about the part which the same structure continues.

  The output Q0 to Q9 of each flip-flop corresponds to the output value of each digit of the up / down counter 2011.

  In this embodiment, the binary number is 10 digits, but is not limited to this.

  In the 10-bit counter configuration as described above, the range of the count output value is 1024 gradations from 0 to 1023 LSB. 3003a to 3003i are AND circuits for downselect. In addition, the figure is abbreviate | omitted about the part which the same structure continues. 3004a to 3004i are down-select AND circuits. In addition, the figure is abbreviate | omitted about the part which the same structure continues. When N outputs are counted, the Down select signal is at a high level, the outputs of 3004a to 3004i are always at a low level, and 3003a to 3003i change according to the high level of the counting flip-flop on the left side of the drawing.

  At the time of counting N outputs, the Down select signal becomes low level, the outputs of 3004a to 3004i change according to the high level of the counting flip-flop on the left side of the figure, and 3003a to 3003i are always low level.

  In summary, the up / down counter 2011 operates as a down counter when the Down select signal is at a high level, and operates as an up counter when the Down select signal is at a low level.

  3005a to 3005i are OR circuits. In addition, the figure is abbreviate | omitted about the part which the same structure continues.

  It is used to receive either the output Q or Q˜ of the left count flip-flop in the figure. Reference numeral 3006 denotes a count period control AND circuit. One of the inputs of the count period control AND circuit 3006 is connected to the output of the comparator, and the up / down counter 2011 counts up or down only during a period when the comparator output is at a high level. Reference numerals 3007b and 3007c denote frequency division ratio control OR circuits.

  The division ratio control OR circuit 3007b becomes high level when either of the upper 2 bits (Q8, Q9) of the up / down counter 2011 becomes high level. Thus, the output of the frequency division flip-flop 3001b is controlled to be supplied to the frequency division flip-flop 3001c instead of ADCLK. The division ratio control OR circuit 3007c goes high when any of the upper 3 bits (Q7, Q8, Q9) of the up / down counter 2011 goes high. Thus, the output of the frequency division flip-flop 3001c is controlled to be supplied to the frequency division ratio control OR circuit 3010c instead of ADCLK.

  When the upper 1 bit (Q9) becomes high level, the output of the frequency division flip-flop 3001a is supplied to the frequency division flip-flop 3001b instead of ADCLK. Reference numerals 3008a to 3008c denote frequency division ratio control AND circuits. Each of the frequency division ratio control AND circuits 3008a to 3008c controls whether or not to supply a clock to the frequency division ratio control flip-flop located on the right side in the drawing. Reference numerals 3009a to 3009c denote frequency division ratio control AND circuits. The division ratio control AND circuits 3009a to 3009c control whether or not ADLCK is supplied to the division ratio control OR circuits 3010a to 3010c.

  Reference numerals 3010a to 3010c denote OR circuits for frequency division ratio control. The division ratio control OR circuits 3010a to 3009c selectively output ADCLK or the output of the frequency division flip-flops 3001a to 3001c.

  Next, the driving chart of this embodiment will be described. FIG. 4 is a timing chart showing the operation of the normal output region of the AD converter according to Embodiment 1 of the present invention.

  Prior to time t1, the count value of the up / down counter 2011 is set to an initial value greater than zero. Here, it is 32LSB. Further, the N output of the unit pixel 2008 is read out to the output signal line 2015. At time t1, counting of N output is started by down-counting. The output of the comparator 2009 becomes high level. At time t2, the magnitude relationship between RAMP and pixel output is reversed, and the output of the comparator becomes low level. As a result, the counting clock is not supplied to the first-stage counting flip-flop 3002a, and the down-counting is stopped.

  At time t3, the N output count period ends. In this configuration, when the count value of the up / down counter 2011 is less than 0, all the bits of the count flip-flops 3002a to 3002j become 1, so that the clock divided by the frequency divider 2010 is the up / down counter. 2011.

  In the above state, the desired frequency dividing operation is disabled. As described above, when the counter value falls below 0, the frequency divider 2010 does not operate normally. Therefore, the N output count period must be set to be equal to or less than the offset amount (32 counts in this embodiment).

  Next, the S output of the unit pixel 2008 is read out to the output signal line 2015 during the period from time t4 to time t5. At time t6, counting of the S output is started. At this time, when Down select becomes low level, the up-counting is performed. At time t7, the count value of the up / down counter 2011 returns to the initial value (32LSB).

  As described above, by performing the SN operation in the counter, the black level of the incident light amount 0 can always be kept constant regardless of the value of the N output. Furthermore, the black level of the incident light quantity 0 is kept constant at the initial value, so that variations between image sensors, between columns in the pixel array 2001, and between unit pixels 2008 can be offset.

  Thus, the clock is always changed with the same count value with respect to the count value of the up / down counter 2011 corresponding to the S output-N output. At time t8, the output Q7 of the flip-flop 3002h becomes high level. At this time, the count value of the up / down counter 2011 is 128 LSB. As a result, the output of the frequency division ratio controlling OR circuit 3007c becomes high level. Note that any one of Q7, Q8, and Q9 is high level, and the frequency division ratio controlling OR circuit 3007c is high level.

  As a result, a clock corresponding to ADCLK is output from the frequency division ratio control AND circuit 3008c via 3009b and 3010b. When the division ratio control OR circuit 3007c becomes high level, the output of the division ratio control AND circuit 3009c becomes low level. As a result, the division ratio control OR circuit 3010c outputs a clock obtained by dividing ADCLK by half through the frequency division flip-flop 3001c, and supplies the divided clock to the up / down counter 2011. Is done. In the following, the clock division is advanced by the same principle.

As a feature of the present embodiment, the division ratio is determined based on the count value of the up / down counter 2011 as described above. At time t9, the output Q8 of the flip-flop 3002i becomes high level. At this time, the count value of the counter is 256LSB.
As a result, the output of the frequency division ratio control OR circuit 3007b becomes high level. The frequency division ratio control OR circuit 3007b is at a high level when either Q8 or Q9 is at a high level.

  As a result, a clock corresponding to ADCLK is output from the frequency division ratio control AND circuit 3008b via 3009a and 3010a. When the dividing ratio control OR circuit 3007b becomes high level, the output of the dividing ratio control AND circuit 3009b becomes low level, and ADCLK is supplied to the dividing ratio control OR circuit 3010b via the dividing flip-flop 3001b. A clock divided by 1/2 is supplied. As a result, the division ratio control OR circuit 3010c outputs a clock obtained by dividing ADCLK by 1/4, and the divided clock is supplied to the up / down counter 2011.

  At time t10, the magnitude relationship between RAMP and the pixel output is reversed, and the output of the comparator 2009 is at a low level. As a result, the counting clock is not supplied to the first-stage counting flip-flop 3002a, and the up-counting is stopped. Depending on the value of the S output, the stop position of this upcount moves back and forth between time t7 and time t12. When the output of the pixel is larger and the count of the up / down counter 2011 is further advanced, the output Q9 of the flip-flop 3002j becomes high level at time t11. At time t11, the count value of the up / down counter 2011 becomes 512LSB.

  As a result, a clock corresponding to ADCLK is output from the frequency division ratio control AND circuit 3008a. When Q9 becomes high level, the output of the frequency division ratio control AND circuit 3009a becomes low level, and the frequency division ratio control OR circuit 3010a receives ADCLK frequency divided by 1/2 via the frequency division flip-flop 3001a. Is supplied. As a result, a clock obtained by dividing ADCLK by 1/8 is output from the dividing ratio control OR circuit 3010c, and the divided clock is supplied to the up / down counter 2011. At time t12, the S output count period ends. The count value at this time is the maximum value of 1023LSB.

  The count value of the up / down counter 2011 is recorded in the memory 2012 and is output from the image sensor via the horizontal output line 2006.

  FIG. 5 shows the amount of incident light and output signal characteristics according to Embodiment 1 of the present invention. With reference to FIG. 5, the quantitative effect of changing the gradation property for each luminance and the effect of the present embodiment compared to the conventional example will be described. The horizontal axis in FIG. 5 is obtained by normalizing the amount of light incident on the unit pixel 2008. The vertical axis represents S output-N output (signal component).

  Here, the marker of Example 1 and Example 2 represents the bending point of each curve. During image processing, the DSP 1007 performs conversion to JPEG with the black level offset removed.

  In this embodiment, 32LSB corresponding to the black level is subtracted from the output value of the image sensor during image processing. First, in the conventional straight line in which the clock is not changed, 4096 gradations are required to express a certain incident light amount range. In the present embodiment, the same incident light amount range can be expressed with 1024 gradations with respect to the conventional straight line. In this embodiment, a 10-bit configuration is used, but conventional data having a gradation of 12 bits or more can be output. Further, the count value for starting the frequency division and the frequency division ratio are not fixed to the pattern of this embodiment.

  For example, frequency division may be started with a smaller count value, and in this case, data having the same gradation can be output with a smaller number of bits. Similarly, by increasing the frequency division ratio, it is possible to output data having the same gradation as that of the prior art with a smaller number of bits. Conversely, when frequency division is started with a larger count value or when the frequency division ratio is lowered, data with adjusted gradation can be output for the same light quantity range.

  Further, in the conventional example in which the clock change point is shifted, correction of the clock change point between the individual image sensors, between the columns of the pixel array 2001, and between the unit pixels 2008 due to variations in N output is performed. This must be performed on the imaging device side, and the configuration of the imaging device is complicated.

  In this embodiment, the black level is offset, the N output is down-counted, and the S output is up-counted in order to cancel the variation of the N output with respect to the black level, and to change the clock frequency. Can be arranged. This eliminates the need to correct the clock change point. A simple imaging device can be provided.

  In the above configuration, unit devices and unit modules as system components, a combination method, a set size, and the like can be appropriately selected based on the actual state of commercialization and the like. The device shall include a wide variety of variations.

  As described above, by counting the N output by down-counting and counting the S output by up-counting, it is possible to align the initial values with respect to the light input amount. As described above, it is possible to provide an imaging device and an imaging device that do not require adjustment for each individual in an imaging device that changes the clock frequency of the counter during AD conversion in order to expand the dynamic range.

[Second Embodiment]
Next, a second embodiment will be described. FIG. 6 is a configuration example of the counter unit 2011 and the frequency dividing unit 2010 according to Embodiment 2 of the present invention. Here, only differences from the first embodiment will be described. Reference numerals 3011b, 3011c, and 3012a to 3012c are gamma control AND circuits. The AND circuits for gamma control 3011b, 3011c, and 3012a to 3012c change the shape of the gamma curve by receiving the gamma select signal and controlling the frequency division ratio of the frequency divider 2010. First, the behavior of frequency division when the image sensor is driven at a high level of gamma select will be described.

  The division ratio control OR circuit 3007b becomes high level when either of the upper 2 bits (Q8, Q9) of the up / down counter 2011 becomes high level. Thus, the output of the frequency division flip-flop 3001b is controlled to be supplied to the frequency division flip-flop 3001c instead of ADCLK. The division ratio control OR circuit 3007c goes high when any of the upper 3 bits (Q7, Q8, Q9) of the up / down counter 2011 goes high.

  Thus, the output of the frequency division flip-flop 3001c is controlled to be supplied to the frequency division ratio control OR circuit 3010c instead of ADCLK. When the upper 1 bit (Q9) becomes high level (512LSB or more), the output of the frequency division flip-flop 3001a is supplied to the frequency division flip-flop 3001b instead of ADCLK.

  By adopting the configuration as described above, the behavior of the frequency divider 2010 with respect to the upper 3 bits (Q7, Q8, Q9) of the up / down counter 2011 is equal to that in the first embodiment when the gamma select is at a high level. For this reason, when the gamma select is at the high level, the same gamma curve as in the first embodiment, in which the slope changes at three positions 128LSB, 256LSB, and 512LSB, is drawn.

  Next, the behavior of frequency division when the image sensor is driven with gamma select at a low level will be described. The division ratio controlling OR circuit 3007b becomes high level when the upper 1 bit (Q9) of the up / down counter 2011 becomes high level.

  Thus, the output of the frequency division flip-flop 3001c is controlled to be supplied to the frequency division ratio control OR circuit 3010c instead of ADCLK. The division ratio control OR circuit 3007c goes high when any of the upper 2 bits (Q8, Q9) of the up / down counter 2011 goes high. Thus, the output of the frequency division flip-flop 3001b is controlled to be supplied to the frequency flip-flop 3001c instead of ADCLK.

  As a result, when the gamma select is at the low level, the division ratio is changed at two timings of 256LSB and 512LSB, and a gamma curve in which the slope changes at the two positions is drawn.

  As shown in FIG. 5, in the second embodiment, by having a plurality of types of timings for changing the frequency division ratio, a gamma curve similar to that in the first embodiment or a plurality of types of gamma curves having a different shape from the first embodiment can be obtained. It can be realized. In this way, an arbitrary gamma curve can be realized by giving a gamma select and a circuit configuration at that time.

  As described above, the dynamic range can be expanded in accordance with the subject and the shooting scene.

  In the above configuration, unit devices and unit modules as system components, a combination method, a set size, and the like can be appropriately selected based on the actual state of commercialization and the like. The device shall include a wide variety of variations.

  As described above, an imaging device that realizes a plurality of types of gamma curves and does not require adjustment for each individual, and an imaging device in an imaging device that changes a counter clock frequency during AD conversion in order to expand a dynamic range. Is possible.

1001 optical system, 1002 imaging unit, 1004 CPU, 1005 ROM,
1006 RAM, 1007 DSP, 1008 External interface,
1009 memory medium, 1010 memory medium controller, 1011 operation panel,
1012 display, 2001 pixel array, 2002 vertical scanning unit,
2003 AD conversion unit, 2004 reference voltage generation unit, 2005 horizontal scanning unit,
2006 horizontal output line, 2007 timing control unit, 2008 unit pixel,
2009 comparator, 2010 divider, 2011 up / down counter,
2012 memory, 2013 AD converter circuit, 2015 output signal line,
2017 AD converter, 3001a to 3001c frequency division flip-flop,
3002a to 3002j counting flip-flops,
3003a to 3003i AND circuit for down select,
3004a to 3004i AND circuit for down select,
3005a to 3005i OR circuit, 3006 AND circuit for count period control,
3007b, 3007c OR circuit for dividing ratio control,
3008a to 3008c AND circuit for dividing ratio control,
3009a to 3009c AND circuit for dividing ratio control,
3010a-3010c dividing ratio control OR circuit,
3011b, 3011c AND circuit for gamma control,
3012a-3012c AND circuit for gamma control

Claims (7)

A CMOS image sensor equipped with an AD converter using a ramp wave and a comparator for each column. N outputs and S outputs are counted separately, and the clock frequency of the AD conversion counter is set to the low luminance side within the S output count period. The image pickup apparatus is characterized in that it is high and low on the high luminance side. The imaging apparatus according to claim 1, wherein N outputs are counted before S outputs are counted. The imaging apparatus according to claim 2, wherein the count of N output is down-counted and the count of S output is up-counted. 4. The imaging apparatus according to claim 2, wherein the clock frequency of the counter is not changed during counting of N outputs. The change point of the clock frequency of the counter is set on the basis of the time when the output reaches the black level in the AD converter circuit of each column. Imaging device. 6. The imaging apparatus according to claim 2, wherein an initial value of the counter at the time of AD conversion is a value larger than zero. The imaging apparatus according to claim 2, wherein the imaging apparatus has a plurality of timings for changing the clock frequency of the AD conversion counter.