JP2016027631A5 - - Google Patents
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- Publication number
- JP2016027631A5 JP2016027631A5 JP2015126213A JP2015126213A JP2016027631A5 JP 2016027631 A5 JP2016027631 A5 JP 2016027631A5 JP 2015126213 A JP2015126213 A JP 2015126213A JP 2015126213 A JP2015126213 A JP 2015126213A JP 2016027631 A5 JP2016027631 A5 JP 2016027631A5
- Authority
- JP
- Japan
- Prior art keywords
- convex portion
- conductive
- insulating layer
- electrode
- conductive convex
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 238000004519 manufacturing process Methods 0.000 claims 15
- 239000004065 semiconductor Substances 0.000 claims 13
- 239000000758 substrate Substances 0.000 claims 7
- 239000011342 resin composition Substances 0.000 claims 6
- 239000007788 liquid Substances 0.000 claims 3
- 239000000463 material Substances 0.000 claims 3
- 239000002904 solvent Substances 0.000 claims 3
- 239000011248 coating agent Substances 0.000 claims 2
- 238000000576 coating method Methods 0.000 claims 2
- 239000000203 mixture Substances 0.000 claims 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 239000004020 conductor Substances 0.000 claims 1
- 238000010304 firing Methods 0.000 claims 1
- 238000005755 formation reaction Methods 0.000 claims 1
- 238000003475 lamination Methods 0.000 claims 1
- 230000002940 repellent Effects 0.000 claims 1
- 239000005871 repellent Substances 0.000 claims 1
- 239000011347 resin Substances 0.000 claims 1
- 229920005989 resin Polymers 0.000 claims 1
Claims (16)
導電性材料、撥液剤および溶媒を含む導体組成物インクを前記第１電極上にパターン状に塗布して焼成することにより、前記第１電極と導通し撥液性を有する導電性凸部を形成する導電性凸部形成工程と、
前記導電性凸部が形成された前記配線部材上に樹脂組成物の塗膜を形成して硬化させることにより、前記導電性凸部が形成された領域にコンタクトホールを有する絶縁層を形成する絶縁層形成工程と、
前記コンタクトホール内で前記導電性凸部と導通するように、前記絶縁層上に第２電極を形成する第２電極形成工程と、
を有し、
前記絶縁層形成工程では、前記導電性凸部の高さよりも前記絶縁層の厚みが大きくなるように前記絶縁層を形成し、
前記導電性凸部の縦断面形状は、半円形状もしくは半楕円形状であることを特徴とする積層配線部材の製造方法。 Preparing a wiring member having a substrate and a first electrode formed on the substrate;
A conductive composition containing a conductive material, a liquid repellent and a solvent is applied onto the first electrode in a pattern and baked to form a conductive convex portion that is electrically connected to the first electrode and has liquid repellency. A conductive protrusion forming step,
Insulating to form an insulating layer having a contact hole in a region where the conductive convex portion is formed by forming a coating film of a resin composition on the wiring member on which the conductive convex portion is formed and curing it. A layer forming step;
A second electrode formation step of forming a second electrode on the insulating layer so as to be electrically connected to the conductive convex portion in the contact hole;
I have a,
In the insulating layer forming step, the insulating layer is formed so that the thickness of the insulating layer is larger than the height of the conductive convex portion,
A method for manufacturing a laminated wiring member, wherein the conductive protrusion has a semi-circular or semi-elliptical longitudinal cross-sectional shape .
前記ソース電極、前記ドレイン電極および前記半導体層を覆うように樹脂組成物の塗膜を形成して硬化させることにより、前記導電性凸部が形成された領域にコンタクトホールを有する絶縁層を形成する絶縁層形成工程と、
前記コンタクトホール内で前記導電性凸部と導通するように、前記絶縁層上に中間電極または外部入出力電極を形成する電極形成工程と、
を有し、
前記絶縁層形成工程では、前記導電性凸部の高さよりも前記絶縁層の厚みが大きくなるように前記絶縁層を形成し、
前記導電性凸部の縦断面形状は、半円形状もしくは半楕円形状であることを特徴とする半導体素子の製造方法。 A wiring member having a base material, a source electrode and a drain electrode formed on the base material, and a semiconductor layer formed in a channel region between the source electrode and the drain electrode is prepared. And a conductive convex portion forming step of forming a conductive convex portion that is electrically connected to the drain electrode and has liquid repellency by applying a conductive composition ink containing a solvent and a solvent in a pattern on the drain electrode and firing. ,
An insulating layer having a contact hole is formed in a region where the conductive convex portion is formed by forming and curing a coating film of a resin composition so as to cover the source electrode, the drain electrode, and the semiconductor layer. An insulating layer forming step;
Forming an intermediate electrode or an external input / output electrode on the insulating layer so as to be electrically connected to the conductive protrusion in the contact hole;
I have a,
In the insulating layer forming step, the insulating layer is formed so that the thickness of the insulating layer is larger than the height of the conductive convex portion,
The method of manufacturing a semiconductor element, wherein a longitudinal cross-sectional shape of the conductive convex portion is a semicircular shape or a semielliptical shape .
前記基材上に形成された第１電極と、
前記第１電極上にパターン状に形成され、前記第１電極と導通する導電性凸部と、
前記第１電極が形成された前記基材上に形成され、前記導電性凸部が形成された領域にコンタクトホールを有し、樹脂を含む絶縁層と、
前記絶縁層上に形成され、前記コンタクトホール内で前記導電性凸部と導通する第２電極と、を有し、
前記導電性凸部の高さよりも前記絶縁層の厚みが大きく、
前記導電性凸部の縦断面形状は、半円形状もしくは半楕円形状であることを特徴とする積層配線部材。 A substrate;
A first electrode formed on the substrate;
A conductive protrusion formed in a pattern on the first electrode and electrically connected to the first electrode;
An insulating layer formed on the base material on which the first electrode is formed and having a contact hole in a region where the conductive protrusion is formed, and including a resin;
A second electrode formed on the insulating layer and electrically connected to the conductive protrusion in the contact hole;
The thickness of the insulating layer than the height of the conductive projection is rather large,
The laminated wiring member according to claim 1, wherein the conductive protrusion has a semi-circular or semi-elliptical longitudinal cross-sectional shape .
前記基材上に形成されたソース電極およびドレイン電極、ならびに前記ソース電極および前記ドレイン電極の間のチャネル領域に形成された半導体層と、
前記ドレイン電極上にパターン状に形成され、前記ドレイン電極と導通する導電性凸部と、
前記ソース電極、前記ドレイン電極および前記半導体層が形成された基板上に形成され、前記導電性凸部が形成された領域にコンタクトホールを有し、樹脂を含む絶縁層と、
前記絶縁層上に形成され、前記コンタクトホール内で前記導電性凸部と導通する中間電極または外部入出力電極と、を有し、
前記導電性凸部の高さよりも前記絶縁層の厚みが大きく、
前記導電性凸部の縦断面形状は、半円形状もしくは半楕円形状であることを特徴とする半導体素子。 A substrate;
A source electrode and a drain electrode formed on the substrate, and a semiconductor layer formed in a channel region between the source electrode and the drain electrode;
A conductive protrusion formed in a pattern on the drain electrode and electrically connected to the drain electrode;
An insulating layer formed on a substrate on which the source electrode, the drain electrode, and the semiconductor layer are formed, and having a contact hole in a region where the conductive convex portion is formed;
An intermediate electrode or an external input / output electrode formed on the insulating layer and electrically connected to the conductive protrusion in the contact hole;
The thickness of the insulating layer than the height of the conductive projection is rather large,
The semiconductor element according to claim 1, wherein a longitudinal cross-sectional shape of the conductive protrusion is a semicircular shape or a semielliptical shape .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2015126213A JP6002817B2 (en) | 2014-06-24 | 2015-06-24 | Manufacturing method of laminated wiring member, manufacturing method of semiconductor element, laminated wiring member, and semiconductor element |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2014129635 | 2014-06-24 | ||
| JP2014129635 | 2014-06-24 | ||
| JP2015126213A JP6002817B2 (en) | 2014-06-24 | 2015-06-24 | Manufacturing method of laminated wiring member, manufacturing method of semiconductor element, laminated wiring member, and semiconductor element |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2016027631A JP2016027631A (en) | 2016-02-18 |
| JP2016027631A5 true JP2016027631A5 (en) | 2016-03-31 |
| JP6002817B2 JP6002817B2 (en) | 2016-10-05 |
Family
ID=54938199
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2015126213A Expired - Fee Related JP6002817B2 (en) | 2014-06-24 | 2015-06-24 | Manufacturing method of laminated wiring member, manufacturing method of semiconductor element, laminated wiring member, and semiconductor element |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP6002817B2 (en) |
| TW (1) | TW201606894A (en) |
| WO (1) | WO2015199120A1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20190068352A (en) * | 2017-12-08 | 2019-06-18 | 삼성에스디아이 주식회사 | Solar cell |
| KR102191495B1 (en) * | 2019-08-27 | 2020-12-15 | 에스디코리아(주) | Polysiloxane surfactant, method of preparing the same and polyurethane foam composition including polysiloxane surfactant |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010010609A1 (en) * | 2008-07-22 | 2010-01-28 | パイオニア株式会社 | Method for forming contact hole, and circuit board |
| JP2010257291A (en) * | 2009-04-27 | 2010-11-11 | Seiko Epson Corp | Methods for manufacturing of touch panel, display device and electronic apparatus |
| JP2011044584A (en) * | 2009-08-21 | 2011-03-03 | Seiko Epson Corp | Method of forming circuit board |
| JP5866783B2 (en) * | 2011-03-25 | 2016-02-17 | セイコーエプソン株式会社 | Circuit board manufacturing method |
-
2015
- 2015-06-24 TW TW104120445A patent/TW201606894A/en unknown
- 2015-06-24 WO PCT/JP2015/068157 patent/WO2015199120A1/en active Application Filing
- 2015-06-24 JP JP2015126213A patent/JP6002817B2/en not_active Expired - Fee Related
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