JP2016025322A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress dishing of a dummy gate electrode.SOLUTION: A method of manufacturing a semiconductor device comprises the steps of: forming, on a semiconductor substrate 2, a first dummy gate electrode 12a having a first gate length, a second dummy gate electrode 12b having a second gate length longer than the first gate length, a first stop film 14a provided on the first dummy gate electrode, containing a first insulating material, and having a first film thickness, and a second stop film 14b provided on the second dummy gate electrode, containing the first insulating material, and having a second film thickness larger than the first film thickness; forming an insulating film containing a second insulating material on the first dummy gate electrode, the second dummy gate electrode, and the semiconductor substrate; and polishing the insulating film, the first stop film, and the second stop film to expose the first dummy gate electrode and the second dummy gate electrode.SELECTED DRAWING: Figure 18

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  The deposited film on the semiconductor substrate can be planarized by polishing. Polishing of a deposited film is widely used in the manufacture of semiconductor devices such as planarization of trench isolation buried insulating films and planarization of interlayer insulating films (Patent Document 1).

  Patent Document 1 discloses that when a deposited film on a substrate convex portion is polished, the deposited film becomes thinner on a substrate convex portion having a small pattern dimension than on a substrate convex portion having a large pattern dimension.

JP 11-260772 A

  A MOSFET (metal-oxide-semiconductor field-effect transistor) having a metal gate electrode is formed by embedding a gate metal material in a region where a dummy gate electrode surrounded by an insulating film is removed. Here, the insulating film surrounding the dummy gate electrode is formed by polishing the insulating film in which the dummy gate electrode is embedded.

  The polishing of the insulating film for embedding the dummy gate electrode has a problem that the longer the dummy gate electrode is, the larger the recess (that is, dishing) on the upper surface of the dummy gate electrode exposed by polishing.

  In order to solve the above problem, according to one aspect of the present manufacturing method, a first dummy gate electrode having a first gate length and a second gate length having a second gate length longer than the first gate length are formed on a semiconductor substrate. Two dummy gate electrodes, a first stop film provided on the first dummy gate electrode and including a first insulating material and having a first film thickness, and the first insulating material provided on the second dummy gate electrode. And forming a second stop film having a second film thickness greater than the first film thickness, a second stop film on the first dummy gate electrode, the second dummy gate electrode, and the semiconductor substrate. Forming an insulating film containing an insulating material; polishing the insulating film, the first stop film, and the second stop film to expose the first dummy gate electrode and the second dummy gate electrode; Said first dummy After the step of exposing the first electrode and the second dummy gate electrode, the step of removing the first dummy gate electrode and the second dummy gate electrode, the first region where the first dummy gate electrode is removed, and the first region And a step of forming a metal gate in each of the second regions from which the two dummy gate electrodes are removed.

  According to the embodiment, dishing of the dummy gate electrode can be suppressed.

FIG. 1 is a diagram for explaining a Fin formation process. FIG. 2 is a diagram for explaining the Fin activation process. FIG. 3 is a diagram for explaining the Fin activation process. FIG. 4 is a diagram for explaining the Fin activation process. FIG. 5 is a diagram for explaining the Fin activation process. FIG. 6 is a diagram for explaining the Fin activation process. FIG. 7 is a diagram illustrating a process for forming a dummy gate material. FIG. 8 is a diagram for explaining the polishing process of the dummy gate material. FIG. 9 is a diagram illustrating a process of forming the first insulating film. FIG. 10 is a diagram illustrating a process of forming the first insulating film. FIG. 11 is a diagram illustrating a process of forming the first insulating film. FIG. 12 is a diagram for explaining a process of forming the first insulating film. FIG. 13 is a diagram illustrating a process of forming the first insulating film. FIG. 14 is a diagram illustrating a process for forming the first insulating film. FIG. 15 is a diagram for explaining a process of forming the first insulating film. FIG. 16 is a diagram for explaining a first mask pattern forming process. FIG. 17 is a diagram for explaining a first mask pattern forming process. FIG. 18 is a diagram for explaining the etching process of the dummy gate material and the first insulating film. FIG. 19 is a diagram illustrating a process of forming source / drain regions and the like. FIG. 20 is a diagram illustrating a process of forming source / drain regions and the like. FIG. 21 is a diagram illustrating a process of forming source / drain regions and the like. FIG. 22 is a diagram illustrating a process of forming source / drain regions and the like. FIG. 23 is a diagram for explaining a step of forming an interlayer insulating film. FIG. 24 is a diagram for explaining the chemical mechanical polishing step of the interlayer insulating film. FIG. 25 is a diagram for explaining the chemical mechanical polishing step of the stop film. FIG. 26 is a diagram illustrating a dummy gate electrode removal process. FIG. 27 is a diagram illustrating a metal gate formation process. FIG. 28 is a diagram for explaining a metal gate forming step. FIG. 29 is a diagram illustrating a wiring layer forming process. FIG. 30 is a diagram illustrating a wiring layer forming process. FIG. 31 is a diagram illustrating a wiring layer forming process. FIG. 32 is a cross-sectional view illustrating chemical mechanical polishing in the case where a third stop film having substantially the same thickness as the first stop film on the first dummy gate electrode is provided on the second dummy gate electrode. FIG. 33 is a Pelgrom diagram of a FinFET manufactured by providing stop films having substantially the same thickness on a plurality of dummy gate electrodes having different gate lengths. FIG. 34 is a diagram for explaining a dummy gate electrode and stop film forming step according to the second embodiment. FIG. 35 is a diagram for explaining a dummy gate electrode and stop film forming step according to the second embodiment. FIG. 36 is a diagram for explaining a dummy gate electrode and stop film forming step according to the second embodiment. FIG. 37 is a diagram for explaining a dummy gate electrode and stop film forming step according to the second embodiment. FIG. 38 is a diagram for explaining a dummy gate electrode and stop film forming step according to the second embodiment. FIG. 39 is a diagram for explaining a dummy gate electrode and stop film forming process according to the second embodiment. FIG. 40 is a diagram for explaining a dummy gate electrode and stop film forming step according to the second embodiment. FIG. 41 is a diagram illustrating a process of forming source / drain regions and the like. FIG. 42 is a diagram illustrating a process for forming an interlayer insulating film. FIG. 43 is a diagram for explaining the chemical mechanical polishing step of the insulating film. FIG. 44 is a diagram for explaining the chemical mechanical polishing step of the stop film. FIG. 45 illustrates a method for manufacturing the semiconductor device of the third embodiment. FIG. 46 illustrates a method for manufacturing the semiconductor device of the fourth embodiment. FIG. 47 illustrates a method for manufacturing the semiconductor device of the fourth embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the technical scope of the present invention is not limited to these embodiments, but extends to the matters described in the claims and equivalents thereof. Note that, even if the drawings are different, corresponding parts are denoted by the same reference numerals, and description thereof is omitted.

(Embodiment 1)
The manufacturing method according to the first embodiment is a method for manufacturing a semiconductor device having a FinFET (Fin field-effect transistor). 1 to 31 are diagrams for explaining the method of manufacturing the semiconductor device of the first embodiment.

  Fig.1 (a), FIG.2 (a) ... FIG.30 (a) is a top view. 1B, FIG. 2B, FIG. 30B are respectively the IB line in FIG. 1A, the IIB line in FIG. 2A, and the XXXB line in FIG. 30A. FIG. FIG. 1 (c), FIG. 2 (c)... FIG. 30 (c) are respectively the IC line in FIG. 1 (a), the IIC line in FIG. 2 (a), and the XXXC line in FIG. FIG. FIG. 31 is a cross-sectional view of the semiconductor device of First Embodiment.

(1) Formation and activation of Fin (see FIGS. 1 to 6)
First, a semiconductor region (Fin) protruding in a fin shape is formed on a semiconductor substrate (for example, a Si substrate), and then activated. Specifically, for example, Fin is formed and activated by the following procedure.

(1-1) Formation of Fin (see FIG. 1)
FIG. 1 is a diagram for explaining a Fin formation process.

  First, as shown in FIG. 1, the semiconductor substrate 2 is dry-etched through, for example, a hard mass (not shown) to protrude into a fin-shaped first semiconductor region 4a (Fin) and a fin. A convex second semiconductor region 4b (Fin) is formed.

  The width of the first semiconductor region 4a and the second semiconductor region 4b is, for example, 10 nm or less (for example, 2 nm or more and 10 nm or less). The height of the first semiconductor region 4a and the second semiconductor region 4b is, for example, not less than 80 nm and not more than 120 nm.

(1-2) Fin activation (see FIGS. 2 to 6)
2-6 is a figure explaining the activation process of Fin.

After the formation of the first semiconductor region 4a and the second semiconductor region 4b, an insulating film 6 (for example, a silicon oxide film (SiO ₂ film)) is deposited on the semiconductor substrate 2 as shown in FIG.

  Next, as shown in FIG. 3, the insulating film 6 is polished by chemical mechanical polishing (ie, chemical mechanical polishing) to expose the upper surfaces of the first semiconductor region 4a and the second semiconductor region 4b. The insulating film 6 is polished by, for example, chemical mechanical polishing using a first slurry described later.

  Next, as shown in FIG. 4, the upper portion of the polished insulating film 6 is removed by, for example, wet etching to expose the upper portions (upper surface and part of side surfaces) of the first semiconductor region 4 a and the second semiconductor region 4 b. . The height of the exposed portion of the first semiconductor region 4a and the second semiconductor region 4b is, for example, 15 nm to 60 nm (for example, 30 nm).

  Next, as shown in FIG. 5, ions 8 of a first conductivity type impurity (for example, p-type impurity) are implanted into the first semiconductor region 4a and the second semiconductor region 4b.

  Next, the first semiconductor region 4a and the second semiconductor region 4b are heat-treated to recover the damage to the first semiconductor region 4a and the second semiconductor region 4b while activating the implanted impurities. As a result, the first semiconductor region 4a and the second semiconductor region 4b become semiconductor regions of the first conductivity type.

  Next, as shown in FIG. 6, the thermal oxide film 10 is formed by oxidizing the upper portions of the first semiconductor region 4a and the second semiconductor region 4b.

  In FIG. 2A, the portions seen through the insulating film 6 (specifically, the first semiconductor region 4a and the second semiconductor region 4b) are indicated by broken lines (the same applies to the following drawings). is there).

(2) Formation of dummy gate electrode (see FIGS. 7 to 18)
7 to 18 are diagrams for explaining a process of forming a dummy gate electrode.

  After the formation of the thermal oxide film 10, a first dummy gate electrode 12a, a second dummy gate electrode 12b, a first stop film 14a, and a second stop film 14b are formed on the semiconductor substrate 2 as shown in FIG. .

  The first dummy gate electrode 12a is a dummy gate electrode having a first gate length L1 (see FIG. 18B) and a first upper surface 16a. The second dummy gate electrode 12b is a dummy gate electrode having a second gate length L2 longer than the first gate length L1 and a second upper surface 16b.

  The first stop film 14a is provided on the first dummy gate electrode 12a, includes a first insulating material (for example, silicon nitride (SiN)), and has a first height H1 (that is, a first film thickness) from the first upper surface 16a. , See FIG. 18C). The second stop film 14b is provided on the second dummy gate electrode 12b, includes a first insulating material (for example, silicon nitride), and has a second height H2 from the second upper surface 16b (that is, higher than the first height H1). , A stop film having a second film thickness greater than the first film thickness.

  The first dummy gate electrode 12a is provided so as to cover the upper surface and the side surface of the first semiconductor region 4a via the first gate insulating film 18a while intersecting the first semiconductor region 4a in plan view. Similarly, the second dummy gate electrode 12b is provided so as to cover the upper surface and the side surface of the second semiconductor region 4b via the second gate insulating film 18b while intersecting the second semiconductor region 4b in plan view. The first gate insulating film 18a is, for example, a part of the thermal oxide film 10 formed by oxidizing the upper portion of the first semiconductor region 4a. For example, the second gate insulating film 18b is a part of the thermal oxide film 10 formed by oxidizing the upper portion of the second semiconductor region 4b.

  The width W1 of the first dummy gate electrode 12a and the width W2 of the second dummy gate electrode 12b are, for example, 10 nm to 1000 nm. The gate length L1 of the first dummy gate electrode 12a is, for example, 10 nm to 50 nm. The gate length L2 of the second dummy gate electrode 12a is, for example, 150 nm to 1000 nm.

  The FinFET corresponding to the first dummy gate electrode 12a is, for example, a field effect transistor that can operate at high speed. The FinFET corresponding to the second dummy gate electrode 12b is, for example, a field effect transistor that can operate with low power consumption.

  Specifically, for example, the first and second dummy gate electrodes 12a and 12b and the first and second stop films 14a and 14b are formed by the following procedure.

(2-1) Formation of dummy gate material (FIGS. 7 to 8)
FIG. 7 is a diagram illustrating a process for forming a dummy gate material. FIG. 8 is a diagram for explaining the polishing process of the dummy gate material.

  After the formation of the thermal oxide film 10, as shown in FIG. 7, a dummy gate material 20 (for example, polycrystalline silicon) is deposited on the semiconductor substrate 2 by, for example, chemical vapor deposition. Thereafter, as shown in FIG. 8, the dummy gate material 20 is planarized by, for example, chemical mechanical polishing.

  In addition, the broken line B shown in FIG.7 (c) and FIG.8 (c) has each shown the refraction | bending position of the VIIC line and the VIIIC line (the same is applied also after FIG. 9).

(2-2) Formation of first insulating film (see FIGS. 9 to 15)
9-15 is a figure explaining the formation process of a 1st insulating film.

  After the formation of the dummy gate material 20, as shown in FIG. 15, the first insulating film 24a including the first insulating material (for example, silicon nitride) having the first protrusions 22a on the planarized dummy gate material 20 is provided. Form.

  Specifically, for example, the first insulating film 24a is formed by the following procedure.

(2-2-1) Formation of lower insulating film and upper insulating film (see FIG. 9)
First, as shown in FIG. 9, a lower insulating film 26 and an upper insulating film 28 on the lower insulating film 26 are formed on the planarized dummy gate material 20 by, for example, plasma CVD (plasma chemical vapor deposition).

The lower insulating film 26 is an insulating film (for example, SiN film) containing a first insulating material (for example, silicon nitride). The thickness of the lower insulating film 26 is, for example, 30 nm to 50 nm. The upper insulating film 28 is an insulating film (for example, SiO ₂ film) containing a third insulating material (for example, silicon oxide (SiO ₂ )) different from the first insulating material. The thickness of the upper insulating film 28 is, for example, 5 nm to 20 nm.

(2-2-2) Formation of mask pattern (see FIG. 10)
As shown in FIG. 10, a third mask pattern 30c (for example, a pattern of a photoresist film) corresponding to the first protrusion 22a is formed on the upper insulating film.

(2-2-3) Formation of first insulating film pattern (see FIGS. 11 to 13)
-Etching of upper insulating film (see Fig. 11)-
As shown in FIG. 11, the upper insulating film 28 and the upper part of the lower insulating film 26 are etched by dry etching using the third mask pattern 30c as a mask to form the second protrusion 22b in the lower insulating film 26. By this etching, the first insulating film pattern 32a is also formed. The first insulating film pattern 32a is an insulating film pattern (for example, a SiO ₂ film pattern) having a portion on the second convex portion 22b of the upper insulating film 28 (see FIG. 10).

The dry etching for forming the first insulating film pattern 32a is, for example, the ratio of the etching rate V _L of the lower insulating film 26 (for example, silicon nitride) to the etching rate V _U of the upper insulating film 28 (for example, silicon oxide) (= V _L / V _U ) is substantially dry etching. Such dry etching is hereinafter referred to as low selectivity dry etching.

Low selective dry etching is performed by, for example, RIE (reactive ion) in which SF ₆ gas having a flow rate of 3 to 10 sccm, O ₂ gas having a flow rate of 20 to 50 sccm, and N ₂ gas having a flow rate of 20 to 80 sccm are converted into plasma and irradiated to the etching target film. etching). According to this low selectivity dry etching, the ratio of the silicon nitride etching rate V _SIN to the silicon oxide etching rate V _SIO (= V _SIN / V _SIO ) is, for example, 1.2 to 2.0.

-Side etching of upper insulating film (see Figs. 12 to 13)-
The first insulating film pattern 32a whose upper surface is covered with the third mask pattern 30c (see FIG. 11) is etched from the side surface (ie, side-etched), for example, by wet etching. As a result, as shown in FIG. 12, the second insulating film pattern 32 b is formed from the upper insulating film 28. The second insulating film pattern 32b is an insulating film pattern (for example, a SiO ₂ film pattern).

  Thereafter, as shown in FIG. 13, the third mask pattern 30c is removed.

(2-2-4) Etching of lower insulating film (see FIGS. 14 to 15)
The upper part of the lower insulating film 26 after the formation of the second protrusion 22b (see FIG. 13) is further etched by, for example, dry etching through the second insulating film pattern 32b. As a result, as shown in FIG. 14, a first insulating film 24a (for example, a SiN film) having the first protrusions 22a is formed.

  Thereafter, as shown in FIG. 15, the second insulating film pattern 32b is removed by, for example, wet etching (for example, etching with diluted HF).

Lower dry etching the upper through the second insulating layer pattern 32b is etched in the insulating film 26 (see FIG. 13), for example, the second insulating film pattern 32b (e.g., silicon oxide) lower insulating layer to the etch rate V _U of This is dry etching in which the ratio (= V _L / V _U ) of the etching rate V _L of 26 (for example, silicon nitride) is larger than 2. Such dry etching is hereinafter referred to as high selectivity dry etching.

  As shown in FIG. 13, the central portion of the second convex portion 22 b is covered with a second insulating film pattern 32 b whose dry etching rate is slower than that of the lower insulating film 26. Therefore, when the upper portion of the lower insulating film 26 is etched through the second insulating film pattern 32b by high selectivity dry etching, as shown in FIG. 15, the first convex portion 22a whose central portion is thicker than the peripheral end portion is formed. It is formed.

The above-described high selectivity dry etching is RIE in which, for example, an O ₂ gas having a flow rate of 5 to 10 sccm and a CHF ₃ gas having a flow rate of 60 to 100 sccm are converted into plasma at a pressure (20 to 60 mTorr) and irradiated onto the etching target film.

According to this high selectivity dry etching, the ratio of the silicon nitride etching rate V _SIN to the silicon oxide etching rate V _SIO (= V _SIN / V _SIO ) is, for example, 4.5-10.

(2-3) Formation of mask pattern (see FIGS. 16 to 17)
16 to 17 are views for explaining a first mask pattern forming process.

  After the formation of the first insulating film 24a, as shown in FIG. 17, the first mask pattern 30a corresponding to the first dummy gate electrode 12a and covering the flat portion of the first insulating film 24a, and the second dummy gate electrode 12b. Then, a second mask pattern 30b covering the first convex portion 22a is formed.

(2-3-1) Formation of protective film (see FIG. 16)
First, as shown in FIG. 16, before forming the first mask pattern 30a (see FIG. 17) and the second mask pattern 30b, a fourth insulating material (for example, silicon nitride) different from the first insulating material (for example, silicon nitride) is formed. The first insulating film 24a is covered with a protective film 34 containing silicon oxide). The protective film 34 is formed on the first insulating film 24a by, for example, plasma CVD.

(2-3-2) Formation of mask pattern (see FIG. 17)
Thereafter, as shown in FIG. 17, a first mask pattern 30 a and a second mask pattern 30 b are formed on the first insulating film 24 a via the protective film 34. The first mask pattern 30a and the second mask pattern 30b are, for example, photoresist film patterns.

(2-4) Etching of dummy gate material and first insulating film (see FIG. 18)
FIG. 18 is a diagram illustrating an etching process of the dummy gate material 20 and the first insulating film 24a.

  The protective film 34, the first insulating film 24a, and the dummy gate material 20 are etched using the first mask pattern 30a (see FIG. 17) and the second mask pattern 30b as a mask. The first insulating film 24a and the dummy gate material 20 are etched by, for example, dry etching.

  Thereafter, the thermal oxide film 10 exposed by etching the dummy gate material 20 is removed by wet etching. Thereafter, the first mask pattern 30a and the second mask pattern 30b are removed.

  Thereby, as shown in FIG. 18, the first dummy gate electrode 12a, the second dummy gate electrode 12b, the first stop film 14a, and the second stop film 14b are formed.

  The first insulating film 24a on the first dummy gate electrode 12a is etched twice ("(2-2-3) Formation of first insulating film pattern" and "(2-2-4) Lower insulating film Etching "). On the other hand, the central portion of the first insulating film 24a on the second dummy gate electrode 12b is never etched. Therefore, the height H2 of the second stop film 14b on the second dummy gate electrode 12b is higher than the height H1 of the first stop film 14a on the first dummy gate electrode 12a.

  The second stop film 14b is formed from the first protrusion 22a (see FIG. 15) of the first insulating film 24a. Accordingly, the central portion of the second stop film 14b is thicker than the peripheral end portion.

Note that the dummy gate material 20 (for example, polycrystalline silicon) is etched by, for example, RIE in which CF ₄ gas and H ₂ gas are turned into plasma and irradiated onto the etching target film.

(3) Formation of source / drain regions and the like (see FIGS. 19 to 22)
19 to 22 are diagrams for explaining a process of forming source / drain regions and the like.

  First, as shown in FIG. 19, sidewalls 36 are formed on the side surfaces of the first dummy gate electrode 12a and the second dummy gate electrode 12b. The sidewall 36 is formed by, for example, depositing a first insulating material (for example, silicon nitride) and etching back.

  At this time, the first insulating material (for example, silicon nitride) is etched by, for example, the above-described high selectivity dry etching. At this time, the first stop film 14a and the second stop film 14b are not etched because they are protected by the protective film 34 (for example, a silicon oxide film).

  Next, an impurity of a second conductivity type opposite to the first conductivity type (for example, an n-type impurity) is ion-implanted on both sides of the first dummy gate electrode 12a and the second dummy gate electrode 12b. Thereafter, the semiconductor substrate 2 is heat treated to recover the damage to the semiconductor substrate 2 while activating the implanted impurities. As a result, source / drain regions 38 are formed on both sides of each of the first dummy gate electrode 12a and the second dummy gate electrode 12b as shown in FIG.

  After the formation of the source / drain regions 38, a metal film (not shown) is deposited on the surface of the semiconductor substrate 2. Thereafter, the semiconductor substrate 2 is heat-treated and reacted with the metal film to form silicide electrodes 40 (for example, NiPtSi electrodes, CoSi electrodes, NiSi electrodes, etc.) in the source / drain regions 38 as shown in FIG. After the heat treatment, the unreacted metal film is removed by wet etching. Next, the protective film 34 is removed by wet etching (for example, etching with diluted HF).

  Thereafter, as shown in FIG. 22, for example, a first insulating material (for example, silicon nitride) is deposited on the semiconductor substrate 2 to form a CESL 42 (contact-etch-stop layer).

(4) Formation of interlayer insulating film (see FIG. 23)
FIG. 23 is a diagram illustrating a process for forming the interlayer insulating film 44.

As shown in FIG. 23, an insulating film 44 containing a second insulating material (for example, silicon oxide) is formed on the first dummy gate electrode 12a, the second dummy gate electrode 12b, and the semiconductor substrate 2 through the CESL 42. (Interlayer insulating film) is formed. The insulating film 44 is formed by, for example, plasma CVD. The insulating film 44 is, for example, a SiO ₂ film.

(5) Chemical mechanical polishing of insulating film and stop film (see FIGS. 24 to 25)
FIG. 24 is a diagram for explaining a chemical mechanical polishing process of the insulating film 44. FIG. 25 is a diagram for explaining a chemical mechanical polishing process of the stop films 14a and 14b.

  As shown in FIGS. 24 and 25, the insulating film 44, the first stop film 14a, and the second stop film 14b are polished to expose the upper surface of the first dummy gate electrode 12a and the upper surface of the second dummy gate electrode 12b. . Specifically, for example, the upper surface of the first dummy gate electrode 12a and the upper surface of the second dummy gate electrode 12b are exposed by the following procedure.

(5-1) First chemical mechanical polishing (see FIG. 24)
First, the insulating film 44 (see FIG. 23) is polished by first chemical mechanical polishing in which the second insulating material (for example, silicon oxide) is polished faster than the first insulating material (for example, silicon nitride). 24, the insulating film 44 on the first stop film 14a (for example, silicon nitride film) and the second stop film 14b (for example, silicon nitride film) is removed.

  The first chemical mechanical polishing is chemical mechanical polishing in which a film to be polished is polished with a first slurry. The first slurry has a second polishing material (for example, oxidation) included in the insulating film 44 at a first polishing rate for the first insulating material (for example, silicon nitride) included in the first stop film 14a and the second stop film 14b. It is an abrasive having a high second polishing rate for silicon. Accordingly, the first chemical mechanical polishing is substantially stopped at the first stop film 14a and the second stop film 14b. Alternatively, when the CECL 42 having the first insulating material is sufficiently thick, the first chemical mechanical polishing is substantially stopped at the CECL 42.

The first slurry is, for example, a slurry in which silica (SiO ₂ ) or ceria (CeO ₂ ) abrasive grains are mixed with an alkaline solution such as potassium hydroxide (KOH) or ammonia water (NH ₄ OH).

(5-2) Second chemical mechanical polishing (see FIG. 25)
Next, as shown in FIG. 25, the first stop film 14a and the second stop are polished by the second chemical mechanical polishing for polishing the first insulating material (for example, silicon nitride) faster than the second insulating material (for example, silicon oxide). The film 14b is removed. When the CECL 42 having the first insulating material remains on the first stop film 14a and the second stop film 14b, the CECL 42, the first stop film 14a, and the second stop film 14b are removed by the second chemical mechanical polishing. To do.

  The second chemical mechanical polishing is chemical mechanical polishing in which a film to be polished is polished with a second slurry. The second slurry is an abrasive having a first polishing rate for a first insulating material (for example, silicon nitride) higher than a second polishing rate for a second insulating material (for example, silicon oxide).

  A slurry (i.e., second slurry) that polishes a first insulating material (e.g., silicon nitride) faster than a second insulating material (e.g., silicon oxide) causes the dummy gate material 20 (e.g., polycrystalline silicon) to be second-insulated. Polish faster than the material (eg, silicon oxide).

  The ratio of the first polishing rate to the second polishing rate in the second chemical mechanical polishing is, for example, 100 to 150. The ratio of the third polishing rate of the second slurry to the dummy gate material 20 (for example, polycrystalline silicon) and the first polishing rate to the first insulating material (for example, silicon nitride) is approximately 1, for example.

The second slurry is, for example, a slurry in which silica (SiO ₂ ) or ceria (CeO ₂ ) abrasive grains are mixed in a phosphoric acid (H ₃ PO ₄ ) aqueous solution.

(6) Removal of dummy gate electrode (see FIG. 26)
FIG. 26 is a diagram illustrating a dummy gate electrode removal process.

  Next, as shown in FIG. 26, the first dummy gate electrode 12a and the second dummy gate electrode 12b are removed. For example, the first dummy gate electrode 12a and the second dummy gate electrode 12b are removed by dry etching of the dummy gate material (see “(2-4) Etching of dummy gate material and first insulating film”).

(7) Formation of metal gate (see FIGS. 27 to 28)
27 and 28 are diagrams for explaining a metal gate formation process.

  A metal gate 48 (see FIG. 28) is formed in each of the first region 46a (see FIG. 26) from which the first dummy gate electrode 12a has been removed and the second region 46b from which the second dummy gate electrode 12b has been removed. For example, the metal gate 48 is formed by the following procedure.

  First, as shown in FIG. 27, a conductive film 51 containing metal (for example, a Ti film, a Ta film, a TiN film, a TaN film, a Ni film, and an Ir film) is deposited on the semiconductor substrate 2. The conductive film 51 is polished by chemical mechanical polishing to form a metal gate 48 disposed in each of the first region 46a and the second region 46b as shown in FIG.

(8) Formation of wiring layer (see FIGS. 29 to 31)
FIG. 29 to FIG. 31 are diagrams for explaining the formation process of the wiring layer.

  After the formation of the metal gate 48, a second interlayer insulating film 44b (see FIG. 29) is formed on the insulating film 44 (hereinafter referred to as the first interlayer insulating film). Thereafter, as shown in FIG. 29, a first contact hole 50a reaching the silicide electrode 40 and a second contact hole 50b reaching the metal gate 48 are formed in the first interlayer insulating film 44 and the second interlayer insulating film 44b. .

  Next, as shown in FIG. 30, a via 52 is formed in each of the first contact hole 50a and the second contact hole 50b. For example, the via 52 is a conductor having a barrier metal film (for example, a TiN film) and a low resistance metal (for example, W). As a result, a first wiring layer 54a (see FIG. 31) is formed.

  Thereafter, as shown in FIG. 31, second and subsequent wiring layers 54b including the wiring 56 connected to the via 52 are formed on the second insulating film 44b. Thus, the semiconductor device 58 is formed.

(9) Suppression of dishing (see FIGS. 32 to 33)
FIG. 32 is a cross-sectional view for explaining chemical mechanical polishing when a third stop film 14c having substantially the same thickness as the first stop film 14a on the first dummy gate electrode 12a is provided on the second dummy gate electrode 12b. It is. The third stop film 14c is an insulating film having the same first insulating material (for example, silicon nitride) as the first stop film 14a.

  FIG. 32A is a cross-sectional view after the insulating film 44 is polished by the first chemical mechanical polishing. FIG. 32B is a cross-sectional view after the first stop film 14a and the third stop film 14c are polished by the second chemical mechanical polishing.

  The second chemical mechanical polishing is continued for a certain period after the upper surfaces of the first and second dummy gate electrodes 12a and 12b are exposed. By this over-etching, the upper surfaces of the first and second dummy gate electrodes 12a and 12b are reliably exposed.

  In the second chemical mechanical polishing, the first polishing rate for the first and third stop films 14a and 14c (for example, silicon nitride film) is higher than the second polishing rate for the insulating film 44 (for example, silicon oxide film). Polishing. Further, the second chemical mechanical polishing is chemical mechanical polishing in which the third polishing rate for the dummy gate material 20 (for example, polycrystalline silicon) is faster than the second polishing rate for the insulating film 44 (for example, silicon oxide).

  Now, the first and third stop films 14 a and 14 c are removed by the second chemical mechanical polishing, and the upper surfaces of the first and second dummy gate electrodes 12 a and 12 b are positioned substantially on the same plane as the insulating film 44. Think about the state. In this state, the polishing rate of the first and second dummy gate electrodes 12a and 12b decreases due to the influence of the insulating film 44 surrounding the periphery.

  The decrease in the polishing rate is greater in the vicinity of the insulating film 44. For this reason, dishing in which the upper surfaces of the first and second dummy gate electrodes 12a and 12b are recessed at the center portion is likely to occur.

  The decrease in the polishing rate decreases as the distance from the insulating film 44 increases. For this reason, as shown in FIG. 32B, a deep dent is generated in the second dummy gate electrode 12b having a long gate length. On the other hand, the dent generated in the first dummy gate electrode 12a having a short gate length is shallow (FIG. 32B shows a case where the dent of the first dummy gate electrode 12a can be ignored). The recess of the second dummy gate electrode 12b becomes deeper as the polishing time becomes longer.

  In the manufacturing method of the first embodiment, as shown in FIG. 18, since the second stop film 14b is thicker than the first stop film 14a, the time when the polishing of the second dummy gate electrode 12b starts is the first dummy gate electrode 12a. It will be later than the time when the polishing starts. For this reason, the polishing time of the second dummy gate electrode 12b is shorter than the polishing time of the first dummy gate electrode 12a. As a result, dishing of the second dummy gate electrode 12b in which deep dents are likely to occur is suppressed. Therefore, according to the first embodiment, dishing can be suppressed.

  Furthermore, in the first embodiment, the central portion of the second stop film 14b is thicker than the peripheral end portion. For this reason, the polishing time of the central portion of the second dummy gate electrode 12b is shorter than that of the peripheral end portion. For this reason, dishing of the second dummy gate electrode 12b is further suppressed.

―Threshold variation due to dishing―
FIG. 33 is a Pelgrom diagram of a FinFET manufactured by providing stop films having substantially the same thickness on a plurality of dummy gate electrodes having different gate lengths as shown in FIG. The vertical axis represents the standard deviation σ of the FinFET threshold. The horizontal axis is the square root of the product of the gate length L and the gate width W of the FinFET, that is, the square root of the gate area (= L × W). FIG. 33 shows a standard deviation σ measured in a FinFET group having a constant pitch and Fin width.

  A data point “■” in FIG. 33 indicates a standard deviation σa obtained by measuring a FinFET having a gate length of 10 nm to 50 nm. A data point “●” in FIG. 33 indicates a standard deviation σb obtained by measuring a FinFET having a gate length of 150 nm to 1000 nm.

  As is apparent from FIG. 33, when the gate area (= L × W) is the same, the standard deviation σb of the FinFET having the long gate length is larger than the standard deviation σa of the FinFET having the short gate length. That is, FIG. 33 shows that the variation in threshold value increases as the gate length increases.

  As described above, the metal gate 48 is formed in a region where the dummy gate electrodes 12a and 12b are removed by dry etching. The surface layer of the semiconductor substrate below the metal gate 48 becomes a channel region where carriers travel.

  As shown in FIG. 32, the second dummy gate electrode 12b having a long gate length is thinner than the first dummy gate electrode 12a having a short gate length by the depth of the recess 60 generated by dishing. Therefore, the second dummy gate electrode 12b is removed in a shorter time than the first dummy gate electrode 12a.

  After the removal of the second dummy gate electrode 12b, the semiconductor substrate 2 in the region where the second dummy gate electrode 12b was present is interposed via the thermal oxide film 10 until the dry etching of the first dummy gate electrode 12a is completed ( Exposure to plasma (dry etching).

  At this time, the surface layer of the semiconductor substrate 2 exposed to the plasma becomes a channel region of the FinFET in which the second dummy gate electrode 12b is replaced with a metal gate. The physical properties of this channel region vary depending on the damage received from the plasma. As a result, in the case of a FinFET in which the second dummy gate electrode 12b is replaced with a metal gate, that is, a FinFET having a long gate length, the variation in threshold value increases.

  As described above, in the first embodiment, dishing is suppressed by increasing the thickness of the second stop film 14b on the second dummy gate electrode 12b as shown in FIG. Therefore, according to the first embodiment, variation in the threshold value of the FinFET can be suppressed.

  By the way, the variation in the threshold value of the FinFET becomes apparent when the dishing of the dummy gate electrode is 5 nm or more. Therefore, the height H2 (see FIG. 18C) of the second stop film 14b is preferably 5 nm or more higher than the height H1 of the first stop film 14a (see FIG. 18C).

  On the other hand, when the height difference between the first stop film 14a and the second stop film 14b is greater than 30 nm, it is difficult to planarize the insulating film 44 by the first chemical mechanical polishing.

  Accordingly, the height H2 of the second stop film 14b is preferably higher than the height H1 of the first stop film 14a by 5 nm or more and 30 nm or less. More preferably, the height H2 of the second stop film 14b is preferably 15 nm or more and 20 nm or less higher than the height H1 of the first stop film 14a.

  For example, when the height H1 of the first stop film 14a is 15 nm to 30 nm, the height H2 of the second stop film 14b is preferably 20 nm (= 15 nm + 5 nm) or more and 60 nm (= 30 nm + 30 nm) or less. More preferably, the height H2 of the second stop film 14b is not less than 30 nm (= 15 nm + 15 nm) and not more than 50 nm (= 30 nm + 20 nm).

(Embodiment 2)
The second embodiment is similar to the first embodiment. Therefore, description of portions common to Embodiment 1 is omitted or simplified.

  34 to 44 are views for explaining the method of manufacturing the semiconductor device of the second embodiment.

  FIG. 34 (a), FIG. 35 (a)... FIG. 44 (a) is a plan view. 34 (b), 35 (b)... FIG. 44 (b) are respectively the XXXIVB line in FIG. 34 (a), the XXXVB line in FIG. 35 (a), and the XLIVB line in FIG. 44 (a). FIG. 34 (c), 35 (c)... FIG. 44 (c) are respectively the XXXIVC line in FIG. 34 (a), the XXXVC line in FIG. 35 (a), and the XLIVC line in FIG. FIG.

(1) Fin formation, etc. (See FIGS. 1-6)
The first semiconductor region 4a (Fin) and the second semiconductor region 4b (Fin) are formed in the semiconductor substrate 2 (for example, Si substrate) by the procedure of the first embodiment described with reference to FIGS. Then activate.

(2) Formation of dummy gate electrode and stop film (see FIGS. 7 to 9 and FIGS. 34 to 40)
34 to 40 are diagrams for explaining the steps of forming the dummy gate electrode and the stop film according to the second embodiment.

  After the formation of the first semiconductor region 4a and the second semiconductor region 4b, as shown in FIG. 40, on the semiconductor substrate 2 (for example, Si substrate), the first dummy gate electrode 12a, the second dummy gate electrode 12b, the first A stop film 14a and a second stop film 14b are formed.

  As shown in FIG. 40, the height H2 (see FIG. 40C) of the second stop film 14b is higher than the height H1 of the first stop film 14a, as in the first embodiment. Further, the central portion of the second stop film 14b is thicker than the peripheral end portion of the second stop film 14b, as in the first embodiment.

  The first stop film 14a of the first embodiment is flat as shown in FIG. On the other hand, the first stop film 14a of the second embodiment is convex as shown in FIG. That is, the central portion of the first stop film 14a of the second embodiment is thicker than the peripheral end portion of the first stop film 14a.

  Specifically, the first dummy gate electrode 12a, the second dummy gate electrode 12b, the first stop film 14a, and the second stop film 14b are formed by the following procedure, for example.

(2-1) Formation of dummy gate material to mask pattern (see FIGS. 7 to 9 and FIG. 34)
FIG. 34 is a diagram for explaining a dummy gate material forming process to a mask pattern forming process.

  First, the dummy gate material 20 (for example, polycrystalline silicon) is deposited on the semiconductor substrate 2 by the procedure of the first embodiment described with reference to FIGS.

  Next, the lower insulating film 26 containing the first insulating material (for example, silicon nitride) is formed on the planarized dummy gate material 20 by the procedure of the first embodiment described with reference to FIG. Further, an upper insulating film 28 containing a third insulating material (for example, silicon oxide) different from the first insulating material is formed on the lower insulating film 26.

  Thereafter, as shown in FIG. 34, a first mask pattern 30a corresponding to the first dummy gate electrode 12a and a second mask pattern 30b corresponding to the second dummy gate electrode 12b are formed on the upper insulating film. The first mask pattern 30a and the second mask pattern 30b are, for example, photoresist film patterns.

(2-2) Etching of dummy gate material (see FIG. 35)
FIG. 35 is a diagram for explaining an etching process of the dummy gate material.

  The upper insulating film 28, the lower insulating film 26, and the dummy gate material 20 are etched using the first mask pattern 30a and the second mask pattern 30b as a mask.

  The first mask pattern 30a and the second mask pattern 30b are etched by, for example, the low selectivity dry etching described in the first embodiment. The dummy gate material 20 is etched by, for example, dry etching of the dummy gate material 20 described in the first embodiment (see “(2-4) Etching of dummy gate material and first insulating film” in the first embodiment). .

  By these etchings, a first dummy gate electrode 12a and a first lower insulating film pattern 62a having a portion of the lower insulating film 26 on the first dummy gate electrode 12a are formed. Further, a first upper insulating film pattern 64a having a portion of the upper insulating film 28 on the first dummy gate electrode 12a is formed.

  Further, the etching forms the second dummy gate electrode 12b and the second lower insulating film pattern 62b having a portion of the lower insulating film 26 on the second dummy gate electrode 12b. Further, a second upper insulating film pattern 64b having a portion of the upper insulating film 28 on the second dummy gate electrode 12b is formed.

(2-3) Side etching of upper insulating film pattern (see FIGS. 36 to 37)
36 and 37 are views for explaining a side etching process of the upper insulating film patterns 64a and 64b.

  The first upper insulating film pattern 64a (see FIG. 35) with the upper surface covered with the first mask pattern 30a and the second upper insulating film pattern 64b (see FIG. 35) with the upper surface covered with the second mask pattern 30b. Are etched from the respective side surfaces as shown in FIG. This etching is, for example, wet etching with diluted HF.

  Thus, as shown in FIG. 37, the third upper insulating film pattern 64c having the first sizes S1 and s1, and the fourth upper insulating film pattern 64d having the second sizes S2 and s2 larger than the first sizes S1 and s1, Form.

  Thereafter, the first mask 30a and the second mask 30b are removed.

(2-4) Formation of stop film (see FIGS. 38 to 40)
38 to 40 are views for explaining the steps of forming the first stop film 14a and the second stop film 14b.

  As shown in FIGS. 38 to 40, the first lower insulating film pattern 62a and the second lower insulating film pattern 62b are etched while etching the third upper insulating film pattern 64c and the fourth upper insulating film pattern 64d. . The first lower insulating film pattern 62a, the second lower insulating film pattern 62b, the third upper insulating film pattern 64c, and the fourth upper insulating film pattern 64d are formed by, for example, the low selectivity dry etching described in the first embodiment. Etch.

  38 and 39 are views showing the states of the first lower insulating film pattern 62a to the fourth upper insulating film pattern 64d according to the progress of etching. FIG. 38 shows a state immediately after the start of etching. FIG. 39 shows a state when the third upper insulating film pattern 64c on the first dummy gate electrode 12a disappears. FIG. 40 is a diagram illustrating a state at the time when the etching of the first lower insulating film pattern 62a to the fourth upper insulating film pattern 64d is completed.

  As shown in FIG. 40, the etching of the first lower insulating film pattern 62a to the fourth upper insulating film pattern 64d is performed when the fourth upper insulating film pattern 64d on the second dummy gate electrode 12b disappears (or thereafter). It will be finished soon. By this etching, the first stop film 14a and the second stop film 14b are formed.

(3) Formation of source / drain regions and the like (see FIG. 41)
FIG. 41 is a diagram illustrating a process for forming the source / drain regions 38 and the like.

  As shown in FIG. 41, for example, by substantially the same procedure as in the first embodiment (refer to “(3) Formation of source / drain regions and the like” in the first embodiment), the sidewalls 36, source / drain regions 38, silicide electrodes 40, and CESL42.

  The sidewalls 36 are formed by etching back a first insulating material (for example, silicon nitride) deposited on the semiconductor substrate 2. Since the first and second stop films 14 a and 14 b are formed of the same first insulating material as that of the sidewall 36, there is a possibility that the sidewall 36 is etched by etching back.

  In the first embodiment, etching of the first and second stop films 14 a and 14 b is suppressed by the protective film 34. However, in the second embodiment, as shown in FIG. 40, no protective film is provided on the first stop film 14a and the second stop film 14b.

  Therefore, in the second embodiment, the etch back of the first insulating material that becomes the side wall 36 is terminated immediately after the disappearance of the first insulating material. Thereby, the etching of the first stop film 14a and the second stop film 14b is suppressed.

  The silicide electrode 40 is formed by heat-treating the semiconductor substrate 2 on which the metal film is deposited. At this time, a metamorphic layer is formed at the metal film / insulating film interface (for example, the metal film / stop film interface). It is not easy to remove such a metamorphic layer by the second chemical mechanical polishing.

  In the first embodiment, after removing the unreacted metal by wet etching, the metamorphic layer is removed together with the protective film 34 (see FIG. 18) by, for example, diluted HF.

  Since the protective film 34 is not provided in the second embodiment, the metamorphic layer is removed together with the unreacted metal by increasing the wet etching time of the unreacted metal.

(4) Formation of interlayer insulating film (see FIG. 42)
FIG. 42 is a diagram illustrating a process for forming the interlayer insulating film 44.

  As shown in FIG. 42, an insulating film 44 (interlayer insulating film) containing a second insulating material (for example, silicon oxide) is formed on the first dummy gate electrode 12a, the second dummy gate electrode 12b, and the semiconductor substrate 2. To do. The insulating film 44 is formed, for example, according to the procedure described in the first embodiment.

(5) Chemical mechanical polishing of insulating film and stop film (see FIGS. 43 to 44)
43 and 44 are diagrams for explaining the chemical mechanical polishing process of the insulating film 44 and the stop films 14a and 14b, respectively.

  First, as shown in FIG. 43, the insulating film 44 is polished, for example, by the procedure described in the first embodiment (see “(5-1) First chemical mechanical polishing” in the first embodiment). By this polishing, the insulating film 44 on the first stop film 14a and the insulating film 44 on the second stop film 14b are removed.

  Next, as shown in FIG. 44, for example, by the procedure described in the first embodiment (see “(5-2) Second chemical mechanical polishing” in the first embodiment), the first stop film 14a and the second stop film 14b. As a result, the upper surface of the first dummy gate electrode 12a and the upper surface of the second dummy gate electrode 12b are exposed.

(6) Removal of dummy gate electrode to formation of wiring layer Next, for example, by the procedure described in the first embodiment (see “(6) Removal of dummy gate electrode” in the first embodiment), the first dummy gate electrode 12a and the second dummy gate electrode 12b are removed.

  Next, for example, by the procedure described in the first embodiment (see “(7) Formation of metal gate” in the first embodiment), the region from which the first dummy gate electrode 12a has been removed and the second dummy gate electrode 12b are removed. A metal gate is formed in each of the regions.

  Thereafter, the wiring layer is formed by the procedure described in the first embodiment (see “(8) Formation of wiring layer” in the first embodiment). As described above, the semiconductor device of the second embodiment is completed.

  In the second embodiment, the first stop film 14a and the second stop film 14b are formed without providing the first protrusion 22a (see FIG. 15). For this reason, the third mask pattern 30c (see FIG. 11) corresponding to the first convex portion 22a is not formed, so that one photolithography process is reduced. Therefore, according to the second embodiment, the manufacturing process is simplified.

(Embodiment 3)
The third embodiment is similar to the second embodiment. Therefore, description of portions common to Embodiment 2 is omitted or simplified.

  FIG. 45 illustrates a method for manufacturing the semiconductor device of the third embodiment.

  FIG. 45A is a plan view. FIG. 45B is a cross-sectional view taken along line XLVB in FIG. FIG. 45 (c) is a cross-sectional view along the XLVC line of FIG. 45 (a).

(1) Formation of Fin to Side Etching of Upper Insulating Film Pattern First, the first lower insulating film pattern 62a (see FIG. 37) and the third upper insulating film pattern 64c are formed on the upper surface by the procedure described in the second embodiment. The first dummy gate electrode 12a is formed. Further, a second dummy gate electrode 12b having a second lower insulating film pattern 62b (see FIG. 37) and a fourth upper insulating film pattern 64d formed on the upper surface is formed. That is, the first and second dummy gate electrodes 12a, 12a, and 12b shown in FIG. 37 according to the procedure described in “(1) Fin formation and the like” to “(2-3) Side etching of the upper insulating film” in the second embodiment. 12b is formed.

(2) Formation of Stop Film Next, the first lower insulating film pattern 62a and the second lower insulating film pattern 62a and the second lower insulating film pattern 64d are etched while etching the third upper insulating film pattern 64c and the fourth upper insulating film pattern 64d by substantially the same procedure as in the second embodiment. The insulating film pattern 62b is etched. By this etching, the first stop film 14a and the second stop film 14b are formed (see “(2-4) Formation of stop film” in the second embodiment).

  In the second embodiment, as shown in FIG. 40, after the fourth upper insulating film pattern 64d on the second dummy gate electrode 12b disappears, the first lower insulating film pattern 62a and the second lower insulating film pattern 62b are etched. finish.

  On the other hand, in the third embodiment, after the third upper insulating film pattern 64c on the first dummy gate electrode 12a disappears and before the fourth upper insulating film pattern 64d disappears, the first lower insulating film pattern 62a and the first 2. The etching of the lower insulating film pattern 62b is finished.

(3) Formation of source / drain regions and the like (see FIG. 45)
Next, sidewalls 36, source / drain regions 38, and silicide electrodes 40 are formed by the procedure described in the second embodiment (see “(3) Formation of source / drain regions and the like” in the second embodiment). Thereafter, the CESL 42 is formed while leaving the fourth upper insulating film pattern 64d (see FIG. 45) on the second stop film 14b.

(4) Formation of Interlayer Insulating Film to Formation of Wiring Layer Next, a semiconductor device is completed by the procedure described in the second embodiment (“(4) Formation of interlayer insulating film” to “(6 (See “Dummy Gate Electrode to Wiring Layer Formation”).

  At this time, the second stop film 14b with the fourth upper insulating film pattern 64d remaining on the upper surface is removed by second chemical mechanical polishing. The etching rate of the second chemical mechanical polishing for the third insulating material (for example, silicon oxide) for forming the fourth upper insulating film pattern 64d is slow.

  However, the fourth upper insulating film pattern 64d is thinned to, for example, 10 nm or less by dry etching for forming the first stop film 14a and the second stop film 14b. Therefore, the fourth upper insulating film pattern 64d can be easily removed by the second chemical mechanical polishing.

  According to the third embodiment, since the number of photolithography processes is reduced by one as in the second embodiment, the manufacturing process is simplified.

(Embodiment 4)
The fourth embodiment is similar to the first embodiment. Therefore, description of portions common to Embodiment 1 is omitted or simplified. The semiconductor device of the fourth embodiment is a semiconductor device having a planar-type MOSFET (metal-oxide-semiconductor field-effect transistor).

  46 and 47 are diagrams illustrating the method of manufacturing the semiconductor device of the fourth embodiment.

  46 (a) and 47 (a) are plan views. 46 (b) and 47 (b) are cross-sectional views taken along the XLVIB line in FIG. 46 (a) and the XLVIIB line in FIG. 47 (a), respectively. FIG. 47C is a cross-sectional view taken along line XLVIIC in FIG.

(1) Formation and activation of active region (see FIG. 46)
First, as shown in FIG. 46, the first and second semiconductor regions 4a and 4b surrounded by the insulating layer 66 in the element isolation trench are formed in the semiconductor substrate 2. Next, for example, the first semiconductor region 4a and the second semiconductor region 4b are activated by the procedure described in the first embodiment (see “(1-2) Fin activation” in the first embodiment).

  Thereafter, the upper surfaces of the first semiconductor region 4 a and the second semiconductor region 4 b are oxidized to form a thermal oxide film 70.

(2) Formation of dummy gate electrode (see FIG. 47)
After the formation of the thermal oxide film 70, as shown in FIG. 47, the first dummy gate electrode 12a, the second dummy gate electrode 12b, the first stop film 14a, the second stop film 14b, and the protective film are formed on the semiconductor substrate 2. 34 is formed. The first dummy gate electrode 12a to the protective film 34 are formed by the procedure described in the first embodiment (see “(2) Formation of dummy gate electrode” in the first embodiment).

  As shown in FIG. 47, the first dummy gate electrode 12a covers the upper surface of the first semiconductor region 4a via the first gate insulating film 18a while intersecting the first semiconductor region 4a (active region) in plan view. It is provided as follows. Similarly, the second dummy gate electrode 12b is provided so as to cover the upper surface of the second semiconductor region 4b via the second gate insulating film 18b while intersecting the second semiconductor region 4b (active region) in plan view. . The first gate insulating film 18a and the second gate insulating film 18b are, for example, parts of the thermal oxide film 10 formed by oxidizing the upper surfaces of the first semiconductor region 4a and the second semiconductor region 4b.

(3) Formation of Source / Drain Region and the like to Formation of Interlayer Insulating Film Thereafter, a semiconductor device having a planar MOSFET is completed by substantially the same procedure as that described in the first embodiment (see “ (3) Formation of source / drain regions and the like "to" (8) Formation of wiring layer ").

  According to the fourth embodiment, a semiconductor device having a planar MOSFET can be manufactured while suppressing dishing of the dummy gate electrode.

  Embodiments 1 to 4 are illustrative and not restrictive.

  For example, in the first to fourth embodiments, the first insulating material is silicon nitride. However, the first insulating material may be another insulating material (for example, silicon oxynitride).

  In the first to fourth embodiments, the second insulating material is silicon oxide. However, the second insulating material may be another insulating material (for example, PSG (Phosphorus silicate glass), USG (un-doped silicate glass), BPSG (boron-silicate glass), etc.). The same applies to the third insulating material and the fourth insulating material.

  In the first to fourth embodiments, the first conductivity type and the second conductivity type are p-type and n-type, respectively. However, the first conductivity type and the second conductivity type may be n-type and p-type, respectively.

  In the first to fourth embodiments, the first semiconductor region 4a and the second semiconductor region 4b are different semiconductor regions. However, the first semiconductor region 4a and the second semiconductor region 4b may be one region.

  The following additional notes are further disclosed with respect to the first to fourth embodiments.

(Appendix 1)
A first dummy gate electrode having a first gate length on a semiconductor substrate, a second dummy gate electrode having a second gate length longer than the first gate length, and a first insulation provided on the first dummy gate electrode. A first stop film having a first film thickness including a material and a second stop film having a second film thickness that is provided on the second dummy gate electrode and includes the first insulating material and is thicker than the first film thickness. Forming a process; and
Forming an insulating film containing a second insulating material on the first dummy gate electrode, on the second dummy gate electrode, and on the semiconductor substrate;
Polishing the insulating film, the first stop film, and the second stop film to expose the first dummy gate electrode and the second dummy gate electrode;
Removing the first dummy gate electrode and the second dummy gate electrode after the step of exposing the first dummy gate electrode and the second dummy gate electrode;
Forming a metal gate in each of the first region from which the first dummy gate electrode has been removed and the second region from which the second dummy gate electrode has been removed.

(Appendix 2)
The manufacturing method of a semiconductor device according to appendix 1, wherein a central portion of the second stop film is thicker than a peripheral end portion of the second stop film.

(Appendix 3)
Forming the first dummy gate electrode and the second dummy gate electrode;
Forming a dummy gate material on the semiconductor substrate;
Forming a first insulating film having a first protrusion and including the first insulating material on the dummy gate material;
Forming a first mask pattern corresponding to the first dummy gate electrode and covering a flat portion of the first insulating film; and a second mask pattern corresponding to the second dummy gate electrode and covering the first convex portion. When,
Etching the first insulating film and the dummy gate material using the first mask pattern and the second mask pattern as a mask to form the first dummy gate electrode and the second dummy gate electrode; The method for manufacturing a semiconductor device according to appendix 2, wherein the method is provided.

(Appendix 4)
The step of forming the first insulating film includes:
Forming a lower insulating film including the first insulating material and an upper insulating film on the lower insulating film including a third insulating material different from the first insulating material on the dummy gate material;
Forming a third mask pattern corresponding to the first protrusion on the upper insulating film;
Etching the upper insulating film and the upper portion of the lower insulating film using the third mask pattern as a mask to form a second convex portion on the lower insulating film, and on the second convex portion of the upper insulating film Forming a first insulating film pattern having a portion of:
Etching the first insulating film pattern whose upper surface is covered with the third mask pattern from a side surface to form a second insulating film pattern of the upper insulating film;
Etching the upper part of the lower insulating film after the formation of the second convex part through the second insulating film pattern to form the first insulating film having the first convex part. The method for manufacturing a semiconductor device according to appendix 3, wherein:

(Appendix 5)
Forming the first dummy gate electrode and the second dummy gate electrode;
Covering the first insulating film with a protective film including a fourth insulating material different from the first insulating material before forming the first mask pattern and the second mask pattern;
Forming the first mask pattern and the second mask pattern on the first insulating film via the protective film;
The protective film, the first insulating film, and the dummy gate material are etched using the first mask pattern and the second mask pattern as a mask to form the first dummy gate electrode and the second dummy gate electrode. Process,
After the step of forming the first dummy gate electrode and the second dummy gate electrode and before the step of forming the insulating film,
Forming sidewalls on side surfaces of the first dummy gate electrode and the second dummy gate electrode;
Forming a source / drain region in the semiconductor substrate on both sides of each of the first dummy gate electrode and the second dummy gate electrode after forming the sidewall;
The method for manufacturing a semiconductor device according to appendix 3 or 4, wherein the protective film is removed after the source / drain regions are formed.

(Appendix 6)
The manufacturing method of a semiconductor device according to appendix 2, wherein a central portion of the first stop film is thicker than a peripheral end portion of the first stop film.

(Appendix 7)
Forming the first dummy gate electrode and the second dummy gate electrode;
Depositing a dummy gate material on the semiconductor substrate;
Forming a lower insulating film containing the first insulating material and an upper insulating film on the lower insulating film containing a third insulating material different from the first insulating material on the dummy gate material;
Forming a first mask pattern corresponding to the first dummy gate electrode and a second mask pattern corresponding to the second dummy gate electrode on the upper insulating film;
Using the first mask pattern and the second mask pattern as a mask, the upper insulating film, the lower insulating film, and the dummy gate material are etched to form the first dummy gate electrode and the first insulating film. A first lower insulating film pattern having a portion on a dummy gate electrode; a first upper insulating film pattern having a portion on the first dummy gate electrode of the upper insulating film; the second dummy gate electrode; Forming a second lower insulating film pattern having a portion of the insulating film on the second dummy gate electrode, and a second upper insulating film pattern having a portion of the upper insulating film on the second dummy gate electrode; ,
Etching the first upper insulating film pattern having an upper surface covered with the first mask pattern from a side surface to form a third upper insulating film pattern having a first size;
Etching the second upper insulating film pattern whose upper surface is covered with the second mask pattern from a side surface to form a fourth upper insulating film pattern having a second size larger than the first size;
The first lower insulating film pattern on the first dummy gate electrode and the second lower insulating film pattern on the second gate electrode while etching the third upper insulating film pattern and the fourth upper insulating film pattern. And a step of forming the first stop film and the second stop film by etching the semiconductor device.

(Appendix 8)
The polishing step includes
The insulating film is polished by first chemical mechanical polishing that polishes the second insulating material faster than the first insulating material, and the insulating film on the first stop film and the insulating film on the second stop film Removing the
Additional steps 1 to 7 including a step of removing the first stop film and the second stop film by a second chemical mechanical polishing that polishes the first insulating material faster than the second insulating material. The manufacturing method of the semiconductor device as described in any one of Claims 1-3.

(Appendix 9)
In the first chemical mechanical polishing, a second polishing rate for the second insulating material contained in the insulating film is higher than a first polishing rate for the first insulating material contained in the first stop film and the second stop film. Is a chemical mechanical polishing that polishes the film to be polished with the first slurry that is fast,
9. The method of manufacturing a semiconductor device according to appendix 8, wherein the second chemical mechanical polishing is chemical mechanical polishing in which a film to be polished is polished with a second slurry whose first polishing rate is higher than the second polishing rate. Method.

(Appendix 10)
The semiconductor substrate has a convex first semiconductor region and a convex second semiconductor region;
The first dummy gate electrode is provided so as to cover the upper surface and the side surface of the first semiconductor region through the first gate insulating film while intersecting the first semiconductor region in a plan view.
The second dummy gate electrode is provided so as to cover the upper surface and the side surface of the second semiconductor region through a second gate insulating film while intersecting the second semiconductor region in plan view. 10. A method for manufacturing a semiconductor device according to 1 to 9.

2 ... Semiconductor substrate 4a ... 1st semiconductor region 4b ... 2nd semiconductor region 12a ... 1st dummy gate electrode 12b ... 2nd dummy gate electrode 14a ... 1st stop film 14b. Second stop film 16a ... first upper surface 16b ... second upper surface 18a ... first gate insulating film 18b ... second gate insulating film 20 ... dummy gate material 22a ... first 1 convex part 22b ... 2nd convex part 24a ... 1st insulating film 26 ... Lower insulating film 28 ... Upper insulating film 30a ... 1st mask pattern 30b ... 2nd mask pattern 30c ... 3rd mask pattern 32a ... 1st insulating film pattern 32b ... 2nd insulating film pattern 34 ... Protection film 36 ... Side wall 38 ... Source / drain region 44 ... Insulation Film 48 ... Metal game 62a ... 1st lower insulating film pattern 62b ... 2nd lower insulating film pattern 64a ... 1st upper insulating film pattern 64b ... 2nd upper insulating film pattern 64c ... 3rd upper insulating film pattern 64d: fourth upper insulating film pattern

Claims (6)

A first dummy gate electrode having a first gate length on a semiconductor substrate, a second dummy gate electrode having a second gate length longer than the first gate length, and a first insulation provided on the first dummy gate electrode. A first stop film having a first film thickness including a material and a second stop film having a second film thickness that is provided on the second dummy gate electrode and includes the first insulating material and is thicker than the first film thickness. Forming a process; and
Forming an insulating film containing a second insulating material on the first dummy gate electrode, on the second dummy gate electrode, and on the semiconductor substrate;
Polishing the insulating film, the first stop film, and the second stop film to expose the first dummy gate electrode and the second dummy gate electrode;
Removing the first dummy gate electrode and the second dummy gate electrode after the step of exposing the first dummy gate electrode and the second dummy gate electrode;
Forming a metal gate in each of the first region from which the first dummy gate electrode has been removed and the second region from which the second dummy gate electrode has been removed. 2. The method of manufacturing a semiconductor device according to claim 1, wherein a central portion of the second stop film is thicker than a peripheral end portion of the second stop film. Forming the first dummy gate electrode and the second dummy gate electrode;
Forming a dummy gate material on the semiconductor substrate;
Forming a first insulating film having a first protrusion and including the first insulating material on the dummy gate material;
Forming a first mask pattern corresponding to the first dummy gate electrode and covering a flat portion of the first insulating film; and a second mask pattern corresponding to the second dummy gate electrode and covering the first convex portion. When,
Etching the first insulating film and the dummy gate material using the first mask pattern and the second mask pattern as a mask to form the first dummy gate electrode and the second dummy gate electrode; The method of manufacturing a semiconductor device according to claim 2, comprising: The step of forming the first insulating film includes:
Forming a lower insulating film including the first insulating material and an upper insulating film on the lower insulating film including a third insulating material different from the first insulating material on the dummy gate material;
Forming a third mask pattern corresponding to the first protrusion on the upper insulating film;
Etching the upper insulating film and the upper portion of the lower insulating film using the third mask pattern as a mask to form a second convex portion on the lower insulating film, and on the second convex portion of the upper insulating film Forming a first insulating film pattern having a portion of:
Etching the first insulating film pattern whose upper surface is covered with the third mask pattern from a side surface to form a second insulating film pattern of the upper insulating film;
Etching the upper part of the lower insulating film after the formation of the second convex part through the second insulating film pattern to form the first insulating film having the first convex part. The method of manufacturing a semiconductor device according to claim 3. The method for manufacturing a semiconductor device according to claim 2, wherein a central portion of the first stop film is thicker than a peripheral end portion of the first stop film. Forming the first dummy gate electrode and the second dummy gate electrode;
Depositing a dummy gate material on the semiconductor substrate;
Forming a lower insulating film containing the first insulating material and an upper insulating film on the lower insulating film containing a third insulating material different from the first insulating material on the dummy gate material;
Forming a first mask pattern corresponding to the first dummy gate electrode and a second mask pattern corresponding to the second dummy gate electrode on the upper insulating film;
Using the first mask pattern and the second mask pattern as a mask, the upper insulating film, the lower insulating film, and the dummy gate material are etched to form the first dummy gate electrode and the first insulating film. A first lower insulating film pattern having a portion on a dummy gate electrode; a first upper insulating film pattern having a portion on the first dummy gate electrode of the upper insulating film; the second dummy gate electrode; Forming a second lower insulating film pattern having a portion of the insulating film on the second dummy gate electrode, and a second upper insulating film pattern having a portion of the upper insulating film on the second dummy gate electrode; ,
Etching the first upper insulating film pattern having an upper surface covered with the first mask pattern from a side surface to form a third upper insulating film pattern having a first size;
Etching the second upper insulating film pattern whose upper surface is covered with the second mask pattern from a side surface to form a fourth upper insulating film pattern having a second size larger than the first size;
The first lower insulating film pattern on the first dummy gate electrode and the second lower insulating film pattern on the second gate electrode while etching the third upper insulating film pattern and the fourth upper insulating film pattern. The method of manufacturing a semiconductor device according to claim 5, further comprising: forming a first stop film and a second stop film by etching the first stop film and the second stop film.

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