JP2016021479A - Solid-state image sensor, manufacturing method and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state image sensor capable of improving the occupancy of photo diodes.SOLUTION: A transistor is constituted of a fin type transistor. Immediately below a gate electrode of the transistor, a P type element isolation is formed. Also in the transistor, a channel is processed on the P type element isolation to form a gate oxide film 62, and further Poly-Si film is formed. Under the transistor channel, an embedded insulation film is formed in a Si substrate with a width generally identical to the width of the channel. This disclosure is applicable to, for example, CMOS solid-state image sensors which are used for an imaging apparatus such as a camera.SELECTED DRAWING: Figure 3

Description

  The present disclosure relates to a solid-state imaging device, a manufacturing method, and an electronic device, and more particularly, to a solid-state imaging device, a manufacturing method, and an electronic device that can increase the occupation ratio of a photodiode.

  Currently, the mainstream CMOS image sensor (CMOS Image Sensor; CIS) has a readout transistor gate (Transfer Gate; TG) and three other pixel transistors (Amp-Tr, Reset-Tr, Select- Therefore, it is difficult to increase the area of the photodiode (PD) occupying the unit pixel.

  On the other hand, the area of the unit pixel has been rapidly reduced in recent years for downsizing and cost reduction, and the PD area that affects the sensitivity characteristics of the CIS has also been reduced. Therefore, it is essential to improve the PD area ratio in the unit pixel.

  As a method for effectively increasing the PD area, a transistor-shared CIS is used for a 3Tr CIS that increases the PD area by reducing the number of Trs by giving the Amp-Tr the role of Select-Tr and multiple PDs. (For example, a 2 × 2 pixel sharing type that has a single set of Amp, Reset, and Select-Tr for a plurality of PDs, and reduces the number of Trs per unit pixel).

  In addition, Patent Document 1 proposes a structure in which PD, Amp, Reset, and Select-Tr are stacked. This proposal is characterized by using a substrate in which an insulating film is sandwiched on a semiconductor substrate and a Si crystal is laminated.

JP 2010-206134 A

  However, in the case of the former CIS, since the read transistor, Amp-Tr, Reset-Tr, and Select-Tr are provided on the same plane, the occupation ratio of the PD is low. The element isolation region for separating the Amp-Tr, Reset-Tr, Select-Tr and PD is not as fast as the unit pixel reduction pace, and the PD region occupied by the unit pixel is relatively narrow.

  On the other hand, if the size of the Amp-Tr is reduced in order to enlarge the PD area, the noise characteristics of the Tr deteriorate, and even if the PD is enlarged, the S / N ratio affecting the CIS characteristics will eventually be increased. It was getting worse.

  In the case of the latter stacked CIS, a substrate in which an insulating film is sandwiched on a semiconductor substrate and a Si crystal is stacked is used. However, the price of such a substrate is high, and depending on the production method, a high-quality Si crystal is used. It may be difficult to produce the material, or the function may be deteriorated, for example, the saturation charge capacity may be reduced.

  The present disclosure has been made in view of such a situation, and can increase the occupation ratio of a photodiode.

  A solid-state imaging device according to one aspect of the present technology includes a photodiode formed on a Si substrate, and a pixel transistor disposed above the surface of the photodiode.

  The photodiode is formed up to the bottom side wall of the pixel transistor.

  The semiconductor device may further include a P-type region formed under the gate sidewall of the pixel transistor and an insulating film buried immediately below the channel of the pixel transistor.

  The insulating film is buried at a predetermined distance from the surface of the Si substrate.

  The predetermined length is 0 to 100 nm.

  The P-type region has the same width as the gate side wall, and the insulating film is formed to have the same width as the channel width of the pixel transistor.

  The semiconductor device further includes an insulating film buried immediately below the channel of the pixel transistor and a gate oxide film formed on the surface of the pixel transistor.

  The insulating film is embedded in contact with the gate oxide film.

  A metal film is embedded in the insulating film.

  A high dielectric constant insulating film is embedded in the insulating film.

  The pixel transistor is made of a Fin type transistor.

  The solid-state imaging device is a backside illumination type.

  In the manufacturing method of one aspect of the present invention, a manufacturing apparatus forms a pixel transistor above a surface of a photodiode formed on a Si substrate, and the photodiode is formed on the Si substrate.

  An electronic apparatus according to an aspect of the present invention includes a solid-state imaging device including a photodiode formed on a Si substrate and a pixel transistor disposed above the surface of the photodiode, and an output output from the solid-state imaging device. An electronic apparatus comprising: a signal processing circuit that processes a signal; and an optical system that makes incident light incident on the solid-state imaging device.

  In one aspect of the present technology, a pixel transistor is formed on the Si substrate above the surface of the photodiode, and the photodiode is formed on the Si substrate.

  According to the present technology, it is possible to manufacture a fixed imaging device in which a pixel transistor and a photodiode are formed. Further, according to the present technology, the occupation ratio of the photodiode can be increased.

  In addition, the effect described in this specification is an illustration to the last, and the effect of this technique is not limited to the effect described in this specification, and there may be an additional effect.

It is a block diagram which shows the schematic structural example of the solid-state imaging device to which this technique is applied. It is a top view which shows the structural example of a pixel. FIG. 3 is a cross-sectional view taken along A-A ′ of the pixel of FIG. 2. FIG. 3 is a cross-sectional view taken along B-B ′ of the pixel in FIG. 2. It is sectional drawing which shows the modification of the pixel of FIG. It is sectional drawing which shows the other modification of the pixel of FIG. FIG. 10 is a cross-sectional view showing still another modification of the pixel in FIG. 3. It is a flowchart explaining the manufacturing process of the solid-state imaging device to which this technique is applied. It is a flowchart explaining the manufacturing process of the solid-state imaging device to which this technique is applied. It is a figure which shows a manufacturing process. It is a figure which shows a manufacturing process. It is a figure which shows a manufacturing process. It is a figure which shows a manufacturing process. It is a figure which shows a manufacturing process. It is a figure which shows a manufacturing process. It is a top view which shows the modification of the pixel of FIG. FIG. 10 is a plan view illustrating another modification of the pixel in FIG. 2. FIG. 10 is a plan view showing still another modification of the pixel in FIG. 2. It is a block diagram which shows the structural example of the electronic device to which this technique is applied.

  Hereinafter, modes for carrying out the present disclosure (hereinafter referred to as embodiments) will be described.

<Schematic configuration example of solid-state imaging device>
FIG. 1 illustrates a schematic configuration example of an example of a complementary metal oxide semiconductor (CMOS) solid-state imaging device applied to each embodiment of the present technology.

  As shown in FIG. 1, a solid-state imaging device (element chip) 1 includes a pixel region (a pixel region in which pixels 2 including a plurality of photoelectric conversion elements are regularly arranged two-dimensionally on a semiconductor substrate 11 (for example, a silicon substrate). A so-called imaging region) 3 and a peripheral circuit section.

  The pixel 2 includes a photoelectric conversion element (for example, a photodiode) and a plurality of pixel transistors (so-called MOS transistors). The plurality of pixel transistors can be constituted by three transistors, for example, a transfer transistor, a reset transistor, and an amplifying transistor, and can further be constituted by four transistors by adding a selection transistor. Since the equivalent circuit of each pixel 2 (unit pixel) is the same as a general one, detailed description thereof is omitted here.

  Further, the pixel 2 may have a pixel sharing structure. The pixel sharing structure includes a plurality of photodiodes, a plurality of transfer transistors, one shared floating diffusion, and one other pixel transistor that is shared. The photodiode is a photoelectric conversion element.

  The peripheral circuit section includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, and a control circuit 8.

  The control circuit 8 receives data for instructing an input clock, an operation mode, and the like, and outputs data such as internal information of the solid-state imaging device 1. Specifically, the control circuit 8 is based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock, and the clock signal or the reference signal for the operations of the vertical drive circuit 4, the column signal processing circuit 5, and the horizontal drive circuit 6 Generate a control signal. The control circuit 8 inputs these signals to the vertical drive circuit 4, the column signal processing circuit 5, and the horizontal drive circuit 6.

  The vertical drive circuit 4 is configured by, for example, a shift register, selects a pixel drive wiring, supplies a pulse for driving the pixel 2 to the selected pixel drive wiring, and drives the pixels 2 in units of rows. Specifically, the vertical drive circuit 4 selectively scans each pixel 2 in the pixel region 3 sequentially in the vertical direction in units of rows, and generates the signal according to the amount of light received by the photoelectric conversion element of each pixel 2 through the vertical signal line 9. A pixel signal based on the signal charge is supplied to the column signal processing circuit 5.

  The column signal processing circuit 5 is disposed, for example, for each column of the pixels 2, and performs signal processing such as noise removal on the signal output from the pixels 2 for one row for each pixel column. Specifically, the column signal processing circuit 5 performs signal processing such as CDS (Correlated Double Sampling), signal amplification, and A / D (Analog / Digital) conversion for removing fixed pattern noise specific to the pixel 2. . At the output stage of the column signal processing circuit 5, a horizontal selection switch (not shown) is provided connected to the horizontal signal line 10.

  The horizontal drive circuit 6 is constituted by, for example, a shift register, and sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits 5 in order, and the pixel signal is output from each of the column signal processing circuits 5 to the horizontal signal line. 10 to output.

  The output circuit 7 performs signal processing and outputs the signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 10. For example, the output circuit 7 may perform only buffering, or may perform black level adjustment, column variation correction, various digital signal processing, and the like.

  The input / output terminal 12 is provided for exchanging signals with the outside.

<Pixel configuration example>
FIG. 2 is a plan view showing the configuration of the pixel. 3 is a cross-sectional view taken along a plane connecting A and A ′ in FIG. 4 is a cross-sectional view taken along a plane connecting B and B ′ in FIG. In these drawings, an example of a four-transistor (hereinafter referred to as Tr.) Configuration (hereinafter also referred to as a 4Tr. Type) is shown. In the example of FIG. 2, the buried insulating film (45) is the insulating film of the pixel 2 on the left side, and the reference numeral is shown in parentheses.

  In the example of FIG. 2, the pixel 2 includes a Si substrate 41, a PD (photodiode) 42, an FD (floating diffusion) 43, a P-type element isolation 44 (FIG. 3), a buried insulating film 45, a reset Tr 51a, an amplification Tr 51b, and a select. It is configured to include a Tr 51c, a read gate 52, and a P-type diffusion layer 53. Hereinafter, the reset Tr 51a, the amplification Tr 51b, and the selection Tr 51c are collectively referred to as Tr 51 unless otherwise distinguished.

  As shown in FIGS. 3 and 4, the read gate 52 is a planar type (planar type), but the Tr 51 is made of a Fin type Tr. That is, the Tr 51 is disposed above the surface of the PD 42. A P-type element isolation 44 is formed immediately below the gate electrode of the Tr 51. In addition, a P-type diffusion layer 53 that is sufficiently dark so as not to be inverted by application of a gate voltage is created immediately below the side wall of the Tr 51, and as an extension, a P-type diffusion layer 53a is also created on the surface of the PD. . The P type diffusion layer 53 has the same width as the gate side wall.

  In addition, the Tr 51 is formed by processing the channel 61 on the P-type element isolation 44 to form the gate oxide film 62 and further depositing the Poly-Si 63. In the P-type element isolation 44, the portion directly below the channel 61 of the Tr 51 (directly above the buried insulating film 45) is thin P-type due to the influence of the P-type element isolation 44, but due to the influence of the dense P-type diffusion layer 53. It tends to be thicker.

  Under the channel 61 of the Tr 51, a buried insulating film 45 is formed in the Si substrate 41 with a width approximately equal to or greater than the width of the channel 61. The buried insulating film 45 prevents the channel 61 of the Tr 51 from extending (electrically connected) to the PD 42 side of the Si substrate 41 and also serves as element isolation between the PD 42 and the PD 42.

  As described above, the three Trs 51 are located above the surface of the PD 42, that is, are arranged three-dimensionally. In addition, the PD 42 can be extended to the bottom of the gate side wall of the Tr 51. Therefore, the occupation ratio of the PD 42 with respect to the pixel unit can be increased.

  Further, since the Tr 51 is provided above the surface of the PD 42, even when the PD 42 is expanded, it is not necessary to reduce the size of the Tr 51 (particularly, the amplified Tr 51b), and the S / N ratio can be improved.

  In addition, there is no difference from a general semiconductor process, and an inexpensive semiconductor substrate can be used, so that it can be realized at a low price.

  2 to 4, there is a P-type element isolation 44 between the channel 61 and the buried insulating film 45, and the channel 61 and the buried insulating film 45 are not in contact with each other. That is, the buried insulating film 45 is buried at a predetermined distance from the surface of the Si substrate 41. The predetermined length is not particularly limited as long as it is between 0 and 100 nm or less, for example.

  FIG. 5 is a diagram illustrating a modification of the pixel in FIG.

  The pixel 2 in FIG. 5 is common to the pixel 2 in FIG. 3 in that it includes a Si substrate 41, PD 42, FD 43, P-type element isolation 44, Tr 51, readout gate 52, and P-type diffusion layer 53. The pixel 2 in FIG. 5 is different from the pixel 2 in FIG. 3 in that the buried insulating film 45 is replaced with a buried insulating film 71.

  That is, in the example of FIG. 5, the buried insulating film 71 is formed in the Si substrate 41 below the channel 61 of the Tr 51 with a width wider than the channel width. In the example of FIG. 5, the buried insulating film 71 has a structure in contact with the gate oxide film 62 on the surface of the Tr 51. Thereby, Tr51 and PD42 can be physically separated.

  Also in the example of FIG. 5, a P-type diffusion layer 53 that is sufficiently dark so as not to invert by application of the gate voltage is created just below the sidewall of the gate electrode of the Tr 51, as in the example of FIG. As an extension, a P-type diffusion layer 53a is also formed on the surface of the PD.

  FIG. 6 is a diagram illustrating another modification of the pixel of FIG.

  The pixel 2 in FIG. 6 is common to the pixel 2 in FIG. 3 in that it includes a Si substrate 41, PD 42, FD 43, P-type element isolation 44, Tr 51, readout gate 52, and P-type diffusion layer 53. The pixel 2 in FIG. 6 is different from the pixel 2 in FIG. 3 in that the buried insulating film 45 is replaced with a buried insulating film 81.

  That is, in the example of FIG. 6, a buried insulating film 81 is formed in the Si substrate 41 under the channel 61 of the amplification Tr 52 with a width equal to or larger than the channel width. In the example of FIG. 6, the buried insulating film 81 is thinly formed at the interface with the Si substrate 41, and the metal 82 is buried in the buried insulating film 81. The metal 82 is made of, for example, tungsten, aluminum, or copper.

  FIG. 7 is a diagram showing still another modification of the pixel of FIG.

  The pixel 2 in FIG. 7 is common to the pixel 2 in FIG. 3 in that the Si substrate 41, the PD 42, the FD 43, the reset Tr 51, the amplification Tr 52, and the selection Tr 53 are provided. The pixel 2 in FIG. 7 is different from the pixel 2 in FIG. 3 in that the buried insulating film 45 is replaced with a buried insulating film 91.

  That is, in the example of FIG. 7, the buried insulating film 91 is formed in the Si substrate 41 under the channel 61 of the Tr 51 with a width equal to or larger than the channel width. In the example of FIG. 7, the buried insulating film 91 is thinly formed at the interface with the Si substrate 41, and a high dielectric constant insulating film 92 is buried in the buried insulating film 91. The high dielectric constant insulating film 92 is made of, for example, hafnium oxide or zirconium oxide.

  As described above, the buried insulating film does not need to be an insulating film. That is, the buried insulating film only needs to be thinly formed at the interface with the Si substrate, and the inside of the insulating film may be a metal as shown in FIG. 6 or a high dielectric constant insulating film as shown in FIG. There may be.

<Example of manufacturing process>
Next, the manufacturing process of the solid-state imaging device according to the present technology will be described with reference to the flowcharts of FIGS. This process is a process executed by a solid-state imaging device manufacturing apparatus (not shown), and the process diagrams of FIGS. 10 to 15 are also referred to as appropriate.

  In step S11, the manufacturing apparatus injects P-type impurities for PD separation, that is, P-type element isolation 44, into the Si substrate 41 as shown in FIG. 10A. In step S12, as shown in FIG. 10B, the manufacturing apparatus processes the channel 61 of the Tr 51 on the P-type element isolation 44 using the photoresist 101 by lithography and etching techniques.

  In step S13, the manufacturing apparatus forms the gate oxide film 62 of PD42 and Tr51 as shown in FIG. 10C.

  In step S14, as shown in FIG. 11A, the manufacturing apparatus performs patterning using the photoresist 101, implants deep P-type ions immediately below the gate sidewall of Tr51 (a portion below the sidewall), and performs P-type diffusion. Layer 53 is created. At this time, masking is performed so that P-type impurities do not enter the channel Si processed in step S12.

  In step S15, the manufacturing apparatus performs patterning using the photoresist 101 as shown in FIG. 11B, implants N-type impurities, and creates the PD.

  In step S <b> 16, the manufacturing apparatus creates the electrode of the read gate 52 and the gate electrode of the Tr 51 with polycrystalline silicon or the like. That is, as shown in FIG. 12A, the manufacturing apparatus forms Poly-Si 63 on the gate oxide film 62 formed. Thereafter, as shown in FIG. 12B, the manufacturing apparatus performs patterning using the photoresist 101 and etching. As a result, an electrode of the read gate 52 and a gate electrode of the Tr 51 are created.

  In step S17, the manufacturing apparatus performs N-type SD injection to form FD43 and Tr51. That is, as shown in FIG. 13A, the manufacturing apparatus performs patterning using a photoresist 101, and implants N-type SD to form FD43. In addition, as shown in FIG. 13B, the manufacturing apparatus performs patterning using the photoresist 101 and performs N-type SD implantation to form Tr 51a, Tr 51b, and Tr 51c.

  The FD 43 is generally created at the same time.

  In step S18, as shown in FIG. 14A, the manufacturing apparatus implants P + on the surface of the PD 42 to create a P-type diffusion layer 53a.

  In step S <b> 19 of FIG. 9, the manufacturing apparatus creates the wiring 112. Further, in step S20, the manufacturing apparatus covers the created wiring 112 (Tr51 or upper part of the wiring layer) with an insulating film 111 as shown in FIG. 14B, and planarizes the surface.

  In step S <b> 21, as shown in FIG. 14C, the manufacturing apparatus puts the Si substrate 41 on which the wiring 112 is formed upside down and bonds it to the support substrate 151. In step S22, the manufacturing apparatus polishes and thins the Si substrate 41.

  In step S23, as shown in FIG. 15A, the manufacturing apparatus removes the Si substrate 41 (a part of the P-type element isolation 44) under the Tr 51 from the back surface by etching using the photoresist 101.

  In step S24, as shown in FIG. 15B, the manufacturing apparatus buryes the insulating film 45 embedded in the place removed in step S23 and the surface of the Si substrate 41 (upward in the drawing) by a film forming technique such as high-density plasma CVD. Fill.

  In step S25, the manufacturing apparatus creates a color filter 161 and an on-chip lens 162 on the buried insulating film 45 on the surface of the Si substrate 41, as shown in FIG. 15C. Furthermore, pad opening etc. are also performed.

  Through the above manufacturing process, a back-illuminated solid-state imaging device (for example, a CMOS image sensor) is generated. That is, as described above, the solid-state imaging device of the present technology is not different from a general semiconductor process, and an inexpensive semiconductor substrate can be used, so that it can be realized at a low price.

<Modification>
FIG. 16 is a plan view illustrating another configuration of the pixel of the present technology.

  The pixel 201 in the example of FIG. 16 is configured similarly to the pixel 2 of FIG. 2 in that the pixel 201 includes the Si substrate 41, PD 42, FD 43, and Tr 51 (reset Tr 51a, amplification Tr 51b, and selection Tr 51c). Yes. The pixel 201 in the example of FIG. 16 is different from the pixel 2 of FIG. 2 in that the buried insulating film 45 is changed to the buried insulating film 211.

  That is, in the example of FIG. 16, the buried insulating film 211 that provides element isolation between the Tr 15 and the PD 42 or between the PD and the PD is buried around the unit pixel in the Si substrate 41. And Tr51 is arrange | positioned over two sides around the unit pixel.

  As described above, since the buried insulating film is buried around the unit pixel, the Tr can be arranged over two sides around the unit pixel. Thereby, the gate length of the Tr (particularly the amplified Tr) can be increased without reducing the area of the PD.

  FIG. 17 is a plan view illustrating a configuration example of a PD shared CIS according to the present technology. In the example of FIG. 17, a configuration in which one Tr. Set is shared by four pixels is shown.

  17 includes a Si substrate 41, a buried insulating film 211, PD 261-1 to PD 261-4, TG (transfer gate) 262-1 to 262-4, FD 263, and Tr 51 (reset Tr 51a, amplification Tr 51b, select Tr 51c). ).

  In the example of FIG. 17, the buried insulating film 211 is buried around the shared pixel in the Si substrate 41. And Tr51 is arrange | positioned over two sides around the shared pixel.

  As described above, in the PD shared type CIS, since the buried insulating film is buried around the shared pixel, the Tr can be arranged over two sides around the shared pixel. Thereby, the gate length of the Tr (particularly the amplified Tr) can be increased without reducing the area of the PD.

  FIG. 18 is a plan view illustrating another configuration example of the PD sharing type CIS according to the present technology. In the example of FIG. 18, a configuration in which one Tr. Set is shared by four pixels is shown.

  The pixel 301 in FIG. 18 includes a Si substrate 41, PD 261-1 to PD 261-4, TG (transfer gate) 262-1 to 262-4, FD 263, and Tr 51 (reset Tr 51a, amplification Tr 51b, select Tr 51c). The configuration point is common to the pixel 211 in FIG.

  A pixel 301 in FIG. 18 is different from the pixel 211 in FIG. 17 in that a buried insulating film 311 is provided instead of the buried insulating film 211. That is, in the example of FIG. 18, the buried insulating film 311 is buried around each PD 261-1 to 261-4 in the Si substrate 41.

  As described above, in the PD shared CIS, the buried insulating film is buried around each pixel, so that the Tr can be arranged over one side around the shared pixel. Thereby, Tr (especially amplification Tr) can be arrange | positioned straight, without reducing the area of PD.

  As described above, according to the present technology, since the PD occupation ratio can be increased, it is possible to increase the amount of saturation charge that is the charge accumulated in one PD. Moreover, since the PD region in the Si deep portion is widened when viewed from the light irradiation side (back side), the sensitivity on the long wavelength side (up to red) is increased.

  Further, in the present technology, since the amplified Tr is above the PD, it is not necessary to reduce the size of the amplified Tr. In particular, in the case of the example of FIGS. 16 and 17, the gate length can be further increased, so that noise caused by the amplified Tr can be reduced.

  Furthermore, in this technology, by introducing P-type impurities into the gate sidewall of the buried insulating film and the amplifying Tr, a general semiconductor process can be used without using an expensive substrate. And the Si substrate can be electrically separated.

  In the above, the configuration in which the present technology is applied to the CMOS solid-state imaging device has been described. However, the present technology may be applied to a solid-state imaging device such as a CCD (Charge Coupled Device) solid-state imaging device.

  In addition, this technique is not restricted to application to a solid-state imaging device, It can apply also to an imaging device. Here, the imaging apparatus refers to a camera system such as a digital still camera or a digital video camera, or an electronic apparatus having an imaging function such as a mobile phone. In some cases, a module-like form mounted on an electronic device, that is, a camera module is used as an imaging device.

<Configuration example of electronic equipment>
Here, with reference to FIG. 19, the structural example of the electronic device of the 2nd Embodiment of this technique is demonstrated.

  An electronic apparatus 500 illustrated in FIG. 19 includes a solid-state imaging device (element chip) 501, an optical lens 502, a shutter device 503, a drive circuit 504, and a signal processing circuit 505. As the solid-state imaging device 501, the above-described solid-state imaging device of the present technology is provided. As a result, it is possible to provide a high-performance electronic device 500 with improved sensitivity, S / N, and the like.

  The optical lens 502 forms image light (incident light) from the subject on the imaging surface of the solid-state imaging device 501. As a result, signal charges are accumulated in the solid-state imaging device 501 for a certain period. The shutter device 503 controls the light irradiation period and the light shielding period for the solid-state imaging device 501.

  The drive circuit 504 supplies a drive signal for controlling the signal transfer operation of the solid-state imaging device 501 and the shutter operation of the shutter device 503. The solid-state imaging device 501 performs signal transfer according to a drive signal (timing signal) supplied from the drive circuit 504. The signal processing circuit 505 performs various types of signal processing on the signal output from the solid-state imaging device 501. The video signal subjected to the signal processing is stored in a storage medium such as a memory or output to a monitor.

  In the present specification, the steps describing the series of processes described above are not limited to the processes performed in time series according to the described order, but are not necessarily performed in time series, either in parallel or individually. The process to be executed is also included.

  The embodiments in the present disclosure are not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present disclosure.

  In addition, each step described in the above flowchart can be executed by being shared by a plurality of apparatuses in addition to being executed by one apparatus.

  Further, when a plurality of processes are included in one step, the plurality of processes included in the one step can be executed by being shared by a plurality of apparatuses in addition to being executed by one apparatus.

  In addition, in the above description, the configuration described as one device (or processing unit) may be divided and configured as a plurality of devices (or processing units). Conversely, the configurations described above as a plurality of devices (or processing units) may be combined into a single device (or processing unit). Of course, a configuration other than that described above may be added to the configuration of each device (or each processing unit). Furthermore, if the configuration and operation of the entire system are substantially the same, a part of the configuration of a certain device (or processing unit) may be included in the configuration of another device (or other processing unit). . That is, the present technology is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present technology.

  The preferred embodiments of the present disclosure have been described in detail above with reference to the accompanying drawings, but the disclosure is not limited to such examples. It is obvious that various changes and modifications can be conceived within the scope of the technical idea described in the claims if the person has ordinary knowledge in the technical field to which the present disclosure belongs, Of course, it is understood that these also belong to the technical scope of the present disclosure.

In addition, this technique can also take the following structures.
(1) a photodiode formed on a Si substrate;
A solid-state imaging device comprising: a pixel transistor disposed above the surface of the photodiode.
(2) The solid-state imaging device according to (1), wherein the photodiode is formed to a position below a gate side wall of the pixel transistor.
(3) a P-type region formed under the gate sidewall of the pixel transistor;
The solid-state imaging device according to (2), further including: an insulating film embedded immediately below the channel of the pixel transistor.
(4) The solid-state imaging device according to (3), wherein the insulating film is embedded at a predetermined distance from the surface of the Si substrate.
(5) The solid-state imaging device according to (4), wherein the predetermined length is 0 to 100 nm.
(6) The P-type region is as wide as the gate sidewall,
The solid-state imaging device according to (3), wherein the insulating film is formed to have a width approximately equal to a channel width of the pixel transistor.
(7) an insulating film buried immediately below the channel of the pixel transistor;
The solid-state imaging device according to (2), further including a gate oxide film formed on a surface of the pixel transistor.
(8) The solid-state imaging device according to (7), wherein the insulating film is embedded in contact with the gate oxide film.
(9) The solid-state imaging device according to (3) or (7), wherein a metal film is embedded in the insulating film.
(10) The solid-state imaging device according to (3) or (7), wherein a high dielectric constant insulating film is embedded in the insulating film.
(11) The solid-state imaging device according to any one of (1) to (9), wherein the pixel transistor is made of a Fin-type transistor.
(12) The solid-state imaging device according to any one of (1) to (10), wherein the solid-state imaging device is a backside illumination type.
(13) The manufacturing equipment is
A pixel transistor is formed above the surface of the photodiode on the Si substrate,
A manufacturing method in which the photodiode is formed up to a gate side wall of the pixel transistor.
(14) a photodiode formed on a Si substrate;
A solid-state imaging device comprising: a pixel transistor disposed above the surface of the photodiode;
A signal processing circuit for processing an output signal output from the solid-state imaging device;
And an optical system that makes incident light incident on the solid-state imaging device.

    DESCRIPTION OF SYMBOLS 1 Solid-state imaging device, 2 pixels, 41 Si substrate, 42 Photodiode (PD), 43 Floating diffusion (FD), 44 P-type element isolation | separation, 51 Tr, 51a Reset Tr, 51b Amplification Tr, 51c Select Tr, 52 Reading gate , 53 P type diffusion layer, 61 channel, 62 gate oxide film, 63 Poly-Si, 81 buried insulating film, 82 metal, 91 buried insulating film, 92 high dielectric constant insulating film, 101 photoresist, 111 insulating film, 112 wiring , 151 support substrate, 161 color filter, 162 on-chip lens, 201 pixel, 211 insulating film, 251 pixel, 261-1 to 261-4 photodiode (PD), 262-1 to 262-4 TG (transfer gate), 301 pixels, 311 insulating film, 500 electricity Equipment, 501 solid-state imaging device, 502 an optical lens, 503 a shutter device, 504 driving circuit, 505 a signal processing circuit

Claims (14)

A photodiode formed on a Si substrate;
A solid-state imaging device comprising: a pixel transistor disposed above the surface of the photodiode. The solid-state imaging device according to claim 1, wherein the photodiode is formed up to a lower side wall of the pixel transistor. A P-type region formed under the gate sidewall of the pixel transistor;
The solid-state imaging device according to claim 2, further comprising: an insulating film embedded immediately below the channel of the pixel transistor. The solid-state imaging device according to claim 3, wherein the insulating film is embedded at a predetermined distance from the surface of the Si substrate. The solid-state imaging device according to claim 4, wherein the predetermined length is 0 to 100 nm. The P-type region is as wide as the gate sidewall,
The solid-state imaging device according to claim 3, wherein the insulating film is formed to have a width approximately equal to a channel width of the pixel transistor. An insulating film buried immediately below the channel of the pixel transistor;
The solid-state imaging device according to claim 2, further comprising: a gate oxide film formed on a surface of the pixel transistor. The solid-state imaging device according to claim 7, wherein the insulating film is embedded in contact with the gate oxide film. The solid-state imaging device according to claim 3, wherein a metal film is embedded in the insulating film. The solid-state imaging device according to claim 3, wherein a high dielectric constant insulating film is embedded in the insulating film. The solid-state imaging device according to claim 2, wherein the pixel transistor is made of a Fin-type transistor. The solid-state imaging device according to claim 2, wherein the solid-state imaging device is a backside illumination type. A pixel transistor is formed above the surface of the photodiode on the Si substrate,
A manufacturing method for forming the photodiode on the Si substrate. A photodiode formed on a Si substrate;
A solid-state imaging device comprising: a pixel transistor disposed above the surface of the photodiode;
A signal processing circuit for processing an output signal output from the solid-state imaging device;
And an optical system that makes incident light incident on the solid-state imaging device.

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