JP2016019269A - Oscillator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simultaneously and appropriately control a control range and a resolution even in the case where a range of an oscillation frequency is wide, in an oscillator which performs digital control of range control and precise control.SOLUTION: The oscillation frequency of an oscillator is controlled by a control value, and the oscillation frequency is specified by a primary function of the control value. For the primary function, a slice and an inclination are specified by digital values and the slice and the inclination can be set. The slices and the inclinations to be set in a plurality of frequency ranges are set to be the same ratio as each other, such that a change amount of the oscillation frequency by 1LSB of precise control can be made geometrical to the frequency in the range. Therefore, it is not necessary for a DAC for control to have bits more than needed.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an oscillator, and can be suitably used for an oscillator that can control an oscillation frequency in a wide frequency range.

  Oscillators with variable oscillation frequency are used to construct clock data recovery (CDR) circuits, PLLs (Phase Locked Loops) mounted on frequency synthesizers, and the like with recent miniaturization of semiconductor processes. More and more, digital control is increasing. In addition, in order to cope with various transmission rates and communication frequencies, there is a demand to widen the control range of the oscillation frequency. For example, eDP (embedded Display Port) Ver. 1.4, which is an internal high-speed interface standard, supports seven operation modes from 1.62 Gbps to 5.4 Gbps.

  Patent Documents 1 and 2 disclose an oscillation circuit capable of coarse and fine adjustment of the oscillation frequency. Patent Document 1 discloses a coarse-controlled DAC (Digital to Analog Converter) and a VCO (Voltage Controlled Oscillator) controlled by a fine-adjusting DAC. Patent Document 2 discloses a digitally controlled LC oscillation circuit. In order to control the oscillation frequency, a capacitor array made of coarse adjustment metal / insulating layer / metal and a fine adjustment MOS (Metal Oxide Semiconductor) capacitor array are provided, and each is switch-controlled by a digital signal.

JP 2007-267375 A International Publication No. WO2012 / 030501

  As a result of examination of Patent Documents 1 and 2 by the present inventors, it has been found that there are the following new problems.

  In a digitally controlled oscillator, when the control range is widened, as described above, control means that combines coarse adjustment and fine adjustment is employed. The oscillation frequency of the oscillator is controlled by a digital control code. For example, the upper bits of the control code are assigned coarsely and the lower bits are assigned finely. At this time, the minimum step size for changing the oscillation frequency corresponds to 1 LSB on the fine adjustment side of the control code and does not depend on the level of the rough oscillation frequency determined by the coarse adjustment. Therefore, if the minimum step size required when the oscillation frequency is low is set, the step size is smaller than necessary when the oscillation frequency is high. For example, if the minimum step size of an oscillator is 1 MHz per 1 LSB, 100 code is required when the oscillation frequency is 500 MHz and this is changed to 400 MHz, and 200 code is required when the oscillation frequency is 1000 MHz and this is changed to 800 MHz. In both cases, although the oscillation frequency is changed by 20%, the change amount of the control code is doubled. Assuming that 1 MHz (0.2%) is an appropriate minimum step size in the 500 MHz band, 1 MHz in the 1000 MHz band is a 0.1% step, and the step size is finer than necessary. Recognize. As a result, in the region where the oscillation frequency is high, the coarse adjustment range is divided more finely than necessary.

  As described in Patent Document 1, when coarse adjustment and fine adjustment are controlled by a DAC, it is difficult to optimize the control range and resolution at the same time. I found out that As described in Patent Document 2, it was found that the resolution optimized in the low frequency range was higher than necessary in the high frequency range even when no DAC was installed.

  An object of the present invention is to appropriately control the control range and resolution simultaneously in an oscillator that performs coarse and fine digital control even when the oscillation frequency range is wide.

  Means for solving such problems will be described below, but other problems and novel features will become apparent from the description of the present specification and the accompanying drawings.

  According to one embodiment, it is as follows.

  In other words, the oscillation frequency is controlled by a control value, and the oscillation frequency is defined by a linear function of the control value. In the linear function, the intercept and the slope are defined by digital values, and the intercept and the slope can be set.

  The effect obtained by the one embodiment will be briefly described as follows.

  That is, in an oscillator that performs digital control of coarse adjustment and fine adjustment, the control range and resolution can be appropriately controlled simultaneously even when the oscillation frequency range is wide.

FIG. 1 is a graph showing a control curve of an oscillator according to the present invention. FIG. 2 is a block diagram showing a configuration example of an oscillator according to the present invention. FIG. 3 is an explanatory diagram showing a method for calibrating (trimming) an oscillator according to the present invention. FIG. 4 is a flowchart showing an example of a method for realizing the calibration (trimming) of FIG. FIG. 5 is an explanatory diagram showing another example of a method for realizing the calibration (trimming) of FIG. FIG. 6 is a block diagram illustrating a configuration example including a range setting unit of an oscillator according to the present invention. FIG. 7 is a block diagram illustrating a first configuration example of the range setting unit. FIG. 8 is a block diagram illustrating a second configuration example of the range setting unit. FIG. 9 is a block diagram illustrating a third configuration example of the range setting unit. FIG. 10 is a block diagram illustrating a configuration example of an oscillator including a current control oscillation unit. FIG. 11 is a circuit diagram illustrating a configuration example of the current control oscillation unit of FIG. FIG. 12 is a block diagram showing a modification of the range setting unit in the oscillator of FIG. FIG. 13 is a block diagram illustrating a configuration example of the LC oscillation unit. FIG. 14 is a circuit diagram showing a configuration example of a tank circuit in the LC oscillation unit of FIG. FIG. 15 is a circuit diagram showing a configuration example of the coarse adjustment capacity bank in the tank circuit of FIG. FIG. 16 is a circuit diagram showing a configuration example of a fine adjustment capacity bank in the tank circuit of FIG. FIG. 17 is a circuit diagram showing a configuration example of a variable capacitance portion for adjusting the oscillation frequency in the LC oscillation unit of FIG. FIG. 18 is a circuit diagram showing a configuration example of the coarse adjustment capacitor bank in FIG. FIG. 19 is a circuit diagram showing a configuration example of the fine adjustment capacitor bank in FIG. FIG. 20 is a block diagram illustrating another configuration example of an oscillator including an LC oscillation unit. FIG. 21 is an explanatory diagram (CV characteristics) of the correction calculation for the nonlinear characteristics of the variable capacitance element (varactor). FIG. 22 is an explanatory diagram (relationship between the parameter a and the voltage V) of the correction calculation for the nonlinear characteristic of the variable capacitance element (varactor). FIG. 23 is a block diagram illustrating still another configuration example of the LC oscillation unit. FIG. 24 is a block diagram illustrating a configuration example of an oscillator including a voltage controlled oscillation unit. FIG. 25 is a block diagram illustrating a configuration example of an oscillator that includes a current control oscillation unit and that feeds back an analog control signal. FIG. 26 is a block diagram illustrating a configuration example of an oscillator including an LC oscillation unit to which an analog control signal is fed back. FIG. 27 is a block diagram illustrating a configuration example of an oscillator in which a gain adjusting unit is added to the output unit of each DA converter in the oscillator of FIG. FIG. 28 is a block diagram illustrating a configuration example of an oscillator in which a gain adjustment unit is added to the reference value input unit of each DA converter in the oscillator of FIG.

1. First, an outline of a typical embodiment disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached. Note that the term “oscillator” or “oscillation circuit” is generally used instead of “oscillation unit” for the current control oscillation unit 61, the LC oscillation unit 62, and the voltage control oscillation unit (VCO) 63. In the specification, since the whole including the frequency control unit 10 is described as the oscillator 1, the term “oscillation unit” is used to distinguish it from this.

[1] <Oscillation frequency = slope × control value + intercept>
A typical embodiment disclosed in the present application is an oscillator (1) in which an oscillation frequency (y) is controlled by a control value (x), and the oscillation frequency is defined by a linear function of the control value. In the linear function, the intercept (b) and the slope (a) are defined by digital values, and the intercept and the slope can be set.

  As a result, in an oscillator that performs digital control of coarse adjustment and fine adjustment, the control range and resolution can be appropriately controlled simultaneously even when the oscillation frequency range is wide. The “control value” may be a digital control code or an analog control voltage or control current.

[2] <Slope is proportional to intercept (oscillation frequency range)>
In the term 1, the set value (a1, a2, a3, a4,...) Of the slope is positively proportional to the set value (b1, b2, b3, b4,...) Of the intercept (a1: b1≈). a2: b2≈a3: b3≈a4: b4≈ ...).

  Thereby, even when the range of the oscillation frequency is wide, the number of bits for fine adjustment can be reduced, and the control range and resolution can be controlled appropriately at the same time. When the control range of the oscillation frequency is wide and the intercept is large, that is, when the frequency range of the oscillation frequency to be controlled is high, by increasing the slope proportionally, the oscillation accompanying the change in the control value with respect to the oscillation frequency The rate of change in frequency can be made constant (equal ratio) regardless of the frequency range. Furthermore, even if there is nonlinearity in the relationship between the oscillation frequency (y) and the control value (x) with respect to the analog control amount of the oscillator (1), if it is monotonically increasing, it can be linearly approximated by narrowing the control interval, and the frequency range Since the control by the linear function can be applied by appropriately dividing and setting the inclination (a) for each range, the control range and the resolution can be controlled appropriately at the same time.

[3] <Range setting section>
In Item 1 or 2, the oscillator (1) includes a range setting unit (20, 30) that has a plurality of frequency ranges and sets the intercept and the slope for each of the plurality of frequency ranges.

  As a result, the configuration of the circuit for setting the control parameter including the intercept and the inclination can be simplified.

[4] <Keep all combinations of intercept and slope>
In Section 3, the range setting unit holds intercept and slope setting values for each of the plurality of frequency ranges (31a, 31b), and the intercept (b) and slope selected according to the designated frequency range. Set (a).

  As a result, the control parameter composed of the intercept and the inclination is obtained in advance by measurement, design, etc., and is set only by selection. Therefore, it is not necessary to obtain the optimum value every time it is set.

[5] <Retaining some combinations of intercept and slope, others calculated by interpolation>
In item 3, the range setting unit holds intercept and slope setting values for a part of the plurality of frequency ranges (32a, 32b), and the designated frequency range is the partial frequency range. Are selected and set for the corresponding intercept and slope, and in cases other than the part of the frequency ranges, the intercept and slope corresponding to two frequency ranges close to the frequency range of the part of the frequency ranges. The values obtained by interpolation (23a, 23b) from these values are set as the intercept (b) and slope (a) corresponding to the frequency range.

  As a result, the control parameter composed of the intercept and the inclination is obtained in advance by measurement, design, etc., and is set only by selection. Therefore, it is not necessary to obtain the optimum value every time it is set.

[6] <Proofreading (trimming)>
In item 4 or item 5, the set values of the intercept and the inclination are calculated based on the relationship between the control value measured by operating the oscillator and the oscillation frequency, and are written in the range setting unit (30).

  Thereby, manufacturing variation is absorbed.

[7] <Function for calculating intercept and slope>
In item 3, the range setting unit includes a function (26a, 26b) for calculating an intercept and a slope corresponding to each of the plurality of frequency ranges, and an intercept calculated by the function according to a specified frequency range. (B) and slope (a) are set as the intercept and slope corresponding to the frequency range.

  As a result, the control parameter composed of the intercept and the inclination is obtained in advance by measurement, design, etc., and is set only by selection. Therefore, it is not necessary to obtain the optimum value every time it is set.

[8] <3 DAC + OSC>
Item 8. The first DA conversion according to any one of Items 1 to 7, wherein the oscillator (1) receives a digital value and a reference value and outputs an analog value based on a product of the digital value and the reference value. A device (11), a second DA converter (12), and a third DA converter (13).

  The intercept is defined by a product (b × Iref) of a reference value (Iref) and a first parameter (b), and the slope is a product (a × Iref) of the reference value and the second parameter (a). It is prescribed.

  The third DA converter receives the second parameter (a) as the digital value, receives the reference value (Iref) as the reference value, and calculates the product (a of the second parameter and the reference value) * Iref) is output.

  The second DA converter receives the first parameter (b) as the digital value, the reference value (Iref) as the reference value, and the product (b of the first parameter and the reference value). * Iref) is output.

  The first DA converter receives the control value (x) as the digital value, and the product of the second parameter and the reference value (a × Iref) output from the third DA converter as the reference value. Is input, and the product (a × x × Iref) of the control value, the second parameter, and the reference value is output.

  The oscillation frequency is controlled based on a sum (a × x × Iref + b × Iref) of a product of the control value, the second parameter, and the reference value and a product of the first parameter and the reference value. The

  As a result, the circuit for adjusting the control range and resolution is constituted by three DA converters, and it is not necessary to increase the bit accuracy more than necessary.

[9] <Current output type DAC + current controlled oscillator>
8. The current output type DA converter according to item 8, wherein each of the first, second, and third DA converters outputs a current value corresponding to a product of a digital value and a reference value input to each of the first, second, and third DA converters. .

  The oscillation frequency is a sum (a × x × Iref + b × Iref) of the current value of the product of the control value, the second parameter, and the reference value, and the current value of the product of the first parameter and the reference value. ).

  As a result, the analog circuit that performs multiplication and addition of current values is configured with a simpler circuit than the multiplication and addition of voltage values, and the overall circuit scale can be reduced.

[10] <Capacitive DAC × 2 + Voltage DAC + LC oscillation unit>
In Claim 1, the oscillator (1) includes a coarse adjustment capacitor bank (71), a fine adjustment capacitor bank (72), and a DA converter (13).

  The coarse adjustment capacitor bank includes a plurality of capacitive elements (77) and a plurality of coarse adjustment switches (79), and is connected by controlling the plurality of coarse adjustment switches based on the value of the intercept (b). By increasing or decreasing the number of capacitor elements, the capacitance value of the entire coarsely adjusted capacitor bank is controlled.

  The fine adjustment bank includes a plurality of variable capacitance elements (78) whose capacitance values are adjusted by an applied voltage and a plurality of fine adjustment switches (79), and controls the plurality of fine adjustment switches based on the control value. By increasing or decreasing the number of variable capacitance elements connected to each other, the capacitance value of the entire fine adjustment capacitor bank is controlled.

  The DA converter converts the value of the slope (a) into an analog voltage and applies it to the plurality of variable capacitance elements.

  Thereby, in an oscillator provided with an LC oscillation circuit, the oscillation frequency can be controlled by a linear function related to the control value.

[11] <Table for correcting nonlinearity of variable capacitance element>
In item 10, the oscillator (1) further includes a correction table (27) that corrects the value of the slope and inputs the value to the DA converter based on a capacitance value characteristic with respect to an applied voltage of the variable capacitance element. .

  Thereby, even when the variable capacitance element has a non-linear characteristic, the oscillation frequency can be finely adjusted linearly by the slope value. The correction table (27) to be added is an inverse function of the applied voltage versus capacitance characteristic of the variable capacitance element, and the oscillation frequency can be corrected so as to be proportional to the slope value.

[12] <R-DAC for correcting nonlinearity of variable capacitance element>
In Item 10, the DA converter has a characteristic that compensates a characteristic of a capacitance with respect to an applied voltage of the variable capacitance element between an input digital value and an output voltage.

  Thereby, even when the variable capacitance element has a non-linear characteristic, the oscillation frequency can be finely adjusted linearly by the slope value. The characteristic for compensating the capacitance characteristic (VC characteristic) with respect to the applied voltage of the variable capacitance element is, for example, a characteristic corresponding to an inverse function of the VC characteristic.

[13] <DAC + VCO>
Item 8 is the DA converter, wherein each of the first, second, and third DA converters outputs an analog value corresponding to a product of a digital value and a reference value input to each, and the oscillation The frequency is controlled based on a voltage value corresponding to a sum of a product of the control value, the second parameter, and the reference value, and a product of the first parameter and the reference value.

  As a result, an oscillator having a voltage-controlled oscillation circuit (VCO) can be configured such that the oscillation frequency is controlled by a linear function related to the control value.

[14] <Analog feedback>
In any one of Items 1 to 7, an analog value is input as the control value. The intercept is defined based on the first parameter (b), the slope is defined based on the second parameter (a), and the oscillation frequency is calculated by multiplying the product of the control value and the second parameter, Control is based on the sum of one parameter.

  Thus, in an oscillator that receives an analog voltage as a control value, the oscillation frequency can be controlled by a linear function related to the control value. For example, in an analog PLL, the loop gain for each frequency range can be controlled by digital parameters in an equal ratio.

[15] <Gain adjuster at output of DA converter>
In item 8, the oscillator (1) further includes a gain adjustment unit (81-83) that adjusts an output of at least one of the first, second, and third DA converters.

  Thereby, the control amount input to the oscillating unit 61 can be adjusted to a value in an appropriate range.

[16] <Gain adjustment unit for reference value input of DA converter>
In item 8, the oscillator (1) includes a gain adjustment unit (81-83) that adjusts the reference value input to at least one DA converter among the first, second, and third DA converters. ).

  Thereby, the control amount input to the oscillating unit 61 can be adjusted to a value in an appropriate range.

2. Details of Embodiments Embodiments will be further described in detail.

[Embodiment 1] <Oscillator capable of setting intercept (coarse adjustment) and inclination (fine adjustment)>
In the oscillator 1 according to the present invention, the oscillation frequency y is defined by a linear function of the intercept b and the slope a of the control value x (y = ax + b), and the intercept b and the slope a can be set. The oscillator 1 has a plurality of oscillation frequency ranges, and the values of the intercept b and the slope a can be set for each oscillation frequency range.

  FIG. 1 is a graph showing a control curve of an oscillator according to the present invention. The horizontal axis is the control code x that is the control value, and the vertical axis is the oscillation frequency y. Four oscillation frequency ranges, b1 to b2, b2 to b3, b3 to b4, and b4 to b5 are shown. In each frequency range, slope set values a1, a2, a3, a4, and intercept Set values b1, b2, b3, and b4 can be set.

  FIG. 2 is a block diagram showing a configuration example of the oscillator 1 according to the present invention.

  The oscillator 1 includes a frequency control unit 10 and an oscillating unit 61 including first to third three DA converters 11 to 13 and an adder 14. Each of the DA converters 11 to 13 is a current type DA converter that converts an input digital value into an analog current value based on the reference current Iref, and the adder 14 is a current addition circuit. Is a current controlled oscillator. The second DA converter (DAC2) 12 receives the intercept b, which is a digital value, and outputs an analog current b × Iref. The third DA converter (DAC3) 13 receives a slope a which is a digital value, outputs an analog current a × Iref, and inputs it to the reference current of the first DA converter (DAC1) 11. The first DA converter (DAC1) 11 receives a digital control code x as a control value, and outputs a product of x × a × Iref with a reference current a × Iref. The adder 14 adds the output current x × a × Iref from the first DA converter (DAC1) 11 and the output current b × Iref from the second DA converter (DAC2) 12 to add Iy = (xx × a + b ) × Iref is obtained and supplied to the oscillating unit 61 as the control current Iy.

  Thus, in the oscillator 1 that performs coarse and fine digital control, the control range and the resolution can be appropriately controlled simultaneously even when the oscillation frequency range is wide. In the conventional combination of simple coarse adjustment and fine adjustment, in which only the “intercept” can be set, the amount of change in oscillation frequency when the control value (control code) is changed is equal. When the range is wide, it is necessary to increase the number of bits for fine adjustment. On the other hand, in the present invention, since the “slope” can also be set, the amount of change in the oscillation frequency when the control value is changed can be increased in the control range where the oscillation frequency is high. It is possible to deal with a wide control range without increasing the number of bits.

  FIG. 2 shows a configuration example of a current type DA converter and a current control oscillation unit, but the present invention is not limited to this, and the oscillator of the present invention includes various embodiments including those described later. Can be configured. For example, the DA converter may calculate the linear function between the output voltages as a voltage output and supply it as a control voltage to the voltage controlled oscillator (VCO). In addition, the above linear function is calculated by a product-sum operation as it is, and the result obtained as a digital value is converted into an analog voltage or current amount or capacitance value. You may supply to the controlled oscillation circuit.

<Slope is proportional to intercept (oscillation frequency range)>
The slope set values a1, a2, a3, a4,... And the intercept set values b1, b2, b3, b4,... Set for each oscillation frequency range are proportional positive correlations a1: b1≈. It is more preferable that the value is defined as having a2: b2≈a3: b3≈a4: b4≈. Accordingly, since the slope is proportional to the oscillation frequency range, the ratio of the change amount of the oscillation frequency accompanying the change of the control value with respect to the oscillation frequency can be made constant (equal ratio) regardless of the frequency range.

  For example, when the oscillation frequency is 500 MHz and the slope is a1 and the intercept b1, and the control code is changed by 1 UI (Unit Interval), the oscillation frequency changes by 1 MHz. %. Here, by setting the setting value of the slope a to a2 = a1 × 2 in the range of the oscillation frequency = 1000 MHz, the oscillation frequency changes by 2 MHz when the control code is changed by 1 UI. At that time, the rate of change of the oscillation frequency with respect to 1 UI of the control code is 0.2%. Thus, regardless of whether the oscillation frequency range is 500 MHz or 1000 MHz, the rate of change of the oscillation frequency with respect to 1 UI of the control code can be set to a constant 0.2%.

  Ideally, the above ratios should be equal to each other, but need not be exactly equal. This is because when the ratio is inaccurate, the rate of change of the oscillation frequency with respect to 1 UI of the control code for each oscillation frequency range is only deviated from a certain value accordingly.

[Embodiment 2] <Calibration (Trimming)>
Since the oscillator 1 can appropriately set the intercept b and the slope a, calibration (trimming) can be performed to compensate for manufacturing variations of the oscillation circuit.

FIG. 3 is an explanatory diagram showing a calibration (trimming) method of the oscillator 1. The horizontal axis is the control code X that is a control value, and the vertical axis is the oscillation frequency Y. The control code X is described as a positive value in the range from 0 to X _max for convenience, but the same applies even if it takes positive and negative values from -X _min to + X _max , for example.

The oscillation frequency curve before calibration is expressed as Y _a = A _a × a _init × X + B _a × b _init ,
The oscillation frequency curve after calibration _{Y c = A a × a t} × X + B a × b t,
The desired oscillation frequency curve and _{Y t = A t × a init} × X + B t × b init.

here,
A _a and B _a are the slope and intercept coefficient [Hz] of the oscillation frequency curve before calibration,
A _t and _{B t} is the coefficient of each slope and intercept of the desired oscillation frequency curves [Hz],
a _init and b _init are initial values of the setting value a and the setting value b, respectively.
a _t and b _t is the optimum value after calibration settings b respectively the set value a.

  [Hz] represents that the unit is Hz.

  A calibration (trimming) method will be described.

(1) Calibration X = 0 intercept b to measure the oscillation frequency _{Y a_0.}

Since in _{Y a_0 = B a × b init} , and _{Y t_0} the desired properties, in order to equalize the oscillation frequency _Y c_0 = _{B a} × _{b t} after calibration at X = _{0, b} t = _b A set value b _t after calibration is obtained by _init × Y _{t — 0} / Y a — ₀ . As shown in FIG. 2, the oscillation frequency curve before calibration, so that the intercept is Y _{t_0} from Y _{a_0,} translates characteristics shown as "after intercept b Calibration".

(2) measuring the oscillation frequency _{Y a_max} calibration X _{= X max} of the slope a.

Since Y a — _max = A _a × a _init × X _max + Y _t — ₀ , the desired characteristic Y _t — _max and the oscillation frequency after calibration at X = X _max Y _c — _max = A _a × a _t × X _max + Y _{t — 0} In order to make them equal to each other, a set value at after calibration is obtained by a _t = a _init × (Y _t — _max −Y _t — ₀ ) / Y a — _max −Y _t — ₀ ). As shown in FIG. 2, from the oscillation frequency curve after calibration of the intercept b, by setting the slope as the set value at after calibration with the intercept Y _{t — 0} , the oscillation frequency curve Y _c after calibration is obtained as a desired value. it can be matched to the oscillation frequency curve Y _t.

When the oscillation frequency curve control codes linear (straight line), as described above, the oscillation frequency curve Y _c, but can be matched to the desired oscillation frequency curve Y _t, actually oscillating frequency Y Has nonlinearity with respect to the control code X, and if this is large, an error occurs in calibration.

  FIG. 4 is a flowchart showing an example of a method for realizing the calibration (trimming) of FIG. When calibrating the intercept b, the measurement of the oscillation frequency and the update of the value of the intercept b are repeated until the calibration value of the intercept b does not change, so that even when the oscillation frequency curve has non-linearity, it is accurate. An optimum calibration value can be obtained.

First, the control code X = 0 and loop index i = 0 are initialized (S1), and other initial values are set (S2). Next, the calibration value b _{t — i + 1} calculation process (S3) is repeated. First, the set value b = _{bt_i} of the intercept b is substituted (S4). Since i = 0 in the first loop, b = b _t — ₀ is substituted. Next, the oscillation frequency _Yc is measured (S5). Compared to the measured frequency Y _c a desired oscillation frequency Y _t, it performs a "calibration intercept b" described above, calculates the updated sections b _{t_i + 1} (S6). The intercept b _{t_i} before the update and the intercept b _{t_i + 1} after the update are compared (S7). When the difference is larger than 1 (1LSB), that is, when the value of the intercept b before and after the update is different, the loop index i is increased by 1. (S8), the process returns to the calibration value b _{t — i + 1} calculation process (S3). Repeat this until the pre-update intercept _{b t_i} and intercept _{b t_i + 1} of the updated match, when there is a match, it is determined as the calibration value _b t = _{b t_i + 1} intercept b (S9). The same applies to the calibration of the inclination a. In the flowchart shown in FIG. 4, and X = Xmax, executes the calibration value _{a t_i + 1} calculation processing in place of the calibration value _{b t_i + 1} calculation processing.

  As a search algorithm, not only the above-described linear function (y = m × x) with a single measurement, but also a linear function with an intercept with two measurements (y = m × x + n) or a three-point measurement and a quadratic function Other function fittings can be used, such as In addition to function fitting, various other algorithms such as binary search can be used.

  FIG. 5 is an explanatory diagram showing another example of a method for realizing the calibration (trimming) of FIG.

  When there are a plurality of frequency ranges to be controlled, function fitting can be used as a search algorithm for the slope a and the intercept b. The coefficients of the functions a = f (Y) and b = g (Y) used for fitting can be obtained by calculating the oscillation frequency Y a required number of times. Further, the number of measurement points can be reduced by substituting the desired frequency into the obtained function and performing interpolation. In the figure, as an example, three points are measured with a quadratic function (stars in the figure) and interpolated (black circles in the figure).

[Embodiment 3] <Range setting unit>
In the case of having a plurality of oscillation frequency ranges, the oscillator 1 is configured so that the set values of the slope a and the intercept b suitable for each range are used.

  FIG. 6 is a block diagram illustrating a configuration example including the range setting unit 20 of the oscillator 1. As in FIG. 2, the oscillator 1 includes a frequency control unit 10 and an oscillation unit 61, and further includes a PLL logic 40 and a range setting unit 20. The frequency control unit 10 and the oscillation unit 61 are as described with reference to FIG. The control code X is supplied from the PLL logic 40, and the set values of the slope a and the intercept b are supplied from the range setting unit 20. The PLL logic 40 is a feedback circuit when a PLL is configured using the oscillator 1. Although an example of configuring the PLL has been adopted, the present invention is not limited to this, and any circuit that supplies the control code X can be changed.

  The range setting unit 20 can be configured in various forms.

  FIG. 7 is a block diagram illustrating a first configuration example of the range setting unit 20.

  The range setting unit 20 includes a parameter holding unit (range setting a) 31a, a parameter holding unit (range setting b) 31b, and selectors 21a and 21b. The parameter holding unit (range setting a) 31a stores set values a1, a2, a3, a4,... Of the slope a corresponding to each oscillation frequency range, and the parameter holding unit (range setting b) 31b stores the corresponding intercept. The set values b1, b2, b3, b4,. The selectors 21 a and 21 b select a corresponding set value according to the oscillation frequency range to be used, and supply it to the frequency control unit 10.

  Since the combination of the set values of the slope a and the intercept b is independently maintained for all the oscillation frequency ranges, the most storage capacity is required as compared with other configuration examples described later, while the set values to be stored are stored. Has the highest degree of freedom.

  FIG. 8 is a block diagram illustrating a second configuration example of the range setting unit 20.

  The range setting unit 20 includes a parameter holding unit (range setting a) 32a, a parameter holding unit (range setting b) 32b, selectors 22a and 22b, interpolation calculation units 23a and 23b, and final stage selectors 24a and 24b. The parameter holding unit (range setting a) 32a stores a part of the set values a1, a2, a3, a4,... Of the slope a corresponding to each oscillation frequency range, and the parameter holding unit (range setting b) 32b. Stores a part of the set values b1, b2, b3, b4,. The selector 22a selects two set values of the slope a corresponding to the oscillation frequency range to be used and supplies them to the interpolation calculation unit 23a. The interpolation calculation unit 23a selects the two set values that have been supplied. The set value of the slope a during that time is calculated by interpolation and output. It may be calculated by multiplying one set value by a predetermined coefficient. The final stage selector 24a selects either the setting value stored in the parameter holding unit (range setting a) 32a or the setting value calculated by the interpolation calculation unit 23a according to the oscillation frequency range to be used, This is supplied to the frequency control unit 10. The same applies to the section b side. The selector 22b selects two set values of the intercept b corresponding to the oscillation frequency range to be used, and supplies the set values to the interpolation calculation unit 23b. The interpolation calculation unit 23b selects the two set values that have been supplied. The set value of the intercept b during that time is calculated by interpolation and output. It may be calculated by multiplying one set value by a predetermined coefficient. The final stage selector 24b selects the setting value stored in the parameter holding unit (range setting b) 32b or the setting value calculated by the interpolation calculation unit 23b according to the oscillation frequency range to be used, This is supplied to the frequency control unit 10.

  Thereby, compared with the range setting part 20 shown by FIG. 6, the memory capacity for memorize | storing a setting value can be restrained small.

  FIG. 9 is a block diagram illustrating a third configuration example of the range setting unit.

  The range setting unit 20 includes a function calculation unit (f (y)) 26a for the inclination a, a function calculation unit (g (y)) 26b for the intercept b, a frequency setting unit 33, and a function f (y ) Includes a parameter holding unit (f (y) coefficient) 34, a parameter holding unit (g (y) coefficient) 35 that holds the coefficient of the function g (y), and selectors 25a and 25b. In the configuration example shown in FIG. 7, the set values of the slope a and the intercept b are obtained by interpolation between two points. However, when there is a nonlinearity between the frequency range and the set values of the slope a and the intercept b, a simple value is used. In such an interpolation calculation, there is a problem that an error becomes large. Therefore, instead of the interpolation calculation, calculation using arbitrary functions f (y) and g (y) from a plurality of points is employed. The frequency setting unit 33 holds the oscillation frequency y in each range. The oscillation frequency y selected according to the range by the selectors 25a and 25b is supplied to the function calculation unit (f (y)) 26a and the function calculation unit (g (y)) 26b, respectively. The function calculation unit (f (y)) 26a and the function calculation unit (g (y)) 26b are derived from the parameter holding unit (f (y) coefficient) 34 and the parameter holding unit (g (y) coefficient) 35, respectively. , The set values of the slope a and the intercept b are calculated and supplied to the frequency control unit 10.

  Thereby, even when the nonlinearity between the frequency range and the set values of the slope a and the intercept b is large, the set values of the slope a and the intercept b can be calculated with high accuracy.

Embodiment 4 <Current DAC + Current Control Oscillator>
The frequency control unit 10 and the oscillation unit 61 can be configured in various forms.

  FIG. 10 is a block diagram illustrating a configuration example of the current control oscillation unit 61. FIG. 7 shows the configuration example shown in FIG. 6 in more detail. The oscillator 1 includes a current control oscillation unit 61, a frequency control unit 10, a range setting unit 20, a memory 30, a PLL logic 40, and a bias circuit 50.

  The frequency control unit 10 includes first to third DA converters 11 to 13 and a current adder 14, and further includes three low-pass filters (LPF1 to LPF3) 15_1 to 15_3. Each of the second and third DA converters 12 and 13 is a current type DA converter that converts an input digital value into an analog current value based on the reference current Iref supplied from the bias circuit 50. A low-pass filter (LPF1) 15_1 is inserted in the path for supplying Iref. Thereby, the high frequency noise mixed in the reference current Iref is removed, and the reference current Iref is stabilized. The second DA converter (DAC2) 12 receives the intercept b, which is a digital value, and outputs an analog current b × Iref. The third DA converter (DAC3) 13 receives a slope a which is a digital value, outputs an analog current a × Iref, and inputs it to the reference current of the first DA converter (DAC1) 11. A low-pass filter (LPF3) 15_3 is inserted in this path, and high-frequency noise mixed in the reference current a × Iref is removed. The first DA converter (DAC1) 11 receives a digital control code x as a control value from the PLL logic 40, and outputs a product of x × a × Iref as a reference current a × Iref. The current adder 14 adds the output current x × a × Iref from the first DA converter (DAC1) 11 and the output current b × Iref from the second DA converter (DAC2) 12 to add Iy = (xx a + b) × Iref is obtained and supplied to the current control oscillator 61 as the control current Iy. A low-pass filter (LPF2) 15_2 is inserted in the path from the second DA converter (DAC2) 12 to the current adder 14, and high-frequency noise mixed in the reference current b × Iref is removed.

  The memory 30 is composed of, for example, a non-volatile memory (NVM), and a part (eight) of the set values a1, a2, a3, a4,... Of the inclination a corresponding to each oscillation frequency range. And a_ratio parameter storage unit (range setting a) 32a, and a corresponding part b set value b1, b2, b3, b4,... (8) and b_ratio parameter storage unit (b_ratio) Range setting b) 32b. The range setting unit 20 includes selectors 22a and 22b, interpolation calculation units 23a and 23b, and final stage selectors 24a and 24b. The selector 22a selects a set value of the slope a corresponding to the oscillation frequency range to be used and supplies it to the interpolation calculation unit 23a. The interpolation calculation unit 23a adds a predetermined coefficient a_ratio to the supplied set value. Performs multiplication interpolation. The final stage selector 24a selects either the setting value stored in the parameter holding unit (range setting a) 32a or the setting value calculated by the interpolation calculation unit 23a according to the oscillation frequency range to be used, This is supplied to the frequency control unit 10. The same applies to the section b side. The selector 22b selects the set value of the intercept b corresponding to the oscillation frequency range to be used, and supplies the selected value to the interpolation calculation unit 23b. The interpolation calculation unit 23b adds a predetermined coefficient b_ratio to the supplied set value. Performs multiplication interpolation. The final stage selector 24b selects the setting value stored in the parameter holding unit (range setting b) 32b or the setting value calculated by the interpolation calculation unit 23b according to the oscillation frequency range to be used, This is supplied to the frequency control unit 10.

  The PLL logic 40 compares the phase of the clock output from the current control oscillator 61 and the clock input from the outside, outputs a control code x based on the result, and supplies the control code x to the frequency controller 10. Since the control is performed to match the phase of the clock output from the current-controlled oscillator 61 and the clock input from the outside, it can be applied to clock data recovery (CDR). On the other hand, when applied to a frequency synthesizer or the like that does not require the phases to coincide, the PLL may be changed to FLL (Frequency Locked Loop) or DLL (Delay Locked Loop). This also applies to the other embodiments.

  FIG. 11 is a circuit diagram illustrating a configuration example of the current control oscillation unit 10 of FIG. The bias circuit 50 and the current control oscillator 61 are also shown. The reference current Iref supplied from the bias circuit 50 is supplied from the second DA converter (DAC2) 12 and the third DA converter (DAC3) 13 by a current mirror composed of n-channel MOS transistors M1 and M2 and a p-channel MOS transistor M3. To be supplied. A low-pass filter (LPF1) 15_1 is inserted between the p-channel MOS transistor M and the second DA converter (DAC2) 12. The second DA converter (DAC2) 12 is composed of a plurality of p-channel MOS transistors whose mirror ratio is controlled by an intercept b (not shown), and outputs an output current b × Iref. The third DA converter (DAC3) 13 is composed of a plurality of p-channel MOS transistors whose mirror ratio is controlled by a slope a (not shown), and outputs an output current a × Iref. The output current a × Iref of the third DA converter (DAC3) 13 is supplied to the first DA converter (DAC1) 11 by a current mirror composed of n-channel MOS transistors M4 and M5 and a p-channel MOS transistor M6. A low-pass filter (LPF3) 15_3 is inserted between the n-channel MOS transistors M4 and M5. The first DA converter (DAC1) 11 includes a plurality of p-channel MOS transistors whose mirror ratio is adjusted by a control code x (not shown), and outputs an output current a × x × Iref. The current adder 14 includes n channel MOS transistors M7, M8, M9 and M10. M7 and M8 constitute a current mirror, the current b × Iref output from the second DA converter (DAC2) 12 is mirrored to the output current Iy, and M7 and M8 constitute a current mirror, and the third DA converter The current a × x × Iref output from (DAC3) 13 is added to the same output current Iy by mirroring and output. A low-pass filter (LPF2) 15_2 is inserted between M7 and M8. In FIG. 10, the current adder 14 is illustrated as being disposed at the input unit, but the effect of noise removal on the current b × Iref output from the second DA converter (DAC2) 12 is the same. The low-pass filters (LPF1 to LPF3) 15_1 to 15_3 are each implemented as an RC filter including a resistor R and a capacitor C, for example. The mirror ratio may be adjusted as appropriate.

  As described above, the analog circuit that performs multiplication (DA conversion) and addition of current values is configured with a simpler circuit than the multiplication and addition of voltage values, and the overall circuit scale can be suppressed. That is, since the frequency range is made equal to control the frequency at the same ratio with respect to 1 UI of the control code, the higher the oscillation frequency, the wider the oscillation frequency range that can be covered, so the second DA converter for coarse tuning ( The number of bits of DAC2) 12 can be suppressed. When the oscillation frequency varies due to manufacturing variation or the like, the inclination a can be adjusted, so that not only the absolute value of the oscillation frequency but also the inclination with respect to the control code can be calibrated. All the frequency ranges are not stored in the memory, but are generated by interpolating between the operations, so that the storage capacity of the memory 30 can be reduced.

  FIG. 12 is a block diagram showing a modification of the range setting unit 20 in the oscillator 1 of FIG. FIG. 10 shows the range setting unit 20 including the interpolation calculation units 23a and 23b corresponding to FIG. 8, but the range setting unit 20 including the function calculation units 26a and 27b corresponding to FIG. 9 is replaced. Can do. The frequency control unit 10, the oscillation unit 61, the PLL logic 40, and the bias circuit 50, which are not illustrated, are the same as those in FIG. The range setting unit 20 includes a function calculation unit (f (y)) 26a for the inclination a, a function calculation unit (g (y)) 26b for the intercept b, and selectors 25a and 25b. Are a frequency setting unit 33, a parameter holding unit (f (y) coefficient) 34 for holding the coefficient of the function f (y), and a parameter holding unit (g (y) coefficient for holding the coefficient of the function g (y) 35). The frequency setting unit 33 holds the oscillation frequency y in each range. The oscillation frequency y selected according to the range by the selectors 25a and 25b is supplied to the function calculation unit (f (y)) 26a and the function calculation unit (g (y)) 26b, respectively. The function calculation unit (f (y)) 26a and the function calculation unit (g (y)) 26b are derived from the parameter holding unit (f (y) coefficient) 34 and the parameter holding unit (g (y) coefficient) 35, respectively. , The set values of the slope a and the intercept b are calculated and supplied to the frequency control unit 10.

  Since it has all the arithmetic functions, the scale of the digital circuit is larger than that of the oscillator 1 shown in FIG. 10. However, since the coefficient of the fitting function and the set frequency are directly stored in the memory, it is more flexible than the oscillator 1 shown in FIG. The oscillation frequency can be controlled by an arbitrary straight line, and an optimum coefficient can be selected in a wide range.

  Also in the oscillator 1 of the present embodiment, it is desirable to give the relationship between the slope a and the intercept b described in the first embodiment as “the slope is proportional to the intercept (oscillation frequency range)”. Furthermore, the application of the calibration (trimming) of the second embodiment and the addition of the range setting unit of the third embodiment can be arbitrarily combined.

[Embodiment 5] <LC Oscillator>
The oscillating unit of the oscillator 1 can also be configured by an oscillating circuit other than the above-described current control oscillating unit 61.

  FIG. 13 is a block diagram illustrating a configuration example of the LC oscillation unit 62. The oscillator 1 includes a frequency controller 10 including first and second capacitor DA converters (C-DAC1, C-DAC2) 11 and 12, a resistor DA converter (R-DAC3) 13, an adder 14, and a PLL logic. 40 and an LC oscillation unit 62.

The second capacitance DA converter (C-DAC2) 12 is a capacitance DA converter that outputs a capacitance value b × C2 proportional to the intercept b. The resistor DA converter (R-DAC3) 13 receives the reference voltage Vref, outputs a voltage Vref × a / 2 ⁿ (n is the number of bits of the R-DAC3) proportional to the slope a, and outputs a first voltage. The capacitor DA converter (C-DAC1) 11 is supplied. The first capacitor DA converter (C-DAC1) 11 includes a plurality of variable capacitor elements (for example, varactors) whose capacitance values are controlled by the voltage Vref × a / 2 ⁿ supplied from the resistor DA converter (R-DAC3) 13. A capacitance value x × Vref × a / 2 ⁿ × K × C1 that is proportional to the control code x is output. Here, K is a varactor coefficient [unit: F / V]. The adder 14 includes a capacitance value b × C2 output from the second capacitance DA converter (C-DAC2) 12 and a capacitance value x × Vref × a output from the first capacitance DA converter (C-DAC1) 11. / 2 ⁿ × K × C1 are added together by connecting them in parallel. The capacitance added by the parallel connection constitutes a part of the resonance circuit of the LC oscillation unit 62.

As a result, the oscillation frequency of the LC oscillation unit 62 is controlled by the added capacitance value x × Vref × a / 2 ⁿ × K × C1 + b × C2, so that the slope is controlled by a variable linear function. Become.

  FIG. 13 is a block diagram schematically showing the above-described configuration. In actual implementation, the first and second capacitor DA converters (C-DAC1, C-DAC2) 11 and 12 and the resistor DA converter (R− It is not necessary to perform clear block division like the DAC 3) 13 and the adder 14, and a circuit having the above-described function may be mounted as a whole. A low-pass filter or the like for removing noise is not shown, but may be installed as appropriate.

FIG. 14 is a circuit diagram showing a configuration example of the tank circuit in the LC oscillation unit 62 of FIG. For example, it is suitable as a tank circuit when the LC oscillation unit 62 is mounted by a differential oscillator. A coarse adjustment capacitor bank 71, a fine adjustment capacitor bank 72, and an inductor 73 are connected in parallel. The coarse adjustment capacity bank 71 is the second capacity DA converter (C-DAC2) 12, and the capacity value is adjusted by the coarse adjustment capacity adjustment bit which is the intercept b. The fine adjustment capacitor bank 72 is a first capacitor DA converter (C-DAC1) 11, and a unit capacitance value is adjusted by applying a voltage Vref × a / 2 ⁿ proportional to the slope a to the capacitance value adjustment voltage terminal. The total capacity value is adjusted by the fine adjustment capacity adjustment bit which is the control code x. Since the coarse adjustment capacity bank 71 and the fine adjustment capacity bank 72 are connected in parallel, the mutual capacitance values are added, so that substantial circuit elements corresponding to the adder 14 are not mounted.

  FIG. 15 is a circuit diagram showing a configuration example of the coarse adjustment capacity bank 71 in the tank circuit of FIG. The coarse adjustment capacitor bank 71 includes a plurality of capacitors 77 and a plurality of switches 79. By controlling the number of switches 79 that are closed (turned on) by the intercept b, the overall capacitance value is proportional to the intercept b.

  FIG. 16 is a circuit diagram showing a configuration example of the fine adjustment capacity bank 72 in the tank circuit of FIG. The fine adjustment capacitor bank 72 includes a plurality of variable capacitance elements (varactors) 78 and a plurality of switches 79. Although a varactor diode is illustrated, it can be configured using other variable capacitance elements. The variable capacitance element (varactor) 78 is connected to the capacitance value adjustment voltage terminal, and the capacitance value (C1) varies depending on the applied voltage (Vc). The number of switches 79 that are closed (turned on) by the control code x, that is, the number of connected variable capacitance elements (varactors) 78 is controlled. The capacitance value of the entire fine adjustment capacitor bank 72 is a product of the capacitance value C1 (Vc) determined based on the voltage (Vc) applied to the capacitance value adjustment voltage terminal and the control code x.

FIG. 17 is a circuit diagram showing a configuration example of a variable capacitance portion for adjusting the oscillation frequency in the LC oscillation unit of FIG. For example, it is suitably mounted on a tank circuit of an LC single-ended oscillator such as a Hartley oscillator or a Colpitts oscillator. The coarse adjustment capacitor bank 71 and the fine adjustment capacitor bank 72 are connected in parallel to each other. The coarse adjustment capacity bank 71 is the second capacity DA converter (C-DAC2) 12, and the capacity value is adjusted by the coarse adjustment capacity adjustment bit which is the intercept b. The fine adjustment capacitor bank 72 is a first capacitor DA converter (C-DAC1) 11, and a unit capacitance value is adjusted by applying a voltage Vref × a / 2 ⁿ proportional to the slope a to the capacitance value adjustment voltage terminal. The total capacity value is adjusted by the fine adjustment capacity adjustment bit which is the control code x. Since the coarse adjustment capacity bank 71 and the fine adjustment capacity bank 72 are connected in parallel, the mutual capacitance values are added, so that substantial circuit elements corresponding to the adder 14 are not mounted.

  FIG. 18 is a circuit diagram showing a configuration example of the coarse adjustment capacitor bank 71 in FIG. The coarse adjustment capacitor bank 71 includes a plurality of capacitors 77 and a plurality of switches 79. By controlling the number of switches 79 that are closed (turned on) by the intercept b, the overall capacitance value is proportional to the intercept b. The coarse adjustment capacity bank 71 of FIG. 15 is balanced, whereas the coarse adjustment capacity bank 71 of FIG. 18 is different in that one is grounded.

  FIG. 19 is a circuit diagram showing a configuration example of the fine adjustment capacity bank 72 in FIG. The fine adjustment capacitor bank 72 includes a plurality of variable capacitance elements (varactors) 78 and a plurality of switches 79. 16 is balanced, while one of the fine tuning capacity banks 72 of FIG. 19 is grounded, and a capacity (DC cut capacity) 77 for cutting off a direct current (DC) component is inserted in the other. Different in that it is. FIG. 19 also shows a varactor diode as a variable capacitance element, but it can also be configured using other variable capacitance elements. The variable capacitance element (varactor) 78 is connected to the capacitance value adjustment voltage terminal, and the capacitance value (C1) varies depending on the applied voltage (Vc). The number of switches 79 that are closed (turned on) by the control code x, that is, the number of connected variable capacitance elements (varactors) 78 is controlled. The capacitance value of the entire fine adjustment capacitor bank 72 is a product of the capacitance value C1 (Vc) determined based on the voltage (Vc) applied to the capacitance value adjustment voltage terminal and the control code x.

  FIG. 20 is a block diagram illustrating another configuration example of an oscillator including an LC oscillation unit. The oscillator 1 includes a frequency controller 10 including first and second capacitor DA converters (C-DAC1, C-DAC2) 11 and 12, a resistor DA converter (R-DAC3) 13, an adder 14, and a PLL logic. 40 and the LC oscillation unit 62, and further includes a varactor nonlinearity correction calculation / table 27. The difference from the oscillator 1 of FIG. 13 is that the slope a is input via the varactor nonlinearity correction calculation / table 27 instead of being directly input to the resistor DA converter (R-DAC3) 13. Other configurations and functions are the same as those of the oscillator 1 shown in FIG. The varactor non-linearity correction calculation / table 27 performs calculation or table conversion for correcting non-linearity of the variable capacitance element (for example, varactor diode) used in the first capacitor DA converter (C-DAC1) 11.

FIG. 21 is an explanatory diagram (CV characteristic) about the correction calculation for the nonlinear characteristic of the variable capacitance element (varactor), and FIG. 22 is an explanatory diagram about the correction calculation for the nonlinear characteristic of the variable capacitance element (varactor). Relationship between parameter a and voltage V). In the oscillator 1 of FIG. 13, when the resistor DA converter (R-DAC3) 13 has a linear conversion characteristic, Vref output corresponding to the slope a is linear as shown by the broken line in FIG. . In the first capacitor DA converter (C-DAC1) 11 to which this Vref is supplied as a reference voltage, the capacitance value C = Vref × a / 2 ⁿ × K of the variable capacitor (for example, varactor diode) is indicated by a broken line in FIG. If the non-linearity is as shown, the entire output capacitance value has the same non-linearity. On the other hand, in the oscillator 1 of FIG. 20, the relationship of the output v of the resistor DA converter (R-DAC3) 13 with respect to the inclination a is, as shown in FIG. 22, the nonlinear characteristic f ( The value of the slope a is corrected in advance by the varactor nonlinearity correction calculation / table 27 so that the inverse function v = f ⁻¹ (a) of v) is obtained. As a result, the output of the first capacitor DA converter (C-DAC1) 11 to which this v = f ⁻¹ (a) is supplied as the reference voltage cancels out the nonlinearity of the variable capacitor (varactor). It can be corrected to a linear characteristic as shown by the solid line 21.

The varactor nonlinearity correction calculation / table 27 is implemented by a logic circuit that performs the above-described inverse function calculation on the gradient a or a correction table that performs inverse transformation. When the correction table is used, the inverse mapping v = f ⁻¹ (a) in which the output voltage v of the resistor DA converter (R-DAC3) 13 linearly corrects the nonlinear characteristic f (v) of the variable capacitance element (varactor). The value of the slope a is converted and input so that Instead of the varactor nonlinearity correction calculation / table 27, the conversion characteristic of the resistor DA converter (R-DAC3) 13 may have the characteristic of an inverse function or inverse mapping v = f ⁻¹ (a). For example, when the resistor DA converter (R-DAC3) 13 is a resistor string type, a desired non-linear characteristic can be provided by adjusting a tap tap position for extracting a voltage from the resistor string.

  The nonlinear characteristic f (v) or its inverse function / inverse mapping characteristic can be obtained by actual measurement by operating the oscillator 1. For example, the nonlinear characteristic f (v) can be obtained by fixing the control code x to a value other than 0, sweeping the slope a, and measuring the oscillation frequency. By assuming the nonlinear characteristic f (v) as a function of an appropriate order and obtaining the coefficient by fitting, the function and the inverse function can be obtained analytically.

  FIG. 23 is a block diagram illustrating still another configuration example of the LC oscillation unit. The oscillator 1 includes first and third resistor DA converters (R-DAC1, R-DAC3) 11 and 13, a capacitor DA converter (C-DAC2) 12, a voltage control variable capacitor (V / C) 16, and an adder. 14 includes a frequency control unit 10, a PLL logic 40, and an LC oscillation unit 62. The difference from the oscillator 1 of FIG. 13 is that the DA converter for fine adjustment is changed from a capacitive DA converter (C-DAC1) to a resistive DA converter (R-DAC1), and a voltage-controlled variable capacitor ( (V / C) 16 is added. The voltage controlled variable capacitor (V / C) 16 is connected in parallel with the capacitor DA converter (C-DAC2) 12 to constitute a tank circuit of the LC oscillation unit 62. A voltage determined by the product a × Vref of the slope a and the reference voltage Vref is output from the third resistor DA converter (R-DAC3) 13 and supplied to the first resistor DA converter (R-DAC1) 11 as a reference voltage. The From the first resistor DA converter (R-DAC1) 11, a product x × a × Vref of the input control code x and the reference voltage supplied from the third resistor DA converter (R-DAC3) 13 is obtained. The determined voltage is output and supplied to the voltage controlled variable capacitor (V / C) 16. The capacitance value of the voltage controlled variable capacitor (V / C) 16 is adjusted by x × a × Vref. Other configurations and functions are the same as those of the oscillator 1 shown in FIG.

  This eliminates the need for digital wiring to the voltage controlled variable capacitor (V / C) 16 constituting the tank circuit of the LC oscillation unit 62, and wiring 1 from the output of the first resistor DA converter (R-DAC1) 11. Can only be a book. Therefore, the influence of the parasitic impedance of the control wiring can be reduced.

  Also in the oscillator 1 of the present embodiment, it is desirable to give the relationship between the slope a and the intercept b described in the first embodiment as “the slope is proportional to the intercept (oscillation frequency range)”. Furthermore, the application of the calibration (trimming) of the second embodiment and the addition of the range setting unit of the third embodiment can be arbitrarily combined.

[Embodiment 6] <VCO>
The oscillator 1 according to the present invention may be configured to include any form of oscillation unit other than the above-described current control oscillation unit and LC oscillation unit.

  FIG. 24 is a block diagram illustrating a configuration example of the oscillator 1 including the voltage controlled oscillation unit 63. The oscillator 1 includes a PLL logic 40, a frequency control unit 10 including first to third three DA converters 11 to 13 and an adder 14, a current / voltage conversion circuit (I / V) 17, a voltage And a control oscillation unit 63. Since the configuration and operation of the frequency control unit 10 are the same as those in the first embodiment described with reference to FIG. 2, detailed description thereof is omitted. A control current Iy output from the frequency control unit 10 is converted into a voltage by a current / voltage conversion circuit (I / V) 17 and supplied to the voltage control oscillation unit 63 as a control voltage. The frequency control unit 10 may perform a calculation based on a voltage value instead of the current type DA conversion and the current addition similar to those in FIG. 2, or may perform a DA conversion of a voltage output after performing a digital calculation.

  Thereby, also in the oscillator 1 including the voltage-controlled oscillation unit 63, the control range and the resolution can be appropriately controlled at the same time even when the oscillation frequency range is wide, similarly to the first embodiment and the like. The effect of can be produced.

  Also in the oscillator 1 of the present embodiment, it is desirable to give the relationship between the slope a and the intercept b described in the first embodiment as “the slope is proportional to the intercept (oscillation frequency range)”. Furthermore, the application of the calibration (trimming) of the second embodiment and the addition of the range setting unit of the third embodiment can be arbitrarily combined.

[Embodiment 7] <Analog feedback>
As described above, the oscillator 1 according to the present invention is not limited to the case where the digital control code x is fed back, and can be configured similarly when an analog control signal is input. The analog control voltage v is fed back from an analog PLL circuit 41 including a phase comparator, a charge pump, and a lag lead filter, for example.

  FIG. 25 is a block diagram illustrating a configuration example of the oscillator 1 that includes the current control oscillation unit 61 and that feeds back an analog control signal. The oscillator 1 includes a frequency control unit 10 including a second and third DA converters (DAC2, DAC3) 12 and 13, a voltage / current conversion circuit (V / I) 18 and an adder 14, a PLL circuit 41, The current control oscillation unit 61 is provided. The second DA converter (DAC2) 12 receives the intercept b, which is a digital value, and outputs an analog current b × Iref. The third DA converter (DAC3) 13 receives a slope a which is a digital value, and outputs an analog current a × Iref. The voltage / current conversion circuit (V / I) 18 receives an analog control voltage v, which is a control value, and a product of the reference current a × Iref input from the third DA converter (DAC3) 13, a × Iref × v × Gm is output. Here, Gm is the transconductance [unit: A / V] of the voltage / current conversion circuit (V / I) 18. The adder 14 adds the output current a × Iref × v × Gm of the voltage / current conversion circuit (V / I) 1 and the output current b × Iref from the second DA converter (DAC2) 12 to obtain Iy = (V × Gm × a + b) × Iref is obtained and supplied to the current control oscillator 61 as the control current Iy.

  As a result, the oscillation frequency of the current control oscillation unit 61 is controlled by Iy = (v × Gm × a + b) × Iref, and therefore is controlled by a linear function with a variable slope.

  FIG. 26 is a block diagram illustrating a configuration example of the oscillator 1 including the LC oscillation unit 62 to which an analog control signal is fed back. The oscillator 1 includes a frequency control unit 10 including a variable capacitance circuit 19 including a varactor bank V / C conversion, a capacitive DA converter (C-DAC3), a capacitive DA converter (C-DAC2) 12, and an adder 14. The PLL circuit 41 and the LC oscillation unit 62 are provided. A variable capacitance circuit 19 including a varactor bank V / C conversion and a capacitance DA converter (C-DAC3) is a variable capacitance connected in parallel with a slope a in a varactor bank composed of a plurality of variable capacitance elements to which a control voltage v is applied. By adjusting the number of elements, the capacitance value a × v × K × C1 is output. Here, K is a varactor coefficient [unit: F / V]. The capacitive DA converter (C-DAC2) 12 is a capacitive DAC that outputs a capacitance value b × C2 proportional to the intercept b. The adder 14 connects the capacitance value b × C2 output from the capacitance DA converter (C-DAC2) 12 and the capacitance value a × v × K × C1 output from the variable capacitance circuit 19 to each other. to add. The capacitance added by the parallel connection constitutes a part of the resonance circuit of the LC oscillation unit 62.

  As a result, the oscillation frequency of the LC oscillation unit 62 is controlled by the added capacitance value a × v × K × C1 + b × C2, and thus is controlled by a linear function with a variable slope.

  As described above, even when an analog control signal is input as the control value instead of the digital control code x, the oscillation frequency is similarly controlled by a linear function related to the control value. be able to. For example, in an analog PLL, the loop gain for each frequency range can be controlled in proportion to the digital parameter.

  Also in the oscillator 1 of the present embodiment, it is desirable to give the relationship between the slope a and the intercept b described in the first embodiment as “the slope is proportional to the intercept (oscillation frequency range)”. Furthermore, the application of the calibration (trimming) of the second embodiment and the addition of the range setting unit of the third embodiment can be arbitrarily combined.

[Eighth embodiment] <Adjustment of output of DA converter>
A gain adjusting unit can be appropriately inserted into the input or output of various DA converters 11 to 13 mounted on the oscillator 1 described in the fourth to sixth embodiments. As a result, the control amount input to the various oscillating units (current control oscillating unit 61, LC oscillating unit 62, voltage controlled oscillating unit (VCO) 63) is set to a value within an appropriate range in order to obtain a desired oscillation frequency. Can be adjusted.

FIG. 27 is a block diagram illustrating a configuration example of an oscillator in which a gain adjusting unit is added to the output unit of each DA converter in the oscillator of FIG. The oscillator 1 includes first to third DA converters (DAC1 to DAC3) 11 to 13, gain adjusting units 81 to 83 that adjust the outputs of the respective DA converters, and a frequency control unit 10 that includes an adder 14. The oscillator 61 is configured. Since it is the same as that of Embodiment 1 described with reference to FIG. 2, detailed description thereof is omitted. The difference from FIG. 2 is that each of the outputs of the first to third DA converters (DAC1 to DAC3) 11 to 13 has gain adjustment units 81 to 83, respectively. The gain adjusting units 81 to 83 have a function of outputting the outputs of the _{first to third} DA converters (DAC1 to DAC3) 11 to 13 by multiplying them by gains G1 to G3, respectively. The second DA converter (DAC2) 12 receives the intercept b, which is a digital value, and outputs an analog current b × Iref. The output of the 2DA converter (DAC2) 12 is _twice the gain _G by the gain adjusting unit 82 to obtain an output current _{G 2} × b × Iref. The third DA converter (DAC3) 13 receives a slope a which is a digital value, outputs an analog current a × Iref, and G ₃ × a × Iref multiplied by a gain G ₃ by the gain adjustment unit 83 is converted into the first DA converter. Input to the reference current of the DAC (DAC1) 11. The first DA converter (DAC1) 11 receives a digital control code x that is a control value, and outputs a product xxG ₃ × a × Iref that is a reference current G ₃ × a × Iref. . The output of the first DA converter (DAC1) 11 is further multiplied by a gain G ₁ by a gain adjustment unit 81 to obtain G ₁ × x × G ₃ × a × Iref. The adder 14 is configured so that an output current from the first DA converter (DAC1) 11 is gain-adjusted and a current G ₁ × x × G ₃ × a × Iref and an output current from the second DA converter (DAC2) 12 are The gain-adjusted current G ₂ × b × Iref is added to obtain Iy = (G ₁ × G ₃ × x × a + G ₂ × b) × Iref and supplied to the oscillating unit 61 as the control current Iy.

  Thereby, the control amount input to the oscillating unit 61 can be adjusted to a value in an appropriate range.

FIG. 28 is a block diagram illustrating a configuration example of an oscillator in which a gain adjustment unit is added to the reference value input unit of each DA converter in the oscillator of FIG. The oscillator 1 includes first to third DA converters (DAC1 to DAC3) 11 to 13, gain adjustment units 81 to 83 that adjust respective reference values to reference value input units of the DA converters, and an adder 14. The frequency control unit 10 and the oscillation unit 61 are provided. Since it is the same as that of Embodiment 1 described with reference to FIG. 2, detailed description thereof is omitted. The difference from FIG. 2 is that each of the DA converters (DAC1 to DAC3) 11 to 13 has gain adjustment units 81 to 83 at reference value inputs. The gain adjusting units 81 to 83 have a function of multiplying input current values by gains G _{1 to} G ₃ and inputting the current values as reference values to the DA converters (DAC _{1 to} DAC ₃ ) 11 to 13, respectively. The first 2DA converter (DAC2) 12, reference current Iref is inputted is _doubled gain _G by the gain adjustment section 82, also is input intercept b is a digital value, an analog current _{G 2} × b × Iref output Is done. The third DA converter (DAC3) 13 is supplied with the reference current Iref multiplied by the gain G ₃ by the gain adjustment unit 83, and also inputted with the slope a which is a digital value, and outputs an analog current G ₃ × a × Iref. Is done. This output current is input to the reference current of the gain adjustment unit first 1DA converter is _1-fold gain _G by 81 (DAC1) 11. The first DA converter (DAC1) 11 receives a digital control code x that is a control value, and is a product G ₁ × G ₃ × x × a × with a reference current G ₁ × G ₃ × a × Iref. Iref is output. The adder 14 outputs the output current G ₁ × G ₃ × x × a × Iref from the first DA converter (DAC1) 11 and the output current G ₂ × b × Iref from the second DA converter (DAC2) 12. By adding, Iy = (G ₁ × G ₃ × x × a + G ₂ × b) × Iref is obtained and supplied to the oscillating unit 61 as the control current Iy.

Thereby, the control amount can be adjusted appropriately by multiplying the input reference value of each DA converter by the gain by the gain adjustment unit. Alternatively, the gain adjustment unit may not be inserted into the reference value input unit, and the gains G _{1 to} G ₃ may be directly multiplied to the input parameters.

Since the gain adjustment unit can be realized by adjusting the output value for the unit input parameter of the DA converter, the gain adjustment may be performed in the DA converter by increasing or decreasing the output value for the unit input parameter. The gains G _{1 to} G ₃ of the gain adjusting unit may be not only an amplifier but also an attenuator.

  FIG. 27 shows a configuration example in which the gain adjusting units are provided in all the output units of the three DA converters, but only the output units of one or two DA converters are appropriately provided with the gain adjusting units. It is good also as a structure. FIG. 28 shows a configuration example in which all the reference value input units of the three DA converters are each provided with a gain adjustment unit, but only in the reference value input units of one or two DA converters, It is good also as a structure provided with a gain adjustment part suitably. Furthermore, it is good also as a structure which equips the reference value input part and output part of a part or all DA converter with a gain adjustment part suitably.

  In the configuration examples shown in FIGS. 27 and 28, the oscillation unit is the current control oscillation unit 61. However, the oscillation unit may be similarly applied to an oscillator including the LC oscillation unit 62 and the voltage control oscillation unit (VCO) 63. it can.

  Also in the oscillator 1 of the present embodiment, it is desirable to give the relationship between the slope a and the intercept b described in the first embodiment as “the slope is proportional to the intercept (oscillation frequency range)”. Furthermore, the application of the calibration (trimming) of the second embodiment and the addition of the range setting unit of the third embodiment can be arbitrarily combined.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

1 Oscillator 10 Frequency Control Unit 11, 12, 13 DAC
14 Adder 15 LPF
16, 19 Voltage controlled variable capacity (V / C)
17 Current / voltage conversion circuit (I / V)
18 Voltage / current conversion circuit (V / I)
19 Variable capacity circuit (varactor bank V / C conversion and capacity DA converter)
20 range setting unit 21a, 21b, 22a, 22b, 24a, 24b selector 23a, 23b interpolation calculation unit 26a, 26b function calculation unit 27 varactor nonlinearity correction calculation / table 30 memory 31-35 parameter holding unit 40 PLL logic 41 analog PLL Feedback circuit 50 Bias circuit 61 Current controlled oscillator 62 LC oscillator 63 Voltage controlled oscillator (VCO)
71 Coarse adjustment capacity bank 72 Fine adjustment capacity bank 73 Inductor 77 Capacity 78 Varactor (variable capacity) diode 79 Switch 81, 82, 83 Gain adjustment section

Claims (16)

  An oscillator in which an oscillation frequency is controlled by a control value, wherein the oscillation frequency is defined by a linear function of the control value, and the linear function has an intercept and a slope defined by a digital value, and the intercept and the An oscillator whose tilt can be set.   The oscillator according to claim 1, wherein the set value of the slope is defined as a value having a positive correlation proportional to the set value of the intercept.   The oscillator according to claim 1, further comprising a range setting unit that has a plurality of frequency ranges and sets the intercept and the inclination for each of the plurality of frequency ranges.   4. The oscillator according to claim 3, wherein the range setting unit holds intercept and slope setting values for each of the plurality of frequency ranges, and sets the intercept and slope selected according to a designated frequency range.   4. The range setting unit according to claim 3, wherein a set value of an intercept and an inclination is held for a part of the plurality of frequency ranges, and the specified frequency range corresponds to the partial frequency range. Intercepts and slopes are selected and set, and if they are outside the partial frequency range, interpolation is performed from intercept and slope values corresponding to two frequency ranges close to the frequency range of the partial frequency ranges. An oscillator that sets the value obtained by the above as the intercept and slope corresponding to the frequency range.   5. The oscillator according to claim 4, wherein the set values of the intercept and the inclination are calculated based on a relationship between the control value measured by operating the oscillator and an oscillation frequency, and are written in the range setting unit.   In Claim 3, the range setting unit includes a function for calculating an intercept and a slope corresponding to each of the plurality of frequency ranges, and the intercept and the slope calculated by the function according to a designated frequency range, An oscillator set as the intercept and slope corresponding to the frequency range. The first DA converter, the second DA converter, and the third DA converter according to claim 1, each of which receives a digital value and a reference value and outputs an analog value based on a product of the digital value and the reference value.
The intercept is defined by a product of a reference value and a first parameter, and the slope is defined by a product of the reference value and the second parameter,
The third DA converter receives the second parameter as the digital value, receives the reference value as the reference value, and outputs a product of the second parameter and the reference value.
The second DA converter receives the first parameter as the digital value, receives the reference value as the reference value, and outputs a product of the first parameter and the reference value.
The first DA converter receives the control value as the digital value, and receives the product of the second parameter and the reference value output from the third DA converter as the reference value, and the control value And the product of the second parameter and the reference value are output,
The oscillator is controlled based on a sum of a product of the control value, the second parameter, and the reference value and a product of the first parameter and the reference value. 9. The current output type DA converter according to claim 8, wherein each of the first, second, and third DA converters outputs a current value corresponding to a product of a digital value and a reference value input to each of the first, second, and third DA converters. Yes,
The oscillator frequency is controlled based on a sum of a current value of a product of the control value, the second parameter, and the reference value, and a current value of a product of the first parameter and the reference value . The oscillator according to claim 1, comprising a coarse adjustment capacitor bank, a fine adjustment capacitor bank, and a DA converter.
The coarse adjustment capacitor bank includes a plurality of capacitance elements and a plurality of coarse adjustment switches, and controls the plurality of coarse adjustment switches to increase or decrease the number of capacitive elements connected based on the intercept value. The capacity value of the entire coarse adjustment capacity bank is controlled,
The fine adjustment capacitor bank includes a plurality of variable capacitance elements whose capacitance values are adjusted by an applied voltage and a plurality of fine adjustment switches, and a variable capacitance connected by controlling the plurality of fine adjustment switches based on the control value. By increasing or decreasing the number of elements, the capacitance value of the entire fine adjustment capacitor bank is controlled,
The DA converter converts the slope value into an analog voltage and applies the analog voltage to the plurality of variable capacitance elements.   11. The oscillator according to claim 10, further comprising a correction table that corrects the value of the slope and inputs the value to the DA converter based on a capacitance value characteristic with respect to an applied voltage of the variable capacitance element.   11. The oscillator according to claim 10, wherein the DA converter has a characteristic that compensates a characteristic of a capacitance with respect to an applied voltage of the variable capacitance element between an input digital value and an output voltage. The DA converter according to claim 8, wherein each of the first, second, and third DA converters outputs an analog value corresponding to a product of a digital value and a reference value input to each of the DA converter,
The oscillator is controlled based on a voltage value corresponding to a sum of a product of the control value, the second parameter, and the reference value and a product of the first parameter and the reference value.   2. The analog value is input as the control value in claim 1, the intercept is defined based on a first parameter, the slope is defined based on the second parameter, and the oscillation frequency is calculated using the control value and the control value. An oscillator controlled based on a sum of a product of a second parameter and the first parameter.   9. The oscillator according to claim 8, further comprising a gain adjusting unit that adjusts an output of at least one of the first, second, and third DA converters.   9. The oscillator according to claim 8, further comprising a gain adjustment unit that adjusts the reference value input to at least one DA converter among the first, second, and third DA converters.

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