JP2016018026A - Production method of semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve problems that: in an optical lithography process, as correction to dimension change due to etching, an etching bias is added according to a gap between an object mask pattern and a proximate mask pattern; but, when the object pattern is a gate electrode, when a proximate pattern is arranged in the vicinity of a boundary of an active area, a bias start point is set inside the active area; and at the time, a step is formed on a contour of the mask pattern, and during exposure, an effect of rounding from the step spreads to the active area, resulting in variation of the gate dimension.SOLUTION: The summary of the present invention relates to a lithography step or the like in a production process of a semiconductor integrated circuit device, in which, when data on an optical mask used in gate electrode patterning is created, in a certain range from the boundary of the active area, a bias correction step is prevented from occurring on a gate electrode pattern on which etching bias correction is performed.SELECTED DRAWING: Figure 8

Description

  The present application relates to a method of manufacturing a semiconductor integrated circuit device (or a semiconductor device), and can be applied to, for example, a mask pattern technique for an optical mask and a pattern data creation technique for an optical mask.

  Japanese Unexamined Patent Publication No. 2001-100390 (Patent Document 1) relates to an OPC (Optical Proximity Correction) technique for exposure mask data. If there is another mask figure close to one mask figure, the correction amount for the one mask figure changes stepwise along the side, so that a step is formed in the mask figure. . If this step exists in relation to a fine figure such as an auxiliary pattern, it will adversely affect mask fabrication and defect inspection. Therefore, the auxiliary pattern related to the step may be resized to eliminate the step, or It is disclosed to take a distance from.

JP 2001-100390 A

  In a photolithographic process of a semiconductor integrated circuit device, a correction value corresponding to a distance between a target mask pattern (target pattern) and another mask pattern (proximity pattern) adjacent to the target mask pattern as a correction for a dimensional change due to an etching process Is obtained from a reference table, and an etching bias is applied based on the obtained information.

  In this etching bias correction, in general, a positive etching bias is applied except for a certain range close to each other so that the target pattern and the proximity pattern are not too close as a result of the correction. Yes.

  However, when the target pattern is a gate electrode, if a proximity pattern is placed near the boundary of the active region, a bias start point may be set inside or near the boundary of the active region. Becomes higher. In such a case, a step is formed in the contour of the mask pattern in that portion, and the influence of the rounding from this step spreads to the surrounding active region at the time of exposure, and device characteristics such as variations in gate dimensions May cause deterioration.

  Means for solving such problems will be described below, but other problems and novel features will become apparent from the description of the present specification and the accompanying drawings.

  An outline of representative ones of the embodiments disclosed in the present application will be briefly described as follows.

  In other words, an outline of one embodiment of the present application is that, within a certain range from the boundary of the active region, when creating data of an optical mask used for patterning a gate electrode, in relation to a lithography process in the manufacturing process of a semiconductor integrated circuit device, etc. This is to prevent a bias correction step from occurring in the gate electrode pattern subjected to etching bias correction.

  The effects obtained by the representative ones of the embodiments disclosed in the present application will be briefly described as follows.

  That is, according to the embodiment of the present application, it is possible to reduce variations in gate electrode pattern dimensions and the like.

FIG. 3 is a schematic layout diagram of a chip area and the like on a wafer for explaining an outline of lithography processing and the like in a manufacturing method (basic example) of a semiconductor integrated circuit device according to an embodiment of the present application. It is a typical sectional view of an immersion reduction projection exposure apparatus at the time of exposure showing an outline of an exposure processing method in the lithography processing of the manufacturing method (basic example) of the semiconductor integrated circuit device of the one embodiment of the present application. FIG. 5 is a software creation processing block flow diagram for explaining an outline of a manufacturing procedure of proximity effect correction software in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. It is a block flow diagram of proximity effect correction processing for explaining the outline of the proximity effect correction process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. FIG. 5 is a detailed block flow diagram of the etching bias processing step of FIG. 4. In the process of explaining the mask data creation process (basic example: step removal etching bias correction by adding a positive value addition correction) and the like in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present invention (loading design data) FIG. 4 is a device top view (at the time) of a device layout by superimposing related mask data (the same applies hereinafter). In the processing step (initial etching bias) for explaining a mask data creation step (basic example: step removal etching bias correction by adding a positive value addition correction) and the like in the manufacturing method of the semiconductor integrated circuit device of the one embodiment of the present application It is a device top view (on mask) of a correction addition step. During the processing step (additional etching bias) for explaining the mask data creation step (basic example: step removal etching bias correction by adding a positive value additional correction) in the manufacturing method of the semiconductor integrated circuit device of the embodiment of the present application It is a device top view (on mask) of a correction process. During the processing steps for explaining the mask data creation step (basic example: step removal etching bias correction by adding positive value addition correction) and the like in the manufacturing method of the semiconductor integrated circuit device according to the embodiment of the present application (optical proximity effect) It is a device top view (on mask) of a correction process. During the processing step (exposure step) for explaining the mask data creation step (basic example: step removal etching bias correction by adding a positive value addition correction) in the manufacturing method of the semiconductor integrated circuit device of the embodiment of the present application. It is a device top view (on a wafer). During the processing step (etching step) for explaining the mask data creation step (basic example: step removal etching bias correction by adding a positive value addition correction) and the like in the manufacturing method of the semiconductor integrated circuit device of the one embodiment of the present application It is a device top view (on a wafer). Corresponding to FIG. 5 for explaining Modification 1 (step removal by adding a positive value correction & minimum interval ensuring processing etching bias correction) related to the etching bias correction of the manufacturing method of the semiconductor integrated circuit device according to the embodiment of the present invention. FIG. 5 is a detailed block flow diagram of the etching bias processing step of FIG. Corresponding to FIG. 6 for explaining Modification 1 (step removal by adding a positive value correction and minimum interval ensuring processing etching bias correction) related to the etching bias correction of the manufacturing method of the semiconductor integrated circuit device of the one embodiment of the present application. It is a device top view (on a mask) during a processing step (design data reading time). Corresponding to FIG. 7 for explaining Modification Example 1 (Step Removal by Adding Positive Value Correction and Minimum Interval Securing Etching Bias Correction) of Etching Bias Correction in the Manufacturing Method of Semiconductor Integrated Circuit Device of One Embodiment of the Present Application It is a device top view (on a mask) during a processing step (initial etching bias correction adding step). Corresponding to FIG. 8 for explaining Modification 1 (etching step correction by adding a positive value correction & minimum gap ensuring processing etching bias correction) related to etching bias correction of the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. It is a device top view (on a mask) during a processing step (additional etching bias correction step). During the processing steps for explaining a modification 1 (step removal by adding a positive value correction & minimum interval ensuring processing etching bias correction) related to the etching bias correction of the manufacturing method of the semiconductor integrated circuit device of the one embodiment of the present application ( It is a device top view (on mask) of a secondary etching bias correction step. Corresponding to FIG. 9 for explaining a modification 1 (step removal by adding a positive value correction & minimum interval ensuring processing etching bias correction) related to the etching bias correction of the manufacturing method of the semiconductor integrated circuit device of the embodiment of the present application. It is a device top view (on a mask) during a processing step (optical proximity effect correction step). Corresponding to FIG. 10 for explaining the first modification (etching step correction by adding a positive value correction & minimum interval ensuring processing etching bias correction) related to the etching bias correction of the manufacturing method of the semiconductor integrated circuit device of the one embodiment of the present application. It is a device top view (on a wafer) in a processing step (exposure step) to be performed. Corresponding to FIG. 11 for explaining Modification 1 (etching step correction by adding a positive value correction & minimum interval ensuring processing etching bias correction) relating to the etching bias correction of the manufacturing method of the semiconductor integrated circuit device of the one embodiment of the present application. It is a device top view (on a wafer) during a processing step (etching step). Etching bias process of FIG. 4 corresponding to FIG. 5 for explaining the modification 2 (step removal etching bias correction by the initial correction removal) related to the etching bias correction of the manufacturing method of the semiconductor integrated circuit device of the one embodiment of the present application. It is a detailed block flow diagram of a process. FIG. 6 is a process diagram corresponding to FIG. 6 (design data) for explaining a modification example 2 (step removal etching bias correction by initial correction removal) related to the etching bias correction of the manufacturing method of the semiconductor integrated circuit device of the embodiment of the present application. It is a device top view (on a mask) at the time of reading). During the processing step corresponding to FIG. 7 (initial etching) for explaining the modification 2 (step removal etching bias correction by the initial correction removal) of the etching bias correction of the manufacturing method of the semiconductor integrated circuit device of the one embodiment of the present application. It is a device top view (on mask) of a bias correction adding step). During the processing step corresponding to FIG. 8 (additional etching) for explaining the modification 2 (step removal etching bias correction by initial correction removal) of the etching bias correction of the manufacturing method of the semiconductor integrated circuit device of the one embodiment of the present application. It is a device top view (on mask) of a bias correction step). During the processing step corresponding to FIG. 9 for explaining the modification 2 (step removal etching bias correction by the initial correction removal) regarding the etching bias correction of the manufacturing method of the semiconductor integrated circuit device of the one embodiment of the present application (optical proximity) It is a device top view (on mask) of an effect correction process. During the processing step corresponding to FIG. 10 (exposure step) for explaining the modification 2 (step removal etching bias correction by the initial correction removal) related to the etching bias correction of the manufacturing method of the semiconductor integrated circuit device of the one embodiment of the present application. 2 is a device top view (on the wafer) of FIG. During the processing step corresponding to FIG. 11 (etching step) for explaining a modification example 2 (step removal etching bias correction by initial correction removal) related to the etching bias correction of the manufacturing method of the semiconductor integrated circuit device of the one embodiment of the present application. 2 is a device top view (on the wafer) of FIG. FIG. 25 is a conceptual explanatory diagram corresponding to FIG. 8 (FIGS. 15 and 23) and the like for describing the outline and the like of the method for manufacturing the semiconductor integrated circuit device of the embodiment of the present application.

[Outline of Embodiment]
First, an outline of a typical embodiment disclosed in the present application will be described.

1. A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) generating mask data based on the design data;
(B) preparing an optical mask having a mask pattern based on the mask data;
(C) forming an integrated circuit pattern on a semiconductor wafer by reducing projection exposure with ultraviolet exposure light using the optical mask;
Here, the step (a) includes the following substeps:
(A1) In the design data, a first gate electrode layer pattern that traverses the active region and a second gate electrode layer pattern that is on the inactive region and is close to the first gate electrode layer pattern Performing a primary etching bias correction,
At this time, an etching bias correction step is prevented from occurring in the first gate electrode layer pattern after the primary correction within a predetermined distance on both sides from the boundary of the active region.

  2. In the method of manufacturing a semiconductor integrated circuit device according to Item 1, in the step (c), when the predetermined distance range is the etching bias correction step at the boundary of the active region, This is a range affected by the etching bias correction step.

  3. In the method of manufacturing a semiconductor integrated circuit device according to the item 2, the range affected by the etching bias correction step is about half the wavelength of the ultraviolet exposure light on both sides from the boundary of the active region. is there.

  4). 4. In the method of manufacturing a semiconductor integrated circuit device according to any one of Items 1 to 3, the first gate electrode layer pattern after the primary correction is opposed to the second gate electrode layer pattern. The positive primary etching bias correction is performed within the predetermined distance on both sides of the active region.

5). 4. The method for manufacturing a semiconductor integrated circuit device according to any one of Items 1 to 3, wherein the step (a) further includes the following substeps:
(A2) After the step (a1), when the interval between the first gate electrode layer pattern after the primary correction and the second gate electrode layer pattern is less than a predetermined minimum interval, Performing a negative secondary etching bias correction on the second gate electrode layer pattern so that the interval is equal to or greater than the predetermined minimum interval.

  6). 4. In the method of manufacturing a semiconductor integrated circuit device according to any one of Items 1 to 3, the first gate electrode layer pattern after the primary correction is opposed to the second gate electrode layer pattern. The primary etching bias correction is not performed within the predetermined distance on both sides of the active region.

7). 6. The method for manufacturing a semiconductor integrated circuit device according to any one of Items 1 to 5, wherein the step (a1) includes the following substeps:
(A11) Positive initial etching bias correction for a portion of the first gate electrode layer pattern before the primary correction excluding a predetermined proximity range on the side facing the second gate electrode layer pattern Applying
(A12) A step of performing positive additional etching bias correction so that the etching bias correction step disappears with respect to the predetermined proximity range after the step (a11).

  8). 8. The method of manufacturing a semiconductor integrated circuit device according to any one of Items 1 to 7, wherein the first gate electrode layer pattern is opposed to the second gate electrode layer pattern after the primary correction. A positive initial etching bias correction is applied to a portion excluding the predetermined proximity range on the side.

[Description format, basic terms, usage in this application]
1. In the present application, the description of the embodiment may be divided into a plurality of sections for convenience, if necessary, but these are not independent from each other unless otherwise specified. Each part of a single example, one part is the other part of the details, or part or all of the modifications. Moreover, as a general rule, the same part is not repeated. In addition, each component in the embodiment is not indispensable unless specifically stated otherwise, unless it is theoretically limited to the number, and obviously not in context.

  Further, in the present application, the term “semiconductor device” or “semiconductor integrated circuit device” mainly refers to various types of transistors (active elements) alone, and resistors, capacitors, etc. as semiconductor chips (eg, single crystal). A silicon substrate) or a semiconductor chip packaged. Here, as a representative of various transistors, a MISFET (Metal Insulator Semiconductor Effect Transistor) typified by a MOSFET (Metal Oxide Field Effect Transistor) can be exemplified. At this time, as a typical integrated circuit configuration, a CMIS (Complementary Metal Insulator Semiconductor) integrated circuit represented by a CMOS (Complementary Metal Oxide Semiconductor) integrated circuit combining an N-channel MISFET and a P-channel MISFET. Can be illustrated.

  The wafer process of today's semiconductor integrated circuit device, that is, LSI (Large Scale Integration), is usually considered in two parts. That is, the first consists of carrying in a silicon wafer as a raw material to a premetal process (formation of an interlayer insulation film between the lower end of the M1 wiring layer and the gate electrode structure, contact hole formation, tungsten plug, embedding, etc. This is a FEOL (Front End of Line) process. The second is BEOL (Back End of Line) starting from the formation of the M1 wiring layer until the formation of the pad opening in the final passivation film on the aluminum-based pad electrode (including the process in the wafer level package process). It is a process.

  2. Similarly, in the description of the embodiment and the like, the material, composition, etc. may be referred to as “X consisting of A”, etc., except when clearly stated otherwise and clearly from the context, except for A It does not exclude what makes an element one of the main components. For example, as for the component, it means “X containing A as a main component”. For example, “silicon member” is not limited to pure silicon, but also includes SiGe alloys, other multi-component alloys containing silicon as a main component, and members containing other additives. Needless to say.

  Similarly, “silicon oxide film”, “silicon oxide insulating film” and the like are not only relatively pure undoped silicon oxide but also other silicon oxide as main components. Including membrane. For example, a silicon oxide insulating film doped with impurities such as TEOS-based silicon oxide (TEOS-based silicon oxide), PSG (phosphorus silicon glass), BPSG (borophosphosilicate glass) is also a silicon oxide film. In addition to a thermal oxide film and a CVD oxide film, a coating system film such as SOG (Spin On Glass) or nano-clustering silica (NSC) is also a silicon oxide film or a silicon oxide insulating film. In addition, a low-k insulating film such as FSG (Fluorosilicate Glass), SiOC (Silicon Oxide silicide), carbon-doped silicon oxide (OSD), or OSG (Organosilicate Glass) is similarly used. It is a membrane. Further, a silica-based Low-k insulating film (porous insulating film, including “porous” or “porous”) including a hole in a member similar to these is also a silicon oxide film or silicon oxide. It is a system insulating film.

  In addition to silicon oxide insulating films, silicon nitride insulating films that are commonly used in the semiconductor field include silicon nitride insulating films. Materials belonging to this system include SiN, SiCN, SiNH, SiCNH, and the like. Here, “silicon nitride” includes both SiN and SiNH unless otherwise specified. Similarly, “SiCN” includes both SiCN and SiCNH, unless otherwise specified.

  Although SiC has similar properties to SiN, SiON (SiOC, SiOCN) should rather be classified as a silicon oxide insulating film, but it is often used as an etch stop film or a reference light reflection promoting film. Is close to SiC, SiN or the like. Therefore, the classification of these oxides and nitrides (carbides, carbonitrides) is classified according to the main factorization.

  A silicon nitride insulating film such as a silicon nitride film is frequently used as an etch stop film in SAC (Self-Aligned Contact) technology, that is, CESL (Contact Etch-Stop Layer), and stress in SMT (Stress Memory Technique). Also used as an application film.

  3. “Wafer” usually refers to a single crystal silicon wafer on which a semiconductor integrated circuit device (same as a semiconductor device and an electronic device) is formed, but an insulating substrate such as an epitaxial wafer, an SOI substrate, an LCD glass substrate and the like. Needless to say, a composite wafer such as a semiconductor layer is also included.

  4). The figure, position, attribute, and the like are preferably illustrated, but it is needless to say that the present invention is not strictly limited to this unless it is clearly indicated otherwise and the context clearly does not. Therefore, for example, “square” includes a substantially square, “orthogonal” includes a case where the two are substantially orthogonal, and “match” includes a case where the two substantially match. The same applies to “parallel” and “right angle”. Therefore, for example, a deviation of about 10 degrees from perfect parallel belongs to parallel.

  In addition, for a certain region, “whole”, “whole”, “whole area”, and the like include cases of “substantially whole”, “substantially general”, “substantially whole area”, and the like. Therefore, for example, 80% or more of a certain area can be referred to as “whole”, “whole”, and “whole area”. The same applies to “all circumferences”, “full lengths”, and the like.

  Further, regarding the shape of a certain object, “rectangular” includes “substantially rectangular”. Therefore, for example, if the area of the portion different from the rectangle is less than about 20% of the whole, it can be said to be a rectangle. In this case, the same applies to “annular” and the like. In this case, when the annular body is divided, a portion obtained by interpolating or extrapolating the divided element portion is a part of the annular body.

  Also, with regard to periodicity, “periodic” includes almost periodic, and for each element, for example, if the deviation of the period is less than about 20%, each element can be said to be “periodic”. . Furthermore, if what is out of this range is, for example, less than about 20% of all the elements to be periodic, it can be said to be “periodic” as a whole.

  Note that the definitions in this section are general, and when there are different definitions in the following individual descriptions, priority is given to the individual descriptions for this part. However, the definition, provisions, etc. of this section are still valid for parts that are not stipulated in the individual description part, unless explicitly denied.

  5. In addition, when a specific number or quantity is mentioned, a numerical value exceeding that specific number will be used unless specifically stated otherwise, unless theoretically limited to that number, or unless otherwise clearly indicated by the context. There may be a numerical value less than the specific numerical value.

  6). In this application, references to “range”, “distance”, etc. are on the wafer (not on the enlarged mask) unless otherwise specified and apparently not in context. Shall be referred to.

  In the present application, the term “exposure light” refers to monochromatic light having a wavelength of 193 nm from an ArF excimer laser, unless otherwise specified and clearly not from the context.

  In the attached drawings and the like, when (1) device layout (mask layout) on data, (2) device layout on wafer or (3) mask pattern layout on mask is shown, it is related as necessary. By overlapping the pattern layers, the device layout can be understood. For convenience of explanation, the same figure may correspond to a plurality of items (1) to (3).

  Similarly, in the present application, for convenience of description and explanation, with regard to layout data, mask data, etc., the process of handling it, the process of reading it, the process of outputting it, and the data itself are represented by the same figure and reference number. May be displayed.

  Further, in the present application, for convenience of description and explanation, the exposure optical system and the exposure method using the exposure optical system may be indicated by the same figure and reference number.

  Further, in the present application, for convenience of description and explanation, a device pattern (including a part thereof) formed by patterning a certain device layer and the device layer that is the basis thereof are displayed in the same figure on the drawing. Sometimes.

  The proximity effect correction is mainly composed of a non-optical contact effect correction part such as an etching bias correction and an optical proximity effect correction part, but the current optical proximity effect correction is very complicated, If it is described as it is, there is a risk that the description of the etching bias correction, which is the main object of the present application, may be hindered. Therefore, the optical proximity effect correction portion is illustrated in a simplified manner.

[Details of the embodiment]
The embodiment will be further described in detail. In the drawings, the same or similar parts are denoted by the same or similar symbols or reference numerals, and description thereof will not be repeated in principle.

  In the accompanying drawings, hatching or the like may be omitted even in a cross section when it becomes complicated or when the distinction from the gap is clear. In relation to this, when it is clear from the description etc., the contour line of the background may be omitted even if the hole is planarly closed. Furthermore, even if it is not a cross section, it may be hatched to clearly indicate that it is not a void.

  In addition, regarding the designation in the case of the alternative, when one is referred to as “first” or the like and the other is referred to as “second” or the like, it is exemplified in association with the representative embodiment. Of course, for example, “first” is not limited to the illustrated option.

1. Description of Outline of Lithographic Processing in Manufacturing Method (Basic Example) of Semiconductor Integrated Circuit Device of One Embodiment of the Present Application (Mainly FIGS. 1 and 2)
Hereinafter, the 55 nm generation will be specifically described as an example of the CMIS integrated circuit device, but it goes without saying that other generation devices may be used.

  In the following, as an example of a reduction projection exposure apparatus, a reduction projection exposure apparatus such as a step & scan system (for example, 4: 1 reduction) is simplified and its structure is schematically displayed. ,explain. However, the exposure method for the entire wafer is not limited to the step & scan method, and may be a step exposure method, and the medium between the wafer and the projection optical system is not limited to liquid but may be gas. Further, the reduction ratio may be other than 4: 1 reduction. Compared with the non-immersion exposure method, the immersion exposure method has an advantage that the resolution can be improved only by replacing the immersion liquid 63 (FIG. 2).

  Further, the exposure light will be specifically described by taking monochromatic light with a wavelength of 193 nm from an ArF excimer laser as an example, but it is needless to say that exposure light with other wavelengths from other light sources may be used.

  FIG. 1 is a schematic layout diagram of chip regions on a wafer for explaining an outline of lithography processing and the like in a manufacturing method (basic example) of a semiconductor integrated circuit device according to an embodiment of the present application. FIG. 2 is a schematic cross-sectional view of an immersion reduction projection exposure apparatus at the time of exposure showing an outline of the exposure process method in the lithography process of the manufacturing method (basic example) of the semiconductor integrated circuit device according to the embodiment of the present application. . Based on these, the outline of the lithography process in the manufacturing method (basic example) of the semiconductor integrated circuit device according to the embodiment of the present application will be described.

  As shown in FIG. 1, a large number of chip regions 2 are formed in a matrix on a surface 1a (first main surface) of a semiconductor wafer 1 (for example, a silicon wafer). In the chip region 2, an integrated circuit pattern forming region 8 in which a large number of MISFETs and the like are formed is provided.

  Next, an example of the light exposure process will be described with reference to FIG. As shown in FIG. 2, for example, exposure light 57 from an exposure light source 61 such as an ArF excimer laser passes through an optical mask 59 along a light source optical system 62 along an optical axis 56, and is exposed to an exposure optical system 58 ( The reduced projection optical system) is projected onto the surface 1a (first main surface) of the wafer 1 placed on the wafer stage 51 through the immersion liquid 63.

2. Description of outline of manufacturing procedure of proximity effect correction software in manufacturing method of semiconductor integrated circuit device of one embodiment of the present application (mainly FIG. 3)
In this section, as an example of proximity effect correction software, an example of integrated proximity effect correction software that integrates basic model-based OPC software and etching correction software will be described as an example. Needless to say, they may be individually divided or appropriately integrated.

  FIG. 3 is a software creation processing block flow diagram for explaining the outline of the production procedure of proximity effect correction software in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. Based on this, an outline of a procedure for producing proximity effect correction software in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application will be described.

  FIG. 3 shows an outline of a process for creating integrated proximity effect correction software as an example of proximity effect correction software. As shown in FIG. 3, first, the manufacturing process of the semiconductor integrated circuit device is determined (process determination step 101). Next, for example, a TEG (Test Element Group) for determining an exposure & resist model, an etching correction amount, and the like is created. Next, for example, exposure & resist data and etching data are acquired by this TEG or the like (exposure and etching data acquisition step 102). Next, for example, an exposure & resist model is created from the acquired exposure & resist data (model creation step 104). Next, for example, an etching correction table is created from the acquired etching data (bias table creation step 103). Next, for example, an exposure & resist model, a basic etching correction table, and additional etching correction are incorporated into the integrated software (integrated software before verification) (table and model incorporating step 105). Next, for example, various verifications are performed on the pre-verification integrated software (verification step 106).

  As one of the verifications, for example, a verification mask is created by pre-verification integrated software, and exposure and etching are performed using the verification mask to perform exposure and etching evaluation (verification mask creation, exposure and etching). Etching evaluation step 106a). As another verification, for example, a simulation is performed using the mask data generated by the pre-verification integrated software (lithography simulation step 106b). As yet another verification, for example, the operation of the integrated software before verification as a whole is verified (software verification step 106c).

  After these verifications have been completed, necessary parameters have been corrected, bugs, etc. have been removed, the final integrated software is output (process & optical proximity effect correction software completion 107). Used to generate mask data.

3. Description of outline of proximity effect correction process in manufacturing method of semiconductor integrated circuit device according to one embodiment of the present application (mainly FIGS. 4 and 5)
In this section, in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application, a process of creating mask data from design data, particularly a proximity effect correction process, will be described focusing on an etching bias correction process. This proximity effect correction step is executed using, for example, the integrated software described in section 2.

  FIG. 4 is a block flow diagram of proximity effect correction processing for explaining the outline of the proximity effect correction process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. FIG. 5 is a detailed block flow diagram of the etching bias processing step of FIG. Based on these, the outline of the proximity effect correction process in the manufacturing method of the semiconductor integrated circuit device according to the embodiment of the present application will be described.

  The outline of the proximity effect correction process is as follows. As shown in FIG. 4, first, the original design data 121 is read (design data reading step). Next, etching bias correction is executed based on a bias table or the like (etching bias correction step 122). Next, optical proximity effect correction is performed on the design data 121 subjected to etching bias correction (optical proximity effect correction step 124). Thereafter, the design data 121 subjected to the optical proximity effect correction, that is, the mask data 125 is output (mask data output process).

  Next, FIG. 5 shows an example of the details of the etching bias correction step 122 of FIG. 4 (in the specific example described in the next section, the primary etching bias correction step 123a). As shown in FIG. 5, an initial etching bias correction step 122a for adding initial etching bias correction (usually adding a positive correction) to the original design data 121 based on, for example, a bias table. Execute.

  Next, an active region crossing edge extraction step 122ba is performed for extracting the edge of the device pattern figure that crosses the active region subjected to the initial etching bias correction. Next, a boundary proximity step edge extraction step 122bb is executed to extract an edge having a step due to a bias within a certain range from the boundary of the active region from the extracted edges. In other words, edges that are at a certain distance in and out of the active region boundary and that have a step due to bias are extracted.

  Next, the same height bias adding step 122bc for adding a bias having the same height as the step to the extracted edge having the step is executed. That is, by applying a bias having the same height as the step to the extracted edge, the step of the edge at that portion is removed.

  Thus, in this example (for example, the specific example described in Section 4), the additional etching bias correction step is performed by the active region crossing edge extraction step 122ba, the boundary proximity step edge extraction step 122bb, and the same height bias addition step 122bc. 122b is configured.

  As described above, the etching bias correction step 122 is composed of the initial etching bias correction step 122a, the additional etching bias correction step 122b, and the like. Therefore, a widely used etching bias correction method (software, hardware resources, etc.) is used. Including) can be used as it is.

4). Description of mask data creation step (basic example: step removal etching bias correction by adding positive value addition correction) and manufacturing process main parts in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present invention (mainly FIG. 6) To FIG. 11 (see FIG. 1, FIG. 2, FIG. 4, FIG. 5, FIG. 27, etc.)
In this section, a specific example of the proximity effect correction process described in section 3 and a specific device of the integrated circuit pattern formation region partial cutout portion R1 in FIG. 1 in the case where the lithography process is performed using the optical mask formed thereby. A layout will be described as an example.

  FIG. 6 is a process diagram for explaining a mask data creation process (basic example: step removal etching bias correction by adding a positive value addition correction) and the like in the method for manufacturing a semiconductor integrated circuit device according to the embodiment of the present invention ( It is a device top view (at the time of design data reading) (relevant mask data is overlaid to form a device layout; the same applies hereinafter). FIG. 7 illustrates a process for explaining a mask data creation process (basic example: step removal etching bias correction by adding a positive value addition correction) and the like in the manufacturing method of the semiconductor integrated circuit device according to the embodiment of the present invention ( It is a device top view (on a mask) of an initial etching bias correction adding step). FIG. 8 illustrates a process for explaining a mask data creation process (basic example: step removal etching bias correction by adding a positive value addition correction) and the like in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present invention ( It is a device top view (on mask) of an additional etching bias correction step. FIG. 9 is a processing step for explaining a mask data creation step (basic example: step removal etching bias correction by adding a positive value additional correction) and the like in the manufacturing method of the semiconductor integrated circuit device according to the embodiment of the present invention ( It is a device top view (on mask) of the optical proximity effect correction step. FIG. 10 is a processing step for explaining a mask data creation step (basic example: step removal etching bias correction by adding a positive value addition correction) and the like in the manufacturing method of the semiconductor integrated circuit device according to the embodiment of the present invention ( It is a device top view (on a wafer) of an exposure step). FIG. 11 illustrates a process for explaining a mask data generation process (basic example: step removal etching bias correction by adding a positive value addition correction) and the like in the manufacturing method of the semiconductor integrated circuit device according to the embodiment of the present invention ( It is a device top view (on a wafer) of an etching process. Based on these, the mask data creation step (basic example: step removal etching bias correction by adding a positive value addition correction) and the main part of the manufacturing process will be described in the manufacturing method of the semiconductor integrated circuit device according to the embodiment of the present application. To do.

  An example of a specific layout of the design data 121 (FIG. 4) corresponding to the integrated circuit pattern formation region partial cutout portion R1 of FIG. 1 is shown in FIG. As shown in FIG. 6, an active region 3 for forming a MISFET is provided in the central portion, and the periphery thereof is an inactive region 4 with a boundary 3 b interposed therebetween. The inactive region 4 is a so-called field insulating film region, for example, an STI (Shallow Trench Isolation) region.

  A gate electrode pattern 5 (first gate electrode layer pattern) composed of, for example, a gate electrode layer 10 (for example, a polysilicon layer) is provided so as to traverse or traverse the active region 3. That is, the gate electrode pattern 5 traverses the active region.

  On the inactive region 4, another gate electrode pattern or a gate electrode layer wiring pattern 6 (second gate electrode layer pattern) is provided in the vicinity of the gate electrode pattern 5. That is, the adjacent gate electrode layer wiring pattern 6. As for the process layer, the integrated circuit pattern 7 is constituted by the gate electrode pattern 5, the gate electrode layer wiring pattern 6, and the like in this way.

  In this example, the width Lg (or gate length) of the gate electrode is about 55 nm, for example, and the width Wa (or gate width) of the active region 3 is about 200 nm or more, for example. The lower limit value of the width Wa of the active region 3 is, for example, the same length as the exposure wavelength (FIG. 2) or slightly longer. The above state corresponds to the design data reading step 121 in FIG.

  Next, FIG. 7 shows a state where the initial etching bias correction step 122a of FIG. 5 is completed. As shown in FIG. 7, initial etching bias correction is performed on the edge of the device figure, that is, the periphery (side) of the gate electrode pattern 5a and the gate electrode layer wiring pattern 6a before the primary etching bias correction, and as a result, An initial etching bias correction unit 11a is added. Thereby, the gate electrode pattern 5 across the active region and the gate electrode pattern or gate electrode layer wiring pattern 6 on the inactive region after the initial etching bias correction are formed.

  However, in order not to create a narrow space exceeding the allowable limit, the portion F1 facing the adjacent figure 6 and the edge of the gate electrode pattern 5a within a certain range D1 from the end of this portion are subject to initial etching bias correction. Excluded from. This fixed range D1 (distance from the boundary) corresponds to, for example, the distance that the proximity effect related to etching extends in the lateral direction from the end of the proximity graphic. Specifically, in this example, the distance D1 is, for example, about 35 nm (a preferable range is, for example, about 20 to 50 nm). The lower limit of the range of the distance D1 is, for example, a distance slightly shorter than half of the gate length (about 55 nm), and the upper limit is, for example, a distance slightly shorter than the gate length.

  Since this also applies to the proximity graphic 6, the portion F2 (including the portion corresponding to the predetermined range D1) facing the gate electrode pattern 5a is also excluded from the initial etching bias correction target. As described above, since the initial etching bias correction is simultaneously applied to the adjacent device pattern figure, it is effective for ensuring the dimensional accuracy of the device portion.

  Next, the active region crossing edge extraction step 122ba of FIG. 5 will be described with reference to FIG. As shown in FIG. 7, only the gate electrode pattern 5 crosses the active region 3 in the device figure of the gate electrode layer 10 that is the target layer. That is, in the active region crossing edge extraction step 122ba, all edges (all circumferences) of the gate electrode pattern 5 are extracted.

  Next, the boundary proximity step edge extraction step 122bb of FIG. 5 will be described with reference to FIG. As shown in FIG. 7, in the boundary proximity step edge extraction step 122bb, the distance B1 to the inside of the boundary 3b of the active region 3 and the distance B2 to the outside are extracted from the edges extracted in the active region crossing edge extraction step 122ba. The step 20a in the band-like region of the range (the region within the range of the predetermined distance) and the peripheral edge are extracted. Specifically, a portion (final extraction edge portion) from the step 20a to the end of the side is extracted from the edge of the gate electrode pattern 5. That is, there is a step 20 a having a height H in a region within a predetermined distance from the boundary 3 b of the active region 3. Note that the distance B1 and the distance B2 are distances that are affected by the step from the boundary of the active region to the inside or the outside during exposure when the step 3a is present at the boundary 3b of the active region 3. In this example, this distance is about 75 nm, for example (a preferable range is about 50 to 100 nm, for example). In other words, this distance is a distance in the range of about 1/4 to 1/2 of the exposure wavelength (FIG. 2). The range of the predetermined distance is set in this way because a step existing in such a range has a great influence on pattern accuracy in exposure or the like.

  As described above, in the state where there is the step 20a, there is a possibility that the influence of the rounding of the exposure pattern due to this step on the pattern sensitive portion in the vicinity of the boundary 3b of the active region 3 during the exposure. Therefore, in order to avoid this, in the same height bias adding step 122bc of FIG. 5, as shown in FIG. 8, a bias having the same height as the step 20a, that is, an additional etching bias correction is applied to the final extracted edge portion. The part 11b (additional etching bias correction) is added. Thereby, the etching bias correction step 122 of FIG. 4 is completed. As a result, the gate electrode pattern 5b (first gate electrode layer pattern) crossing the active region after the primary etching bias correction and the gate electrode pattern or gate electrode layer wiring pattern 6b on the non-active region after the primary etching bias correction. (Second gate electrode layer pattern) is obtained.

  Next, when the optical proximity effect correction step 124 of FIG. 4 is executed, as shown in FIG. 9, the mask patterns 5w and 6m after the etch bias correction include OP portions added by OPC, etc. (to be precise, there are deleted portions). ) Is added. Thereby, the optical proximity effect correction process 124 of FIG. 4 is completed, and the mask data 125 of FIG. 4 is output (mask data output process).

  When reduced projection exposure (for example, a reduction ratio of 4: 1) is executed using the created optical mask based on the mask data 125 output here, the result is as shown in FIG. That is, as shown in FIG. 10, projection images corresponding to the gate electrode patterns 5a and 6a, that is, exposure image patterns 5r and 6r are formed on the wafer 1 (specifically, on the photoresist film on the wafer). Is done. The photoresist film pattern obtained by developing the photoresist film substantially corresponds to these exposure image patterns 5r and 6r (in this case, although not essential, generally a positive resist film is assumed). .

  Next, when anisotropic dry etching or the like is performed using the developed photoresist film pattern or the like, as shown in FIG. 11, device patterns 5w after etching corresponding to the gate electrode patterns 5a and 6a, 6w is obtained.

  As described above, according to this example, the effect of the corner round at the time of exposure due to the step is reduced by moving the step due to the correction near the boundary of the active region away from the boundary of the active region. Can do.

  Further, according to this example, since the additional correction adds the same height correction as the initial correction, it has an advantage of high process consistency.

  Furthermore, since the correction step does not appear in the critical part of the etching of the device pattern figure that crosses the active region by the etching bias correction, it is possible to reduce the influence of the corner round at the time of exposure caused by the step, and as a result, Variations in device characteristics can be reduced.

5). Description of Modification Example 1 (Step Removal by Adding Additional Positive Value Correction and Minimum Interval Securing Etching Bias Correction) Regarding Etching Bias Correction in the Manufacturing Method of the Semiconductor Integrated Circuit Device According to the One Embodiment of the Present Application (Mainly FIG. 12 to FIG. 19)
In this section, FIG. 5 of the example described in section 1 to section 4, that is, modification 1 (etching correction for step difference & minimum interval ensuring processing etching bias correction by adding a positive value addition correction) relating to etching bias correction will be described. In the following description, only the parts different from those described in sections 1 to 4 will be described in principle.

  FIG. 12 is a diagram for explaining a modification 1 (step removal by adding a positive value correction and minimum gap ensuring processing etching bias correction) related to etching bias correction in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. 5 is a detailed block flow diagram of the etching bias processing step of FIG. 4 corresponding to FIG. FIG. 13 is a view for explaining a modification 1 (step removal by adding a positive value correction and minimum gap ensuring process etching bias correction) related to etching bias correction in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. 6 is a device top view (on the mask) during a processing step corresponding to 6 (at the time of design data reading). FIG. FIG. 14 is a diagram for explaining a modification 1 (step removal by adding a positive value correction and minimum interval ensuring processing etching bias correction) related to etching bias correction in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. 7 is a device top view (on the mask) during a processing step corresponding to 7 (initial etching bias correction adding step). FIG. FIG. 15 is a diagram for explaining a modification 1 (step removal by adding a positive value correction and minimum interval ensuring processing etching bias correction) related to etching bias correction in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present invention. 9 is a device top view (on the mask) during the processing step corresponding to FIG. 8 (additional etching bias correction step). FIG. FIG. 16 is a process for explaining a modification 1 (step removal by adding a positive value and adding a minimum gap and etching bias correction) related to etching bias correction in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present invention. It is a device top view (on a mask) in the process (secondary etching bias correction process). FIG. 17 is a diagram for explaining a modification 1 (step removal by adding a positive value correction and minimum gap ensuring process etching bias correction) related to etching bias correction in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. 9 is a device top view (on the mask) during the processing step corresponding to 9 (optical proximity effect correction step). FIG. FIG. 18 is a view for explaining a modification 1 (step removal by adding a positive value correction and minimum gap ensuring process etching bias correction) related to etching bias correction in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present invention. 10 is a device top view (on a wafer) during a processing step (exposure step) corresponding to FIG. FIG. 19 is a diagram for explaining a modification example 1 (step removal by adding a positive value correction and minimum interval ensuring processing etching bias correction) related to etching bias correction in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. 11 is a device top view (on the wafer) during a processing step (etching step) corresponding to FIG. Based on these, a first modification (etching step correction and minimum gap ensuring processing etching bias correction by adding a positive value addition correction) relating to the etching bias correction of the manufacturing method of the semiconductor integrated circuit device according to the embodiment of the present invention will be described.

  First, an overall outline of the etching bias correction of FIG. 12 corresponding to FIG. 5 will be described. In FIG. 12, since the primary etching bias correction step 123a is exactly the same as that in FIG. 5, the secondary etching bias correction step 123b will be described.

  As shown in FIG. 12, in the secondary etching bias correction step 123b, as a result of the primary etching bias correction step 123a, a gap S1 between device figures with a neighboring pattern among gate electrode patterns crossing the active region is predetermined. A fine interval extraction step 123ba for extracting a portion (edge) that is less than the minimum interval S2 is included as a first step. This extracted edge is referred to as an “over-close edge region”.

  Further, the secondary etching bias correction step 123b includes a fine enlargement extraction step 123bb that cuts the opposing edge of the proximity pattern that opposes the over-adjacent edge region and sets the interval S1 to the minimum interval S2 or more as a second step. .

  Next, as in FIGS. 6 to 11 in the previous section, a specific device layout of the integrated circuit pattern formation region partial cutout portion R1 in FIG. 1 will be described as an example.

  FIG. 13 shows an example of a specific layout of the design data 121 (FIG. 4) corresponding to the integrated circuit pattern formation region partial cutout portion R1 of FIG. As shown in FIG. 13, an active region 3 for forming a MISFET is provided in the upper portion, and the periphery thereof is an inactive region 4 with a boundary 3b interposed therebetween. The inactive region 4 is a so-called field insulating film region, for example, an STI region.

  A gate electrode pattern 5 (first gate electrode layer pattern) composed of, for example, a gate electrode layer 10 (for example, a polysilicon layer) is provided so as to traverse or traverse the active region 3. That is, the gate electrode pattern 5 traverses the active region.

  On the inactive region 4, another gate electrode pattern or a gate electrode layer wiring pattern 6 (second gate electrode layer pattern) is provided in the vicinity of the gate electrode pattern 5. That is, the adjacent gate electrode layer wiring pattern 6. As for the process layer, the integrated circuit pattern 7 is constituted by the gate electrode pattern 5, the gate electrode layer wiring pattern 6, and the like in this way.

  In this example, the width Lg (or gate length) of the gate electrode is about 55 nm, for example, and the width (or gate width) of the active region 3 is about 200 nm or more, for example. The lower limit value of the width of the active region 3 is, for example, the same length as the exposure wavelength (FIG. 2) or slightly longer. The above state corresponds to the design data reading step 121 in FIG.

  Next, FIG. 14 shows a state where the initial etching bias correction step 122a of FIG. 12 is completed. As shown in FIG. 14, initial etching bias correction is performed on the edge of the device figure, that is, the periphery (side) of the gate electrode pattern 5a and the gate electrode layer wiring pattern 6a before the primary etching bias correction, and as a result, An initial etching bias correction unit 11a is added. Thereby, the gate electrode pattern 5 across the active region and the gate electrode pattern or gate electrode layer wiring pattern 6 on the inactive region after the initial etching bias correction are formed.

  However, in order not to create a narrow space exceeding the allowable limit, the portion F1 facing the adjacent figure 6 and the edge of the gate electrode pattern 5a within a certain range D1 from the end of this portion are subject to initial etching bias correction. Excluded from. This fixed range D1 (distance from the boundary) corresponds to, for example, the distance that the proximity effect related to etching extends in the lateral direction from the end of the proximity graphic. Specifically, in this example, the distance D1 is, for example, about 35 nm (a preferable range is, for example, about 20 to 50 nm). The lower limit of the range of the distance D1 is, for example, a distance slightly shorter than half of the gate length (about 55 nm), and the upper limit is, for example, a distance slightly shorter than the gate length.

  Since this also applies to the proximity figure 6, the portion F2 facing the gate electrode pattern 5a (the portion corresponding to the predetermined range D1, that is, the distance D2 at which the proximity effect relating to etching extends from the end portion in the lateral direction). Are also excluded from the target of initial etching bias correction. By this process (initial etching bias correction), steps 20a and 20b are formed.

  Next, the active region crossing edge extraction step 122ba of FIG. 12 will be described with reference to FIG. As shown in FIG. 14, only the gate electrode pattern 5 crosses the active region 3 in the device figure of the gate electrode layer 10 that is the target layer. That is, in the active region crossing edge extraction step 122ba, all edges (all circumferences) of the gate electrode pattern 5 are extracted.

  Next, the boundary proximity step edge extraction step 122bb of FIG. 12 will be described with reference to FIG. As shown in FIG. 14, in the boundary proximity step edge extraction step 122bb, the distance B1 to the inside of the boundary 3b of the active region 3 and the distance B2 to the outside from the edges extracted in the active region crossing edge extraction step 122ba. A step 20a in the band-like region of the range (region of a predetermined distance range) and its peripheral edge are extracted. Specifically, a portion (final extraction edge portion) from the step 20a to the end of the side is extracted from the edge of the gate electrode pattern 5. That is, there is a step 20 a having a height H in a region within a predetermined distance from the boundary 3 b of the active region 3. Note that the distance B1 and the distance B2 are distances that are affected by the step from the boundary of the active region to the inside or the outside during exposure when the step 3a is present at the boundary 3b of the active region 3. In this example, this distance is about 75 nm, for example (a preferable range is about 50 to 100 nm, for example). In other words, this distance is a distance in the range of about 1/4 to 1/2 of the exposure wavelength (FIG. 2). Here, the gate electrode pattern 6 and the like 6 also has a step 20b, but is not a target because it does not relate to a device pattern figure that crosses the active region 3.

  As described above, in the state where there is the step 20a, there is a possibility that the influence of the rounding of the exposure pattern due to this step on the pattern sensitive portion in the vicinity of the boundary 3b of the active region 3 during the exposure. Therefore, in order to avoid this, in the same height bias adding step 122bc of FIG. 12, as shown in FIG. 15, a bias having the same height as the step 20a, that is, an additional etching bias correction is applied to the final extracted edge portion. The part 11b (additional etching bias correction) is added. Thus, the primary etching bias correction process 123a in FIG. 12 is completed. As a result, the gate electrode pattern 5b (first gate electrode layer pattern) crossing the active region after the primary etching bias correction and the gate electrode pattern or gate electrode layer wiring pattern 6b on the non-active region after the primary etching bias correction. (Second gate electrode layer pattern) is obtained.

  Next, the fine interval extracting step 123ba, which is the first step of the secondary etching bias correcting step 123b of FIG. 12, will be described with reference to FIGS. As shown in FIGS. 15 and 16, the space S1 between the edge of the gate electrode pattern 5b and the adjacent device pattern figure (gate electrode pattern 6b) after the primary etching bias correction is the minimum distance Edges smaller than S2 (predetermined minimum interval) are extracted.

  Next, the fine expansion extraction process 123bb, which is the second process of the secondary etching bias correction process 123b of FIG. 12, will be described with reference to FIG. As shown in FIG. 16, the edge of the gate electrode pattern 6b facing the edge extracted in the fine interval extraction step 123ba and the edge part belonging to the range of the distance D2 in FIG. The space is set to the minimum interval S2 (predetermined minimum interval) or more. That is, a secondary etching bias correction unit 12 (secondary etching bias correction) is added (negative value correction). As a result, the etching bias correction step 122 of FIG. 4 is completed.

  Next, when the optical proximity effect correction step 124 of FIG. 4 is executed, as shown in FIG. 17, the mask patterns 5w and 6m after the etch bias correction have OP portions added by OPC, etc. (to be precise, there are deleted portions). ) Is added. Thereby, the optical proximity effect correction process 124 of FIG. 4 is completed, and the mask data 125 of FIG. 4 is output (mask data output process).

  When reduced projection exposure (for example, a reduction ratio of 4: 1) is executed using the created optical mask based on the mask data 125 output here, the result is as shown in FIG. That is, as shown in FIG. 18, projection images corresponding to the gate electrode patterns 5a and 6a, that is, exposure image patterns 5r and 6r are formed on the wafer 1 (specifically, on the photoresist film on the wafer). Is done. The photoresist film pattern obtained by developing the photoresist film substantially corresponds to these exposure image patterns 5r and 6r (in this case, although not essential, generally a positive resist film is assumed). .

  Next, when anisotropic dry etching or the like is performed using the developed photoresist film pattern or the like, for example, as shown in FIG. 19, device patterns 5w after etching corresponding to the gate electrode patterns 5a and 6a, 6w is obtained.

  In this example, as described above, the initial etching bias correction unit added to the side of the gate electrode pattern or the like crossing the active region is left as it is, and the side of other adjacent same layer wiring (or gate electrode pattern or the like). The main part of the figure is deleted instead of the correction part. Therefore, this is particularly effective when the space between the gate electrode pattern and the like crossing the active region and other adjacent gate electrode patterns is relatively small (for example, close to the predetermined minimum interval S2 in FIG. 16). is there.

6). Description of Modified Example 2 (Step Removal Etching Bias Correction by Initial Correction Removal) of Etching Bias Correction in the Manufacturing Method of Semiconductor Integrated Circuit Device According to One Embodiment of the Present Application (Mainly FIGS. 20 to 26)
In this section, FIG. 5 of the example described in section 1 to section 4, that is, modification 2 (step removal etching bias correction by removing initial correction) related to etching bias correction will be described. In the following description, only the parts different from those described in sections 1 to 4 will be described in principle.

  FIG. 20 corresponds to FIG. 4 corresponding to FIG. 5 for explaining a modification 2 (step removal etching bias correction by initial correction removal) related to the etching bias correction of the manufacturing method of the semiconductor integrated circuit device according to the embodiment of the present application. It is a detailed block flow diagram of an etching bias process. FIG. 21 is a process corresponding to FIG. 6 for explaining a modification 2 (step removal etching bias correction by initial correction removal) regarding the etching bias correction of the manufacturing method of the semiconductor integrated circuit device of the embodiment of the present invention. It is a device top view (on a mask) at the time of design data reading. FIG. 22 is a view showing a process step corresponding to FIG. 7 for explaining a modification 2 (step removal etching bias correction by initial correction removal) regarding the etching bias correction of the manufacturing method of the semiconductor integrated circuit device of the one embodiment of the present application. It is a device top view (on mask) of (initial etching bias correction adding step). FIG. 23 is a view showing a process step corresponding to FIG. 8 for explaining Modification Example 2 (Step Removal Etching Bias Correction by Initial Correction Removal) of Etching Bias Correction in the Manufacturing Method of the Semiconductor Integrated Circuit Device of the One Embodiment of the Present Application. It is a device top view (on mask) of (additional etching bias correction process). FIG. 24 is a view showing a process step corresponding to FIG. 9 for explaining a modification 2 (step removal etching bias correction by initial correction removal) regarding the etching bias correction of the manufacturing method of the semiconductor integrated circuit device according to the embodiment of the present application. It is a device top view (on mask) of (optical proximity effect correction process). FIG. 25 is a process corresponding to FIG. 10 for explaining a modification 2 (step removal etching bias correction by initial correction removal) regarding the etching bias correction of the manufacturing method of the semiconductor integrated circuit device of the one embodiment of the present application. It is a device top view (on wafer) of (exposure process). FIG. 26 is a process corresponding to FIG. 11 for explaining Modification 2 (step removal etching bias correction by initial correction removal) related to the etching bias correction of the manufacturing method of the semiconductor integrated circuit device of the one embodiment of the present application. It is a device top view (on a wafer) of (etching step). Based on these, a second modification (step removal etching bias correction by initial correction removal) relating to the etching bias correction of the manufacturing method of the semiconductor integrated circuit device according to the one embodiment of the present application will be described.

  First, an overall outline of the etching bias correction of FIG. 20 corresponding to FIG. 5 will be described. 20, since the initial etching bias correction step 122a to the boundary proximity step edge extraction step 122bb are exactly the same as those in FIG. 5, the initial bias deletion for deleting the added initial etching bias in the additional etching bias correction step 122b is performed. Only step 122bcd will be described. This initial bias deletion step 122bcd replaces the same height bias addition step 122bc in the example of FIG.

  As shown in FIG. 20, by removing the initial etching bias of the edge extracted in the boundary proximity step edge extraction step 122bb, the step in that portion is removed.

  Next, as in FIGS. 6 to 11 in section 4, a specific device layout of the integrated circuit pattern formation region partial cutout portion R1 in FIG. 1 will be described as an example.

  FIG. 21 shows an example of a specific layout of the design data 121 (FIG. 4) corresponding to the integrated circuit pattern formation region partial cutout portion R1 of FIG. As shown in FIG. 21, an active region 3 for forming a MISFET is provided at the center, and the periphery thereof is an inactive region 4 with a boundary 3b interposed therebetween. The inactive region 4 is a so-called field insulating film region, for example, an STI region.

  A gate electrode pattern 5 (first gate electrode layer pattern) composed of, for example, a gate electrode layer 10 (for example, a polysilicon layer) is provided so as to traverse or traverse the active region 3. That is, the gate electrode pattern 5 traverses the active region.

  On the inactive region 4, another gate electrode pattern or a gate electrode layer wiring pattern 6 (second gate electrode layer pattern) is provided in the vicinity of the gate electrode pattern 5. That is, the adjacent gate electrode layer wiring pattern 6. As for the process layer, the integrated circuit pattern 7 is constituted by the gate electrode pattern 5, the gate electrode layer wiring pattern 6, and the like in this way.

  In this example, the width Lg (or gate length) of the gate electrode is about 55 nm, for example, and the width Wa (or gate width) of the active region 3 is about 200 nm or more, for example. The lower limit value of the width Wa of the active region 3 is, for example, the same length as the exposure wavelength (FIG. 2) or slightly longer. The above state corresponds to the design data reading step 121 in FIG.

  Next, FIG. 22 shows a state where the initial etching bias correction step 122a of FIG. 20 is completed. As shown in FIG. 22, initial etching bias correction is performed on the edge of the device figure, that is, the periphery (side) of the gate electrode pattern 5a and the gate electrode layer wiring pattern 6a before the primary etching bias correction, and as a result, An initial etching bias correction unit 11a is added. Thereby, the gate electrode pattern 5 across the active region and the gate electrode pattern or gate electrode layer wiring pattern 6 on the inactive region after the initial etching bias correction are formed.

  However, in order not to create a narrow space exceeding the allowable limit, the portion F1 facing the adjacent figure 6 and the edge of the gate electrode pattern 5a within a certain range D1 from the end of this portion are subject to initial etching bias correction. Excluded from. This fixed range D1 (distance from the boundary) corresponds to, for example, the distance that the proximity effect related to etching extends in the lateral direction from the end of the proximity graphic. Specifically, in this example, the distance D1 is, for example, about 35 nm (a preferable range is, for example, about 20 to 50 nm). The lower limit of the range of the distance D1 is, for example, a distance slightly shorter than half of the gate length (about 55 nm), and the upper limit is, for example, a distance slightly shorter than the gate length.

  Since this also applies to the proximity graphic 6, the portion F2 (including the portion corresponding to the predetermined range D1) facing the gate electrode pattern 5a is also excluded from the initial etching bias correction target.

  Next, the active region crossing edge extraction step 122ba of FIG. 20 will be described with reference to FIG. As shown in FIG. 22, only the gate electrode pattern 5 crosses the active region 3 in the device figure of the gate electrode layer 10 that is the target layer. That is, in the active region crossing edge extraction step 122ba, all edges (all circumferences) of the gate electrode pattern 5 are extracted.

  Next, the boundary proximity step edge extraction step 122bb of FIG. 20 will be described with reference to FIG. As shown in FIG. 22, in the boundary proximity step edge extraction step 122bb, the distance B1 to the inside of the boundary 3b of the active region 3 and the distance B2 to the outside from the edges extracted in the active region crossing edge extraction step 122ba. The step 20a in the band-like region of the range (the region within the range of the predetermined distance) and the peripheral edge are extracted. Specifically, a portion (final extraction edge portion) included in the range of distances B1 and B2 affected by the step among the edges of the gate electrode pattern 5 is extracted. That is, there is a step 20 a having a height H in a region within a predetermined distance from the boundary 3 b of the active region 3. Note that the distance B1 and the distance B2 are distances that are affected by the step from the boundary of the active region to the inside or the outside during exposure when the step 3a is present at the boundary 3b of the active region 3. In this example, this distance is about 75 nm, for example (a preferable range is about 50 to 100 nm, for example). In other words, this distance is a distance in the range of about 1/4 to 1/2 of the exposure wavelength (FIG. 2).

  As described above, in the state where there is the step 20a, there is a possibility that the influence of the rounding of the exposure pattern due to this step on the pattern sensitive portion in the vicinity of the boundary 3b of the active region 3 during the exposure. Therefore, in order to avoid this, in the initial bias deletion step 122bcd of FIG. 20, the initial etching bias correction unit 11a is deleted at the final extraction edge as shown in FIG. Specifically, the portion 11x that is deleted by the additional etching bias correction is deleted.

  Thereby, the etching bias correction step 122 of FIG. 4 is completed. As a result, the gate electrode pattern 5b (first gate electrode layer pattern) crossing the active region after the primary etching bias correction and the gate electrode pattern or gate electrode layer wiring pattern 6b on the non-active region after the primary etching bias correction. (Second gate electrode layer pattern) is obtained.

  Next, when the optical proximity effect correcting step 124 of FIG. 4 is executed, as shown in FIG. 24, the mask patterns 5w and 6m after the etch bias correction have OP portions added by OPC, etc. (to be precise, there are deleted portions). ) Is added. Thereby, the optical proximity effect correction process 124 of FIG. 4 is completed, and the mask data 125 of FIG. 4 is output (mask data output process).

  When reduced projection exposure (for example, a reduction ratio of 4: 1) is executed using the created optical mask based on the mask data 125 output here, the result is as shown in FIG. That is, as shown in FIG. 25, projection images corresponding to the gate electrode patterns 5a and 6a, that is, exposure image patterns 5r and 6r are formed on the wafer 1 (specifically, on the photoresist film on the wafer). Is done. The photoresist film pattern obtained by developing the photoresist film substantially corresponds to these exposure image patterns 5r and 6r (in this case, although not essential, generally a positive resist film is assumed). .

  Next, when, for example, anisotropic dry etching or the like is performed using the developed photoresist film pattern or the like, as shown in FIG. 26, device patterns 5w after etching corresponding to the gate electrode patterns 5a and 6a, 6w is obtained.

  In this example, as described above, since the initial etching bias correction unit added to the side of the gate electrode pattern or the like crossing the active region is deleted, it is possible to connect with other adjacent same layer wiring (or gate electrode pattern or the like). This is also effective when the space is relatively small (for example, close to the predetermined minimum interval S2 in FIG. 16).

  In other words, in this example, as a result, the etching shift correction is not performed on a predetermined portion of the edge facing the other gate electrode pattern or the like that crosses the active region.

7). Supplementary explanation about the above-described embodiment (including modifications) and general consideration (mainly FIG. 27)
FIG. 27 is a conceptual explanatory diagram corresponding to FIG. 8 (FIGS. 15 and 23) and the like for explaining the outline and the like of the manufacturing method of the semiconductor integrated circuit device according to the embodiment of the present application. Based on this, a supplementary explanation regarding the above-described embodiment (including modifications) and a general consideration will be given.

(1) Additional description such as technical problems related to the above-described embodiment (including modifications):
As described above, in the photolithography process of the semiconductor integrated circuit device, as a correction for the dimensional change by the etching process, a target mask pattern (target pattern) and another mask pattern (proximity pattern) adjacent thereto are used. A correction value corresponding to the interval is obtained from a reference table, and an etching bias is added based on the correction value. In other words, a reference table is created using process characteristics such as microloading effect as seen in dry etching, etc., using the distance of adjacent figures as a parameter, and the etching bias correction amount is determined based on the reference table.

  Such correction is usually performed in combination with optical proximity correction, and generally as part of proximity correction, prior to optical proximity correction (which may, of course, be performed thereafter or simultaneously).

  In this etching bias correction, in general, a positive etching bias is applied except for a certain range close to each other so that the target pattern and the proximity pattern are not too close as a result of the correction. Yes.

  However, when the target pattern is a gate electrode, if a proximity pattern is placed near the boundary of the active region, a bias start point may be set inside or near the boundary of the active region. Becomes higher. In such a case, a step is formed in the contour of the mask pattern in that portion, and the influence of the rounding from this step spreads to the surrounding active region at the time of exposure, and device characteristics such as variations in gate dimensions May cause deterioration. That is, CD (Critical Dimension) variation occurs.

(2) Description of outline of manufacturing method of semiconductor integrated circuit device of one embodiment of the present application (mainly FIG. 27):
The outline of the manufacturing method of the semiconductor integrated circuit device according to the embodiment of the present application will be described with reference to FIG.

  As shown in FIG. 27, the outline of the above-described embodiment is that the active region 3 of the optical mask 59 used in the patterning of the gate electrode is created in relation to the lithography process in the manufacturing process of the semiconductor integrated circuit device. Within a certain range from the boundary 3b, a bias correction step is prevented from occurring in the gate electrode pattern 5b subjected to the etching bias correction.

That is, a method for manufacturing a semiconductor integrated circuit device includes the following steps.
(A) Step 131 of generating mask data 125 based on the design data 121;
(B) Step 132 of preparing an optical mask 59 having a mask pattern 9 based on the mask data 125;
(C) Step 133 of forming an integrated circuit pattern 7 on the semiconductor wafer 1 by performing reduced projection exposure 58 with ultraviolet exposure light 57 using the optical mask 59;
Here, the step (a) includes the following substeps:
(A1) In the design data 121, the first gate electrode layer pattern 5a crossing the active region 3 and the second gate electrode layer on the inactive region 4 and in proximity to the first gate electrode layer pattern 5a Applying a primary etching bias correction 11 to the pattern 6a;
At this time, in the range of predetermined distances B1 and B2 on both sides from the boundary 3b of the active region 3, an etching bias correction step is prevented from occurring in the first gate electrode layer pattern 5b after the primary correction. The first gate electrode layer pattern 5 and the second gate electrode layer pattern 6 are formed by patterning the gate electrode layer 10.

  In this way, variations in gate electrode pattern dimensions and the like can be reduced.

8). Summary The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.

  For example, in the above-described embodiment, the gate first process has been mainly described as an example, but the present invention is not limited thereto, and the gate last process is not limited thereto. Needless to say, the present invention can also be applied to the mixing process.

  In the above-described embodiment, the gate electrode layer is specifically described as the target layer. However, the present invention is not limited to this and can be applied to other layers.

1 Semiconductor wafer 1a Wafer or chip surface (first main surface)
2 Semiconductor integrated circuit chip (chip area)
3 Active region 3b Boundary between active region and inactive region 4 Inactive region 5 Gate electrode pattern (first gate electrode layer pattern) across the active region
5a Gate electrode pattern (first gate electrode layer pattern) crossing the active region (design data) before primary etching bias correction
5b Gate electrode pattern (first gate electrode layer pattern) crossing the active region after correcting the primary etching bias
5m Mask pattern (after etch bias correction) corresponding to the gate electrode pattern crossing the active region 5r Exposure image pattern corresponding to the gate electrode pattern crossing the active region at the time of exposure 5w Gate electrode pattern crossing the active region after etching Device pattern corresponding to 6 etc. 6 Gate electrode pattern or gate electrode layer wiring pattern on the inactive region (second gate electrode layer pattern)
6a Gate electrode pattern or gate electrode layer wiring pattern (second gate electrode layer pattern) on inactive region (design data) before primary etching bias correction
6b Gate electrode pattern or gate electrode layer wiring pattern (second gate electrode layer pattern) on the inactive region after correcting the primary etching bias
6m Mask pattern (after etch bias correction) corresponding to the gate electrode pattern etc. on the non-active region 6r Exposure image pattern corresponding to the gate electrode pattern etc. on the non-active region at the time of exposure 6w On the non-active region after etching Device pattern corresponding to gate electrode pattern, etc. 7 Integrated circuit pattern 8 Integrated circuit pattern formation region 9 Mask pattern 10 Gate electrode layer 11 Primary etching bias correction unit (primary etching bias correction)
11a Initial etching bias correction unit (initial etching bias correction)
11b Additional etching bias correction unit (additional etching bias correction)
11x portion where the bias corrected by the primary etching bias is deleted by the additional etching bias correction 12 secondary etching bias correction unit (secondary etching bias correction)
20a, 20b Etching bias correction step (correction step)
51 Wafer stage 56 Optical axis 57 Exposure light 58 Exposure optical system (reduction projection optical system, reduction projection exposure)
59 Optical mask 61 Light source 62 Light source optical system 63 Liquid for immersion 101 Process determination step 102 Exposure and etching data acquisition step 103 Bias table creation step 104 Exposure etc. model creation step 105 Table and model etc. incorporation step 106 Verification step 106a Verification mask creation , Exposure and etching evaluation process 106b lithography simulation process 106c software verification process 107 process & optical proximity correction software completed 121 design data reading process (design data)
122 Etching Bias Correction Step 122a Initial Etching Bias Correction Step 122b Additional Etching Bias Correction Step 122ba Step of Extracting Edge Crossed by Active Region (Active Region Crossing Edge Extraction Step)
122bb Extracting an edge at a certain distance in and out of the active region boundary (boundary proximity step edge extracting step)
122bc A step of applying a bias having the same height as the step to the extracted edge (same height bias adding step)
122bcd The step of deleting the added initial etching bias (initial bias deleting step)
123a Primary etching bias correction step 123b Secondary etching bias correction step 123ba Fine interval extraction step 123bb Fine enlargement extraction step 124 Optical proximity effect correction step 125 Mask data output step (mask data)
131 Mask data generation step 132 Optical mask manufacturing step 133 Lithography processing step B1 Distance affected by the step from the boundary of the active region to the inside B2 Distance affected by the step from the boundary of the active region to the outside D1, D2 Edges of the adjacent figure Distance from which the proximity effect related to etching extends from side to side F1 Regions of opposing sides such as gate electrode patterns crossing the active region F2 Regions of opposing sides such as gate electrode patterns on the inactive region H Step height Lg Gate electrode Width (or gate length)
Additional part by OP OPC, etc. R1 Integrated circuit pattern formation region part cutout part S1 Interval with adjacent figure S2 Minimum interval (predetermined minimum interval)
Wa Active region width (or gate width)

Claims (10)

A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) generating mask data based on the design data;
(B) preparing an optical mask having a mask pattern based on the mask data;
(C) forming an integrated circuit pattern on a semiconductor wafer by reducing projection exposure with ultraviolet exposure light using the optical mask;
Here, the step (a) includes the following substeps:
(A1) In the design data, a first gate electrode layer pattern that traverses the active region and a second gate electrode layer pattern that is on the inactive region and is close to the first gate electrode layer pattern Performing a primary etching bias correction,
At this time, an etching bias correction step is prevented from occurring in the first gate electrode layer pattern after the primary correction within a predetermined distance on both sides from the boundary of the active region.     2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the range of the predetermined distance is the step (c) when the etching bias correction step is present at the boundary of the active region. This is a range affected by the etching bias correction step.     3. The method of manufacturing a semiconductor integrated circuit device according to claim 2, wherein the range affected by the etching bias correction step is about half the wavelength of the ultraviolet exposure light on both sides from the boundary of the active region. is there.     4. The method of manufacturing a semiconductor integrated circuit device according to claim 3, wherein the active region is located on a side facing the second gate electrode layer pattern in the first gate electrode layer pattern after the primary correction. In the range of the predetermined distance on both sides from the boundary, positive primary etching bias correction is performed. 4. The method of manufacturing a semiconductor integrated circuit device according to claim 3, wherein the step (a) further includes the following substeps:
(A2) After the step (a1), when the interval between the first gate electrode layer pattern after the primary correction and the second gate electrode layer pattern is less than a predetermined minimum interval, Performing a negative secondary etching bias correction on the second gate electrode layer pattern so that the interval is equal to or greater than the predetermined minimum interval.     4. The method of manufacturing a semiconductor integrated circuit device according to claim 3, wherein the active region is located on a side facing the second gate electrode layer pattern in the first gate electrode layer pattern after the primary correction. The primary etching bias correction is not performed within the predetermined distance on both sides from the boundary. 4. The method of manufacturing a semiconductor integrated circuit device according to claim 3, wherein the step (a1) includes the following substeps:
(A11) Positive initial etching bias correction for a portion of the first gate electrode layer pattern before the primary correction excluding a predetermined proximity range on the side facing the second gate electrode layer pattern Applying
(A12) A step of performing positive additional etching bias correction so that the etching bias correction step disappears with respect to the predetermined proximity range after the step (a11). 5. The method of manufacturing a semiconductor integrated circuit device according to claim 4, wherein the step (a1) includes the following substeps:
(A11) Positive initial etching bias correction for a portion of the first gate electrode layer pattern before the primary correction excluding a predetermined proximity range on the side facing the second gate electrode layer pattern Applying
(A12) A step of performing positive additional etching bias correction so that the etching bias correction step disappears with respect to the predetermined proximity range after the step (a11). 6. The method of manufacturing a semiconductor integrated circuit device according to claim 5, wherein the step (a1) includes the following substeps:
(A11) Positive initial etching bias correction for a portion of the first gate electrode layer pattern before the primary correction excluding a predetermined proximity range on the side facing the second gate electrode layer pattern Applying
(A12) A step of performing positive additional etching bias correction so that the etching bias correction step disappears with respect to the predetermined proximity range after the step (a11).     4. The method of manufacturing a semiconductor integrated circuit device according to claim 3, wherein a predetermined proximity range on a side facing the first gate electrode layer pattern in the second gate electrode layer pattern after the primary correction is set. A positive initial etching bias correction is applied to the other portions.

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