JP2016015769A - Amplifier and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an amplifier and a semiconductor device that suppress power consumption in a power-down state.SOLUTION: An amplifier 10 includes: a PMOS transistor 12C configured to enter a block state to block a supply of driving voltage to a gate of a PMOS transistor 12A when an input inverted power-down signal indicates a normal operating state of a differential amplification circuit 12, and enter a supply state to supply a driving voltage to the gate of the PMOS transistor 12A when a power-down state of the differential amplification circuit 12 is indicated; and a PMOS transistor 12D configured to bring the gate and a drain of the PMOS transistor 12A to a conductive state when an input power-down signal indicates the normal operating state of the differential amplification circuit 12, and bring the gate and the drain of the PMOS transistor 12A to a nonconductive state when the power-down state of the differential amplification circuit 12 is indicated.

Description

  The present invention relates to an amplifier and a semiconductor device.

  FIG. 7 shows an example of the configuration of a conventional amplifier. In the example shown in FIG. 7, “PD” means a signal level indicating a state where the amplifier is powered down (power down state) and a signal level indicating a non-power down state where the amplifier is not powered down (normal operation state). This is a first power-down input terminal to which a transitioning power-down signal is input. “PDN” is an input of an inverted power-down signal obtained by inverting the power-down signal input to the first power-down input terminal PD. The “INN” is the inverting input terminal of the differential amplifier circuit, and “INP” is the non-inverting input terminal of the differential amplifier circuit. Yes, “VBN” is a bias voltage signal that corresponds to the bias voltage and whose signal level transitions in response to the transition of the signal level of the inverted power down signal. It is a bias voltage input terminal, “OUT” is an output terminal of the amplifier, “VDD” is a drive voltage terminal to which a drive voltage for the amplifier is supplied, and “VSS”. "Is a low voltage terminal to which a low voltage (ground voltage as an example) smaller than the magnitude of the driving voltage is supplied.

  The term “power down” as used herein means stopping the driving of the amplifier (for example, stopping the output from the amplifier). Therefore, the amplifier is powered down when the signal level of the power down signal is high, and operates (normal operation) in a steady state when the signal level is low. Hereinafter, a P-channel MOS field effect transistor is referred to as a “PMOS transistor”, and an N-channel MOS field effect transistor is referred to as an “NMOS transistor”. The power down signal, the inverted power down signal, and the bias voltage are all signals whose signal level transitions between a high level and a low level. For example, the signal level of the power down signal is set to a low level in a normal operation state. High level in power-down state. In the following description, it is assumed that the power-down signal, the inverted power-down signal, and the bias voltage are all set so that the low-level voltage has the same magnitude as the low voltage VSS. In the following description, it is assumed that the voltage level when the signal level of the bias voltage signal is high is half the voltage level when the signal level of the inverted power down signal is high.

  The amplifier shown in FIG. 7 includes a differential amplifier circuit having a current mirror circuit and an output circuit having a CMOS switch connected to the output terminal of the differential amplifier circuit. The drain of the power-down PMOS transistor is connected to the gate of the PMOS transistor (output stage PMOS transistor) which is a component of the CMOS switch included in the output circuit. The gate of the power-down PMOS transistor is connected to a second power-down input terminal PDN to which an inverted power-down signal is input during power-down. Therefore, at the time of power-down, the gate of the power-down PMOS transistor is pulled down, thereby pulling up the gate of the output stage PMOS transistor. Such an amplifier is also disclosed in Patent Document 1.

JP-A 64-10709

  However, despite the fact that the gate of the output stage PMOS transistor was pulled up to power down the amplifier, current leaked out from the differential amplifier circuit and the power down PMOS transistor. There was a problem that it was not possible. Note that the current value in each transistor shown in FIG. 7 is an example related to the current flowing through each transistor during power-down.

  The present invention has been made to solve the above-described problems, and an object thereof is to provide an amplifier and a semiconductor device capable of suppressing power consumption during power-down.

  In order to achieve the above object, the amplifier according to claim 1 is an amplifier including a differential amplifier circuit, and the differential amplifier circuit is driven by a pair of transistors having control terminals connected together and one end thereof. A first switching element having a second end connected to the control terminal, a first end connected to the drain of one of the pair of transistors, and a second end connected to the control terminal. A switching element; a first terminal and a back gate connected to the back gate of the first switching element and supplied with the driving voltage; a second terminal connected to the back gate of the second switching element; and A third auxiliary transistor having a control terminal to which a control terminal of the first switching element is connected; and a first terminal to which a back gate of the second switching element is connected. A fourth auxiliary transistor having a second terminal connected to the one drain, a control terminal connected to the control terminal of the second switching element, and a back gate connected to the back gate of the third auxiliary transistor; , With.

  In order to achieve the above object, an amplifier according to claim 3 is an amplifier including a differential amplifier circuit and an output circuit having an output element in which an output of the differential amplifier circuit is connected to a control terminal. The output circuit has a first switching element having one end connected to the driving voltage and the other end connected to the control terminal, one end connected to the output, and the other end connected to the control terminal. A second switching element, a first terminal connected to the back gate of the first switching element and supplied with the driving voltage and a back gate, and a second terminal connected to the back gate of the second switching element And a first auxiliary transistor having a control terminal to which a control terminal of the first switching element is connected, a first terminal to which a back gate of the second switching element is connected, and the output There with a second terminal connected, a control terminal to which a control terminal connected to said second switching element, and a second auxiliary transistor having a back gate back gate connected to the first auxiliary transistor.

  According to the present invention, an effect that power consumption at the time of power-down can be suppressed is obtained as compared with the case where the present configuration is not provided.

1 is a circuit diagram showing an example of a configuration of an amplifier according to a first embodiment. FIG. It is a time chart which shows the example of a transition of the signal level of the signal supplied to each of the 1st power down input terminal, the 2nd power down input terminal, and bias voltage input terminal which are included in the amplifier which concerns on 1st Embodiment. It is a graph which shows an example of the relationship of the magnitude | size of the electric current which flows out from the specific several transistor contained in the amplifier with respect to the magnitude | size of a drive voltage, and the terminal for low voltage with respect to the magnitude | size of a drive voltage as an experimental result using the amplifier of a prior art example. FIG. 7 is a graph showing an example of the relationship between the magnitude of current flowing out from the main PMOS transistor included in the amplifier and the terminal for low voltage with respect to the magnitude of the driving voltage as an experimental result using the amplifier according to the first embodiment. is there. It is a circuit diagram which shows an example of a structure of the amplifier which concerns on 2nd Embodiment. As an experimental result using the amplifier according to the first embodiment, an example of the relationship between the magnitude of the on-resistance of a specific PMOS transistor with respect to the magnitude of the driving voltage and the amplifier according to the second embodiment were used. It is a graph which shows an example of the relationship of the magnitude | size of the ON resistance of a specific PMOS transistor with respect to the magnitude | size of a drive voltage as an experimental result. It is a circuit diagram which shows an example of a structure of the conventional amplifier.

  Embodiments for carrying out the present invention will be described below in detail with reference to the drawings. In the following embodiment, the first power-down input terminal PD, the second power-down input terminal PDN, the inverting input terminal INN, the non-inverting input terminal INP, the bias voltage input terminal VBN described in the example illustrated in FIG. The output terminal OUT, the drive voltage terminal VDD, and the low voltage terminal VSS are used, and the power down signal, the inverted power down signal, the bias voltage signal, the drive voltage, and the low voltage described in the example illustrated in FIG. 7 are also used. ing. Further, in the following description, the wording “ON” and the wording “OFF” are used as the words expressing the switching state of the PMOS transistor and the NMOS transistor, and “ON” means that the source and the drain are in a conductive state. It means that “off” means that the source and the drain are in a non-conductive state. In addition, the conduction state refers to a state within a predetermined allowable range (including when the current value is 0 A) that is recognized as a state in which no current is flowing, and the non-conduction state refers to a state in which current is flowing. This refers to a recognized state (a state outside the above-mentioned tolerance).

[First Embodiment]
FIG. 1 is a circuit diagram showing an example of the configuration of the amplifier 10 according to the first embodiment. As shown in FIG. 1, the amplifier 10 includes a differential amplifier circuit 12 and an output circuit 14, which are a semiconductor device formed as a single chip. The amplifier 10 includes a control unit including a computer having a central processing unit (CPU), a random access memory (RAM), and a read only memory (ROM). This control unit supplies a signal (ON signal or OFF signal) for performing switching control to the gate of a predetermined transistor included in the amplifier 10. Examples of the “on signal or off signal” herein include a power down signal, an inverted power down signal, and a bias voltage signal.

  The differential amplifier circuit 12 includes PMOS transistors 12A, 12B, 12C, and 12D and NMOS transistors 12E, 12F, and 12G. The PMOS transistor 12A, which is an example of a predetermined switching element, has a source that is an example of a first terminal to which a driving voltage is supplied, and a current that flows into the first terminal can flow out (is a low voltage supply destination). A drain which is an example of two terminals, a gate which is an example of a third terminal, and a back gate are provided. In the PMOS transistor 12A, the back gate and the source are connected to the driving voltage terminal VDD. In the NMOS transistor 12E, the drain is connected to the drain of the PMOS transistor 12A, and the gate is connected to the inverting input terminal INN.

  In the PMOS transistor 12B, the source and the back gate are connected to the drive voltage terminal VDD, and the gate is connected to the gate of the PMOS transistor 12A. In the NMOS transistor 12F, the drain is connected to the drain of the PMOS transistor 12B, the gate is connected to the non-inverting input terminal INP, and the back gate is connected to the back gate of the NMOS transistor 12E.

  In the NMOS transistor 12G, the gate is to the bias voltage input terminal VBN, the source is to the low voltage terminal VSS, the drain is to each source of the NMOS transistors 12E and 12F, and the back gate is each back to the low voltage terminal VSS and the NMOS transistors 12E and 12F. Each is connected to a gate.

  In the PMOS transistor 12C as an example of the first switching element, the source and the back gate are connected to the driving voltage terminal VDD, and the gate is connected to the second power-down input terminal PDN. The drain of the PMOS transistor 12C is connected to the gate of the PMOS transistor 12A. Accordingly, the PMOS transistor 12C can supply a driving voltage to the gate of the PMOS transistor 12A. That is, the PMOS transistor 12C is turned off when the input inverted power-down signal indicates the normal operation state of the differential amplifier circuit 12, thereby preventing the driving voltage from being supplied to the gate of the PMOS transistor 12A. It becomes a blocking state. The PMOS transistor 12C is turned on when the input inverted power-down signal indicates the power-down state of the differential amplifier circuit 12, and thereby enters a supply state in which the driving voltage is supplied to the gate of the PMOS transistor 12A. .

  In the PMOS transistor 12D as an example of the second switching element, the gate is the first power-down input terminal PD, the source is the PMOS transistor 12A, the drain is the drain of the PMOS transistor 12A, and the back gate is the back gate of the PMOS transistor 12C. Each is connected. That is, the PMOS transistor 12D connects the drain and gate of the PMOS transistor 12A so as to be conductive, and is turned on when the input power-down signal indicates the normal operation state of the differential amplifier circuit 12. The drain and gate (diode connection section) of the transistor 12A are turned on. In addition, the PMOS transistor 12D is turned off when the power-down state of the differential amplifier circuit 12 is indicated, and thereby the non-conducting state is established between the drain and gate (diode connection section) of the PMOS transistor 12A.

  The output circuit 14 includes PMOS transistors 14A, 14B, and 14C, NMOS transistors 14D and 14E, a resistor 14F, and a phase compensation capacitor 14G. The resistor 14F and the capacitor 14G are connected in series, and the output terminal α of the differential amplifier circuit 12 corresponding to the connection point between the drain of the PMOS transistor 12B and the drain of the NMOS transistor 12F in the differential amplifier circuit 12 is a resistor. 14F and a capacitor 14G are connected to the output terminal OUT.

  The PMOS transistor 14A, which is an example of the output switching element, can discharge the current flowing into the source and the fourth terminal, which are examples of the fourth terminal to which the driving voltage is supplied (the supply destination of the low voltage). A drain as an example of a fifth terminal, a gate as an example of a sixth terminal connected to the output terminal α via the PMOS transistor 14C, and a back gate are provided. In the PMOS transistor 14A, the source and back gate are connected to the driving voltage terminal VDD, and the drain is connected to the output terminal OUT.

  In the PMOS transistor 14B, which is an example of a power-down switching element, the source and back gate are connected to the drive voltage terminal VDD, and the gate is connected to the second power-down input terminal PDN. The drain of the PMOS transistor 14B is connected to the gate of the PMOS transistor 14A. Accordingly, the PMOS transistor 14B can supply a driving voltage to the gate of the PMOS transistor 14A. That is, the PMOS transistor 14B is turned off when the input inverted power-down signal indicates the normal operation state of the differential amplifier circuit 12, thereby preventing the driving voltage from being supplied to the gate of the PMOS transistor 14A. It becomes a blocking state. The PMOS transistor 14B is turned on when the inverted power down signal input from the control unit indicates the power down state of the differential amplifier circuit 12, thereby supplying the driving voltage to the gate of the PMOS transistor 14A. It becomes a state.

  In the PMOS transistor 14C as an example of a power-down switching element, the gate is the first power-down input terminal PD, the source is the gate of the PMOS transistor 14A, the drain is the output terminal α, and the back gate is the back gate of the PMOS transistor 14B. Is connected to each. That is, the PMOS transistor 14C connects the output terminal α and the gate of the PMOS transistor 14A so as to be conductive, and turns on when the input power-down signal indicates the normal operation state of the differential amplifier circuit 12. As a result, the output terminal α and the gate of the PMOS transistor 14A are made conductive. Further, the PMOS transistor 4C is turned off when the power-down state of the differential amplifier circuit 12 is indicated, and thereby the non-conduction state is established between the output terminal α and the gate of the PMOS transistor 14A.

  The NMOS transistor 14D, which is an example of another output switching element having a conductivity type paired with the conductivity type of the output switching element, is an example of a source and an eighth terminal that are examples of a seventh terminal to which a low voltage is supplied. A drain, a gate which is an example of a control terminal to which an input bias voltage signal is supplied, and a back gate are provided. In the NMOS transistor 14D, the source and back gate are connected to the low voltage terminal VSS, the drain is connected to the output terminal OUT, and the gate is connected to the bias voltage input terminal VBN.

  In the NMOS transistor 14E, which is an example of another power down element, the source and back gate are connected to the low voltage terminal VSS, and the gate is connected to the first power down input terminal PD. The drain of the NMOS transistor 14E is connected to the gate of the NMOS transistor 14D. Therefore, the NMOS transistor 14E can supply a low voltage to the gate of the PMOS transistor 14D. That is, the NMOS transistor 14E is turned off when the input power-down signal indicates the normal operation state of the differential amplifier circuit 12, thereby preventing a low voltage from being supplied to the gate of the NMOS transistor 14D. It becomes. The NMOS transistor 14E is turned on when the input power-down signal indicates the power-down state of the differential amplifier circuit 12, thereby entering a supply state in which a low voltage is supplied to the gate of the NMOS transistor 14D.

  Next, the operation of the amplifier 10 according to the first embodiment will be described for each of the normal operation state and the power-down state with reference to FIGS. 1 and 2. FIG. 2 shows the power down signal input to the first power down input terminal PD, the inverted power down signal input to the second power down input terminal PDN, and the bias voltage signal input to the bias voltage input terminal VBN. It is a time chart which shows an example of the state transition of each signal level.

  First, the normal operation state will be described. In a normal operation state, a low-level power-down signal is input to the first power-down input terminal PD, a high-level inverted power-down signal is input to the second power-down input terminal PDN, and a high level is input to the bias voltage input terminal VBN. The bias voltage signal is input. Thereby, in the differential amplifier circuit 12, the PMOS transistor 12C is turned off and the PMOS transistor 12D and the NMOS transistor 12G are turned on. On the other hand, in the output circuit 14, the PMOS transistor 14B and the NMOS transistor 14E are turned off, and the PMOS transistor 14C is turned on. Since it is turned on, an output signal indicating the magnitude of the voltage corresponding to the difference between the inverting input signal input to the inverting input terminal INN and the non-inverting input signal input to the non-inverting input terminal INP is output from the output terminal OUT. The

  Next, the power down state will be described. In the power down state, a high level power down signal is input to the first power down input terminal PD, a low level inverted power down signal is input to the second power down input terminal PDN, and a low level is input to the bias voltage input terminal VBN. The bias voltage signal is input. As a result, in the differential amplifier circuit 12, the PMOS transistor 12C is turned on and the PMOS transistor 12D and the NMOS transistor 12G are turned off. In the output circuit 14, the PMOS transistor 14B and the NMOS transistor 14E are turned on, and the PMOS transistor 14C is turned on. Since the circuit is turned off, the amount of current flowing out from the differential amplifier circuit 12 and the amount of current flowing out from the output circuit 14 are drastically reduced as compared with the conventional example shown in FIG.

  That is, in the differential amplifier circuit 12, the gate of the PMOS transistor 12A is pulled down when the PMOS transistor 12C is turned on, so that the PMOS transistor 12A is turned off and current leakage from the drain of the PMOS transistor 12A is prevented. Here, if the drain and gate of the PMOS transistor 12A are simply diode-connected as in the conventional example shown in FIG. 7, the current flowing out from the drain of the PMOS transistor 12C when the PMOS transistor 12C is turned on. Leaks from the differential amplifier circuit 12. In the amplifier 10 according to the first embodiment, the PMOS transistor 12D is turned off at the timing when the PMOS transistor 12C is turned on. The current flowing out from the drain is blocked by the PMOS transistor 12D.

  On the other hand, as for the output circuit 14, since the PMOS transistor 14B is turned on to pull down the gate of the PMOS transistor 14A, the PMOS transistor 14A is turned off and current leakage from the drain of the PMOS transistor 14A is prevented. Here, if the output terminal α and the gate of the PMOS transistor 14A are simply connected by a connection line as in the conventional example shown in FIG. 7, the PMOS transistor 14B is turned on to turn on the drain of the PMOS transistor 14B. In the amplifier 10 according to the first embodiment, since the current flowing out from the differential amplifier circuit 12 is leaked, the PMOS transistor 14C is turned off at the timing when the PMOS transistor 14B is turned on. A current flowing out from the drain of the PMOS transistor 14B is blocked by the PMOS transistor 14C.

  Therefore, when the magnitude of the current flowing through each transistor in the conventional amplifier shown in FIG. 7 is compared with the magnitude of the current flowing through each transistor in the amplifier 10 shown in FIG. 1, the current flows out from the drain of the PMOS transistor 14B shown in FIG. The magnitude of the current to be generated is overwhelmingly smaller than the magnitude of the current flowing out from the drain of the power-down PMOS transistor (PMOS transistor MP1) shown in FIG. Further, the magnitude of the current flowing out from the drain of the PMOS transistor 12A shown in FIG. 1 is larger than the magnitude of the current flowing out from the drain of the diode-connected PMOS transistor (PMOS transistor MP6) in the differential amplifier circuit shown in FIG. Overwhelmingly smaller. Further, the magnitude of the current leaking from the differential amplifier circuit 12 shown in FIG. 1 is overwhelmingly smaller than the magnitude of the current leaking from the differential amplifier circuit shown in FIG. As described above, according to the amplifier 10 according to the first embodiment, the amount of current leakage from the amplifier 10 in the power-down state can be overwhelmingly smaller than that in the conventional example.

  In addition, the power-down signal, the inverted power-down signal, and the bias voltage signal that are conventionally used are used as they are without generating a new signal for switching control of the PMOS transistors 12C, 12D, and 14C. Compared with the case where this configuration is not provided, current consumption can be efficiently reduced.

  FIG. 3 shows a plurality of specific transistors (PMOS transistors MP6, MP8, MP1 shown in FIG. 3) and low voltage terminals included in the amplifier with respect to the magnitude of the driving voltage VDD as a result of an experiment using the conventional amplifier. An example showing the relationship between the magnitudes of currents flowing out from VDD is shown, and FIG. 4 shows an amplifier for the magnitude of drive voltage VDD as an experimental result using amplifier 10 according to the first embodiment. 10 shows an example of the relationship between each of the PMOS transistors 12A, 14A, and 14B included in 10 (transistors corresponding to the specific plurality of transistors) and the magnitude of current flowing out from the low voltage terminal VDD. As shown in FIGS. 3 and 4, the PMOS transistors MP6, MP8, MP1 included in the conventional amplifier and the PMOS transistors 12A, 14A, 14B included in the amplifier 10 according to the first embodiment are both for driving. Although the amount of leakage current decreases as the voltage VDD increases, the magnitude of the current flowing out from each of the PMOS transistors 12A, 14A, and 14B included in the amplifier 10 according to the first embodiment is as follows. It can be seen that the current flowing out from each of the PMOS transistors MP6, MP8, and MP1 included in the conventional amplifier is overwhelmingly smaller.

[Second Embodiment]
In the second embodiment, a case will be described in which phase compensation necessary for the amplifier to stably operate normally is ensured. The phase compensation is a circuit (compensation circuit) provided to stabilize the phase of a waveform in a feedback amplifier circuit or the like. In an amplifier circuit such as an operational amplifier, if the phase shift exceeds a certain limit, oscillation occurs (a state in which a constant frequency is continuously output) and a correct waveform cannot be obtained. Phase compensation suppresses this phase shift within a certain limit, thereby preventing oscillation and stabilizing the waveform.

  Hereinafter, the same components as those described in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  FIG. 5 is a circuit diagram showing an example of the configuration of the amplifier 20 according to the second embodiment. As shown in FIG. 5, the amplifier 20 according to the second embodiment is different from the amplifier 10 according to the first embodiment in that a differential amplifier 22 is applied instead of the differential amplifier 12 and The difference is that an output circuit 24 is applied instead of the output circuit 14.

  The output circuit 24 is different from the output circuit 14 according to the first embodiment in that PMOS transistors 14H and 14J are further provided. The PMOS transistor 14H, which is an example of the first auxiliary transistor, is connected to the back gate of the PMOS transistor 14B, whereby the source and back gate to which the driving voltage is supplied, and the drain to which the back gate of the PMOS transistor 14C is connected. And a gate connected to the gate of the PMOS transistor 14B. The PMOS transistor 14J, which is an example of the second auxiliary transistor, includes a source to which the back gate of the PMOS transistor 14C is connected, a drain to which the output terminal α is connected, a gate to which the gate of the PMOS transistor 14C is connected, And a back gate connected to the back gate of the PMOS transistor 14H.

  The differential amplifier 22 is different from the differential amplifier 12 according to the first embodiment in that PMOS transistors 12H and 12J are further provided. The PMOS transistor 12H, which is an example of a third auxiliary transistor, is connected to the back gate of the PMOS transistor 12B, whereby the source and back gate to which the driving voltage is supplied, and the drain to which the back gate of the PMOS transistor 12D is connected. And a gate to which the gate of the PMOS transistor 12C is connected. The PMOS transistor 12J, which is an example of the fourth auxiliary transistor, includes a source to which the back gate of the PMOS transistor 12D is connected, a drain to which the drain of the PMOS transistor 12A is connected, and a gate to which the gate of the PMOS transistor 12D is connected. And a back gate connected to the back gate of the PMOS transistor 12H.

  In the amplifier 10 according to the first embodiment, the phase compensation is reduced under the condition that the on-resistance of the PMOS transistor 14C included in the output circuit 14 is high (for example, the condition such as the temperature in the guaranteed operation range). There is a risk of it. That is, in the conventional example shown in FIG. 7, no circuit element is inserted in the connection line connecting the gate of the output stage PMOS transistor and the output terminal of the differential amplifier circuit. In the amplifier 10 according to the embodiment, it can be considered that the PMOS transistor 14C is inserted.

  Therefore, in the amplifier 20 according to the second embodiment, the back gate and the source of the PMOS transistor 14C are short-circuited by further providing the PMOS transistors 14H and 14J. As a result, the substrate bias effect of the PMOS transistor 14C is reduced and the on-resistance is lowered, so that phase compensation can be improved. The reason why the on-resistance is lowered is that the phase may be delayed if the on-resistance is high (since the on-resistance is low (closer to 0Ω), the oscillation is difficult). The phase compensation can be said to be a circuit for returning the phase lag, and if the on-resistance is high, it is difficult to return the phase lag. Therefore, it is preferable to reduce the on-resistance.

  In order to further enhance the effect of improving phase compensation, in the amplifier 20 according to the second embodiment, the back gate and the source of the PMOS transistor 12D are short-circuited by further providing the PMOS transistors 12H and 12J. As a result, the substrate bias effect of the PMOS transistor 12D is reduced and the on-resistance is lowered, so that phase compensation can be improved.

  As described above, according to the amplifier 20 according to the second embodiment, the PMOS transistors 12H, 12J, 14H, and 14J are further provided to the amplifier 10 according to the first embodiment, and the PMOS transistors 12D and 14C are provided. Since the back gate and the source are short-circuited in each of these, the current consumption can be reduced as compared with the conventional example shown in FIG. 7 while performing the same function as the conventional example shown in FIG.

  FIG. 6 shows an example of the relationship between the magnitude of the on-resistance of the PMOS transistor 14C and the magnitude of the driving voltage VDD as an experimental result using the amplifier 10 according to the first embodiment, and the second example. As an experimental result using the amplifier 20 according to the embodiment, an example showing the relationship between the magnitude of the on-resistance of the PMOS transistor 14C and the magnitude of the driving voltage VDD is shown. As shown in FIG. 6, the present inventors set the second condition under the conditions of −45 ° C., an ON voltage magnitude of a predetermined value or more, and a driving voltage magnitude of 2.1V. The magnitude of the on-resistance of the PMOS transistor 14C included in the amplifier 20 according to the embodiment is 1/10 or less of the magnitude of the on-resistance of the PMOS transistor 14C included in the amplifier 10 according to the first embodiment. We have already confirmed that phase compensation has improved.

10, 20 Amplifiers 12, 22 Differential amplifier circuits 12A, 12C, 12D, 12H, 12J, 14A, 14B, 14C, 14H, 14J PMOS transistors 14D, 14E NMOS transistors

Claims (5)

An amplifier including a differential amplifier circuit,
The differential amplifier circuit is:
A pair of transistors with their control terminals connected together;
A first switching element having one end connected to the driving voltage and the other end connected to the control terminal;
A second switching element having one end connected to one drain of the pair of transistors and the other end connected to the control terminal;
A first terminal and a back gate connected to a back gate of the first switching element and supplied with the driving voltage, a second terminal connected to a back gate of the second switching element, and the first switching A third auxiliary transistor having a control terminal to which the control terminal of the element is connected;
A first terminal to which a back gate of the second switching element is connected; a second terminal connected to the one drain; a control terminal to which a control terminal of the second switching element is connected; and a third auxiliary transistor. A fourth auxiliary transistor having a back gate to which the back gate is connected.   2. The amplifier according to claim 1, wherein the back gate of the third auxiliary transistor is connected to the back gate of the fourth auxiliary transistor without passing through the back gate of the second switching element. A differential amplifier circuit;
An output circuit having an output element connected to a control terminal, the output of the differential amplifier circuit,
The output circuit is
A first switching element having one end connected to the driving voltage and the other end connected to the control terminal;
A second switching element having one end connected to the output and the other end connected to the control terminal;
A first terminal and a back gate connected to a back gate of the first switching element and supplied with the driving voltage, a second terminal connected to a back gate of the second switching element, and the first switching A first auxiliary transistor having a control terminal to which the control terminal of the element is connected;
A first terminal to which a back gate of the second switching element is connected; a second terminal to which the output is connected; a control terminal to which a control terminal of the second switching element is connected; and a back gate of the first auxiliary transistor. And a second auxiliary transistor having a back gate connected to the amplifier.   The amplifier according to claim 3, wherein the back gate of the first auxiliary transistor is connected to the back gate of the second auxiliary transistor without passing through the back gate of the second switching element.   A semiconductor device in which the amplifier according to any one of claims 1 to 4 is integrated into one chip.