JP2016015070A - Error detection method and error detection apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily discriminate an address error from a data error, while reducing communication time per data-write operation.SOLUTION: Data in an EEPROM (first memory) is read and stored in an SRAM (second memory) in advance. An address and write data are transmitted to the EEPROM (S701). After the write data is written in the address, the data in the address written in the EEPROM is read (S702) and compared with the write data (S703). When they are not coincident with each other, the read data is compared with data in an address corresponding to the write address in the data stored in the SRAM (S704). When they are coincident with each other, an address error is determined (S705). When they are not coincident with each other, a data error is determined (S707).

Description

  The present invention relates to a detection method and an error detection device for errors that occur when digital data is transmitted.

  Conventionally, when writing digital data to the memory, the address of the write destination (hereinafter referred to as “write destination address”) and the data to be written (hereinafter referred to as “write target”) performed from the transmission side to the memory module (reception side). It is known that errors may occur in the transmission of "data". For example, the digital signal transmitted from the transmission side changes due to noise mixing.

Also, for this error, the write destination address value changes and an address error that causes writing to an address different from the request, and the write target data value changes and data different from the request is written. There are two types of errors: data errors.
As a technique related to such error detection, for example, a technique described in Patent Document 1 is known.

By the way, as a method for detecting an error at the time of data transmission described above, for example, the following method can be considered.
That is, first, the transmission side transmits a write command including a write destination address and write target data to the memory module. Next, the memory module executes data writing based on the write command.

  Next, the transmission side transmits to the memory module a read command requesting to read and transmit data stored in the write destination address in the write command. Then, in response to this read command, the memory module reads the data stored in the write destination address in the write command and transmits it to the transmission side.

The transmission side compares the data to be written in the write command with the data transmitted from the memory module in response to the read command, and determines whether or not the two data match. If the two data do not match, an error has occurred during transmission of the write command.
However, this method has a problem that it is impossible to distinguish whether an address error or a data error has occurred only by knowing whether an error has occurred.

Patent Document 1 discloses the following method that improves this point.
That is, the transmission side microcomputer first sets each instruction to echo back to the reception side EEPROM (Electrically Erasable Programmable ROM), and then transmits an address set instruction for designating the write destination address. Check that the address is correctly specified by echo back.

  If this confirmation can be made, a word write command including data to be written is then transmitted to execute writing, and it is confirmed that this command has also been correctly transmitted by echo back. In any command, when the echoed content is different from the transmitted content, the same command is retransmitted and executed.

  Also, after writing once, the sending side sends the address set command and the word read command again, causing the EEPROM to send the data at the address that was previously written by the word write command, and the data written by this Make sure it matches. Echo back is also confirmed for these address set instructions and word read instructions.

  According to the above method, the word write command is issued after confirming that the write destination address has been correctly transmitted first, and when it is not correctly transmitted, the transmission is performed again. Therefore, the transmission side can recognize (distinguish) whether or not an error has occurred in the transmission of the write destination address or the write target data, and can easily correct this even if a transmission error occurs. it can.

  However, even with the method described in Patent Document 1, there is a problem that the number of times that data needs to be transmitted and received between the transmission side and the reception side for one data writing is large, and communication time is long.

  The present invention solves such a problem and easily separates an address error and a data error while suppressing a communication time per one data write in digital data transmission for writing data into a memory (division). It is intended to be able to be detected separately.

  In order to achieve the above object, the present invention provides an error detection method for detecting an error when writing data to a first memory, and reads at least data in an address range to be written in the first memory, A data holding procedure for storing in a second memory different from the first memory, and a writing procedure for transmitting an address and write target data to the first memory and writing the write target data to the address; A reading procedure for reading data stored in the address transmitted in the writing procedure from the first memory, a data read from the first memory in the reading procedure, and a writing transmitted in the writing procedure. When the comparison result in the first comparison procedure for comparing the target data and the comparison result in the first comparison procedure is inconsistent, the readout procedure reads out the first memory from the first memory. A second comparison procedure for comparing the read data with the data read from the address corresponding to the address transmitted in the writing procedure among the data stored in the second memory in the holding procedure; A determination procedure for determining that an address error has been detected when the comparison result in the comparison procedure is a match, and determining that a data error has been detected when the comparison result is a match;

  According to the above configuration, in digital data transmission for writing data to the memory, it is possible to easily distinguish between an address error and a data error while suppressing a communication time per one data write. Can do.

It is a hardware block diagram of the information processing apparatus which is embodiment of the error detection apparatus of this invention. It is a figure for demonstrating generation | occurrence | production of the error in transmission of digital data. It is a figure explaining the kind of error which may occur at the time of transmission of a write command. It is a figure for demonstrating the error correction which the information processing apparatus shown in FIG. 1 performs. It is a flowchart of the process which CPU of the information processing apparatus shown in FIG. 1 performs at the time of starting. 2 is a flowchart of processing executed by the CPU of the information processing apparatus shown in FIG. 1 when data is written to an EEPROM. It is a figure for demonstrating the error detection by the process of FIG.

EMBODIMENT OF THE INVENTION Hereinafter, the form for demonstrating this invention is demonstrated based on drawing.
FIG. 1 is a hardware configuration diagram of an information processing apparatus which is an embodiment of the error detection apparatus of the present invention.
An information processing apparatus A shown in FIG. 1 includes a microcomputer 10, a nonvolatile memory EEPROM 20, and SCL (Serial Clock Line) 31 and SDA (Serial DAta) which are I2C (Inter-Integrated Circuit) standard buses for connecting them. Line) 32. The microcomputer 10 includes a CPU 101, an SRAM 102, and an internal bus 103.

  Among these, the CPU 101 can access the SRAM 102 via the internal bus 103 to write and read data. In addition, the EEPROM 20 can be accessed via the SCL 31 and the SDA 32 to write and read data. In addition, the CPU 101 controls all processing necessary for error detection when writing data to the EEPROM 20.

The SRAM 102 is a second memory, and has a function of storing and holding at least a copy of data in an address range to be written among data stored in the EEPROM 20.
The internal bus 103 functions as a data transfer path between the CPU 101 and the SRAM 102.

  The EEPROM 20 is a first memory and is a non-volatile memory provided outside the microcomputer 10. Further, it accepts a write command and a read command from the CPU 101, and reads / writes data to / from a data holding unit included in the CPU 101 accordingly. Here, the write command includes a write destination address and write target data, and the read command includes a read destination address (hereinafter referred to as “read destination address”).

The SCL 31 is a bus for transmitting a serial clock signal used for I2C standard data transmission. The SDA 32 is also a bus for transmitting data signals. These buses are capable of transmitting digital data in both directions.
In the I2C standard, a device that starts communication is a master, and a device selected as a communication destination is a slave that simultaneously performs one-to-one communication. In the present embodiment, the microcomputer 10 is a master and the EEPROM 20 is a slave, and the CPU 101 of the microcomputer 10 controls communication.

  One of the characteristic features of the information processing apparatus A described above is processing for error detection related to transmission of a write command from the microcomputer 10 to the EEPROM 20. Therefore, this point will be described below, but before that, errors that may occur regarding this transmission will be described with reference to FIGS.

  FIG. 2 is a diagram for explaining the occurrence of an error in digital data transmission. FIG. 3 is a diagram illustrating the types of errors that can occur during transmission of a write command.

  In the information processing apparatus A, the above write command is transmitted as digital data. As a cause of an error occurring in this transmission, there is a case where noise is mixed in the transmission signal. However, not all noise causes an error, and a problem occurs when noise exceeding the threshold level occurs.

  When digital data is transmitted from the CPU 101 to the EEPROM 20 using the SCL 31 and SDA 32 according to the I2C standard, the CPU 101 sends a clock signal to the SCL 31 and sends a data signal to the SDA 32.

  Then, the EEPROM 20 acquires the value of the data signal of the SDA 32 at the rising edge of the clock signal as the received data. The mixing of noise into the transmission signal becomes a problem when noise exceeding the threshold level is mixed at the rising edge of the clock signal of the SCL 31.

  In the signal example shown in FIG. 2, the CPU 101 transmits a signal “001100...”. That is, the data signal is transmitted so that the data signal transmitted by the SDA 32 becomes “0 (Low)” or “1 (High)” at the rising edge of the clock transmitted by the SCL 31 from p201 to p206.

In the example of FIG. 2, since no noise is mixed in at timings p201, p202, p203, and p205 among p201 to p206, data is correctly transmitted.
Although noise is mixed at p207 and p208, since the EEPROM 20 receives the signal at the rise of the SCL 31, these noises have no influence on the digitally transmitted signal value.

  On the other hand, at the timing of p204 and p206, noise is mixed when the SCL 31 rises, and the noise exceeds the threshold level. Therefore, noise affects the data signal, and data is not transmitted correctly. The EEPROM 20 acquires “1” as “0” at the timing of p204, and acquires “0” as “1” at the timing of p206.

  For this reason, the EEPROM 20 determines that the received data is “001001...”. The fourth bit and the sixth bit are different from the data transmitted by the CPU 101. This is the cause of errors in digital data transmission.

  Incidentally, when data is written from the CPU 101 to the EEPROM 20, for example, the CPU 101 first accesses the SRAM 102 via the internal bus 103, and acquires write target data temporarily stored in the SRAM 102.

  Next, the CPU 101 designates a write destination address to the EEPROM 20 and issues a write command to write the write target data. This write command includes information of a write destination address and write target data. The EEPROM 20 writes the write target data at the address designated by the CPU 101 in accordance with the received write command.

  In the example of FIG. 3, the CPU 101 transmits a write command including a write destination address “0x02” and write target data “0x11” to the EEPROM 20. A state 301 in which the write command is normally performed is state 301.

  However, an error as described with reference to FIG. 2 may occur when a write command is transmitted. An error occurs in transmission of the write destination address included in the write command, that is, an address error occurs, and the write target data “0x11” is generated at an address “0x00” different from the write destination address included in the write command. The state 302 has been written is the state 302.

  On the other hand, an error occurs in transmission of the write target data included in the write command, that is, a data error occurs, and data “0x00” different from the write target data included in the write command is the write destination address. The state 303 has been written to “0x02”.

  As described in the background art section, such an error occurs when the CPU 101 issues a write command to the EEPROM 20 and then sends a read command in which the same address as the write destination address is designated as the read destination address to the EEPROM 20. By transmitting, it can be detected once.

  That is, if the write target data included in the write command matches the read data transmitted in response to the read command, it can be determined that no error has occurred. On the other hand, if the two data do not match, an error has occurred.

  In the example of FIG. 3, in the state 301 in which no error has occurred, the data “0x11” read from the write destination address “0x02” included in the write command is the write target data included in the write command. Matches. However, in the states 302 and 303 in which an error has occurred, the data read from the same address is “0xd5” and “0x10”, which do not match the write target data included in the write command.

  In this error detection method, if there is a data mismatch, it can be determined that there is an error, and even if an address error or a data error occurs, even if the error reaches multiple bits or multiple bytes, writing is successful. Can be detected. However, whether the data does not match because the data was written to an address different from the address requested by the write command (address error) or the address where the data was written is correct, but the written data is requested by the write command. It is not possible to determine whether the data does not match due to the difference from the data (data error).

Next, FIG. 4 shows an outline of address error and data error correction processing.
FIG. 4 shows a process for correcting an error occurring in the states 302 and 303 shown in FIG.

  First, in the case of a data error in the state 303, the same command as the write command that was not normally written is transmitted to the EEPROM 20, and the same write target data “0x11” is again transmitted to the same write destination address “0x02”. Should be written. A state 402 is a state in which the writing is normally performed. When a data error occurs, correction is easily completed in this way.

  On the other hand, even in the case of an address error in the state 302, writing to the same write destination address is performed in the same manner. The state 401 is a case where this writing has been performed correctly, but the write target data “0x11” is still written to an address “0x00” that is different from the write destination address included in the first write instruction. It is in.

  Therefore, as in the state 403, it is necessary to correct the data “0x11” written in the address “0x00” to the original data “0x2b”. Here, in the first place, since the CPU 101 has not been able to detect the address at which the write target data included in the write command is written (an address different from the write destination address in the write command), first, the written address Need to explore. However, when an address error occurs, the written address candidates are all the addresses of the EEPROM 20, and enormous time is required to specify them.

  As described above, the address error correction process takes much longer time than the data error correction process. However, the error detection method of FIG. 3 cannot distinguish between an address error and a data error as described above. Therefore, when an error occurs, even if no address error has occurred, an address error correction process is performed, and the correction process takes a very long time.

  Therefore, in the information processing apparatus A of the present embodiment, the error detection method capable of distinguishing the address error and the data error described above is executed. As a result, the correction processing of the address error with a high processing load may be performed only when an address error occurs, and the data error correction processing may be performed when a data error occurs. Hereinafter, the procedure of this error detection method will be described with reference to FIGS. The procedure described below is an embodiment of the error detection method of the present invention.

First, FIG. 5 shows a flowchart of processing executed by the CPU 101 at startup.
The CPU 101 starts the processing shown in the flowchart of FIG. 5 when the information processing apparatus A is started by turning on or resetting the information processing apparatus A.

  In the process of FIG. 5, the CPU 101 first performs a process necessary for starting the system used for controlling the information processing apparatus A (S601). Thereafter, the data stored at a predetermined address is read from the EEPROM 20 (S602), the read data is stored in the SRAM 102 (S603), and the process is terminated. The processing of these steps S602 and S603 is processing of a data holding procedure, and the CPU 101 functions as data holding means in these processing.

Note that the range of data read in step S602 is data in an address range that is assumed to be a writing target at least during the operation of the information processing apparatus A among the data stored in the EEPROM 20. If data in this range is read at a minimum, the comparison in step S704 in FIG. 6 described later can be performed without any problem, and if the amount of data to be read can be reduced, the processing time can be shortened. However, it is not hindered to read all data without paying particular attention to the writing range.
In addition, the reason why the processing of step S602 is performed at the time of starting is that, when the system is started up, devices having elements that may cause noise such as motors are often not operating yet, so relatively noise is mixed in the signal. Because it is difficult to do. Here, the time of system startup includes not only when the power is turned on but also restart after reset.

  Further, data storage in the SRAM 102 in step S603 may be performed once at the time of activation. Thereafter, as will be described later with reference to FIG. 6, in order to make the contents of the EEPROM 20 and the SRAM 102 coincide with each other, the contents of the SRAM 102 are rewritten in accordance with each rewriting of the contents of the EEPROM 20. However, the processing of steps S602 and S603 is executed again at an appropriate timing, or the processing of steps S602 and S603 is executed for a new region at the timing of writing to the region of the EEPROM 20 that has not been read at step S602. It is not hindered to do. However, in this case as well, it is desirable to execute this processing when the information processing apparatus A is in an operation state in which noise is unlikely to be mixed as described above.

Next, FIG. 6 shows a flowchart of processing executed by the CPU 101 when data is written to the EEPROM 20.
The CPU 101 starts the process shown in the flowchart of FIG. 6 when writing data to the EEPROM 20. It is assumed that the write destination address and the write target data are specified at the start of this process. In addition, here, the processing of FIG. 6 is executed every time writing to one address is performed, but the configuration in which the same processing is executed collectively for a plurality of addresses is not hindered.

  In the process of FIG. 6, the CPU 101 first transmits a write command including a write destination address and write target data to the EEPROM 20 (S701). In response to this write command, the EEPROM 20 writes the write target data to the write destination address included in the write command in response to a request for the write command in its own storage area. However, at this time, an error may occur in the transmission of the write command, and the writing may not be performed according to the command transmitted by the CPU 101. The process in step S701 described above is the process of the writing procedure, and the CPU 101 functions as a writing unit in this process.

Next, CPU 101 transmits a read command to EEPROM 20 that instructs reading of data stored in the address transmitted as the write destination address in step S701 (designating the write destination address as the read destination address). (S702). In response to this read command, the EEPROM 20 reads the data stored in the read destination address in its own storage area and transmits it to the CPU 101. The processing in step S702 described above is the reading procedure, and the CPU 101 functions as a reading unit in this processing.
Next, the CPU 101 compares whether the write target data transmitted to the EEPROM 20 in step S701 matches the data read in step S702 (S703). This process is a process of the first comparison procedure. In this process, the CPU 101 functions as a first comparison unit.

  As a result of the comparison in step S703, if the two data match, it is considered that the writing according to the writing command transmitted in step S701 was correctly performed. Therefore, the CPU 101 ends the processing related to writing and updates the data stored in the SRAM 102 in accordance with the change of the data stored in the EEPROM 20 (S709).

  Specifically, the data at the address corresponding to the write destination address transmitted at step S701 in the SRAM 102 is rewritten to the write target data (or data read according to the read command) transmitted at step S701. With the above update, even when the data content of the EEPROM 20 is changed, the data in the EEPROM 20 and the data in the SRAM 102 can be kept in agreement.

In the next process of FIG. 6 as well, the data in the SRAM 102 can be used for comparison in step S704 described later.
The process in step S709 described above is an update procedure process, and the CPU 101 functions as an update unit in this process. Further, the processing shown in the flowchart of FIG. 6 is ended up to step S709.

  On the other hand, if the data read in step S702 and the write target data transmitted in step S701 do not match, it is considered that some error has occurred in the data writing. However, at this stage, it is unknown whether a data error or an address error has occurred.

  Therefore, in this case (NO in S703), the CPU 101 stores the data read in step S702 and the data stored in the address corresponding to the write destination address transmitted in step S701 among the data stored in the SRAM 102 in step S603. Are compared (S704). The latter data is the data read from the write destination address of the EEPROM 20 in step S602 and stored in the SRAM 102, or the updated data obtained by updating this data in step S708. This process is a process of the second comparison procedure. In this process, the CPU 101 functions as a second comparison unit.

  If the data match in this comparison (YES in S704), the data at the write destination address at the time of the write command in the EEPROM 20 is not changed from that before the execution of the write, so that the write to the correct address is not performed. I understand that. Therefore, the CPU 101 determines that an address error has occurred (S705), and performs an address error correction process (S706). As the address error correction process, a known process may be applied as appropriate, including the one described with reference to FIG.

  On the other hand, if they do not match in step S704 (NO in S704), it can be determined that the data in the write destination address at the time of the write command has been rewritten in the EEPROM 20 itself. Therefore, when combined with the comparison result in step S703, the write target data transmitted in step S701 is different. Therefore, the CPU 101 determines that a data error has occurred (S707), and performs a data error correction process (S708). As for the data error correction process, a known process may be applied as appropriate, including the one described with reference to FIG. The procedure of steps S704, S705, and S707 is a determination procedure process for detecting an error by separating an address error and a data error. In this process, the CPU 101 functions as a determination unit.

  Although detailed illustration is omitted, as described with reference to FIG. 4, the error correction processing in step S706 or S708 is performed at the correct write destination address (the write data included in the write command). Including a destination address and data to be written). At the end of this process, it is confirmed by the same procedure as in steps S702 to S704 that the writing has been performed correctly. After step S706 or S708, as in the case of Yes in step S703, the CPU 101 updates the data stored in the SRAM 102 (S709) and ends the process.

Here, a specific example of error detection by the processing of FIG. 6 will be described with reference to FIG.
Prior to performing the processing in FIG. 6, the CPU 101 executes the processing in steps S <b> 601 to S <b> 603 in FIG. 5 when the information processing apparatus A is activated, reads out the data stored in the EEPROM 20, and stores it in the SRAM 102.

  Thereafter, when the CPU 101 operates in accordance with an application program or the like, it is necessary to write data to the EEPROM 20. In this case, the write target data “0x11” scheduled to be written this time is stored in the SRAM 102, and the write target address (here, “0x02”) is also determined.

Then, the CPU 101 transmits a write command for instructing to write the write target data “0x11” to the write destination address “0x02” to the EEPROM 20 in step S701 in FIG.
Then, an address error occurs during transmission of the write command, and the write target data “0x11” is written to the address “0x00” different from the write destination address “0x02” included in the write command in state 302. (This is the same as the example of FIG. 3).

  In this state, when the CPU 101 transmits a read command of data at the write destination address “0x02” included in the write command to the EEPROM 20 in step S702, the data of “0xd5” is returned from the EEPROM 20. In step S703, the CPU 101 compares this “0xd5” with the write target data “0x11” included in the write command transmitted in step S701. Here, since there is a mismatch, the CPU 101 detects the occurrence of an error.

  Next, in step S704, the CPU 101 reads out the data “0xd5” and the address corresponding to the write destination address “0x02” included in the write instruction in step S701 among the data stored in the SRAM 102 (FIG. The data “0xd5” in FIG.

  Here, since both data match, the data stored in the write destination address of the EEPROM 20 when the write command is issued is not rewritten even after the write command is transmitted. Therefore, the writing is performed to an address different from the write destination address included in the write command transmitted in step S701, and the CPU 101 determines that an address error has occurred (S705). Therefore, the CPU 101 performs the address error correction process in step S706, and updates the data stored in the SRAM 102 after the correction (S709).

  On the other hand, an address error occurred during transmission of the write command in step S701, and data “0x10” different from the write target data “0x11” specified in the write destination address “0x02” included in the write command was written. Is the state 303 (this is the same as the example of FIG. 3).

  In this state, when the CPU 101 transmits a read command of data at the write destination address “0x02” included in the write command transmitted in step S701 to the EEPROM 20 in step S702, the EEPROM 20 receives “0x10”. Data is returned. In step S703, the CPU 101 compares this “0x10” with the write target data “0x11” when the write command is issued in step S701. Again, since there is a mismatch, the CPU 101 detects the occurrence of an error.

  Next, in step S704, the CPU 101 reads the data “0x10” read in step S702 and the address corresponding to the write destination address “0x02” at the time of the write command out of the data stored in the SRAM 102 (in the drawing). Compared with data “0xd5” (shown by a thick frame).

  Here, both data are inconsistent. That is, although the address where the data is written by the write command is not wrong, data different from the write target data in the write command is written. For this reason, the CPU 101 determines that a data error has occurred (S707). Therefore, the CPU 101 performs the data error correction process in step S708, and updates the data stored in the SRAM 102 after correction (S709).

  As described above, according to the processing of FIG. 6, the data actually written in the write destination address included in the write command performed in step S701 in the EEPROM 20 is the write target included in the write command. If the data does not match, it is further compared with the corresponding data stored in the SRAM 102 in advance. Thereby, an address error and a data error can be distinguished and detected.

  The process required for this distinction is only the comparison process in step S104 if the data in the EEPROM 20 is first copied to the SRAM 102. Further, it may be performed only when an error is detected in step S103. Therefore, the communication time per data write for error detection does not increase greatly.

  Further, if an address error and a data error can be distinguished as described above, an address error correction process with a large processing load may be performed only when an address error is detected. When a data error is detected, it is only necessary to perform a data error correction process equivalent to the retry of writing. Therefore, efficient error detection and correction can be realized.

In the description of FIGS. 6 and 7, errors that occur during transmission of a read command (particularly, a read destination address) and transmission of data read in accordance therewith are not considered. However, even if this is taken into consideration, the effects described with reference to FIGS. 6 and 7 can be obtained without problems.
First, when an error occurs in the transmission of the read destination address or the read data, there is no error in the transmission of the write command, and even when the writing is correctly executed in the EEPROM 20, the determination in step S703 in FIG.

  However, even if such a situation occurs, the determination in the next step S704 is basically No. This is because the data read from the wrong read destination address mixed with an error or the data read erroneously mixed with an error happens to coincide with the correct data in the SRAM 102.

  Therefore, even if the transmission of the data of the write command is erroneously detected due to an error in the transmission of the read command or the read data, the error correction performed in accordance with the data is not time consuming. In most cases, error correction is performed. This data error correction is also a process of overwriting correct data on the write destination address, so there is no inconvenience even if it is performed while correct data is written. Therefore, even if some erroneous detection occurs, the effect described with reference to FIGS. 6 and 7 can be obtained without any problem.

  It is rare that an error occurs in both transmission of a read command (and read data) and transmission of a write command in view of error frequency in general data transmission. Therefore, even if this case is not taken into consideration, there is generally no particular problem with the operation of the apparatus.

  In particular, when it is desired to reduce false detections, it is possible to consider a case in which the same instruction is transmitted twice for the read instruction, and when both read results match, there is no error and the process proceeds to the next process. However, considering the communication time, such a response is not necessarily desirable, and it is considered that it should be adopted only when it is particularly desired to reduce the probability of erroneous detection.

  This is the end of the description of the embodiment. In the present invention, the specific configuration of the apparatus, the configuration of circuits and elements, the specific processing procedure, the data storage format, and the like are limited to those described in the embodiment. It is not a thing.

  For example, in the above-described embodiment, the external bus of the I2C standard is used for communication (digital transmission) between the CPU 101 and the EEPROM 20, but the present invention is not limited to this, and a bus of another standard may be used. Good. Further, the transmission path is not limited to two communication methods. Further, the SRAM 102 and the EEPROM 20 are not limited to these, and other memories may be used.

  Of course, the error detection device may have functions other than the data reading / writing and error detection described with reference to FIGS. For example, in an image processing apparatus having any one of functions such as copying, printing, scanning, facsimile communication, and image storage, the control unit performs data reading / writing and error detection described with reference to FIGS. What has a function is also an embodiment of the error detection apparatus of the present invention.

Further, the present invention can be implemented as such an image processing apparatus. In addition to the image processing apparatus, the present invention can be applied to any electronic apparatus in which a control unit such as a CPU writes data to a memory.
Moreover, it is needless to say that the configurations of the embodiment and the modified examples described above can be arbitrarily combined and implemented as long as they do not contradict each other.

A: Information processing apparatus, 10: Microcomputer, 101: CPU, 102: SRAM, 103: Internal bus, 20: EEPROM, 31: SCL, 32: SDA

JP-A-6-303222

Claims (4)

An error detection method for detecting an error when writing data to a first memory,
A data holding procedure for reading at least data in an address range to be written in the first memory and storing the data in a second memory different from the first memory;
A write procedure for sending an address and write target data to the first memory, and writing the write target data to the address;
A reading procedure for reading data stored in the address transmitted in the writing procedure from the first memory;
A first comparison procedure for comparing the data read from the first memory in the read procedure with the write target data transmitted in the write procedure;
Of the data read from the first memory in the reading procedure and the data stored in the second memory in the holding procedure when the comparison result in the first comparison procedure is inconsistent, the writing procedure A second comparison procedure for comparing the address transmitted in step 1 and the data read from the corresponding address;
An error comprising: a determination procedure for determining that an address error has been detected when the comparison result in the second comparison procedure is a match, and a determination that a data error has been detected when the comparison result is a mismatch. Detection method. The error detection method according to claim 1,
An error detection method, wherein the data holding procedure is executed when a system including control means for writing data to the first memory, the second memory, and the first memory is started. The error detection method according to claim 1 or 2,
When the comparison result in the first comparison procedure is coincident, the data read from the address corresponding to the address transmitted in the writing procedure among the data stored in the second memory in the holding procedure, An error detection method, further comprising an update procedure for updating the data read from the first memory in the read procedure. An error detection device for detecting an error when writing data to a first memory,
Data holding means for reading at least data in an address range to be written in the first memory and storing the data in a second memory different from the first memory;
Writing means for transmitting an address and write target data to the first memory, and writing the write target data to the address;
Reading means for reading data stored in the address transmitted by the writing means from the first memory;
First comparison means for comparing the data read by the reading means from the first memory with the write target data transmitted by the writing means;
Of the data read from the first memory by the reading means and the data stored in the second memory by the data holding means when the comparison result by the first comparing means is inconsistent, the writing means A second comparison means for comparing the address read by the data read from the corresponding address;
An error detection comprising: determination means for determining that an address error has been detected when the comparison result by the second comparison means is coincident, and for determining that a data error has been detected if the comparison result is inconsistent apparatus.

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