JP2016006909A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the performance of a semiconductor device.SOLUTION: A semiconductor device has a gate electrode GE formed through a gate insulation film GI on a substrate; and a semiconductor layer EP1 for a source and drain formed on the substrate. A top surface of the semiconductor layer EP1 is at a position higher than a top surface of the substrate just below the gate electrode GE. An edge of the gate electrode GE in a gate length direction is positioned on the semiconductor layer EP1.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and can be suitably used for, for example, a semiconductor device including a MISFET and a manufacturing method thereof.

  A MISFET is formed by forming a gate electrode on a substrate via a gate insulating film and forming source / drain regions on the substrate.

  There is also a technique for forming a MISFET by growing an epitaxial layer for source / drain on a substrate.

  Japanese Patent Application Laid-Open No. 2000-277745 (Patent Document 1) discloses a technique related to a double gate MOSFET using an SOI substrate.

  In Japanese Patent Application Laid-Open No. 2007-165665 (Patent Document 2), a p-channel MISFET is formed on a Si substrate. A technique is disclosed in which grooves are formed in regions serving as the source and drain of a p-channel MISFET, and a SiGe layer is embedded in the grooves by an epitaxial growth method.

JP 2000-277745 A JP 2007-165665 A

  When forming a semiconductor layer for source / drain on a substrate, it is desired to improve the performance as much as possible for a semiconductor device in which a MISFET is formed by using, for example, an epitaxial growth method or the like. Alternatively, it is desired to improve the reliability of the semiconductor device. Alternatively, it is desirable to realize both.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, a semiconductor device has a source / drain semiconductor layer formed on a substrate, and an end of the gate electrode in the gate length direction runs over the semiconductor layer.

  According to one embodiment, a method for manufacturing a semiconductor device includes forming a dummy gate on a substrate, and then forming a semiconductor layer for forming a source / drain on the substrate by, for example, an epitaxial method. A sidewall film is formed on the sidewall of the dummy gate. Then, an insulating film is formed on the substrate so as to cover the dummy gate, and then the upper surface of the dummy gate is exposed. Then, a gate electrode is formed through a gate insulating film in a groove formed by removing the dummy gate and the side wall film.

  According to one embodiment, the performance of a semiconductor device can be improved. Alternatively, the reliability of the semiconductor device can be improved. Alternatively, both can be realized.

2 is a main-portion cross-sectional view of the semiconductor device of First Embodiment; FIG. 2 is a main-portion cross-sectional view of the semiconductor device of First Embodiment; FIG. FIG. 6 is a process flow diagram showing a manufacturing process of the semiconductor device of First Embodiment; FIG. 6 is a process flow diagram showing a manufacturing process of the semiconductor device of First Embodiment; 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 6 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 5; FIG. FIG. 7 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 6; FIG. 8 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 7; FIG. 9 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 8; FIG. 10 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 9; FIG. 11 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 10; FIG. 12 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 11; FIG. 13 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 12; FIG. 14 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 13; FIG. 15 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 14; FIG. 16 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 15; FIG. 17 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 16; FIG. 18 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 17; FIG. 19 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 18; FIG. 20 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 19; FIG. 20 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 19; FIG. 22 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 21; FIG. 23 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 22; FIG. 24 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 20 and FIG. 23; FIG. 25 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 24; FIG. 26 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 25; FIG. 27 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 26; FIG. 28 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 27; FIG. 29 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 28; It is principal part sectional drawing of the semiconductor device of a 1st examination example. It is principal part sectional drawing of the semiconductor device of a 1st examination example. It is principal part sectional drawing in the manufacturing process of the semiconductor device of a 2nd examination example. FIG. 33 is an essential part cross sectional view of the semiconductor device of the second examination example following FIG. 32 during the manufacturing step; It is principal part sectional drawing of the semiconductor device of the 2nd examination example. It is principal part sectional drawing of the semiconductor device of the 2nd examination example. FIG. 10 is a main-portion cross-sectional view of the semiconductor device of the modification example of the first embodiment. FIG. 10 is a main-portion cross-sectional view of the semiconductor device of the modification example of the first embodiment. FIG. 10 is a main-portion cross-sectional view of the semiconductor device of the modification example of the first embodiment during the manufacturing process; FIG. 10 is a fragmentary cross-sectional view of the semiconductor device of Second Embodiment during a manufacturing step thereof. FIG. 40 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 39; FIG. 41 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 40; FIG. 42 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 41; FIG. 43 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 42; FIG. 44 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 43; FIG. 45 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 44; FIG. 10 is a process flow diagram showing a manufacturing process of the semiconductor device of Third Embodiment. FIG. 10 is a process flow diagram showing a manufacturing process of the semiconductor device of Third Embodiment. FIG. 10 is a fragmentary cross-sectional view of the semiconductor device of Third Embodiment during a manufacturing step thereof. FIG. 49 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 48; FIG. 50 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 49; FIG. 51 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 50; FIG. 52 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 51; FIG. 53 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 52; FIG. 54 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 53; FIG. 55 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 54; FIG. 56 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 55; FIG. 57 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 56; FIG. 57 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 56; FIG. 59 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 58; FIG. 60 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 59; FIG. 61 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIGS. 57 and 60; FIG. 62 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 61; FIG. 63 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 62; FIG. 10 is a main-portion cross-sectional view of the semiconductor device of Embodiment 3; FIG. 10 is a main-portion cross-sectional view of the semiconductor device of Embodiment 3; FIG. 10 is a process flow diagram showing a manufacturing process of a semiconductor device of Embodiment 4; FIG. 10 is a process flow diagram showing a manufacturing process of a semiconductor device of Embodiment 4; FIG. 24 is an essential part cross-sectional view during a manufacturing step of the semiconductor device of the fourth embodiment. FIG. 69 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 68; FIG. 70 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 69; FIG. 71 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 70; FIG. 72 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 71; FIG. 73 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 72; FIG. 74 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 73; FIG. 75 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 74; FIG. 76 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 75; FIG. 77 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 76; FIG. 77 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 76; FIG. 79 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 78; FIG. 80 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 79; FIG. 81 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIGS. 77 and 80; FIG. 82 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 81; FIG. 83 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 82; FIG. 10 is a main-portion cross-sectional view of the semiconductor device of Embodiment 4;

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  In the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view so as to make the drawings easy to see. Further, even a plan view may be hatched to make the drawing easy to see.

(Embodiment 1)
<Structure of semiconductor device>
1 and 2 are cross-sectional views of main parts of the semiconductor device according to the first embodiment. 1 and 2 are cross-sectional views of the same region. However, in FIG. 1, the entire semiconductor layer EP1 is indicated by hatching of dots and the entire semiconductor layer SM1 is indicated by hatching of thin lines so that it can be easily understood which region the semiconductor layer SM1 and the semiconductor layer EP1 are. The n ⁻ type semiconductor region EX and the formation region of the n ⁺ type semiconductor region SD are not shown. Further, in FIG. 2, n ^- -type semiconductor region EX and the n ⁺ -type semiconductor region and are so easy to understand whether any respective region SD, n ^- given the same hatching in the entire -type semiconductor regions EX, n ⁺ -type The same hatching is given to the entire semiconductor region SD. Therefore, when FIG. 1 and FIG. 2 are taken together, the configuration of the semiconductor layer SM1 and the semiconductor layer EP1, and the formation region of the n ⁻ type semiconductor region EX and the n ⁺ type semiconductor region SD in the semiconductor layer SM1 and the semiconductor layer EP1 Easy to understand. In FIGS. 1 and 2, the illustration of an insulating film IL3 and wiring M1, which will be described later, and the upper layer structure thereof are omitted.

  The semiconductor device according to the first embodiment and the following second to fourth embodiments is a semiconductor device including a MISFET (Metal Insulator Semiconductor Field Effect Transistor).

  The semiconductor device of the first embodiment shown in FIG. 1 and FIG. 2 is a semiconductor device using an SOI (SOI: Silicon On Insulator) substrate SUB.

  The SOI substrate SUB includes a substrate (semiconductor substrate, support substrate) SUB1 made of single crystal silicon or the like, and an insulating layer (buried insulating film, buried oxide film, BOX (BOX) (formed on the main surface of the substrate SUB1). (Bried Oxide) layer) BOX1 and a semiconductor layer (SOI layer) SM1 made of single crystal silicon formed on the upper surface of the insulating layer BOX1. The substrate SUB1 is a support substrate that supports the insulating layer BOX1 and the structure above it. The SOI substrate SUB is formed by the substrate SUB1, the insulating layer BOX1, and the semiconductor layer SM1. A MISFET is formed on the main surface of the SOI substrate SUB. Here, a case where the MISFET is an n-channel MISFET will be described.

  A gate electrode GE is formed on the semiconductor layer SM1 via the gate insulating film GI.

  The gate electrode GE is made of a metal such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium carbide (TiC), tantalum carbide (TaC), tungsten carbide (WC), or tantalum nitride carbide (TaCN). A metal gate electrode (metal gate electrode) using a material is used. In addition, the metal said here means the conductor which shows metal conduction, and contains not only a single metal (pure metal) and an alloy but the metal compound (metal nitride, metal carbide, etc.) which shows metal conduction. By using the gate electrode GE as a metal gate electrode, the depletion phenomenon of the gate electrode GE can be suppressed and the parasitic capacitance can be eliminated. Further, there is an advantage that the MISFET element can be miniaturized (the gate insulating film can be thinned).

  As the gate electrode GE, a metal gate electrode is preferable, but as another form, a stacked gate in which the metal material (metal film) is formed in a lower layer and a polysilicon film (doped polysilicon film) is used as an upper layer. It can also be an electrode.

  As another form of the metal gate electrode (gate electrode GE), a structure in which a plurality of different metal films are stacked may be employed.

  In addition, as the gate insulating film GI, a metal oxide film such as a hafnium oxide film, a zirconium oxide film, an aluminum oxide film, a tantalum oxide film, or a lanthanum oxide film can be used. One or both of nitrogen (N) and silicon (Si) can also be contained. In this case, the gate insulating film GI is a high dielectric constant film (so-called High-k film) having a dielectric constant (relative dielectric constant) higher than that of the silicon nitride film. When a high dielectric constant film is used for the gate insulating film GI, the physical film thickness of the gate insulating film GI can be increased as compared with the case where a silicon oxide film is used, so that the leakage current can be reduced. Can be obtained.

  Although not shown, a silicon oxide film having a thickness of 1 nm or less can be formed as an interface layer between the metal oxide film and the semiconductor layer SM1. The physical thickness of the interface layer is formed thinner than the physical thickness of the metal oxide film.

  The semiconductor layer SM1 below the gate electrode GE becomes a region where a channel of the MISFET is formed (channel formation region).

  A semiconductor layer EP1 that is an epitaxial layer (epitaxial semiconductor layer) is formed on the semiconductor layer SM1. The semiconductor layer EP1 is formed by epitaxial growth on the semiconductor layer SM1, and is made of silicon (single crystal silicon).

  The semiconductor layer EP1 is formed on both sides of the gate electrode GE (on both sides in the gate length direction). 1 and 2 is a plane parallel to the gate length direction of the gate electrode GE (a plane along the gate length direction).

  In the present embodiment, a part of the gate electrode GE exists on the semiconductor layer EP1 (more specifically, on the inclined side surface SF1 of the semiconductor layer EP1). Specifically, the end of the gate electrode GE in the gate length direction is located on the semiconductor layer EP1. In other words, the end of the gate electrode GE is located on the semiconductor layer EP1 in the gate length direction of the MISFET (MISFET having the gate electrode GE as the gate electrode). That is, the central portion side of the gate electrode GE in the gate length direction is on the semiconductor layer SM1 where the semiconductor layer EP1 is not formed, but both end portions of the gate electrode GE in the gate length direction are on the semiconductor layer SM1. The semiconductor layer EP1 is formed on the semiconductor layer EP1. That is, the central portion side (the central portion side in the gate length direction) of the gate electrode GE does not overlap the semiconductor layer EP1 (does not overlap in the thickness direction of the SOI substrate SUB), but the end portion (gate length) of the gate electrode GE. The end in the direction) overlaps the semiconductor layer EP1 (overlaps in the thickness direction of the SOI substrate SUB). For this reason, the semiconductor layer EP1 exists immediately below both ends of the gate electrode GE (near both ends in the gate length direction), and immediately below the center of the gate electrode GE (center of the gate length). The semiconductor layer EP1 is not present (the semiconductor layer SM1 is present).

  However, the gate electrode GE is not in contact with the semiconductor layers SM1 and EP1, and the gate insulating film GI is interposed between the gate electrode GE and the semiconductor layer SM1 and between the gate electrode GE and the semiconductor layer EP1. . The gate insulating film GI is continuously formed from the bottom surface of the gate electrode GE to both side surfaces (side walls).

  In the present embodiment, the end of the gate electrode GE in the gate length direction is located on the semiconductor layer EP1, but the side surface (side surface on the gate electrode GE side) SF1 of the semiconductor layer EP1 is inclined. The end of the gate electrode GE in the gate length direction is located on the inclined side surface SF1 of the semiconductor layer EP1. In other words, the side surface (side surface on the gate electrode GE side) SF1 of the semiconductor layer EP1 is inclined in the gate length direction of the MISFET (MISFET having the gate electrode GE as the gate electrode), and the MISFET (the gate electrode GE is used as the gate electrode). In the gate length direction of MISFET, the end of the gate electrode GE is located on the inclined side surface SF1 of the semiconductor layer EP1. That is, the end portion (end portion in the gate length direction) of the gate electrode GE rides on the inclined side surface SF1 of the semiconductor layer EP1.

  Further, since the semiconductor layer EP1 is formed on the substantially flat upper surface of the semiconductor layer SM1, the upper surface of the semiconductor layer EP1 is higher than the upper surface of the semiconductor layer SM1 directly below the gate electrode GE. Here, the upper surface of the semiconductor layer SM1 immediately below the gate electrode GE corresponds to the surface (upper surface) of the semiconductor layer SM1 in contact with the gate insulating film GI below the gate electrode GE. In FIG. It is shown as an upper surface UF1.

A semiconductor region for the source or drain of the MISFET is formed in the semiconductor layers SM1 and EP1 on both sides of the gate electrode GE (both sides in the gate length direction). The semiconductor region for the source or drain is an n ⁻ type semiconductor. The region EX and the n ⁺ type semiconductor region SD having a higher impurity concentration than the n ⁻ type semiconductor region EX are formed. That is, in the stack of the semiconductor layer SM1 and the semiconductor layer EP1, (a pair of) n ⁻ type semiconductor regions (extension regions, LDD regions) EX are formed in regions separated from each other with the channel formation region interposed therebetween, and the n ⁻ type Outside the semiconductor region EX (on the side away from the channel formation region), a (pair) n ⁺ type semiconductor region SD for source / drain having a higher impurity concentration than the n ⁻ type semiconductor region EX is formed. Since the semiconductor region for the source or drain region has an n ⁻ type semiconductor region EX and an n ⁺ type semiconductor region SD having a higher impurity concentration than the n ⁻ type semiconductor region EX, an LDD (Lightly Doped Drain) structure It has.

The n ⁻ type semiconductor region EX is adjacent to the channel formation region, and the n ⁺ type semiconductor region SD is separated from the channel formation region by the n ⁻ type semiconductor region EX and is in contact with the n ⁻ type semiconductor region EX. Is formed.

When viewed in the thickness direction of the SOI substrate SUB, the n ⁻ type semiconductor region EX is formed from the semiconductor layer EP1 to the semiconductor layer SM1, and the n ⁺ type semiconductor region SD is also formed from the semiconductor layer EP1 to the semiconductor layer SM1. Yes. Further, at least a part of the n ⁻ type semiconductor region EX is located immediately below the gate electrode GE.

Since a semiconductor region for source or drain (corresponding to the n ⁻ type semiconductor region EX and the n ⁺ type semiconductor region SD) is formed in the semiconductor layer EP1, the semiconductor layer EP1 is used for source / drain (source / drain). It can be regarded as an epitaxial layer.

A metal silicide layer SIL is formed on the n ⁺ type semiconductor region SD. The metal silicide layer SIL is, for example, a cobalt silicide layer, a nickel silicide layer, or a nickel platinum silicide layer.

  Over the main surface of the SOI substrate SUB, an insulating film IL1 is formed so as to cover the semiconductor layer EP1 (and the metal silicide layer SIL). The insulating film IL1 is preferably a laminated film of a silicon nitride film (liner film) SN3 that is a liner film and an insulating film SO3 on the silicon nitride film SN3. The thickness of the silicon nitride film SN3 is thinner than the insulating film SO3.

  As the insulating film SO3, a silicon oxide insulating film can be used. Here, the silicon oxide-based insulating film is an insulating film mainly composed of silicon oxide, and among carbon (C), fluorine (F), nitrogen (N), boron (B), and phosphorus (P). One or more of these can also be contained.

  The upper surface of the insulating film IL1 is substantially flattened, and a trench TR is formed in the insulating film IL1. A gate electrode GE is embedded (formed) in the trench TR via the gate insulating film GI. That is, the gate electrode GE is formed in the trench TR of the insulating film IL1, and the gate insulating film GI is continuously formed on the side wall (side surface) and the bottom surface (lower surface) of the gate electrode GE.

  That is, in the present embodiment, the insulating film IL1 is formed over the SOI substrate SUB so as to cover the semiconductor layer EP1, and the gate electrode GE is embedded in the trench TR formed in the insulating film IL1. Yes. Specifically, the gate insulating film GI is formed on the side surface and the bottom surface of the trench TR, and the gate electrode GE is embedded in the trench TR via the gate insulating film GI.

  Preferably, the sidewall insulating film SW3 is formed on the sidewall of the gate electrode GE via the gate insulating film GI. That is, not only the gate insulating film GI but also the side wall insulating film SW3 is interposed between the side wall of the gate electrode GE and the insulating film IL1. The gate insulating film GI is in contact with the gate electrode GE, but the side wall insulating film SW3 is not in contact with the gate electrode GE, and the gate insulating film GI is between the side wall insulating film SW3 and the gate electrode GE. Intervene.

  On the insulating film IL1 in the state where the gate electrode GE is embedded, an insulating film IL2 is formed so as to cover the gate electrode GE.

  A contact hole CNT (not shown here) described later is formed in the insulating films IL1 and IL2, and a plug PG (not shown here) is formed in the contact hole CNT. Illustration is omitted. An insulating film IL3 (not shown here) and a wiring M1 (not shown here) described later are formed on the insulating film IL2, but the illustration thereof is omitted here.

<About semiconductor device manufacturing process>
Next, the manufacturing process of the semiconductor device of this embodiment will be described with reference to the drawings. 3 and 4 are process flowcharts showing the manufacturing process of the semiconductor device of the present embodiment. 5 to 29 are main-portion cross-sectional views during the manufacturing process of the semiconductor device of the present embodiment.

  First, as shown in FIG. 5, an SOI substrate SUB is prepared (step S1 in FIG. 3).

  The SOI substrate SUB is made of a substrate SUB1 made of single crystal silicon or the like, an insulating layer BOX1 made of silicon oxide or the like formed on the main surface of the substrate SUB1, and single crystal silicon formed on the upper surface of the insulating layer BOX1. The semiconductor layer SM1 is included.

  The thickness of the semiconductor layer SM1 is smaller than the thickness of the substrate SUB1. The thickness of the semiconductor layer SM1 can be about 3 to 20 nm, for example.

The SOI substrate SUB can be manufactured using various methods. For example, after a semiconductor substrate (silicon substrate) having an oxide film formed on the surface and another semiconductor substrate (silicon substrate) are bonded and bonded together by applying high heat and pressure, a silicon layer on one side ( The SOI substrate SUB can be formed by reducing the thickness of the silicon substrate. Alternatively, O ₂ (oxygen) is ion-implanted with high energy into the main surface of the semiconductor substrate made of Si (silicon), and Si (silicon) and oxygen are combined in a subsequent heat treatment, so that the surface is larger than the surface of the semiconductor substrate. The SOI substrate SUB can be formed by a SIMOX (Silicon Implanted Oxide) method in which a buried oxide film (BOX film) is formed at a slightly deeper position. Further, the SOI substrate SUB can be manufactured by using another method, for example, a smart cut process.

  Next, an element isolation region (not shown) is formed in the SOI substrate SUB. In the element isolation region, for example, an element isolation groove having a bottom portion located in the substrate SUB1 through the semiconductor layer SM1 and the insulating layer BOX1 is formed on the main surface of the SOI substrate SUB (semiconductor layer SM1). It can be formed by using a technique or the like and embedding an insulating film in the element isolation trench using a film formation technique or a CMP technique. A MISFET is formed in the semiconductor layer SM1 that is planarly surrounded by the element isolation region as described below.

  Next, a p-type impurity (for example, boron) for forming a p-type well (p-type semiconductor region) is ion-implanted into the semiconductor layer SM1 in the region where the n-channel MISFET is to be formed in the semiconductor layer SM1. Etc.

  Next, as shown in FIG. 6, a dummy gate (dummy gate electrode, dummy gate structure) GED is formed on the SOI substrate SUB, that is, on the semiconductor layer SM1 (step S2 in FIG. 3).

  The dummy gate GED (particularly, the polysilicon film PL1 of the dummy gate GED) is a dummy (pseudo) gate (gate electrode) that does not function as the gate (gate electrode) of the MISFET. The dummy gate GED is composed of a laminated film of an insulating film GID, a polysilicon film (polycrystalline silicon film) PL1 thereon, and a silicon nitride film SN1 thereon. Instead of the silicon nitride film SN1, another insulating film such as a silicon oxide film can be used. As the insulating film GID, a silicon oxide film can be used.

  Although the polysilicon film PL1 can be formed directly on the semiconductor layer SM1, it is preferable to form the polysilicon film PL1 on the semiconductor layer SM1 via the insulating film GID. The insulating film GID is a dummy gate insulating film that does not function as a gate insulating film because it is removed later. A silicon oxide film can be suitably used as the insulating film GID, and the thickness of the insulating film GID is thinner than that of the polysilicon film PL1.

  The insulating film GID can be used as an etching stopper film (an anti-etching film for the semiconductor layer SM1) when the polysilicon film PL1 is later removed (corresponding to the second stage etching in step S13 described later). It is possible to prevent the semiconductor layer SM1 from being etched. For this reason, it is preferable to interpose the insulating film GID between the polysilicon film PL1 and the semiconductor layer SM1.

  To form the dummy gate GED, for example, after forming a silicon oxide film (this silicon oxide film becomes the insulating film GID) on the main surface of the SOI substrate SUB (that is, on the main surface of the semiconductor layer SM1), A polysilicon film PL1 and a silicon nitride film SN1 are sequentially formed (deposited) thereon. Then, the dummy gate GED can be formed by patterning the laminated film of the polysilicon film PL1 and the silicon nitride film SN1 using a photolithography technique and an etching technique. An insulating film GID (in this case, a silicon oxide film) is interposed between the dummy gate GED and the semiconductor layer SM1.

  Further, since the dummy gate GED is removed later, it does not have to be conductive, and the polysilicon film PL1 can be replaced with another material film. However, from the viewpoint of easy removal later, easy to ensure a high etching selection ratio with respect to silicon oxide film, silicon nitride film, etc. The silicon film PL1 is preferable. Further, another element (for example, a polysilicon resistor) can be formed by using a polysilicon film in the same layer as the polysilicon film PL1.

  Next, a sidewall insulating film (offset spacer) SW1 is formed as a sidewall film on the sidewall of the dummy gate GED (step S3 in FIG. 3).

  The sidewall insulating film SW1 forming step in step S3 can be performed as follows. That is, first, as shown in FIG. 7, a silicon oxide film SO1 is formed on the entire main surface of the SOI substrate SUB by a CVD (Chemical Vapor Deposition) method so as to cover the dummy gate GED. (accumulate. Then, the silicon oxide film SO1 is etched back (anisotropic etching) to leave the silicon oxide film SO1 on the side wall of the dummy gate GED to form the side wall insulating film SW1, as shown in FIG. The silicon oxide film SO1 in the region is removed. Thereby, the sidewall insulating film SW1 is formed on the sidewall of the dummy gate GED. The thickness of the sidewall insulating film SW1 (thickness in the direction substantially perpendicular to the sidewall of the dummy gate GED) can be set to, for example, about 3 to 10 nm.

  Further, the side wall insulating film SW1 and the side wall insulating film SW2, which will be described later, are not necessarily insulative in order to be removed later. An insulating film is preferable from the viewpoint of preventing problems in some cases, and silicon oxide and silicon nitride are particularly preferable. For this reason, silicon oxide is used in the present embodiment and silicon nitride is used in the second embodiment described later as the material of the sidewall insulating film SW1 and the sidewall insulating film SW2 described later.

  Next, as shown in FIG. 9, the semiconductor layer EP1 is epitaxially grown on the semiconductor layer SM1 (step S4 in FIG. 3).

  The semiconductor layer EP1 is formed on the semiconductor layer SM1 in a region on both sides of the dummy gate GED (more specifically, a structure including the dummy gate GED and the sidewall insulating film SW1). That is, on the semiconductor layer SM1, the dummy gate GED (more specifically, the dummy gate GED and the side wall insulation is provided on both sides of the dummy gate GED (more specifically, the structure including the dummy gate GED and the side wall insulating film SW1). The semiconductor layer EP1 is formed so as to be adjacent to the structure including the film SW1.

  The semiconductor layer EP1 is an epitaxial layer (epitaxial semiconductor layer) formed by epitaxial growth, and is made of silicon (single crystal silicon). The semiconductor layer EP1 is selectively epitaxially grown on the semiconductor layer SM1, and is not formed on the sidewall insulating film SW1 or the silicon nitride film SN1.

  When epitaxially growing the semiconductor layer EP1, the polysilicon film PL1 of the dummy gate GED has its upper surface covered with the silicon nitride film SN1 and its side surface (side wall) covered with the sidewall insulating film SW1, and the polysilicon film PL1 of the dummy gate GED The semiconductor layer EP1 is epitaxially grown in a state where the silicon film PL1 is not exposed. Therefore, it is possible to prevent an epitaxial layer from being formed on the polysilicon film PL1 of the dummy gate GED.

  That is, if the formation of the sidewall insulating film SW1 is omitted and the semiconductor layer EP1 is epitaxially grown with the sidewalls of the polysilicon film PL1 of the dummy gate GED exposed, the semiconductor layer EP1 is also epitaxially grown on the exposed portion of the polysilicon film PL1. As a result, the semiconductor layer EP1 may adhere to the polysilicon film PL1. This can be prevented by the sidewall insulating film SW1.

  Further, it is preferable to epitaxially grow the semiconductor layer EP1 so that the side surface SF1 of the semiconductor layer EP1 has a taper. That is, the side surface SF1 of the semiconductor layer EP1 is preferably inclined with respect to the main surface of the SOI substrate SUB (that is, the main surface of the semiconductor layer SM1). That is, the angle α formed between the main surface of the SOI substrate SUB (that is, the main surface of the semiconductor layer SM1) and the side surface SF1 of the semiconductor layer EP1 is preferably smaller than 90 ° (that is, α <90 °). In other words, the side surface SF1 of the semiconductor layer EP1 is preferably inclined so that the thickness of the semiconductor layer EP1 increases as the distance from the dummy gate GED increases. The taper of the side surface SF1 of the semiconductor layer EP1 can be controlled by adjusting the composition of the film forming gas for the semiconductor layer EP1, the film forming temperature, and the like.

  The case where the angle formed between the side surface SF1 of the semiconductor layer EP1 and the main surface of the semiconductor layer SM1 (and hence the main surface of the SOI substrate SUB) is an acute angle is referred to as the side surface SF1 of the semiconductor layer EP1 being inclined. The side surface SF1 is an inclined side surface of the semiconductor layer EP1. For this reason, when the side surface SF1 of the semiconductor layer EP1 is perpendicular to the main surface of the semiconductor layer SM1 (and thus the main surface of the SOI substrate SUB), it is not said that the side surface SF1 of the semiconductor layer EP1 is inclined.

  Since the semiconductor layer EP1 is formed on a substantially flat upper surface of the semiconductor layer SM1, the upper surface of the semiconductor layer EP1 is higher than the upper surface of the semiconductor layer SM1. For this reason, the upper surface of the semiconductor layer EP1 formed in step S4 is higher than the upper surface of the semiconductor layer SM1 immediately below the dummy gate GED. Note that the height corresponds to the height in the direction substantially perpendicular to the main surface of the substrate SUB.

  A combination of the semiconductor layer SM1 and the semiconductor layer EP1 formed on the semiconductor layer SM1 is hereinafter referred to as a semiconductor layer SM2.

Next, as shown in FIG. 10, n-type such as phosphorus (P) or arsenic (As) is formed in the regions on both sides of the dummy gate GED and the sidewall insulating film SW1 in the semiconductor layer SM2 (ie, the semiconductor layers SM1, EP1). The n ⁻ type semiconductor region (extension region, LDD region) EX is formed by ion implantation of the impurity (step S5 in FIG. 3). In the ion implantation step for forming the n ⁻ type semiconductor region EX, the dummy gate GED and the sidewall insulating film SW1 can function as a mask (ion implantation blocking mask). Therefore, the n ⁻ type semiconductor region EX is formed in the semiconductor layer SM1 and the semiconductor layer EP1 (stacked body thereof) in a self-aligned manner with respect to the sidewall insulating film SW1 on the sidewall of the dummy gate GED.

  Next, a sidewall insulating film (sidewall spacer) SW2 is formed as a sidewall film on the sidewall of the dummy gate GED (step S6 in FIG. 3).

  The step of forming the sidewall insulating film SW2 in step S6 can be performed as follows. That is, first, as shown in FIG. 11, a silicon oxide film SO2 is formed (deposited) over the entire main surface of the SOI substrate SUB by CVD or the like so as to cover the dummy gate GED and the sidewall insulating film SW1. Then, the silicon oxide film SO2 is etched back (anisotropic etching) to leave the silicon oxide film SO2 on the side wall of the dummy gate GED to form the side wall insulating film SW2, as shown in FIG. The silicon oxide film SO2 in the region is removed. As a result, the sidewall insulating film SW2 is formed on the sidewall of the dummy gate GED via the sidewall insulating film SW1. The two thicknesses of the sidewall insulating film SW (thickness in a direction substantially perpendicular to the sidewall of the dummy gate GED) can be set to, for example, about 3 to 10 nm.

  The sidewall insulating film SW2 is formed adjacent to the sidewall of the dummy gate GED via the sidewall insulating film SW1 and on the semiconductor layer EP1 (specifically, on the inclined side surface SF1 of the semiconductor layer EP1). That is, the bottom surface of the sidewall insulating film SW2 is in contact with the semiconductor layer EP2 (specifically, the inclined side surface SF1 of the semiconductor layer EP1), and the inner wall of the sidewall insulating film SW2 (the side surface facing the dummy gate GED) is the dummy gate GED. Is in contact with the side wall insulating film SW1 on the side wall.

Next, as shown in FIG. 13, phosphorus (P) or arsenic (As) or the like is formed in the regions on both sides of the dummy gate GED and the sidewall insulating films SW1 and SW2 in the semiconductor layer SM2 (that is, the semiconductor layers SM1 and EP1). By ion-implanting n-type impurities, an n ⁺ -type semiconductor region SD is formed (step S7 in FIG. 3). In the ion implantation process for forming the n ⁺ type semiconductor region SD, the dummy gate GED and the sidewall insulating films SW1 and SW2 can function as a mask (ion implantation blocking mask). Therefore, the n ⁺ type semiconductor region SD is formed in self-alignment with the sidewall insulating film SW2 formed on the sidewall of the dummy gate GED via the sidewall insulating film SW1. The n ⁺ type semiconductor region SD has a higher impurity concentration than the n ⁻ type semiconductor region EX.

The n ^- -type semiconductor region by ion implantation to form the EX, may be an n-type impurity is implanted at a relatively shallow region of the semiconductor layer SM2 (SM1, EP1), compared to that, ^{n +} -type semiconductor region SD In the ion implantation for forming the n-type impurity, the n-type impurity is implanted into the deep region of the semiconductor layer SM2 (SM1, EP1) (that is, the entire thickness of the semiconductor layer SM2).

Before forming the sidewall insulating film SW2 in step S6, ion implantation (step S5) for forming the n ⁻ type semiconductor region EX is performed, and after forming the sidewall insulating film SW2 in step S6, the n ⁺ type semiconductor is formed. Ion implantation (step S7) for forming the region SD is performed. For this reason, when the process up to step S7 is performed, the n ⁻ type semiconductor region EX is formed in the semiconductor layer SM2 (SM1, EP1) immediately below the sidewall insulating film SW2. Since the side wall insulating film SW2 is also removed together with the dummy gate GED in step S13 described later and then the gate electrode GE is formed in steps S14 to S16 described later, the gate electrode GE is also formed in the region where the side wall insulating film SW2 was present. Will be. For this reason, when the gate electrode GE is formed later, the n ⁻ type semiconductor region EX is substantially formed directly below a part of the gate electrode GE (both ends in the gate length direction).

Next, activation annealing which is a heat treatment for activating impurities introduced into the n ⁺ type semiconductor region SD, the n ⁻ type semiconductor region EX, and the like is performed (step S8 in FIG. 3). If the ion-implanted region is made amorphous, it can be crystallized during the activation annealing in step S8.

  Next, a sidewall insulating film (sidewall spacer) SW3 is formed as a sidewall film on the sidewall of the dummy gate GED (step S9 in FIG. 3).

  The step of forming the sidewall insulating film SW3 in step S9 can be performed as follows. That is, first, as shown in FIG. 14, a silicon nitride film SN2 is formed (deposited) over the entire main surface of the SOI substrate SUB by CVD or the like so as to cover the dummy gate GED and the sidewall insulating films SW1 and SW2. To do. Then, the silicon nitride film SN2 is etched back (anisotropic etching) to leave the silicon nitride film SN2 on the side wall of the dummy gate GED to form the side wall insulating film SW3 as shown in FIG. The silicon nitride film SN2 in the region is removed. Thereby, a sidewall insulating film (sidewall spacer) SW3 is formed on the sidewall of the dummy gate GED via the sidewall insulating films SW1 and SW2. The thickness of the sidewall insulating film SW3 (thickness in the direction substantially perpendicular to the sidewall of the dummy gate GED) can be set to about 10 to 30 nm, for example.

  At this stage, the side wall insulating film SW1, the side wall insulating film SW2, and the side wall insulating film SW3 are formed (laminated) on the side wall of the dummy gate GED in the order close to the dummy gate GED.

  Although the formation of the sidewall insulating film SW3 can be omitted, it is more preferable to form the sidewall insulating film SW3. When the sidewall insulating film SW3 is formed, the formation position of the metal silicide layer SIL is separated from the position of the dummy gate GED by the thickness of the sidewall insulating film SW3 in addition to the thickness of the sidewall insulating films SW1 and SW2. Can do. Therefore, the metal silicide layer SIL can be formed in a region where the thickness of the semiconductor layer EP1 is relatively thick (and thus a region where the thickness of the semiconductor layer SM2 is relatively thick). Therefore, in the semiconductor layer SM2, it is possible to prevent a region where the silicon region disappears in the thickness direction due to the formation of the metal silicide layer SIL. In addition, if the gate electrode GE and the gate insulating film GI are formed in a state where the side wall insulating film SW3 is left in a later step, not only the gate insulating film GI but also the side wall insulation is formed between the metal silicide layer SIL and the gate electrode GE. Since the film SW3 is also interposed, the breakdown voltage between the gate electrode GE and the metal silicide layer SIL can be improved.

Next, a low-resistance metal silicide layer SIL is formed on the surface (upper layer portion) of the n ⁺ type semiconductor region SD by using a salicide (Salicide: Self Aligned Silicide) technique (step S10 in FIG. 4).

The step of forming the metal silicide layer SIL in step S10 can be performed as follows. That is, first, after exposing the surface of the n ⁺ type semiconductor region SD (specifically, the surface of the semiconductor layer EP1 that is not covered with the dummy gate GED and the sidewall insulating films SW1, SW2, and SW3), FIG. As shown in FIG. 4, a metal film ME is formed (deposited) on the main surface (entire surface) of the SOI substrate SUB so as to cover the dummy gate GED, the sidewall insulating films SW1, SW2, SW3, and the n ⁺ type semiconductor region SD. To do. The metal film ME is made of, for example, a cobalt (Co) film, a nickel (Ni) film, or a nickel platinum alloy film, and can be formed using a sputtering method or the like. Then, the metal film ME is reacted with the n ⁺ type semiconductor region SD (which constitutes silicon) by heat treatment. Thereby, as shown in FIG. 17, a metal silicide layer SIL is formed on the surface of the n ⁺ type semiconductor region SD. Thereafter, the unreacted metal film ME is removed, and FIG. 17 shows this stage.

When the metal film ME is a cobalt film, the metal silicide layer SIL is a cobalt silicide layer. When the metal film ME is a nickel film, the metal silicide layer SIL is a nickel silicide layer, and the metal film ME is a nickel platinum alloy film. In this case, the metal silicide layer SIL is a nickel platinum silicide layer. By forming the metal silicide layer SIL, the diffusion resistance, contact resistance, etc. of the n ⁺ type semiconductor region SD can be reduced.

A metal silicide layer SIL is formed on the surface (upper layer portion) of the n ⁺ type semiconductor region SD, and the metal silicide layer SIL is mainly formed in the semiconductor layer EP1.

  Note that the sidewall insulating films SW1 and SW2 are formed on the sidewall of the dummy gate GED, and the silicon nitride film SN1 is formed on the polysilicon film PL1 of the dummy gate GED, so that the polysilicon film PL1 of the dummy gate GED is formed. Does not contact the metal film ME, and the polysilicon film PL1 does not react with the metal film ME. Therefore, no metal silicide layer is formed on the surface of the polysilicon film PL1 of the dummy gate GED.

  Next, as shown in FIG. 18, an insulating film (interlayer insulating film) IL1 is formed on the main surface (entire main surface) of the SOI substrate SUB (step S11 in FIG. 4). That is, the insulating film IL1 is formed on the main surface of the SOI substrate SUB so as to cover the dummy gate GED and the side wall insulating films SW1, SW2, and SW3. The insulating film IL1 is preferably composed of a laminated film of a silicon nitride film (liner film) SN3 and an insulating film (interlayer insulating film) SO3 on the silicon nitride film SN3. The insulating film SO3 is thicker than the silicon nitride film SN3. As the insulating film SO3, a silicon oxide insulating film can be used. Here, the silicon oxide-based insulating film is an insulating film mainly composed of silicon oxide, and among carbon (C), fluorine (F), nitrogen (N), boron (B), and phosphorus (P). One or more of these can also be contained.

  In the present embodiment, the silicon nitride film SN3 that is an insulating film is illustrated as the liner film SN3, but a silicon oxynitride film may be used instead. That is, any insulating film that functions as an etching stopper when forming a trench TR or a contact hole CNT, which will be described later, may be used.

  Next, as shown in FIG. 19, the surface (upper surface) of the insulating film IL1 is polished by a CMP (Chemical Mechanical Polishing) method or the like, so that the upper surface of the dummy gate GED (that is, the silicon nitride film SN1) is polished. The upper surface is exposed (step S12 in FIG. 4). That is, the insulating film IL1 is polished by CMP until the upper surface of the silicon nitride film SN1 of the dummy gate GED is exposed. Step S12 is a step of removing a part of the insulating film IL1 (at least the insulating film IL1 covering the dummy gate GED) to expose the upper surface of the dummy gate GED.

  Next, as shown in FIG. 20, the dummy gate GED and the sidewall insulating films SW1 and SW2 are removed by etching (step S13 in FIG. 4).

  By removing the dummy gate GED and the sidewall insulating films SW1 and SW2 in this step S13, as shown in FIG. 20, a trench (recess, opening, recess) TR is formed. The trench TR is composed of a region (space) where the dummy gate GED and the sidewall insulating films SW1 and SW2 existed before the removal of the dummy gate GED and the sidewall insulating films SW1 and SW2. From the trench TR, the upper surface of the semiconductor layer SM1, the inclined side surface SF1 of the semiconductor layer EP1, and the inner wall of the sidewall insulating film SW3 are exposed.

  The bottom surface of the trench TR is formed by the upper surface of the semiconductor layer SM1 and the inclined side surface SF1 of the semiconductor layer EP1. The side surface (side wall) of the trench TR is formed by the inner wall of the side wall insulating film SW3. In other words, the upper surface of the semiconductor layer SM1 exposed from the trench TR to the inclined side surface SF1 of the semiconductor layer EP1 can be regarded as the bottom surface of the trench TR. The upper part of the trench TR is open. Here, the inner wall of the side wall insulating film SW3 corresponds to the side surface (side wall) of the side wall insulating film SW3 that is in contact with the side wall insulating film SW2 until the side wall insulating film SW2 is removed.

  The etching process in step S13 will be specifically described below.

  The etching in step S13 is preferably performed by the following three stages (first stage, second stage and third stage, see FIGS. 21 to 23).

  That is, after obtaining the structure of FIG. 19 by the CMP process in step S12, the silicon nitride film SN1 of the dummy gate GED is removed by the first-stage etching in step S13 as shown in FIG. In this first-stage etching, it is preferable that the silicon nitride film SN1 is selectively etched under etching conditions such that the etching speed of the silicon nitride film SN1 is higher than the etching speed of the polysilicon film PL1. By the first stage etching, the silicon nitride film SN1 is removed, and the polysilicon film PL1 is exposed.

  After removing the silicon nitride film SN1 by the first stage etching, the etching conditions are changed, and the polysilicon film PL1 of the dummy gate GED is removed by the second stage etching in step S13 as shown in FIG. . This second stage etching is performed under the etching conditions such that the etching rate of the polysilicon film PL1 is faster than the etching rates of the sidewall insulating films SW1 and SW2 and the insulating film GID (specifically, silicon oxide). It is preferable to selectively etch the film PL1. By the second-stage etching, the polysilicon film PL1 is removed, and the sidewall insulating film SW1 and the insulating film GID are exposed. That is, in the second stage etching, the polysilicon film PL1 can be etched, and the sidewall insulating film SW1 and the insulating film GID can function as an etching stopper. Here, since the sidewall insulating films SW1, SW2 and the insulating film GID are formed of silicon oxide, it is easy to ensure a high etching selectivity between the polysilicon film PL1, the sidewall insulating films SW1, SW2, and the insulating film GID. It is. In addition, since the insulating film GID is provided between the semiconductor layer SM1 and the polysilicon film PL1, the semiconductor layer SM1 is etched when the polysilicon film PL1 is removed by the second stage etching. Can be prevented.

  After removing the polysilicon film PL1 in the second stage etching, the etching conditions are changed, and the third stage etching in step S13 is performed to change the sidewall insulating films SW1 and SW2 and the insulating film GID as shown in FIG. Remove. This third stage of etching is performed under such etching conditions that the etching rates of the sidewall insulating films SW1 and SW2 and the insulating film GID are higher than the etching rates of the semiconductor layers SM1 and EP1. It is preferable to selectively etch the GID. Thereby, it is possible to suppress or prevent the semiconductor layers SM1 and EP1 from being etched by the third stage etching. If sidewall insulating film SW1 and sidewall insulating film SW2 are formed of the same material (here, silicon oxide), sidewall insulating film SW1 and sidewall insulating film SW2 can be continuously etched in the same etching step. Further, if the insulating film GID and the side wall insulating films SW1 and SW2 are formed of the same material (here, silicon oxide), the insulating film GID is removed in the same etching process as the side wall insulating films SW1 and SW2 are removed. can do.

  In the third stage etching, the sidewall insulating films SW1 and SW2 are removed, but the sidewall insulating film SW3 is preferably left. For this reason, in this embodiment, the sidewall insulating film SW3 is formed of a material different from that of the sidewall insulating films SW1 and SW2, and the etching rate of the sidewall insulating films SW1 and SW2 (specifically, silicon oxide) is increased. The third-stage etching is performed under the etching conditions such that the etching rate of the insulating film SW3 (specifically, silicon nitride) and the semiconductor layers SM1 and EP1 is higher. Here, since the side wall insulating films SW1 and SW2 are formed of the silicon oxide films SO1 and SO2 and the side wall insulating film SW3 is formed of the silicon nitride film SN2, the side wall insulating films SW1 and SW2 and the side wall insulating film SW3 are high. It is easy to ensure the etching selectivity. That is, in the third stage etching, the sidewall insulating films SW1 and SW2 can be etched and the sidewall insulating film SW3 can function as an etching stopper. Further, since the sidewall insulating films SW1 and SW2 are formed of the silicon oxide films SO1 and SO2, it is easy to ensure a high etching selectivity between the sidewall insulating films SW1 and SW2 and the semiconductor layers SM1 and EP1.

  If the formation of the sidewall insulating film SW3 is omitted, the insulating film IL1 (more specifically, the silicon nitride film SN3 of the insulating film IL1) is exposed when the sidewall insulating films SW1 and SW2 are removed by the third stage etching. Will do. In this case, the silicon nitride film SN3 of the insulating film IL1 can function as an etching stopper. That is, the sidewall insulating film SW3 is not necessarily formed. Note that a silicon oxynitride film may be used instead of the silicon nitride film as the material of the liner film SN3.

  When the insulating film GID is formed of a material different from that of the sidewall insulating films SW1 and SW2, the sidewall insulating films SW1 and SW2 are removed by etching, and then the insulating film GID is selectively removed by changing the etching conditions. You can also

  In addition, when the sidewall insulating films SW1 and SW2 are removed, a part of the insulating film SO3 of the insulating film IL1 may be etched, but the insulating film SO3 is thick and under the insulating film SO3. Since there is the silicon nitride film SN3, it can be tolerated.

  The trench TR is formed as shown in FIGS. 20 and 23 by removing the dummy gate GED and the side wall insulating films SW1 and SW2 by etching in the above three steps (first step, second step and third step). Is done.

  Then, the process after step S13 is demonstrated.

  After step S13, as shown in FIG. 24, an insulating film GIa for a gate insulating film is formed on the main surface (entire main surface) of SOI substrate SUB including the bottom surface and side surface (sidewall) of trench TR. (Step S14 in FIG. 4).

  The insulating film GIa can be formed by, for example, an ALD (Atomic layer Deposition) method or a CVD method. As the insulating film GIa, for example, a metal oxide film such as a hafnium oxide film, a zirconium oxide film, an aluminum oxide film, a tantalum oxide film, or a lanthanum oxide film can be used. One or both of (N) and silicon (Si) can also be contained. In this case, the insulating film GIa is a high dielectric constant film (so-called High-k film) having a higher dielectric constant (relative dielectric constant) than that of the silicon nitride film. Alternatively, a silicon oxide or silicon oxynitride film can be used as the insulating film GIa. However, when a high dielectric constant film is used as the insulating film GIa, the equivalent silicon oxide thickness of the gate insulating film (GI) is increased as compared with the case where a silicon oxide film having the same physical film thickness is used. Therefore, the advantage that the leakage current can be reduced can be obtained. The physical film thickness of the insulating film GIa is about 2 nm to 5 nm.

  When a high dielectric constant film is used for the insulating film GIa, a silicon oxide film having a thickness of 1 nm or less may be formed as an interface layer prior to the formation of the insulating film GIa. The physical thickness of the interface layer is formed thinner than the physical thickness of the metal oxide film (high dielectric constant film). The interface layer can be formed on the semiconductor layer SM1 by a thermal oxidation method.

  The insulating film GIa needs to be formed at least on the portions of the semiconductor layers SM1 and EP1 exposed from the trench TR. Actually, the insulating film GIa is not only on the portions of the semiconductor layers SM1 and EP1 exposed from the trench TR. Insulating film GIa is also formed on the inner wall of sidewall insulating film SW3 exposed from TR and on insulating film IL1. That is, insulating film GIa is formed on insulating film IL1 including the bottom of trench TR and the side wall.

  Next, as shown in FIG. 25, a conductive film (conductor film) CD for the gate electrode is formed on the main surface of the SOI substrate SUB, that is, on the insulating film GIa (step S15 in FIG. 4). The conductive film CD is formed on the insulating film GIa so as to fill the trench TR.

  As the conductive film CD, for example, a titanium nitride (TiN) film, a tantalum nitride (TaN) film, a tungsten nitride (WN) film, a titanium carbide (TiC) film, a tantalum carbide (TaC) film, a tungsten carbide (WC) film, or A metal film such as a tantalum nitride nitride (TaCN) film can be used. In addition, the metal film said here is the electrically conductive film which shows metal conduction, and not only a single metal film (pure metal film) and an alloy film, but also a metal compound film (metal nitride film and metal carbide film) which shows metal conduction. Etc.). In the case of a metal film, the conductive film CD can be formed using, for example, a sputtering method. When a metal film is used for the conductive film CD, a gate electrode GE formed later can be used as a metal gate electrode, so that the depletion phenomenon of the gate electrode GE can be suppressed and parasitic capacitance can be eliminated. Benefits. Further, there is an advantage that the MISFET element can be miniaturized (the gate insulating film can be thinned).

  As a modification of the metal gate electrode, a stacked gate electrode of the metal film and a polysilicon film (doped polysilicon film) can be used. In this case, first, the metal film is formed in the trench TR, and then a polysilicon film is formed so as to fill the trench TR, whereby a stacked gate electrode can be obtained. In this case, the conductive film CD is composed of a laminated film of the metal film and a polysilicon film (doped polysilicon film) thereon.

  Moreover, you may laminate | stack a different metal film as another modification of a metal gate electrode. In this case, for example, by forming a first metal film in the trench TR and then forming a second metal film so as to fill the trench TR, a stacked gate electrode can be obtained. In this case, the conductive film CD is composed of a laminated film of the first metal film and the second metal film thereon. At this time, the metal (metal film) to be laminated is not limited to two layers, and may be a plurality of layers of two or more layers.

  Next, as shown in FIG. 26, the conductive film CD is left in the trench TR, and the conductive film CD outside the trench TR is removed by CMP or the like to form the gate electrode GE (step S16 in FIG. 4). ). The gate electrode GE is made of the conductive film CD remaining in the trench TR.

  In step S16, when the conductive film CD outside the trench TR is removed by polishing using the CMP method, the insulating film GIa outside the trench TR is also removed. That is, the conductive film CD and the insulating film GIa are polished until the upper surface of the insulating film IL1 (the insulating film SO3) is exposed, whereby the conductive film CD and the insulating film GIa outside the trench TR are removed, and the trench TR The conductive film CD and the insulating film GIa are left. As a result, the conductive film CD and the insulating film GIa remain in the trench TR, the conductive film CD remaining in the trench TR becomes the gate electrode GE, and the insulating film GIa remaining in the trench TR becomes the gate insulating film GI. . That is, steps S14 to S16 are steps of forming the gate electrode GE in the trench TR via the gate insulating film GI.

  Between the gate electrode GE and the semiconductor layer SM1 (the upper surface thereof), between the gate electrode GE and the semiconductor layer EP1 (the inclined side surface SF1 thereof), and between the gate electrode GE and the sidewall insulating film SW3 (the inner wall thereof). The gate insulating film GI (insulating film GIa) is interposed between the two. The gate electrode GE and the gate insulating film GI function as a gate electrode and a gate insulating film of the MISFET, respectively. That is, the gate electrode GE is formed on the semiconductor layer SM2 via the gate insulating film GI.

A channel region of the MISFET is formed in the semiconductor layer SM1 located under the gate electrode GE via the gate insulating film GI (insulating film GIa). The semiconductor region (impurity diffusion layer) functioning as the source or drain of the MISFET includes an n ⁻ type semiconductor region EX provided in the semiconductor layer SM2 (SM1, EP1) and an n ⁺ type semiconductor region having a higher impurity concentration than that. SD and has an LDD (Lightly doped Drain) structure.

  In the gate length direction, the upper length of the gate electrode GE is about 48 nm, and the lower length of the gate electrode GE (the length of the channel region) is about 28 nm. That is, the minimum length of the gate electrode GE in the gate length direction is used as a substantial channel region.

  In this way, an n-channel MISFET is formed.

In the present embodiment, the sidewall insulating film SW2 formed on the sidewall of the dummy gate GED and located on the semiconductor layer EP1 is removed together with the dummy gate GED in step S13, and the removed region (trench TR) is removed. A gate electrode GE is formed. Therefore, the gate electrode GE can be formed not only in the region where the dummy gate GED was present but also in the region where the sidewall insulating film SW2 was present. For this reason, the dimension in the gate length direction of the gate electrode GE can be made larger than the dimension of the dummy gate GED, and a part of the gate electrode GE (both ends in the gate length direction) is located on the semiconductor layer EP1. That is, it rides on the semiconductor layer EP1. Therefore, the end of the gate electrode GE in the gate length direction is located on the semiconductor layer EP1. At least a part of the n ⁻ type semiconductor region EX is located immediately below the gate electrode GE.

  Next, as shown in FIG. 27, an insulating film (interlayer insulating film) IL2 is formed over the entire main surface of the SOI substrate SUB, that is, over the insulating film IL1 in which the gate electrode GE is embedded. As the insulating film SO3, a silicon oxide insulating film can be used. The insulating film IL2 is formed over the insulating film IL1 so as to cover the upper surface of the gate electrode GE.

  After the formation of the insulating film IL2, the flatness of the upper surface of the insulating film IL2 can be improved by polishing the surface (upper surface) of the insulating film IL2 by a CMP method.

  Next, as shown in FIG. 28, by using the photoresist pattern (not shown) formed on the insulating film IL2 as an etching mask, the insulating film IL2 and the insulating film IL1 are dry-etched, thereby forming the insulating film IL1. , IL2 are formed with contact holes (through holes, holes) CNT. The contact hole CNT is formed so as to penetrate the laminated film (laminated insulating film) made of the insulating film IL1 and the insulating film IL2.

  In order to form the contact hole CNT, first, the insulating film IL2 and the insulating film SO3 are dry-etched under conditions that allow the insulating film SO3 and the insulating film IL2 to be etched more easily than the silicon nitride film SN3. By functioning as an etching stopper film, contact holes CNT are formed in the insulating film IL2 and the insulating film SO3. Then, the silicon nitride film SN3 at the bottom of the contact hole CNT is removed by dry etching under a condition that the silicon nitride film SN3 is more easily etched than the insulating film IL2 and the insulating film SO3, thereby removing the contact hole CNT as a through hole. Is formed.

The contact hole CNT is formed, for example, above the n ⁺ type semiconductor region SD or above the gate electrode GE. At the bottom of the n ⁺ -type semiconductor region SD of the contact hole CNT formed on the upper metal silicide layer SIL on n ⁺ -type semiconductor regions SD are exposed. By making the silicon nitride film SN3 function as an etching stopper film at the time of forming the contact hole CNT, excessive digging of the contact hole CNT and damage to the semiconductor layer SM2 can be suppressed or prevented.

  Next, a conductive plug PG made of tungsten (W) or the like is formed (embedded) in the contact hole CNT as a connecting conductor portion. The plug PG can be formed as follows.

That is, first, on the insulating film IL2 including the inside (on the bottom and side walls) of the contact hole CNT, the barrier conductor film BR1 (for example, a titanium film, a titanium nitride film, or a laminated film thereof) is formed by sputtering or plasma CVD. Form. Then, a main conductor film MC1 made of a tungsten film or the like is formed so as to fill the contact hole CNT on the barrier conductor film BR1 by a CVD method or the like. Thereafter, unnecessary main conductor film MC1 and barrier conductor film BR1 outside the contact hole CNT (on the insulating film IL2) are removed by a CMP method, an etch back method, or the like. As a result, the upper surface of the insulating film IL2 is exposed, and the plug PG is formed by the barrier conductor film BR1 and the main conductor film MC1 that remain buried in the contact holes CNT of the insulating films IL1 and IL2. n ⁺ -type semiconductor regions plugs PG formed in the upper portion of the SD are in contact with and electrically connected to the metal silicide layer SIL on the surface of the n ⁺ -type semiconductor region SD at its bottom. Although not shown, when the plug PG is formed on the top of the gate electrode GE, the plug PG is in contact with and electrically connected to the gate electrode GE at the bottom of the plug PG.

  Next, as shown in FIG. 29, an insulating film IL3 for wiring formation is formed on the insulating film IL2 in which the plug PG is embedded. The insulating film IL3 can be a single film (single insulating film) or a laminated film (laminated insulating film).

Next, a first layer wiring is formed by a single damascene method. First, after a wiring groove WT is formed in a predetermined region of the insulating film IL3 by dry etching using a photoresist pattern (not shown) as a mask, the main surface of the SOI substrate SUB (that is, on the bottom and side walls of the wiring groove WT). A barrier conductor film (barrier metal film) is formed on the insulating film IL3 including As the barrier conductor film, for example, a titanium nitride film, a tantalum film, a tantalum nitride film, or the like can be used. Subsequently, a copper seed layer is formed on the barrier conductor film by CVD or sputtering, and a copper plating film (main conductor film) is further formed on the seed layer by electrolytic plating or the like. The inside of the wiring trench WT is embedded with a copper plating film. Then, the copper plating film, the seed layer, and the barrier metal film in regions other than the wiring trench WT are removed by CMP to form a first layer wiring M1 using copper as a main conductive material. In order to simplify the drawing, in FIG. 29, the copper plating film, the seed layer, and the barrier metal film constituting the wiring M1 are shown in an integrated manner. The wiring M1 is connected to the plug PG, and is electrically connected to the n ⁺ type semiconductor region SD or the gate electrode GE through the plug PG.

  Thereafter, the second and subsequent wirings are formed by the dual damascene method, but illustration and description thereof are omitted here. Further, the wiring M1 and the wirings in the second and subsequent layers are not limited to damascene wiring, and can be formed by patterning a conductive film for wiring, for example, tungsten wiring or aluminum wiring.

  In this embodiment, the case where an n-channel MISFET is formed as the MISFE has been described. However, a p-channel MISFET can be formed by reversing the conductivity type. In addition, both an n-channel MISFET and a p-channel MISFET can be formed on the same SOI substrate SUB. The same applies to the following second to fourth embodiments.

<About study example>
When manufacturing a semiconductor device using an SOI substrate, a source / drain silicon layer is epitaxially grown on the semiconductor layer of the SOI substrate. Thereby, for example, the resistance can be reduced while reducing the depth of the source / drain diffusion layer, and a silicon film thickness suitable for forming the metal silicide layer by the salicide process can be secured. Such a semiconductor device was examined.

  30 and 31 are main-portion cross-sectional views of the semiconductor device of the first study example. FIG. 30 corresponds to FIG. 1 of the present embodiment, and FIG. 31 corresponds to FIG. 2 of the present embodiment.

  The semiconductor device of the first study example shown in FIG. 30 and FIG. 31 performs the same process as the present embodiment until step S10 (metal silicide layer SIL formation process), but the subsequent processes are different. doing. That is, when the semiconductor device of the first study example is manufactured, the process up to step S10 (metal silicide layer SIL formation process) is performed to obtain the structure of FIG. 17 and then the main surface (main surface) of the SOI substrate SUB. On the entire surface, an interlayer insulating film IL101 made of a laminated film of a silicon nitride film SN103 corresponding to the silicon nitride film SN3 and a silicon oxide film SO103 corresponding to the insulating film SO3 is formed. Then, the upper surface of the interlayer insulating film IL101 is planarized by the CMP method. At this time, unlike the present embodiment, the dummy gate GED is not exposed. Thereafter, without performing steps S13 to S16, a contact hole (not shown) corresponding to the contact hole CNT is formed in the interlayer insulating film IL101, and a plug (not shown) corresponding to the plug PG is formed in the contact hole. In addition, a film (not shown) corresponding to the insulating film IL3 and the wiring M1 is formed.

  Therefore, in the semiconductor device of the first study example shown in FIGS. 30 and 31, the insulating film GID, the polysilicon film PL1, and the silicon nitride film SN1 remain without being removed, and the gate insulating film GI101, gate electrode GE101, and silicon nitride film SN101 are formed. That is, the stacked structure of the gate insulating film GI101, the gate electrode GE101, and the silicon nitride film SN101 formed in step S2 and left as it is in the manufactured semiconductor device is the semiconductor device of the first study example. It corresponds to.

  32 and 33 are fragmentary cross-sectional views of the semiconductor device of the second study example during the manufacturing process. 34 and 35 are cross-sectional views of the principal part of the semiconductor device of the second study example, FIG. 34 corresponds to FIG. 1 of the present embodiment, and FIG. This corresponds to FIG.

  In the case of manufacturing the semiconductor device of the second study example, the same processes as in the present embodiment are performed up to the above-described step S12 (CMP process of the insulating film IL1), but the subsequent processes are different. That is, in the case of manufacturing the semiconductor device of the second study example, the process up to step S12 (CMP process of the insulating film IL1) is performed to obtain the structure of FIG. 19, and as shown in FIG. The silicon nitride film SN1 and the polysilicon film PL1 of the dummy gate GED are removed by etching, but the insulating film GID and the sidewall insulating films SW1, SW2, and SW3 are left without being removed. Then, a conductive film is formed on the insulating film IL1 so as to fill the trench TR101 formed by removing the silicon nitride film SN1 and the polysilicon film PL1, and then the conductive film outside the trench TR101 is formed by CMP. As a result, the gate electrode GE102 is formed in the trench TR101. The insulating film GID remaining under the gate electrode GE102 becomes the gate insulating film GI102. Thereafter, as in the present embodiment, the insulating film IL2 is formed, the contact hole CNT is formed, the plug PG is formed, the insulating film IL3 is formed, and the wiring M1 is formed. The illustration is omitted here.

  In the semiconductor device of the first study example shown in FIGS. 30 and 31, since the semiconductor layer EP1 that is an epitaxial layer is formed after the formation of the gate electrode GE101, the end portions (both ends in the gate length direction) of the gate electrode GE101 are formed. Part) does not run on the semiconductor layer EP1 which is an epitaxial layer for source / drain.

  Further, in the semiconductor device of the second examination example shown in FIGS. 34 and 35, the silicon nitride film SN1 and the polysilicon film PL1 of the dummy gate GED are removed by etching, and the gate electrode GE102 is formed there. However, in the semiconductor device of the second study example, the side wall insulating films SW1, SW2, and SW3 (particularly the side wall insulating film SW2) are left, so that the ends of the gate electrode GE102 (both ends in the gate length direction) It does not run on the semiconductor layer EP1, which is an epitaxial layer.

  As in the semiconductor device of the first study example shown in FIGS. 30 and 31 and the semiconductor device of the second study example shown in FIGS. 34 and 35, end portions of gate electrodes GE101 and GE102 (both end portions in the gate length direction). However, there is the following problem in the structure that does not run on the semiconductor layer EP1.

As a first problem, in a semiconductor device having a MISFET, if the source or drain semiconductor region has a parasitic resistance between the channel region and the semiconductor region, the characteristics (electrical characteristics) may be deteriorated. is there. For example, if the parasitic resistance between the source or drain semiconductor region and the channel region is large, the on-resistance is increased and the on-current is decreased, so that the electrical characteristics of the MISFET are degraded. Further, there is a concern that variation in characteristics between MISFETs may increase due to variations in the value of the parasitic resistance between the semiconductor region for source or drain and the channel region. Hereinafter, “parasitic resistance” refers to parasitic resistance between a semiconductor region for a source or drain and a channel region. The source or drain semiconductor region corresponds to a combination of the n ⁻ type semiconductor region EX and the n ⁺ type semiconductor region SD.

  In order to suppress the parasitic resistance between the source or drain semiconductor region and the channel region, the end portions of the gate electrode (both end portions in the gate length direction) overlap the source or drain semiconductor region. It is valid.

  However, in the semiconductor device of the first study example shown in FIGS. 30 and 31 and the semiconductor device of the second study example shown in FIGS. 34 and 35, a gate is formed on the semiconductor layer EP1 which is an epitaxial layer for source / drain. Since the end portions (both end portions in the gate length direction) of the electrodes GE101 and GE102 do not run over, it is difficult for the gate electrodes GE101 and GE102 to overlap the source or drain semiconductor region, and the parasitic resistance tends to increase.

  Even if it is considered that the semiconductor region for source / drain is simply diffused below the gate electrodes GE101 and GE102, the gate length is already very short due to miniaturization, so that the semiconductor region for source or drain is diffused. If too much is used, punch-through is likely to occur.

  Further, in the second study example, when the insulating film GIa as shown in FIG. 24 of the present application is formed as the gate insulating film in the trench TR101, the thickness of the gate insulating film GI (GIa) is also added. It becomes more difficult to overlap the gate electrode GE102 with the semiconductor region for use.

  As a second problem, in the case where an SOI substrate is used, even if the end portions (both ends in the gate length direction) of the gate electrode overlap the semiconductor region for the source or drain, the overlap portion When the thickness of the semiconductor layer is small, the parasitic resistance increases.

  In the semiconductor device of the first study example and the semiconductor device of the second study example, the semiconductor region for source or drain is diffused below the gate electrodes GE101 and GE102, so that the gate electrodes GE101 and GE102 are semiconductors for source or drain Suppose we were able to overlap the region. However, even in this case, since the gate electrodes GE101 and GE102 do not run on the semiconductor layer EP1, the thickness of the semiconductor layer in the overlap portion is the same as the thickness of the semiconductor layer SM1, thereby suppressing parasitic resistance. There are limits. The thickness of the semiconductor layer (semiconductor layer corresponding to the semiconductor layer SM1) of the SOI substrate is thin. For this reason, it is difficult to increase the thickness of the semiconductor layer in the overlap portion between the semiconductor region for the source or drain and the gate electrode when using the SOI substrate as compared with the case where the semiconductor substrate in the bulk state is used. Parasitic resistance tends to increase.

  For this reason, in the semiconductor device of the first study example and the semiconductor device of the second study example, the parasitic resistance between the semiconductor region for the source or drain and the channel region is increased, which may lead to deterioration of electrical characteristics. .

  Note that the gate electrode overlaps with the source or drain semiconductor region when the gate electrode overlaps a part of the source or drain semiconductor region in the thickness direction (a direction substantially perpendicular to the main surface of the substrate). It corresponds. In this case, a part of the semiconductor region for source or drain is located immediately below the gate electrode.

  As a third problem, when the insulating film GIa as shown in FIG. 24 of the present application is formed as the gate insulating film in the trench TR101 in the second study example, the bottom surface and the side surface of the trench TR101 are almost vertical. ing. Therefore, when the insulating film GIa is formed by the CVD method or the ALD method, the thickness of the insulating film GIa tends to be thin at the corner portion of the trench TR101. Then, since the insulating film GIa is thin at the end of the gate electrode GE102, electric field concentration is likely to occur, and the breakdown voltage of the MISFET is reduced.

  As a fourth problem, when the gate length of the gate electrode GE102 is shortened by miniaturization, it is difficult to completely fill the gate electrode GE102 in the trench TR101 in the second study example. That is, when the diameter of the trench TR101 becomes small, the aspect ratio naturally becomes strict (large), so that the conductive film to be the gate electrode GE102 is not completely buried in the trench TR101, and holes are generated. Fear comes out. Therefore, the reliability of the MISFET is lowered. In particular, when the insulating film GIa is formed as the gate insulating film in the trench TR101 by the CVD method or the ALD method, the insulating film GIa is also formed on the side surface of the trench TR101. Smaller caliber. Therefore, the embedding of the gate electrode GE102 becomes more severe.

  The present embodiment and other embodiments have been devised based on the above-described multiple problems. That is, the first and second problems described above are to improve the performance of the semiconductor device. The third and fourth problems described above are to improve the reliability of the semiconductor device.

<Main features of the present embodiment>
In the present embodiment, the end portions of the gate electrode GE (both end portions in the gate length direction) run on the semiconductor layer EP1 which is an epitaxial layer for source / drain in order to deal with the above-described problems. That is, the end of the gate electrode GE in the gate length direction is located on the semiconductor layer EP1 that is an epitaxial layer for source / drain. In other words, in the gate length direction of the MISFET (MISFET having the gate electrode GE as the gate electrode), the end of the gate electrode GE is located on the semiconductor layer EP1 which is an epitaxial layer for source / drain. Note that an end portion in the gate length direction of the gate electrode GE (that is, an end portion of the gate electrode GE in the gate length direction) is indicated as an end portion EG in FIG.

For this reason, the gate electrode GE can be surely overlapped with the semiconductor region for source or drain (a combination of the n ⁻ type semiconductor region EX and the n ⁺ type semiconductor region SD). Alternatively, parasitic resistance between the semiconductor region for drain and the channel region can be suppressed. That is, since at least part of the n ⁻ type semiconductor region EX is located immediately below the gate electrode GE, parasitic resistance can be suppressed. Therefore, the first problem can be solved.

  The semiconductor layer EP1 is formed on the upper surface of the semiconductor layer SM1, and the upper surface of the semiconductor layer EP1 is higher than the upper surface of the semiconductor layer SM1 immediately below the gate electrode GE. The end of the gate electrode GE in the gate length direction is located on the semiconductor layer EP1 which is an epitaxial layer for source / drain. As described above, the upper surface of the semiconductor layer SM1 immediately below the gate electrode GE corresponds to the surface (upper surface) of the semiconductor layer SM1 in contact with the gate insulating film GI below the gate electrode GE.

For this reason, in the present embodiment, the semiconductor layer (SM2) in the overlapping portion between the semiconductor region for source or drain (a combination of the n ⁻ type semiconductor region EX and the n ⁺ type semiconductor region SD) and the gate electrode GE. ) Can be made thicker than the semiconductor layer SM1 by the thickness of the semiconductor layer EP1 in the overlap portion. Therefore, in the present embodiment, the thickness of the semiconductor layer (SM2) in the overlap portion between the semiconductor region for source or drain and the gate electrode GE can be increased, and parasitic resistance can be suppressed. Therefore, the second problem can be solved.

  For this reason, in this embodiment mode, parasitic resistance between the semiconductor region for the source or drain and the channel region can be suppressed, so that the characteristics (electrical characteristics) of the semiconductor device including the MISFET can be improved. it can. For example, by suppressing the parasitic resistance between the source or drain semiconductor region and the channel region, the on-resistance can be reduced and the on-current can be increased. Accordingly, the electrical characteristics of the MISFET can be improved. In addition, since the parasitic resistance between the semiconductor region for source or drain and the channel region can be suppressed, variation in characteristics of each MISFET due to variation in the value of the parasitic resistance can also be suppressed. For this reason, the performance of the semiconductor device can be improved.

  In addition, when an SOI substrate is used, a gate electrode is formed on a thin semiconductor layer of the SOI substrate. Therefore, compared with a case where a bulk semiconductor substrate is used, a semiconductor region for a source or a drain and a gate electrode are formed. It is difficult to increase the thickness of the semiconductor layer in the overlap portion. On the other hand, in the present embodiment, the end of the gate electrode GE in the gate length direction is located on the semiconductor layer EP1 (that is, the end of the gate electrode GE rides on the semiconductor layer EP1). Therefore, even if the thickness of the semiconductor layer SM1 of the SOI substrate SUB is not increased, the semiconductor region for the source or drain and the gate electrode GE are overlaid by the thickness of the semiconductor layer EP1 in the portion where the gate electrode GE rides. The thickness of the semiconductor layer (SM2) in the wrap portion can be increased, and parasitic resistance can be suppressed. For this reason, the performance of the semiconductor device manufactured using the SOI substrate can be improved.

The n ⁻ type semiconductor region EX and the n ⁺ type semiconductor region SD are formed in the semiconductor layers SM1 and EP1. That is, the n ⁻ type semiconductor region EX and the n ⁺ type semiconductor region SD are formed from the semiconductor layer EP1 to the semiconductor layer SM1 when viewed in the thickness direction (a direction substantially perpendicular to the main surface of the SOI substrate SUB). That is, a semiconductor region for source or drain (a combination of the n ⁻ type semiconductor region EX and the n ⁺ type semiconductor region SD) is formed in the semiconductor layer EP1 and the semiconductor layer SM1 therebelow. For this reason, when the end of the gate electrode GE in the gate length direction is positioned on the semiconductor layer EP1, the n ⁻ type semiconductor region EX (n ⁺ Type semiconductor region SD) may exist. Accordingly, the semiconductor region for source or drain and the gate electrode GE can be reliably overlapped.

  Further, as shown in FIG. 24 and the like, the gate insulating film GIa (and hence the gate insulating film GI) is formed along the shape of the semiconductor layer EP1. In the present embodiment, the semiconductor layer EP1 has an inclined portion (inclined side surface SF1), and the gate insulating film GI (insulating film GIa) and the gate electrode GE are along the inclined portion (inclined side surface SF1). It is formed. For this reason, it is easy to form the gate insulating film GI (insulating film GIa) uniformly in the trench TR. Therefore, it is possible to solve the problem that the breakdown voltage of the MISFET is lowered as shown in the third problem.

  Further, as shown in FIGS. 22 and 23, the diameter of the trench TR can be made larger than the length of the dummy gate GED. For this reason, as shown in FIG. 25, since the aspect ratio is ensured (the aspect ratio of the trench TR can be reduced), even when the conductive film CD serving as the gate electrode GE is deposited in the trench TR, there is no vacancy. Less likely to occur. Therefore, it is possible to solve the problem as shown in the fourth problem. This is particularly effective when miniaturization advances and a MISFET having a gate length of 30 nm or less is designed.

  Furthermore, in the first and second study examples described above, the length of the upper part and the lower part of the gate electrode is substantially the same. However, in the MISFET of this embodiment, the length of the upper part of the gate electrode GE Since the total volume of the gate electrode GE can be increased, the resistance of the gate electrode GE can be reduced.

<Modification of Embodiment 1>
FIG. 36 and FIG. 37 are principal part sectional views of a semiconductor device according to a modification of the present embodiment. FIG. 36 corresponds to FIG. 1 and FIG. 37 corresponds to FIG. . FIG. 38 is a fragmentary cross-sectional view of the semiconductor device of the variation shown in FIGS. 36 and 37 during the manufacturing process. FIG. 38 corresponds to FIG. 9 and shows a stage where step S4 (pitaxial growth process of the semiconductor layer EP1) has been performed.

  36 and 37, when the semiconductor layer EP1 is epitaxially grown in step S4, the side surface SF1a of the semiconductor layer EP1 does not have a taper as shown in FIG. This is a semiconductor device manufactured when the semiconductor layer EP1 is epitaxially grown. That is, in the modified example, as shown in FIG. 38, the side surface SF1a of the semiconductor layer EP1 is substantially perpendicular to the main surface of the SOI substrate SUB (that is, the main surface of the semiconductor layer SM1). Layer EP1 is epitaxially grown. The presence or absence of a taper on the side surface of the semiconductor layer EP1 can be controlled by adjusting the composition of the film forming gas for the semiconductor layer EP1, the film forming temperature, and the like.

  Also in the semiconductor device of the modification shown in FIGS. 36 and 37, the end portions (both end portions in the gate length direction) of the gate electrode GE run on the semiconductor layer EP1 which is the source / drain epitaxial layer. That is, the end of the gate electrode GE in the gate length direction is located on the semiconductor layer EP1 that is an epitaxial layer for source / drain. In other words, in the gate length direction of the MISFET (MISFET having the gate electrode GE as the gate electrode), the end of the gate electrode GE is located on the semiconductor layer EP1 which is an epitaxial layer for source / drain. The semiconductor layer EP1 is formed on the upper surface of the semiconductor layer SM1, and the upper surface of the semiconductor layer EP1 is higher than the upper surface of the semiconductor layer SM1 directly below the gate electrode GE. For this reason, as described above, the parasitic resistance between the source or drain semiconductor region and the channel region can be suppressed. That is, the above first and second problems can be solved.

  However, as compared with the semiconductor device of the modification shown in FIGS. 36 and 37, the semiconductor device of the present embodiment shown in FIGS. 1 and 2 has the following advantages.

  That is, in the semiconductor device of the present embodiment shown in FIGS. 1 and 2, the end of the gate electrode GE in the gate length direction is located on the semiconductor layer EP1, but the side surface SF1 of the semiconductor layer EP1 is The end of the gate electrode GE in the gate length direction is located on the inclined side surface SF1 of the semiconductor layer EP1. In other words, the side surface (side surface on the gate electrode GE side) SF1 of the semiconductor layer EP1 is inclined in the gate length direction of the MISFET (MISFET having the gate electrode GE as the gate electrode), and the MISFET (the gate electrode GE is used as the gate electrode). In the gate length direction of MISFET, the end of the gate electrode GE is located on the inclined side surface SF1 of the semiconductor layer EP1. That is, the end portion (end portion in the gate length direction) of the gate electrode GE rides on the inclined side surface SF1 of the semiconductor layer EP1.

  In the case of the semiconductor device of the modification shown in FIGS. 36 and 37, the corner portions EG1 and EG2 facing the semiconductor layers SM1 and EP1 in the gate electrode GE shown in FIG. There is a concern that the electric field concentrates at the corner portions EG1 and EG2 to cause gate leakage. On the other hand, the semiconductor device of the present embodiment shown in FIGS. 1 and 2 has the semiconductor layer SM1 in the gate electrode GE shown in FIG. 1 because the side surface SF1 of the semiconductor layer EP1 is inclined. Since the corners EG3 and EG4 facing the EP1 are obtuse, the electric field concentration at the corners EG3 and EG4 can be reduced. For this reason, compared with the semiconductor device of the modification shown in FIGS. 36 and 37, the semiconductor device of the present embodiment shown in FIGS. Current) can be suppressed.

  Further, when the insulating film GIa and the conductive film CD are formed in Steps S14 and S15, the side surface of the semiconductor layer EP1 exposed from the trench TR is a vertical side surface SF1a (in the case of the modified example of FIGS. 36 and 37). In the case of the inclined side surface SF1 (corresponding to the case of the present embodiment in FIGS. 1 and 2), it is easier to form the insulating film GIa and the conductive film CD in the trench TR. Therefore, compared with the semiconductor device of the modification shown in FIGS. 36 and 37, the semiconductor device of the present embodiment shown in FIGS. 1 and 2 has the gate electrode GE and the gate insulating film GI, It can be formed more easily and accurately.

  Therefore, it is more preferable that the side surface SF1 of the semiconductor layer EP1 is inclined, and the end of the gate electrode GE in the gate length direction is located on the inclined side surface SF1 of the semiconductor layer EP1. That is, it is more preferable that the end portion (end portion in the gate length direction) of the gate electrode GE rides on the inclined side surface SF1 of the semiconductor layer EP1. That is, the semiconductor device of the present embodiment shown in FIGS. 1 and 2 has the same effect for the fourth problem, but the third problem shown in FIGS. 36 and the modified semiconductor device shown in FIG.

  In the present embodiment, the end of the gate electrode GE in the gate length direction is located on the semiconductor layer EP1. That is, the end portions (both end portions in the gate length direction) of the gate electrode GE run on the semiconductor layer EP1. In order to obtain such a structure, the following process is adopted as a manufacturing process.

  That is, in this embodiment, after forming the dummy gate GED in step S2, the semiconductor layer EP1 which is an epitaxial layer for source / drain is formed in step S4, and then on the sidewall of the dummy gate GED in step S6. Then, the sidewall insulating film SW2 is formed. Then, after forming the insulating film IL1 so as to cover the dummy gate GED in step S11, a part of the insulating film IL1 is removed in step S12 to expose the upper surface of the dummy gate GED. Thereafter, the dummy gate and the sidewall insulating film SW2 are removed in step S13 to form the trench TR, and then in steps S14 to S16, the gate electrode GE is formed in the trench TR via the gate insulating film GI.

  Here, it is particularly important to form the side wall insulating film SW2 on the side wall of the dummy gate GED after forming the semiconductor layer EP1 which is the source / drain epitaxial layer, and to remove the dummy gate GED in step S13. Not only the sidewall insulating film SW2 but also the gate electrode GE is formed in the trench TR formed by removing the dummy gate GED and the sidewall insulating film SW2. Unlike the present embodiment, as in the second study example (FIGS. 32 to 35), when the dummy gate GED is removed in step S13 but the sidewall insulating film SW2 is left without being removed, The end portions (both end portions in the gate length direction) of the electrode GE102 do not run on the semiconductor layer EP1.

  That is, the side wall insulating film SW2 formed on the side wall of the dummy gate GED is removed together with the dummy gate GED in step S13, so that the dimension in the gate length direction of the gate electrode GE formed thereafter is changed to the dummy gate GED. It can be made larger than the dimension. Since the sidewall insulating film SW2 is formed after the semiconductor layer EP1 is formed, the sidewall insulating film SW2 is formed on the semiconductor layer EP1, and after the sidewall insulating film SW2 is removed together with the dummy gate GED in step S13, If the gate electrode GE is formed, the gate electrode GE also occupies the region where the sidewall insulating film SW2 existed before the removal. For this reason, a part of the gate electrode GE is located on the semiconductor layer EP1, that is, runs on the semiconductor layer EP1.

  When the sidewall insulating films SW1, SW2, and SW3 are formed on the sidewalls of the dummy gate GED, the sidewall insulating film SW1 formed before the formation of the semiconductor layer EP1 is removed in step S13, but formed after the formation of the semiconductor layer EP1. When the side wall insulating films SW2 and SW3 are left without being removed, the end portions of the gate electrode GE (both end portions in the gate length direction) do not run on the semiconductor layer EP1. Therefore, when the sidewall insulating films SW1, SW2, SW3 are formed on the sidewalls of the dummy gate GED, in step S13, not only the sidewall insulating film SW1 formed before the formation of the semiconductor layer EP1 is removed, but also the semiconductor It is necessary to remove the sidewall insulating film SW2 formed after the formation of the layer EP1 or to reduce the thickness of the sidewall insulating film SW2 by etching. That is, the side wall insulating film SW2 formed on the side wall of the dummy gate GED after the formation of the semiconductor layer EP1 is removed together with the dummy gate GED (or the side wall insulating film SW2 is thinned) in step S13. A structure in which the portions (both end portions in the gate length direction) ride on the semiconductor layer EP1 can be obtained.

  In the present embodiment, the structure in which the gate electrode GE runs over the semiconductor layer EP1 can be formed by self-alignment (self-alignment) while suppressing the use of the photolithography process. For this reason, the malfunction by the position shift of a photomask pattern can be prevented. Further, the semiconductor element can be reduced in size. Therefore, the semiconductor device can be reduced in size.

  Further, in this embodiment, a so-called gate last process is used in which the gate insulating film GI and the gate electrode GE are formed after the dummy gate GED is removed. Therefore, it is easy to apply a metal gate electrode and a high dielectric constant gate insulating film as the gate electrode GE and the gate insulating film GI. Further, a structure in which the gate electrode GE rides on the semiconductor layer EP1 can be formed by self-alignment while suppressing an increase in the number of manufacturing steps by using the gate last process.

(Embodiment 2)
The second embodiment corresponds to a modification of the manufacturing process of the semiconductor device of the first embodiment. 39 to 45 are fragmentary cross-sectional views of the semiconductor device of Second Embodiment during the manufacturing process thereof.

  In the first embodiment, the case where the sidewall insulating films SW1 and SW2 are formed of silicon oxide and the sidewall insulating film SW3 is formed of silicon nitride has been described. However, in the second embodiment, the sidewall insulating films SW1 and SW2 are formed. A case where SW2 and SW3 are formed of silicon nitride will be described.

  In the second embodiment, in step S3, a silicon nitride film is used instead of the silicon oxide film SO1, so that the side wall insulating film SW1a made of silicon nitride is used instead of the side wall insulating film SW1 made of silicon oxide. Form. The sidewall insulating film SW1a is basically the same as the sidewall insulating film SW1 except that it is made of silicon nitride instead of silicon oxide. That is, the side wall insulating film SW1 when formed of silicon nitride is referred to as a side wall insulating film SW1a.

  In the second embodiment, in step S6, by using a silicon nitride film instead of the silicon oxide film SO2, side wall insulation made of silicon nitride instead of the side wall insulation film SW2 made of silicon oxide. A film SW2a is formed. The sidewall insulating film SW2a is basically the same as the sidewall insulating film SW2 except that it is made of silicon nitride instead of silicon oxide. That is, the sidewall insulating film SW2 when formed of silicon nitride is referred to as a sidewall insulating film SW2a.

  Also in the present second embodiment, in step S9, as in the first embodiment, the sidewall insulating film SW3 made of silicon nitride is formed.

  Other than this, the structure shown in FIG. 39 corresponding to FIG. 19 is obtained by performing the steps up to the CMP step of step S12 in the same manner as in the first embodiment.

  In the stage of FIG. 39, the difference from the stage of FIG. 19 of the first embodiment is that the side wall insulating films SW1 and SW2 made of silicon oxide are replaced with the side wall insulating films SW1a and SW2a made of silicon nitride. Other than that, it is basically the same.

  After the CMP process of step S12 is performed in the same manner as in the first embodiment to obtain the structure of FIG. 39, in the second embodiment also, the dummy gate GED and the sidewall insulating film SW1 are etched by the etching in step S13. , SW2 is removed. The etching conditions in step S13 are partially different from those described in the first embodiment because the side wall insulating films SW1 and SW2 made of silicon oxide are replaced with the side wall insulating films SW1a and SW2a made of silicon nitride. ing. Hereinafter, step S13 in the case of this Embodiment 2 is demonstrated concretely.

  First, as shown in FIG. 40, as the first stage of etching in step S13, the silicon nitride film SN1 of the dummy gate GED is removed. This first stage etching is performed in the second embodiment as well. The same as in the first embodiment. By the first stage etching, the silicon nitride film SN1 is removed, and the polysilicon film PL1 is exposed.

  Next, as a second stage of etching in step S13, as shown in FIG. 41, the polysilicon film PL1 of the dummy gate GED is removed. This second stage of etching is also performed in the second embodiment. This is the same as in the first embodiment. By the second-stage etching, the polysilicon film PL1 is removed, and the sidewall insulating film SW1 and the insulating film GID are exposed.

  The third and subsequent stages of etching in step S13 are different from those in the first embodiment. That is, after the polysilicon film PL1 is removed by the second stage etching, in the second embodiment, as shown in FIG. 42, the insulating film GID is removed by the third stage etching. This third stage etching is performed under such an etching condition that the etching rate of the insulating film GID (silicon oxide) is faster than the etching rates of the sidewall insulating films SW1a and SW2a (silicon nitride) and the semiconductor layers SM1 and EP1 (silicon). Thus, it is preferable to selectively etch the insulating film GID. Thereby, it is possible to suppress or prevent the semiconductor layers SM1 and EP1 from being etched by the third stage etching.

  If the insulating film GID is formed of a material film (specifically, a silicon oxide film or the like) different from the sidewall insulating films SW1a and SW2a, the insulating film GID can be removed by this third stage etching. On the other hand, if the insulating film GID is formed of the same material as the sidewall insulating films SW1a and SW2a (specifically, a silicon nitride film), the third stage etching is not performed and the next fourth stage etching is performed. The insulating film GID is also removed by the fourth stage etching.

  In the second embodiment, the third-stage etching (etching for removing the insulating film GID) is performed after the fourth-stage etching (etching for removing the sidewall insulating films SW1a and SW2a) described below. It can also be done.

  Next, as a fourth stage of etching in step S13, as shown in FIG. 43, the sidewall insulating films SW1a and SW2a made of silicon nitride are removed. This fourth stage etching is performed under etching conditions such that the etching rate of the sidewall insulating films SW1a, SW2a (silicon nitride) is higher than the etching rate of the semiconductor layers SM1, EP1. Thereby, it is possible to suppress or prevent the semiconductor layers SM1 and EP1 from being etched by the fourth stage etching. Further, since the sidewall insulating films SW1a, SW2a, SW3 are formed of silicon nitride, it is easy to ensure a high etching selectivity between the sidewall insulating films SW1a, SW2a, SW3 and the semiconductor layers SM1, EP1.

  In the fourth stage etching, not only the sidewall insulating films SW1a and SW2a, but also the sidewall insulating film SW3 is formed of silicon nitride. Therefore, in the fourth stage etching, the etching time is controlled so that the sidewall insulating films SW1a and SW2a are removed by etching and the sidewall insulating film SW3 remains. That is, in the fourth stage etching, the sidewall insulating films SW1a and SW2a are removed by etching by setting the total thickness of the sidewall insulating film SW1a and the sidewall insulating film SW2a to an etching time that can be etched. The film SW3 can be left.

  Note that in the fourth stage of etching in step S13, it is necessary to remove the entire sidewall insulating film SW1a (total thickness).

  Further, in the fourth stage etching of step S13, it is desirable to remove the entire sidewall insulating film SW1a (total thickness). However, a case where a part of the sidewall insulating film SW2a remains in a layer form on the inner wall of the sidewall insulating film SW3 can be allowed. Even in this case, the thickness of the sidewall insulating film SW2a remaining on the inner wall of the sidewall insulating film SW3 is acceptable. Needs to be thinner than the thickness of the sidewall insulating film SW2a in the state before the fourth stage etching.

  In the fourth stage etching of step S13, it is desirable that the side wall insulating film SW3 is left almost entirely (total thickness), but the side wall insulating film SW3 is slightly etched (thickness of the side wall insulating film SW3). It is also possible to allow a case where a part of the sidewall insulating film SW3 remains in a layered state after a part of the film is etched. For this reason, the thickness of the sidewall insulating film SW3 may be thinner than the thickness of the sidewall insulating film SW3 in the state before the fourth-stage etching, but at least a part of the sidewall insulating film SW3 remains in a layered manner. At this stage, the fourth stage of etching in step S13 is terminated.

  That is, the sidewall insulating film SW1a, the sidewall insulating film SW2a, and the sidewall insulating film SW3 are formed of silicon nitride, but the etching in the fourth stage of the etching in step S13 has an etching thickness that is larger than the thickness of the sidewall insulating film SW1a. The etching time is set so that the thickness is increased and the etching thickness is smaller than the total thickness of the sidewall insulating film SW1a, the sidewall insulating film SW2a, and the sidewall insulating film SW3. In other words, the etching in the fourth stage of step S13 is such that the etching continues even after the sidewall insulating film SW1a is removed and the sidewall insulating film SW2a is exposed, and the total thickness of the sidewall insulating film SW3 is reduced. The etching time is set so that the etching is stopped at the stage before being etched. In other words, the end point of the etching in the fourth stage of the etching in step S13 is from the stage where the etching has progressed to the middle of the thickness of the sidewall insulating film SW2a to the stage where the etching has progressed to the middle of the thickness of the sidewall insulating film SW3. Set in between.

  If the formation of the sidewall insulating film SW3 is omitted, the sidewall insulating films SW1a and SW2a are removed and the insulating film IL1 (more specifically, the silicon nitride film of the insulating film IL1) is removed in the fourth stage etching in step S13. Etching may be terminated when SN3) is exposed.

  43, by removing the dummy gate GED, the insulating film GID, and the side wall insulating films SW1a and SW2a by etching in the above four stages (first stage, second stage, third stage and fourth stage) of step S13. As described above, the trench TR is formed.

  Subsequent steps are substantially the same as those in the first embodiment. That is, the insulating film GIa for the gate insulating film is formed in the step S14, the conductive film CD for the gate electrode is formed in the step S15, and the conductive film CD and the insulating film outside the trench TR are formed in the step S16. By removing GIa by a CMP method or the like, a gate electrode GE is formed in the trench TR via the gate insulating film GI as shown in FIG. Then, as shown in FIG. 45, as in the first embodiment, the insulating film IL2 is formed, the contact hole CNT is formed, the plug PG is formed in the contact hole CNT, and the insulating film is formed. IL3 is formed, and the wiring M1 is formed.

  Thus, also in the second embodiment, a semiconductor device substantially similar to the first embodiment can be manufactured. That is, the above first to fourth problems can be solved.

  In the first embodiment, since the sidewall insulating films SW1 and SW2 are silicon oxide films, the sidewall insulating film SW3 or the silicon nitride film SN3 can be used as an etching stopper, and the etching control in step S13 is facilitated. be able to.

  On the other hand, in the second embodiment, since the sidewall insulating films SW1a and SW2a are silicon nitride films, there is an advantage that the selection ratio with the interlayer insulating film SO3 can be easily obtained. That is, in the first embodiment, when the material of the sidewall insulating films SW1a, SW2a and the interlayer insulating film SO3 is the same silicon oxide film, the surface of the interlayer insulating film SO3 tends to recede. However, since the materials of the sidewall insulating films SW1a and SW2a and the interlayer insulating film SO3 are different in the second embodiment, the surface of the interlayer insulating film SO3 is unlikely to recede. Therefore, it is possible to easily control the height of the interlayer insulating film SO3.

  Note that a silicon oxynitride film may be used instead of the silicon nitride film as the material of the liner film SN3. In this case, since the silicon oxynitride film (liner film SN3) is different from the material of the sidewall insulating films SW1, SW2, and SW3 and the material of the insulating film SO3, the surface of the interlayer insulating film SO3 recedes when the trench TR is formed. It can also deal with the problem.

(Embodiment 3)
46 and 47 are process flowcharts showing the manufacturing process of the semiconductor device of the third embodiment. 48 to 63 are cross-sectional views of relevant parts in the manufacturing process of the semiconductor device of Third Embodiment.

  In the first embodiment, only one epitaxial layer for source / drain (corresponding to the semiconductor layer EP1) is formed on the semiconductor layer SM1 of the SOI substrate SUB. On the other hand, in the third embodiment, two source / drain epitaxial layers (corresponding to semiconductor layers EP2 and EP3 described later) are formed on the semiconductor layer SM1 of the SOI substrate SUB. In the third embodiment, the first, second, and fourth problems described above can be solved.

  Hereinafter, specific description will be given with reference to the drawings.

  Also in the third embodiment, similarly to the first embodiment, the steps up to the step S3 for forming the sidewall insulating film SW1 are performed to obtain the structure of FIG. 48 corresponding to FIG.

  Next, as shown in FIG. 49, the semiconductor layer EP2 is epitaxially grown on the semiconductor layer SM1 (step S4a in FIG. 46).

  Similar to the semiconductor layer EP1, the semiconductor layer EP2 is also formed on the semiconductor layer SM1 in a region on both sides of the dummy gate GED (more specifically, a structure including the dummy gate GED and the sidewall insulating film SW1). That is, on the semiconductor layer SM1, the dummy gate GED (more specifically, the dummy gate GED and the side wall insulation is provided on both sides of the dummy gate GED (more specifically, the structure including the dummy gate GED and the side wall insulating film SW1). The semiconductor layer EP2 is formed so as to be adjacent to the structure including the film SW1.

  Similar to the semiconductor layer EP1, the semiconductor layer EP2 is an epitaxial layer (epitaxial semiconductor layer) formed by epitaxial growth, and is made of silicon (single crystal silicon). The semiconductor layer EP2 is selectively epitaxially grown on the semiconductor layer SM1, and is not formed on the sidewall insulating film SW1 or the silicon nitride film SN1. Further, as described in the first embodiment, since the polysilicon film PL1 of the dummy gate GED is covered with the silicon nitride film SN1 and the sidewall insulating film SW1, no epitaxial layer is formed on the polysilicon film PL1. .

  In the first embodiment, the semiconductor layer EP1 is epitaxially grown so that the side surface of the semiconductor layer EP1 has a taper. However, in the third embodiment, the side surface of the semiconductor layer EP2 does not have a taper. The semiconductor layer EP2 can be epitaxially grown. That is, the semiconductor layer EP2 is epitaxially grown so that the side surface of the semiconductor layer EP2 is substantially perpendicular to the main surface of the SOI substrate SUB (that is, the main surface of the semiconductor layer SM1). The presence or absence of taper on the side surface of the semiconductor layer EP2 (therefore, the angle between the main surface of the semiconductor layer SM1 and the side surface of the semiconductor layer EP2) is adjusted by adjusting the composition of the film forming gas of the semiconductor layer EP2, the film forming temperature, and the like. Can be controlled.

  Since the semiconductor layer EP2 is formed on a substantially flat upper surface of the semiconductor layer SM1, the upper surface of the semiconductor layer EP2 is located higher than the upper surface of the semiconductor layer SM2. Therefore, the upper surface of the semiconductor layer EP1 formed in step S4a is higher than the upper surface of the semiconductor layer SM1 immediately below the dummy gate GED.

Next, as shown in FIG. 50, n-type impurities such as phosphorus (P) or arsenic (As) are ion-implanted into the regions on both sides of the dummy gate GED and the sidewall insulating film SW1 in the semiconductor layers SM1 and EP2. Thereby, the n ⁻ type semiconductor region EX is formed (step S5 in FIG. 46).

The ion implantation process in step S5 is basically the same as that of the first embodiment in the third embodiment, but in the first embodiment, the stacked body of the semiconductor layer SM1 and the semiconductor layer EP1 is used. In contrast to the n ⁻ type semiconductor region EX formed by implanting the n type impurity, in the third embodiment, the n type impurity is implanted into the stacked body of the semiconductor layer SM1 and the semiconductor layer EP2. Thus, the n ⁻ type semiconductor region EX is formed.

In the ion implantation step for forming the n ⁻ type semiconductor region EX, the dummy gate GED and the sidewall insulating film SW1 can function as a mask (ion implantation blocking mask). Therefore, the n ⁻ type semiconductor region EX is formed in the semiconductor layer SM1 and the semiconductor layer EP2 (stacked body thereof) in a self-aligned manner with respect to the sidewall insulating film SW1 on the sidewall of the dummy gate GED.

  Next, as shown in FIG. 51, a sidewall insulating film (sidewall spacer) SW4 is formed as a sidewall film on the sidewall of the dummy gate GED (step S6a in FIG. 46). The sidewall insulating film SW4 is formed on the sidewall of the dummy gate GED via the sidewall insulating film SW1.

  The sidewall insulating film SW4 is formed by stacking a sidewall insulating film SW4a that is a sidewall film and a sidewall insulating film SW4b that is a sidewall film. The sidewall insulating film SW4a and the sidewall insulating film SW4b are formed of different materials. Preferably, the sidewall insulating film SW4a is formed of silicon oxide (silicon oxide film), and the sidewall insulating film SW4b is silicon nitride (silicon nitride film). It is formed by.

  The sidewall insulating film SW4a is not necessarily insulative because it will be removed later, but it is easy to form as a sidewall film, and from the viewpoint that it is possible to prevent problems when etching residue occurs during removal. An insulating film is desirable. Further, since the sidewall insulating film SW4b remains in the manufactured semiconductor device, it has an insulating property.

  In order to form the sidewall insulating film SW4, first, the sidewall insulating film SW4a is formed. In order to form the sidewall insulating film SW4a, first, a silicon oxide film is formed over the entire main surface of the SOI substrate SUB by a CVD method or the like so as to cover the dummy gate GED and the sidewall insulating film SW1. Then, the silicon oxide film is etched back (anisotropic etching) to leave the silicon oxide film on the side wall of the dummy gate GED to form the side wall insulating film SW4a, and the silicon oxide film in other regions is removed. Thereby, the sidewall insulating film SW4a is formed on the sidewall of the dummy gate GED via the sidewall insulating film SW1. After the formation of the sidewall insulating film SW4a, the sidewall insulating film SW4b is formed. In order to form the sidewall insulating film SW4b, first, a silicon nitride film is formed over the entire main surface of the SOI substrate SUB by a CVD method or the like so as to cover the dummy gate GED and the sidewall insulating films SW1 and SW4a. Then, this silicon nitride film is etched back (anisotropic etching) to leave the silicon nitride film on the side wall of the dummy gate GED to form the side wall insulating film SW4b and to remove the silicon nitride film in other regions. As a result, the sidewall insulating film SW4b is formed on the sidewall of the dummy gate GED via the sidewall insulating films SW1 and SW4a. In this way, the side wall insulating film SW4 formed of the stacked layer of the side wall insulating film SW4a and the side wall insulating film SW4b is formed on the side wall of the dummy gate GED via the side wall insulating film SW1.

  The thickness of the side wall insulating film SW4a (thickness in the direction substantially perpendicular to the side wall of the dummy gate GED) can be, for example, about 5 to 10 nm, and the thickness of the side wall insulating film SW4b (direction substantially perpendicular to the side wall of the dummy gate GED). ) Can be about 10 to 30 nm, for example.

  The side wall insulating film SW4 is formed adjacent to the side wall of the dummy gate GED via the side wall insulating film SW1 and on the semiconductor layer EP2. That is, the bottom surface of the sidewall insulating film SW4 is in contact with the semiconductor layer EP2 (specifically, the top surface of the semiconductor layer EP2), and the inner wall (side surface on the side facing the dummy gate GED) of the sidewall insulating film SW4 is on the sidewall of the dummy gate GED. Is in contact with the side wall insulating film SW1.

  Next, as shown in FIG. 52, the semiconductor layer EP3 is epitaxially grown on the semiconductor layer EP2 (step S4b in FIG. 46).

  The semiconductor layer EP3 is formed on the semiconductor layer SM1 in a region on both sides of the dummy gate GED (more specifically, a structure including the dummy gate GED and the sidewall insulating films SW1 and SW4). That is, on the semiconductor layer SM1, dummy gates GED (more specifically, dummy gates GED and more specifically, dummy gates GED and more specifically, dummy gates GED and dummy gates GED) The semiconductor layer EP3 is formed so as to be adjacent to the structure including the sidewall insulating films SW1 and SW4.

  Similar to the semiconductor layers EP1 and EP2, the semiconductor layer EP3 is an epitaxial layer (epitaxial semiconductor layer) formed by epitaxial growth and is made of silicon (single crystal silicon). The semiconductor layer EP3 is selectively epitaxially grown on the semiconductor layer EP2, and is not formed on the sidewall insulating films SW1 and SW4 or the silicon nitride film SN1. As described above, since the polysilicon film PL1 of the dummy gate GED is covered with the silicon nitride film SN1 and the sidewall insulating films SW1 and SW4, no epitaxial layer is formed on the polysilicon film PL1. Further, although the semiconductor layer EP3 is formed on the semiconductor layer EP2, the semiconductor layer EP3 is not formed on the portion of the semiconductor layer EP2 covered with the sidewall insulating film SW4. Therefore, the side surface of the semiconductor layer EP2 is adjacent to the sidewall insulating film SW1, while the side surface of the semiconductor layer EP3 is adjacent to the sidewall insulating film SW4b.

  Similarly to the semiconductor layer EP2, the semiconductor layer EP3 can be epitaxially grown so that the side surface of the semiconductor layer EP3 does not have a taper. That is, the semiconductor layer EP3 is epitaxially grown so that the side surface of the semiconductor layer EP3 is substantially perpendicular to the main surface of the SOI substrate SUB (that is, the main surface of the semiconductor layer SM1). The presence or absence of taper on the side surface of the semiconductor layer EP3 (therefore, the angle between the main surface of the semiconductor layer SM1 and the side surface of the semiconductor layer EP3) is adjusted by adjusting the composition of the film forming gas of the semiconductor layer EP3, the film forming temperature, and the like. Can be controlled.

  In addition, the formation thickness of the semiconductor layer EP3 in step S4b is preferably thicker than the formation thickness of the semiconductor layer EP2 in step S4a. This makes it easy to prevent the occurrence of a region where the silicon region disappears in the thickness direction with the subsequent formation of the metal silicide layer SIL.

Next, as shown in FIG. 53, n-type impurities such as phosphorus (P) or arsenic (As) are formed in the regions on both sides of the dummy gate GED and the sidewall insulating films SW1 and SW4 in the semiconductor layers SM1, EP2, and EP3. Are ion-implanted to form an n ⁺ type semiconductor region SD (step S7 in FIG. 46).

The ion implantation process in step S7 is basically the same as that in the first embodiment in the third embodiment. However, in the first embodiment, the n ⁺ -type semiconductor region SD is formed by injecting the n-type impurity into the stacked body of the semiconductor layer SM1 and the semiconductor layer EP1. 3, an n ⁺ -type semiconductor region SD is formed by implanting an n-type impurity into the stacked body of the semiconductor layer SM1, the semiconductor layer EP2, and the semiconductor layer EP3.

In the ion implantation process for forming the n ⁺ type semiconductor region SD, the dummy gate GED and the sidewall insulating films SW1 and SW4 can function as a mask (ion implantation blocking mask). Therefore, the n ⁺ type semiconductor region SD is formed in self-alignment with the sidewall insulating film SW4 formed on the sidewall of the dummy gate GED via the sidewall insulating film SW1. The n ⁺ type semiconductor region SD has a higher impurity concentration than the n ⁻ type semiconductor region EX.

Before forming the sidewall insulating film SW4 in step S6a, ion implantation (step S5) for forming the n ⁻ type semiconductor region EX is performed, and after forming the sidewall insulating film SW4 in step S6a, the n ⁺ type semiconductor is formed. Ion implantation (step S7) for forming the region SD is performed. For this reason, when the steps up to step S7 are performed, the n ⁻ type semiconductor region EX is formed in the semiconductor layers SM1 and EP2 immediately below the sidewall insulating film SW4 (4a and 4b). In step S13a, which will be described later, since the gate electrode GE is formed after the sidewall insulating film SW4a is also removed together with the dummy gate GED, the gate electrode GE is also formed in the region where the sidewall insulating film SW4a was present. Become. For this reason, when the gate electrode GE is formed later, the n ⁻ type semiconductor region EX is substantially formed directly below a part of the gate electrode GE (on both ends in the gate length direction) and directly below the sidewall insulating film SW4b. It becomes a state.

Next, activation annealing which is a heat treatment for activating the impurities introduced into the n ⁺ type semiconductor region SD, the n ⁻ type semiconductor region EX, and the like is performed (step S8 in FIG. 46). If the ion-implanted region is made amorphous, it can be crystallized during the activation annealing in step S8.

Next, as shown in FIG. 54, a low resistance metal silicide layer SIL is formed on the surface (upper layer portion) of the n ⁺ type semiconductor region SD by the salicide technique, as in the first embodiment (FIG. 47). Step S10).

  The metal silicide layer SIL forming step in step S10 is basically the same as that in the first embodiment, but the metal silicide layer SIL is mainly formed in the semiconductor layer EP1 in the first embodiment. However, in the third embodiment, the metal silicide layer SIL is formed mainly in the semiconductor layer EP3 (or the semiconductor layers EP3 and EP2). Similarly to the first embodiment, since the silicon nitride film SN1 is formed on the polysilicon film PL1 of the dummy gate GED, the metal silicide layer is not formed on the surface of the polysilicon film PL1 of the dummy gate GED. Not formed.

  Next, as shown in FIG. 55, as in the first embodiment, an insulating film IL1 is formed on the main surface (entire main surface) of the SOI substrate SUB (step S11 in FIG. 47). That is, the insulating film IL1 is formed on the main surface of the SOI substrate SUB so as to cover the dummy gate GED and the side wall insulating films SW1 and SW4. Since the insulating film IL1 has been described in the first embodiment, repeated description thereof is omitted here.

  Next, as shown in FIG. 56, similarly to the first embodiment, the surface (upper surface) of the insulating film IL1 is polished by the CMP method, so that the upper surface of the dummy gate GED (that is, the silicon nitride film SN1) is polished. The upper surface is exposed (step S12 in FIG. 47).

  Next, as shown in FIG. 57, the dummy gate GED and the sidewall insulating films SW1 and SW4a are removed by etching (step S13a in FIG. 47).

  By removing the dummy gate GED and the sidewall insulating films SW1 and SW4a in this step S13a, a trench (recess, opening, recess) TR1 is formed. The trench TR1 is formed of a region (space) where the dummy gate GED and the sidewall insulating films SW1 and SW4a existed before the removal of the dummy gate GED and the sidewall insulating films SW1 and SW4a. From trench TR1, the upper surface of semiconductor layer SM1, the side surface and upper surface of semiconductor layer EP2, and the inner wall of sidewall insulating film SW4b are exposed.

  The bottom surface of the trench TR1 is formed by the upper surface of the semiconductor layer SM1 and the side surfaces and the upper surface of the semiconductor layer EP2. The side surface (side wall) of the trench TR1 is formed by the inner wall of the side wall insulating film SW4a. On the bottom surface of the trench TR1, a step portion is formed by the side surface and the top surface of the semiconductor layer EP2. Here, the inner wall of the side wall insulating film SW4b corresponds to the side surface (side wall) of the side wall insulating film SW4b that is in contact with the side wall insulating film SW4a until the side wall insulating film SW4a is removed.

  The etching process in step S13a will be specifically described below.

  The etching in step S13a is preferably performed by the following three stages (first stage, second stage and third stage, see FIGS. 58 to 60).

  First, as shown in FIG. 58, the silicon nitride film SN1 of the dummy gate GED is removed as the first stage of etching in step S13a. This first stage etching is performed in the third embodiment as well. This is the same as in the first embodiment (the first stage etching in step S13). By the first stage etching, the silicon nitride film SN1 is removed, and the polysilicon film PL1 is exposed.

  Next, as a second stage of etching in step S13a, as shown in FIG. 59, the polysilicon film PL1 of the dummy gate GED is removed. This second stage of etching is also performed in the third embodiment. This is the same as in the first embodiment (the second stage etching in step S13). By the second-stage etching, the polysilicon film PL1 is removed, and the sidewall insulating film SW1 and the insulating film GID are exposed.

  The third stage of etching in step S13a is slightly different from the third stage of step S13 in the first embodiment. In the etching process of step S13a, after the polysilicon film PL1 is removed by the second stage etching, the etching conditions are changed, and the third stage etching is performed to form the sidewall insulating films SW1, SW4a and The insulating film GID is removed. This third stage etching is performed under the etching conditions such that the etching rates of the sidewall insulating films SW1, SW4a and the insulating film GID are higher than the etching rates of the semiconductor layers SM1, EP2, and the sidewall insulating films SW1, SW4a and the insulating film. It is preferable to selectively etch the GID. Thereby, it is possible to suppress or prevent the semiconductor layers SM1 and EP2 from being etched by the third stage etching. If sidewall insulating film SW1 and sidewall insulating film SW4a are formed of the same material (here, silicon oxide), sidewall insulating film SW1 and sidewall insulating film SW4a can be continuously etched in the same etching step. Further, if the insulating film GID is formed of the same material (here, silicon oxide) as the side wall insulating films SW1 and SW4a, the insulating film GID is removed in the same etching step as the side wall insulating films SW1 and SW4a are removed. be able to.

  In the third stage etching, the sidewall insulating films SW1 and SW4a are removed, but the sidewall insulating film SW4b is preferably left. Therefore, in the third embodiment, the sidewall insulating film SW4b is formed of a material different from that of the sidewall insulating film SW4a, and the etching rate of the sidewall insulating films SW1 and SW4a (specifically, silicon oxide) is set to be the sidewall insulating film. The third-stage etching is performed under the etching conditions such that the etching speed of the film SW4b (specifically, silicon nitride) and the semiconductor layers SM1 and EP2 is higher. Here, since the sidewall insulating films SW1 and SW4a are formed of silicon oxide and the sidewall insulating film SW4b is formed of silicon nitride, a high etching selectivity between the sidewall insulating films SW1 and SW4a and the sidewall insulating film SW4b is ensured. It is easy. That is, in the third stage etching, the sidewall insulating films SW1 and SW4a can be etched and the sidewall insulating film SW4b can function as an etching stopper. Further, since the sidewall insulating films SW1 and SW4a are made of silicon oxide, it is easy to ensure a high etching selectivity between the sidewall insulating films SW1 and SW4a and the semiconductor layers SM1 and EP2.

  57 and 60 are obtained by removing the dummy gate GED, the insulating film GID, and the sidewall insulating films SW1 and SW4a by etching in the above three stages (first stage, second stage, and third stage) of step S13a. Thus, the trench TR1 is formed.

  Next, as in the first embodiment, as shown in FIG. 61, on the main surface (entire main surface) of SOI substrate SUB including the bottom surface and side surface (side wall) of groove TR1, that is, in trench TR1. An insulating film GIa for the gate insulating film is formed on the insulating film IL1 including the bottom and side walls (step S14 in FIG. 47). Since the insulating film GIa has been described in the first embodiment, repeated description thereof is omitted here.

  Next, as in the first embodiment, a conductive film CD for the gate electrode is formed on the main surface of the SOI substrate SUB, that is, on the insulating film GIa so as to fill the trench TR1 (FIG. 47). Step S15). Since the conductive film CD has been described in the first embodiment, repeated description thereof is omitted here.

  Next, as shown in FIG. 62, the conductive film CD and the insulating film GIa are left in the trench TR1, and the conductive film CD and the insulating film GIa outside the trench TR1 are removed by a CMP method or the like, so that the gate electrodes GE and A gate insulating film GI is formed (step S16 in FIG. 47). Since step S16 is the same as the first embodiment, the third embodiment is not described here. Step S16 is a step of forming the gate electrode GE in the trench TR1 via the gate insulating film GI.

  The conductive film CD remaining in the trench TR1 becomes the gate electrode GE, and the insulating film GIa remaining in the trench TR1 becomes the gate insulating film GI. Then, between the gate electrode GE and the semiconductor layer SM1 (the upper surface thereof), between the gate electrode GE and the semiconductor layer EP2 (the side surfaces and the upper surface thereof), and between the gate electrode GE and the sidewall insulating film SW4b (the inner wall thereof). The gate insulating film GI is interposed therebetween. The gate electrode GE and the gate insulating film GI function as a gate electrode and a gate insulating film of the MISFET, respectively.

A channel region of the MISFET is formed in the semiconductor layer SM1 located under the gate electrode GE via the gate insulating film GI (insulating film GIa). Further, the semiconductor region (impurity diffusion layer) functioning as the source or drain of the MISFET is formed by the n ⁻ type semiconductor region EX and the n ⁺ type semiconductor region SD having a higher impurity concentration than that, and has an LDD structure. Yes.

  In this way, an n-channel MISFET is formed.

In the present embodiment, the side wall insulating film SW4a formed on the side wall of the dummy gate GED and located on the semiconductor layer EP2 is removed together with the dummy gate GED in step S13a, and the removed region (trench TR1) is removed. A gate electrode GE is formed. Therefore, the gate electrode GE can be formed not only in the region where the dummy gate GED was present but also in the region where the sidewall insulating film SW4a was present. For this reason, the dimension in the gate length direction of the gate electrode GE can be made larger than the dimension of the dummy gate GED, and part of the gate electrode GE (both ends in the gate length direction) is located on the semiconductor layer EP2. That is, it rides on the semiconductor layer EP2. Therefore, the end of the gate electrode GE in the gate length direction is located on the semiconductor layer EP1. At least a part of the n ⁻ type semiconductor region EX is located immediately below the gate electrode GE.

  Subsequent steps are substantially the same as those in the first embodiment. That is, as shown in FIG. 63, as in the first embodiment, the insulating film IL2 is formed, the contact hole CNT is formed, the plug PG is formed in the contact hole CNT, and the insulating film is formed. IL3 is formed, and the wiring M1 is formed.

  64 and 65 are cross-sectional views of the main part of the semiconductor device according to the third embodiment. FIG. 64 corresponds to FIG. 1 and FIG. 65 corresponds to FIG.

However, in FIG. 64, in order to easily understand which region is the semiconductor layer SM1 and the semiconductor layers EP2 and EP3, the total of the semiconductor layer EP2 and the semiconductor layer EP3 is indicated by dot hatching, and the semiconductor layer SM1 The whole is indicated by hatching with thin diagonal lines. Accordingly, FIG. 1 does not illustrate the formation region of the n ⁻ type semiconductor region EX and the n ⁺ type semiconductor region SD. Further, in FIG. 65, n ^- -type semiconductor region EX and the n ⁺ -type semiconductor region as SD is easy to understand if it is any region, n ^- -type semiconductor regions EX entirety denoted by the same hatching, n ⁺ -type semiconductor region The same SD is added to the entire SD. Therefore, when FIG. 64 and FIG. 65 are viewed together, the configuration of the semiconductor layers SM1, EP2, and EP3, and the formation region of the n ⁻ type semiconductor region EX and the n ⁺ type semiconductor region SD in the semiconductor layers SM1, EP2, and EP3, Easy to understand. As in FIGS. 1 and 2, in FIGS. 64 and 64, the insulating film IL3, the wiring M1, and the upper layer structure thereof are not shown.

  Major differences between the semiconductor device of the third embodiment shown in FIGS. 64 and 65 and the semiconductor device of the first embodiment shown in FIGS. 1 and 2 are as follows. Note that description of common points is omitted.

  In the semiconductor device of the first embodiment, as shown in FIGS. 1 and 2, the semiconductor layer EP1 is formed as the source / drain epitaxial layer on the semiconductor layer SM1 of the SOI substrate SUB. Then, end portions (both end portions in the gate length direction) of the gate electrode GE run on the semiconductor layer EP1. That is, the end of the gate electrode GE in the gate length direction is located on the semiconductor layer EP1 that is an epitaxial layer for source / drain.

  On the other hand, as shown in FIGS. 64 and 65, the semiconductor device according to the third embodiment has a semiconductor layer EP2 on the semiconductor layer SM1 on the semiconductor layer SM1 of the SOI substrate SUB as an epitaxial layer for source / drain. And a semiconductor layer EP3 on the semiconductor layer EP2 are formed. Then, end portions (both end portions in the gate length direction) of the gate electrode GE run on the semiconductor layer EP2. That is, the end of the gate electrode GE in the gate length direction is located on the semiconductor layer EP2 which is an epitaxial layer for source / drain. Note that the end of the gate electrode GE in the gate length direction is indicated as an end EG by adding a symbol EG in FIG.

  In the first embodiment, as shown in FIGS. 1 and 2, a part of the gate electrode GE, the sidewall insulating film SW3, and a portion located between the gate electrode GE and the sidewall insulating film SW3. The gate insulating film GI is present on the semiconductor layer EP1.

  On the other hand, in the third embodiment, as shown in FIGS. 64 and 65, a part of the gate electrode GE, the side wall insulating film SW4b, and a portion located between the gate electrode GE and the side wall insulating film SW4b are shown. A gate insulating film GI is present on the semiconductor layer EP2.

  Further, in the first embodiment, a part (both ends) of the gate electrode GE rides on the inclined side surface SF1 of the semiconductor layer EP1. On the other hand, in the present third embodiment, the side surface of the semiconductor layer EP2 is not inclined, and part (both ends) of the gate electrode rides on the upper surface of the semiconductor layer EP2.

  In the first embodiment, the insulating film IL1 is formed on the SOI substrate SUB so as to cover the semiconductor layer EP1, and the gate electrode GE is embedded in the trench TR formed in the insulating film IL1. It was. On the other hand, in the third embodiment, the insulating film IL1 is formed on the SOI substrate SUB so as to cover the semiconductor layers EP2 and EP3, and the gate electrode GE is embedded in the trench TR1 formed in the insulating film IL1. It is. In the first embodiment, the gate insulating film GI is formed on the side surface and the bottom surface of the trench TR, and the gate electrode GE is embedded in the trench TR via the gate insulating film GI. On the other hand, in the third embodiment, the gate insulating film GI is formed on the side surface and the bottom surface of the trench TR1, and the gate electrode GE is embedded in the trench TR1 through the gate insulating film GI.

  Also in the semiconductor device of the third embodiment, the parasitic resistance between the source or drain semiconductor region and the channel region is suppressed for almost the same reason as described in the first embodiment. Therefore, the characteristics (electrical characteristics) of the semiconductor device can be improved.

  That is, also in the semiconductor device of the present embodiment, the end portions (both end portions in the gate length direction) of the gate electrode GE run on the source / drain epitaxial layers (here, the semiconductor layer EP2). That is, the end of the gate electrode GE in the gate length direction is located on the source / drain epitaxial layer (here, the semiconductor layer EP2). In other words, in the gate length direction of the MISFET (MISFET having the gate electrode GE as the gate electrode), the end of the gate electrode GE is positioned on the source / drain epitaxial layer (here, the semiconductor layer EP2). Yes. The epitaxial layer (here, the semiconductor layer EP2) is formed on the upper surface of the semiconductor layer SM1, and the upper surface of the epitaxial layer (here, the semiconductor layer EP2) is the surface of the semiconductor layer SM1 immediately below the gate electrode GE. Located higher than the top surface.

For this reason, the gate electrode GE can be surely overlapped with the semiconductor region for source or drain (a combination of the n ⁻ type semiconductor region EX and the n ⁺ type semiconductor region SD). Alternatively, parasitic resistance between the semiconductor region for drain and the channel region can be suppressed. In addition, the thickness of the semiconductor layer in the overlapping portion between the semiconductor region for source or drain (a combination of the n ⁻ type semiconductor region EX and the n ⁺ type semiconductor region SD) and the gate electrode GE is the thickness of the semiconductor layer SM1. Rather, the parasitic resistance can be further suppressed because the thickness can be increased by the thickness of the semiconductor layer EP2 in the overlap portion. Therefore, the characteristics (electrical characteristics) of the semiconductor device including the MISFET can be improved. Further, variation in characteristics of each MISFET due to variation in the value of the parasitic resistance can be suppressed. Therefore, the performance of the semiconductor device can be improved. Also in the present third embodiment, the structure in which the gate electrode GE rides on the semiconductor layer EP2 can be formed by self-alignment.

Further, after forming the semiconductor layer EP2, a sidewall insulating film SW4 is formed on the sidewall of the dummy gate GED, and then ion implantation is performed using the sidewall insulating film SW4 as a mask to form an n ⁺ type semiconductor region SD. However, in the third embodiment, the sidewall insulating film SW4 is formed of the sidewall insulating film SW4a and the sidewall insulating film SW4b. Therefore, the semiconductor layers EP2 and SM1 immediately below the sidewall insulating films SW4a and SW4b become the n ⁻ type semiconductor region EX. In step S13, the sidewall insulating film SW4a is removed from the sidewall insulating films SW4a and SW4b, and the sidewall insulating film SW4b is left. Therefore, the gate electrode GE is formed in the region where the sidewall insulating film SW4a is present, but the gate electrode GE is not formed in the region where the sidewall insulating film SW4b is present. Therefore, by adjusting the ratio of the thickness of the sidewall insulating film SW4a and the sidewall insulating films SW4b, n ^- without changing the dimensions of the type semiconductor region EX, n ^- amount of overlap type semiconductor region EX and the gate electrode GE It can be controlled to a desired value. Further, since not only the gate insulating film GI but also the sidewall insulating film SW4a is interposed between the metal silicide layer SIL and the gate electrode GE, the breakdown voltage between the gate electrode GE and the metal silicide layer SIL is improved. be able to.

  In the first embodiment and the fourth embodiment described later, the sidewall insulating film SW4 of the third embodiment can be applied instead of the sidewall insulating film SW2. In this case, the step S13 described above and the steps described later are performed. In S13b, as in step S13a of the third embodiment, the sidewall insulating film SW4a can be removed and the sidewall insulating film SW4b can be left.

  In the third embodiment, the source / drain epitaxial layers are formed in two layers of the semiconductor layer EP2 and the semiconductor layer EP3. Thereby, the following advantages can be obtained.

That is, in the present third embodiment, after the semiconductor layer EP2 is formed, ion implantation for forming the n ⁻ type semiconductor region EX is performed, and then after the semiconductor layer EP3 is formed, the n ⁺ type semiconductor region SD is formed. For ion implantation. For this reason, the ion implantation for forming the n ⁺ -type semiconductor region SD is performed on the semiconductor layer EP3, but the ion implantation for forming the n ⁻ -type semiconductor region EX is not performed. Compared to the case where the seed crystal is formed, the seed crystal is likely to remain even if the amorphization is advanced by ion implantation. For this reason, at the time of activation annealing in step S8, crystallization (single crystallization) is facilitated by the presence of the seed crystal. Therefore, the resistance of the source / drain regions can be further reduced, and the performance of the semiconductor device can be further improved.

(Embodiment 4)
In the first to third embodiments, the case where the MISFET is formed on the SOI substrate SUB has been described. In the fourth embodiment, a case where a MISFET is formed on the semiconductor substrate SUB2 will be described. In the fourth embodiment, the first, third, and fourth problems described above can be solved.

  66 and 67 are process flow diagrams showing the manufacturing process of the semiconductor device of the fourth embodiment. 68 to 83 are main-portion cross-sectional views during the manufacturing process of the semiconductor device of the fourth embodiment.

  First, as shown in FIG. 68, a semiconductor substrate (semiconductor wafer) SUB2 made of p-type single crystal silicon having a specific resistance of, for example, about 1 to 10 Ωcm is prepared (step S1b in FIG. 66).

  Next, an element isolation region (not shown) is formed in the semiconductor substrate SUB2. In the element isolation region, for example, an element isolation groove is formed on the main surface of the semiconductor substrate SUB2 using a photolithography technique, a dry etching technique, or the like, and the element isolation groove is insulated using a film formation technique, a CMP technique, or the like. It can be formed by embedding a film. In the semiconductor substrate SUB2, a MISFET is formed in the active region defined by the element isolation region as described below.

  Next, as shown in FIG. 69, an n-type well NW is formed in the semiconductor substrate SUB2 in a region where a p-channel MISFET is to be formed. The n-type well NW can be formed by ion-implanting an n-type impurity (for example, arsenic) into the semiconductor substrate SUB2.

  Next, a dummy gate GED is formed on the semiconductor substrate SUB2 (step S2 in FIG. 66). The dummy gate GED is formed on the semiconductor substrate SUB2 (on the n-type well NW), and the formation method and configuration of the dummy gate GED are the same as those in the first embodiment.

  Next, as shown in FIG. 70, a sidewall insulating film SW1 is formed as a sidewall film on the sidewall of the dummy gate GED (step S3 in FIG. 66). Since the configuration and formation method of the sidewall insulating film SW1 are the same as those in the first embodiment, the repeated description thereof is omitted here.

  Next, as shown in FIG. 71, the semiconductor substrate SUB2 (n-type well NW) is etched to a predetermined depth by performing either anisotropic or isotropic dry etching alone or in combination. Groove (substrate recess portion, substrate recess portion, recess, recess) TR2 is formed (step S21 in FIG. 66).

  In step S21, the dummy gate GED and the sidewall insulating film SW1 function as an etching mask. Therefore, the trench TR2 is formed in self-alignment with the sidewall insulating film SW1 on the sidewall of the dummy gate GED. However, when isotropic dry etching is performed, the trench TR2 is formed to slightly overlap the sidewall insulating film SW1 and the dummy gate GED. At the bottom and side walls of trench TR2, the Si substrate region (the portion of semiconductor substrate SUB2 constituting n-type well NW) is exposed. The depth of the trench TR2 can be about 20 to 40 nm, for example.

  Next, as shown in FIG. 72, a silicon germanium layer (SiGe layer, silicon germanium region, epitaxial silicon germanium layer) EP4 is epitaxially grown as a semiconductor layer in the trench TR2 of the semiconductor substrate SUB2 (step S4c in FIG. 66). .

  The silicon germanium layer EP4 is an epitaxial layer (epitaxial semiconductor layer) formed by epitaxial growth, and is made of silicon germanium (single crystal silicon germanium). The silicon germanium layer EP4 is selectively epitaxially grown on the Si substrate region exposed from the trench TR2 of the semiconductor substrate SUB2, and is not formed on the sidewall insulating film SW1 or the silicon nitride film SN1. Further, as described in the first embodiment, since the polysilicon film PL1 of the dummy gate GED is covered with the silicon nitride film SN1 and the sidewall insulating film SW1, no epitaxial layer is formed on the polysilicon film PL1. .

  Further, the silicon germanium layer EP4 may be formed so as to fill the trench TR2 and to swell the silicon germanium layer EP4 over the main surface of the semiconductor substrate SUB2 (the upper surface of the semiconductor substrate SUB2 where the trench TR2 is not formed). preferable. In this case, the upper surface of the silicon germanium layer EP4 formed in step S4c is higher than the upper surface of the semiconductor substrate SUB2 immediately below the dummy gate GED. For example, the silicon germanium layer EP4 is formed so that the upper surface of the silicon germanium layer EP4 is about 10 to 40 nm higher than the main surface of the semiconductor substrate SUB2.

  Further, the silicon germanium layer EP4 is formed so that the upper surface of the silicon germanium layer EP4 is higher than the main surface of the semiconductor substrate SUB2, but the silicon germanium layer EP4 in a portion higher than the main surface of the semiconductor substrate SUB2 is formed. It is preferable to epitaxially grow the silicon germanium layer EP4 so that the side surface SF2 has a taper. That is, it is preferable that the side surface SF2 of the silicon germanium layer EP4 that is higher than the main surface of the semiconductor substrate SUB2 is inclined with respect to the main surface of the semiconductor substrate SUB2. That is, it is preferable that the side surface SF2 of the silicon germanium layer EP4 is inclined so that the thickness of the silicon germanium layer EP4 increases as the distance from the dummy gate GED increases. The taper of the side surface SF2 of the silicon germanium layer EP4 that is higher than the main surface of the semiconductor substrate SUB2 is controlled by adjusting the composition of the film forming gas of the silicon germanium layer EP4, the film forming temperature, and the like. Can do.

  The silicon germanium layer EP4 is preferably a silicon germanium layer EP4 into which impurities of a conductive type are introduced by introducing a doping gas during epitaxial growth. When forming a p-channel type MISFET, it is preferable to use a p-type silicon germanium layer EP4 into which a p-type impurity is introduced. In this case, the ion implantation process for forming the source / drain regions may not be performed.

  Further, a silicon germanium layer is suitable as a semiconductor layer to be epitaxially grown in the trench TR2 of the semiconductor substrate SUB2. By using silicon germanium, for example, the stress acting on the channel can be controlled.

  That is, such a technique is generally called a strained Si transistor using uniaxial stress. In the channel region of the p-channel MISFET of the fourth embodiment, compressive stress is generated by the silicon germanium layer EP4 formed in the source and drain regions. By this compressive stress, the distance between Si atoms in the channel region is narrowed, whereby the mobility of carriers (holes) flowing between the source and the drain can be improved. Therefore, the current flowing between the source and the drain can be increased. In the fourth embodiment, the value of the stress generated in the channel region is −1.3 GP or more, and the current increases by 10% or more compared to the case where the channel is unstrained. ing.

  In the fourth embodiment, a p-channel type MISFET is mainly exemplified. However, when the n-channel type MISFET is used, SiC (silicon carbide, silicon carbide) is used instead of SiGe (silicon germanium). use. That is, in the case of an n channel MISFET, a SiC layer is used instead of the silicon germanium layer EP4. In this case, tensile stress is generated in the channel region of the n-channel type MISFET by the SiC layers formed in the source and drain regions. This tensile stress increases the distance between Si atoms in the channel region, so that the mobility of carriers (electrons) flowing between the source and the drain can be improved. Therefore, the current flowing between the source and the drain can be increased. At that time, the value of the stress generated in the channel region is +1.3 GP or more, and the current is increased by 10% or more compared to the case where the channel is unstrained.

  In addition, the above-described SiGe layer or SiC layer can generate a strong stress by being formed by epitaxial growth. That is, when the Si layer is simply epitaxially grown and then Ge or C is ion-implanted, a strong stress cannot be generated.

  In the fourth embodiment, the SiGe layer may be used only for the p-channel MISFET among the p-channel MISFET and the n-channel MISFET, or the SiC layer is used only for the n-channel MISFET. Alternatively, the SiGe layer may be used for the p-channel type MISFET and the SiC layer may be used for the n-channel type MISFET.

  Next, as shown in FIG. 73, a sidewall insulating film SW2 is formed as a sidewall film on the sidewall of the dummy gate GED (step S6 in FIG. 66). The configuration and formation method of the sidewall insulating film SW2 are basically the same as those in the first embodiment. However, in Embodiment 1 described above, the bottom surface of the sidewall insulating film SW2 is in contact with the semiconductor layer EP1, whereas in Embodiment 4, the bottom surface of the sidewall insulating film SW2 is in contact with the silicon germanium layer EP4. .

  That is, in the fourth embodiment, the side wall insulating film SW2 is adjacent to the side wall of the dummy gate GED via the side wall insulating film SW1, and on the silicon germanium layer EP4 (specifically, the silicon germanium layer EP4 is inclined). (On side surface SF2). That is, the bottom surface of the sidewall insulating film SW2 is in contact with the silicon germanium layer EP4 (specifically, the inclined side surface SF2 of the silicon germanium layer EP4), and the inner wall of the sidewall insulating film SW2 (the side surface facing the dummy gate GED) is a dummy. It is in contact with the side wall insulating film SW1 on the side wall of the gate GED.

  Next, activation annealing which is a heat treatment for activating impurities introduced into the silicon germanium layer EP4 or the like is performed (step S8 in FIG. 66).

  In the case where ion implantation is not performed after the sidewall insulating film SW2 is formed in step S6 and before the metal silicide layer SIL is formed in step S10 described later, activation annealing in step S8 is performed, and sidewall insulation is performed in step S6. It can also be performed before forming the film SW2 and after forming the silicon germanium layer EP4 in step S4c.

  Next, as shown in FIG. 74, a metal silicide layer SIL is formed on the surface (upper layer portion) of the silicon germanium layer EP4 by the salicide technique (step S10 in FIG. 67).

  The metal silicide layer SIL forming step in step S10 is basically the same as the fourth embodiment as in the first embodiment, but in the first embodiment, the metal silicide layer SIL is mainly formed in the semiconductor layer EP1. However, in the third embodiment, the metal silicide layer SIL is formed in the silicon germanium layer EP4. Similarly to the first embodiment, since the silicon nitride film SN1 is formed on the polysilicon film PL1 of the dummy gate GED, the metal silicide layer is not formed on the surface of the polysilicon film PL1 of the dummy gate GED. Not formed.

  Next, as shown in FIG. 75, an insulating film IL1 is formed on the main surface (entire main surface) of the semiconductor substrate SUB2 as in the first embodiment (step S11 in FIG. 67). That is, the insulating film IL1 is formed on the main surface of the semiconductor substrate SUB2 so as to cover the dummy gate GED and the side wall insulating films SW1 and SW4. Since the insulating film IL1 has been described in the first embodiment, repeated description thereof is omitted here.

  Next, as shown in FIG. 76, as in the first embodiment, the surface (upper surface) of the insulating film IL1 is polished by the CMP method to thereby form the upper surface of the dummy gate GED (that is, the upper surface of the silicon nitride film SN1). ) Is exposed (step S12 in FIG. 67).

  Next, as shown in FIG. 77, the dummy gate GED and the sidewall insulating films SW1 and SW4a are removed by etching (step S13b in FIG. 67).

  By removing the dummy gate GED and the sidewall insulating films SW1 and SW2 in this step S13b, a trench (recess, opening, recess) TR3 is formed. The trench TR3 is formed of a region (space) in which the dummy gate GED and the sidewall insulating films SW1 and SW2 existed before the removal of the dummy gate GED and the sidewall insulating films SW1 and SW2. From the trench TR3, the semiconductor substrate SUB2 (the upper surface thereof), the silicon germanium layer EP4 (the inclined side surface SF2 thereof), and the inner surface of the silicon nitride film SN3 of the insulating film IL1 are exposed.

  The bottom surface of the trench TR3 is formed by the upper surface of the semiconductor layer SM1 and the inclined side surface SF2 of the silicon germanium layer EP4. The side surface (side wall) of the trench TR3 is formed by the inner surface of the silicon nitride film SN3. From the upper surface of the semiconductor substrate SUB2 exposed from the trench TR3 to the inclined side surface SF2 of the silicon germanium layer EP4 can be regarded as the bottom surface of the trench TR3. The upper part of the trench TR3 is open. Here, the inner surface of the silicon nitride film SN3 corresponds to the surface opposite to the side in contact with the insulating film SO3.

  The etching in step S13b is preferably performed by the following three stages (first stage, second stage and third stage, see FIGS. 78 to 80).

  First, as shown in FIG. 78, as the first stage of etching in step S13b, the silicon nitride film SN1 of the dummy gate GED is removed. This first stage etching is also performed in the fourth embodiment. This is the same as in the first embodiment (the first stage etching in step S13). By the first stage etching, the silicon nitride film SN1 is removed, and the polysilicon film PL1 is exposed.

  Next, as shown in FIG. 79, as the second stage of etching in step S13b, the polysilicon film PL1 of the dummy gate GED is removed. This second stage of etching is also performed in the fourth embodiment. This is the same as in the first embodiment (the second stage etching in step S13). By the second-stage etching, the polysilicon film PL1 is removed, and the sidewall insulating film SW1 and the insulating film GID are exposed.

  The third stage of etching in step S13b is basically the same as that in the first embodiment, and can be performed as follows.

  That is, in the fourth embodiment, in the etching process of step S13b, after the polysilicon film PL1 is removed by the second stage etching, the etching conditions are changed, and the third stage etching is shown in FIG. As described above, the sidewall insulating films SW1 and SW2 and the insulating film GID are removed. This third stage etching is performed under such etching conditions that the etching rates of the sidewall insulating films SW1 and SW2 and the insulating film GID are faster than the etching rates of the semiconductor substrate SUB2 (n-type well NW) and the silicon germanium layer EP4. Sidewall insulating films SW1, SW2 and insulating film GID are preferably selectively etched. Thereby, it is possible to suppress or prevent the semiconductor substrate SUB2 (n-type well NW) and the silicon germanium layer EP4 from being etched by the third-stage etching. If sidewall insulating film SW1 and sidewall insulating film SW2 are formed of the same material (here, silicon oxide), sidewall insulating film SW1 and sidewall insulating film SW2 can be continuously etched in the same etching step. Further, if the insulating film GID and the side wall insulating films SW1 and SW2 are formed of the same material (here, silicon oxide), the insulating film GID is removed in the same etching process as the side wall insulating films SW1 and SW2 are removed. can do.

  In the third-stage etching, the sidewall insulating films SW1 and SW2 are removed, but it is preferable that the silicon nitride film SN3 of the insulating film IL1 is left. Therefore, in the fourth embodiment, the sidewall insulating film SW2 is formed of a material different from that of the silicon nitride film SN3 of the insulating film IL1, and the etching rate of the sidewall insulating films SW1 and SW2 (specifically, silicon oxide) is increased. However, the third-stage etching is performed under the etching conditions such that the etching rate is higher than the etching rate of the silicon nitride film SN3 of the insulating film IL1, the semiconductor substrate SUB2, and the silicon germanium layer EP4. Here, since the sidewall insulating films SW1 and SW2 are formed of silicon oxide, it is easy to ensure a high etching selectivity between the sidewall insulating films SW1 and SW2 and the silicon nitride film SN3 of the insulating film IL1. That is, in the third stage etching, the sidewall insulating films SW1 and SW2 can be etched and the silicon nitride film SN3 of the insulating film IL1 can function as an etching stopper. Further, since the sidewall insulating films SW1 and SW2 are made of silicon oxide, it is easy to ensure a high etching selectivity between the sidewall insulating films SW1 and SW2, the semiconductor substrate SUB2, and the silicon germanium layer EP4.

  As shown in FIGS. 77 and 80, the dummy gate GED and the sidewall insulating films SW1 and SW2 are removed by etching in the above-described three stages (first stage, second stage, and third stage) of step S13b. TR3 is formed.

  Also in the fourth embodiment, as in the first embodiment, the step S9 is performed to form the sidewall insulating film SW3 on the sidewall of the dummy gate GED via the sidewall insulating films SW1 and SW2. Thus, the metal silicide layer SIL can be formed in step S10. In this case, as in the first embodiment, also in the fourth embodiment, it is preferable to leave the sidewall insulating film SW3 in step S13, and the side surface (sidewall) of the trench TR3 is formed by the inner wall of the sidewall insulating film SW3. Will be formed.

  Also in the fourth embodiment, as in the second embodiment, the sidewall insulating films SW1 and SW2 can be formed of silicon nitride. In this case, the etching in step S13b is performed in the first embodiment. This can be performed in the same manner as in step S13 of FIG.

  Next, as in the first embodiment, as shown in FIG. 81, on the main surface (entire main surface) of the semiconductor substrate SUB2 including the bottom surface and side surfaces (sidewalls) of the trench TR3, that is, the trench TR1. An insulating film GIa for the gate insulating film is formed on the insulating film IL1 including the bottom and side walls (step S14 in FIG. 67). Since the insulating film GIa has been described in the first embodiment, repeated description thereof is omitted here. Note that a silicon oxide film having a thickness of 1 nm or less may be formed as an interface layer before the insulating film GIa is formed as in the first embodiment.

  Next, as in the first embodiment, as shown in FIG. 82, the conductive film for the gate electrode is formed so as to fill the trench TR3 on the main surface of the semiconductor substrate SUB2, that is, on the insulating film GIa. (Conductive film) CD is formed (step S15 in FIG. 67). Since the conductive film CD has been described in the first embodiment, repeated description thereof is omitted here.

  Next, as shown in FIG. 82, the conductive film CD and the insulating film GIa are left in the trench TR3, the conductive film CD and the insulating film GIa outside the trench TR3 are removed by a CMP method or the like, and the gate electrode GE and A gate insulating film GI is formed (step S16 in FIG. 67). Since step S16 is the same as the first embodiment, the third embodiment is not described here. Step S16 is a step of forming the gate electrode GE in the trench TR1 via the gate insulating film GI. As in the first embodiment, the gate electrode GE may have a stacked structure of a metal film and a polysilicon film or a structure in which different metal films are stacked.

  The conductive film CD remaining in the trench TR3 becomes the gate electrode GE, and the insulating film GIa remaining in the trench TR3 becomes the gate insulating film GI. Then, between the gate electrode GE and the upper surface of the semiconductor substrate SUB2, between the gate electrode GE and the inclined side surface SF2 of the silicon germanium layer EP4, and between the gate electrode GE and the silicon nitride film SN3 (the inner surface thereof). Then, the gate insulating film GI is interposed. The gate electrode GE and the gate insulating film GI function as a gate electrode and a gate insulating film of the MISFET, respectively.

  A channel region of the MISFET is formed in the semiconductor substrate SUB2 located under the gate electrode GE via the gate insulating film GI (insulating film GIa). Further, the semiconductor region (impurity diffusion layer) functioning as the source or drain of the MISFET is formed by the silicon germanium layer EP4.

  In this way, a p-channel type MISFET is formed.

  In the fourth embodiment, the side wall insulating film SW2 formed on the side wall of the dummy gate GED and located on the silicon germanium layer EP4 is removed together with the dummy gate GED in step S13b, and the removed region (trench TR3 ) Is formed with a gate electrode GE. Therefore, the gate electrode GE can be formed not only in the region where the dummy gate GED was present but also in the region where the sidewall insulating film SW2 was present. For this reason, the dimension in the gate length direction of the gate electrode GE can be made larger than the dimension of the dummy gate GED, and a part of the gate electrode GE (both ends in the gate length direction) is positioned on the silicon germanium layer EP4. That is, it rides on the silicon germanium layer EP4. Therefore, the end of the gate electrode GE in the gate length direction is located on the silicon germanium layer EP4. A part of the silicon germanium layer EP4 (and thus a part of the semiconductor region for the source or drain) is located immediately below the gate electrode GE.

  Subsequent steps are substantially the same as those in the first embodiment. That is, as shown in FIG. 83, as in the first embodiment, the insulating film IL2 is formed, the contact hole CNT is formed, the plug PG is formed in the contact hole CNT, and the insulating film is formed. IL3 is formed, and the wiring M1 is formed.

  FIG. 84 is a fragmentary cross-sectional view of the semiconductor device of Fourth Embodiment.

  In the fourth embodiment, the MISFET is formed not on the SOI substrate but on the bulk semiconductor substrate SUB2. A gate electrode GE is formed on the semiconductor substrate SUB2 via a gate insulating film GI. Further, a trench TR2 is formed in the semiconductor substrate SUB2, and a silicon germanium layer EP4 is formed as an epitaxial layer for source / drain in the trench TR2.

  That is, a trench TR2 is formed in the semiconductor substrate SUB2, and an epitaxial layer for source / drain is buried in the trench TR2. The source / drain epitaxial layer buried in the trench TR2 is a silicon germanium layer EP4 in the case of a p-channel MISFET. As described above, when the fourth embodiment is applied to an n-channel MISFET, the source / drain epitaxial layers embedded in the trench TR2 are SiC layers. 84 illustrates the case of a p-channel type MISFET. However, when the fourth embodiment is applied to an n-channel type MISFET, the n-type well NW is replaced with a p-type well in FIG. Layer EP4 will replace the SiC layer. The channel region of the MISFET is a silicon substrate region of the semiconductor substrate SUB2 (a single crystal Si region (Si substrate region) constituting an n-type well NW in the case of a p-channel type MISFET, and a p-type well in the case of an n-channel type MISFET). Are formed in a single crystal Si region (Si substrate region)).

  The silicon germanium layer EP4 is formed on both sides of the gate electrode GE (on both sides in the gate length direction), but the end of the gate electrode GE in the gate length direction is located on the silicon germanium layer EP4. In other words, the end of the gate electrode GE is located on the silicon germanium layer EP4 in the gate length direction of the MISFET (MISFET having the gate electrode GE as the gate electrode). That is, the end portions of the gate electrode GE (both end portions in the gate length direction) run on the silicon germanium layer EP4.

  That is, the central portion side of the gate electrode GE in the gate length direction is on the semiconductor substrate SUB2 where the silicon germanium layer EP4 is not formed, but the both ends of the gate electrode GE in the gate length direction are the silicon germanium layer. I am riding on EP4. That is, the central portion side (the central portion side in the gate length direction) of the gate electrode GE does not overlap with the silicon germanium layer EP4 (does not overlap with the thickness direction of the semiconductor substrate SUB2), but the end portion of the gate electrode GE (gate The end in the long direction) overlaps the silicon germanium layer EP4 (overlaps in the thickness direction of the semiconductor substrate SUB2). In other words, the silicon germanium layer EP4 exists immediately below both ends of the gate electrode GE (near both ends in the gate length direction), and immediately below the center portion side (the center portion side in the gate length direction) of the gate electrode GE. There is no silicon germanium layer EP4 (Si substrate region is present).

  The silicon germanium layer EP4 is formed (embedded) in the trench TR2 of the semiconductor substrate SUB2, but the upper surface of the silicon germanium layer EP4 is higher than the upper surface of the semiconductor substrate SUB2 immediately below the gate electrode GE. In position. Here, the upper surface of the semiconductor substrate SUB2 immediately below the gate electrode GE corresponds to the surface (upper surface) of the semiconductor substrate SUB2 in contact with the gate insulating film GI below the gate electrode GE. In FIG. It is shown as an upper surface UF2.

  Since the p-type impurity is introduced into the silicon germanium layer EP4, the silicon germanium layer EP4 is a semiconductor region that functions as a source or a drain. The semiconductor substrate SUB2 below the gate electrode GE becomes a region where a channel of the MISFET is formed (channel formation region). For this reason, a part of the semiconductor region for source or drain (here, the silicon germanium layer EP4) is located immediately below the gate electrode GE.

  In the first embodiment, the insulating film IL1 is formed on the SOI substrate SUB so as to cover the semiconductor layer EP1, and the gate electrode GE is embedded in the trench TR formed in the insulating film IL1. It was. On the other hand, in the fourth embodiment, the insulating film IL1 is formed on the semiconductor substrate SUB2 so as to cover the silicon germanium layer EP4, and the gate electrode GE is embedded in the trench TR3 formed in the insulating film IL1. ing. In the first embodiment, the gate insulating film GI is formed on the side surface and the bottom surface of the trench TR, and the gate electrode GE is embedded in the trench TR via the gate insulating film GI. On the other hand, in the fourth embodiment, the gate insulating film GI is formed on the side surface and the bottom surface of the trench TR3, and the gate electrode GE is embedded in the trench TR3 via the gate insulating film GI.

  In the first embodiment, the side surface SF1 of the semiconductor layer EP1 is inclined, and the end of the gate electrode GE in the gate length direction is located on the inclined side surface SF1 of the semiconductor layer EP1. On the other hand, in the fourth embodiment, the side surface SF2 of the silicon germanium layer EP4 is inclined, and the end of the gate electrode GE in the gate length direction is located on the inclined side surface SF2 of the silicon germanium layer EP4. In other words, the side surface (side surface on the gate electrode GE side) SF2 of the silicon germanium layer EP4 is inclined in the gate length direction of the MISFET (MISFET having the gate electrode GE as the gate electrode), and the MISFET (gate electrode GE is gated). In the gate length direction of the MISFET as an electrode), the end of the gate electrode GE is located on the inclined side surface SF2 of the semiconductor layer EP1. That is, the end portion (end portion in the gate length direction) of the gate electrode GE runs on the inclined side surface SF2 of the silicon germanium layer EP4.

  In such a semiconductor device, the following effects can be obtained.

  That is, when the silicon germanium layer EP4 is formed as an epitaxial layer doped with a conductive impurity (p-type impurity in the case of forming a p-channel MISFET) in step S4c, a semiconductor region for source or drain (silicon germanium layer EP4) ) And the dummy gate GED are difficult to form. Therefore, unlike this embodiment, when the polysilicon film PL1 of the dummy gate GED is used as a gate electrode of a semiconductor device without being removed, the semiconductor region for the source or drain (silicon germanium layer EP4) and There is a possibility that parasitic resistance between the semiconductor region for the source or drain and the channel region is increased due to insufficient overlap with the gate electrode.

Further, as a modification of the fourth embodiment, after the silicon germanium layer EP4 is formed as an undoped or lightly doped silicon germanium layer in step S4c, the p ⁻ type semiconductor region EX is formed as in step S5. In some cases, after ion implantation is performed and the sidewall insulating film SW2 is formed in step S6, ion implantation for forming the p ⁺ -type semiconductor region SD is performed in the same manner as in step S7. In this case, the p ⁻ type semiconductor region EX and the p ⁺ type semiconductor region SD are mainly formed in the silicon germanium layer EP4. However, since the upper surface of the silicon germanium layer EP4 is higher than the upper surface of the semiconductor substrate SUB2 immediately below the gate electrode GE, the p-type impurity introduced by ion implantation diffuses to the region immediately below the dummy gate GED. Therefore, it is difficult to form an overlap between the semiconductor region for source or drain and the dummy gate GED. Therefore, unlike this embodiment, when the polysilicon film PL1 of the dummy gate GED is used as a gate electrode of a semiconductor device without being removed, the semiconductor region for the source or drain (silicon germanium layer EP4) and There is a possibility that parasitic resistance between the semiconductor region for the source or drain and the channel region is increased due to insufficient overlap with the gate electrode.

In contrast, in the fourth embodiment, the sidewall insulating film SW2 formed on the sidewall of the dummy gate GED after the formation of the silicon germanium layer EP4 is removed together with the dummy gate GED in step S13b, and then the gate electrode GE is formed. ing. As a result, the gate electrode GE is formed not only in the region where the dummy gate GED is formed, but also in the region where the sidewall insulating film SW2 is formed. For this reason, the end portions (both ends in the gate length direction) of the gate electrode GE run on the silicon germanium layer EP4, and the end portions in the gate length direction of the gate electrode GE are positioned on the silicon germanium layer EP4. Therefore, the overlap between the semiconductor region for source or drain (silicon germanium layer EP4) and the gate electrode GE can be reliably ensured, and the parasitic resistance between the semiconductor region for source or drain and the channel region is suppressed. can do. That is, when the silicon germanium layer EP4 is grown as a p-type doped epitaxial layer and as in the modification of the fourth embodiment, the p ⁻ type semiconductor region EX and the silicon germanium layer EP4 are formed by ion implantation. The parasitic resistance can be suppressed both in the case where the n ⁺ type semiconductor region SD is formed. For this reason, the said 1st subject can be solved.

  Therefore, the characteristics (electrical characteristics) of the semiconductor device including the MISFET can be improved. Further, variation in characteristics of each MISFET due to variation in the value of the parasitic resistance can be suppressed. For this reason, the performance of the semiconductor device can be improved. Also in the fourth embodiment, the structure in which the gate electrode GE rides on the silicon germanium layer EP4 can be formed by self-alignment.

  Also in the fourth embodiment, the silicon germanium layer EP4 has the inclined portion (inclined side surface SF2), and the gate insulating film GI (insulating film GIa) and the gate electrode GE are in the inclined portion (inclined side surface). SF2). For this reason, it is easy to form the gate insulating film GI (insulating film GIa) uniformly in the trench TR3. Therefore, it is possible to solve the problem that the breakdown voltage of the MISFET is lowered as shown in the third problem.

  Also in the fourth embodiment, the diameter of the trench TR3 can be made larger than the length of the dummy gate GED. For this reason, as shown in FIG. 81, since the aspect ratio is ensured (the aspect ratio of the trench TR3 can be reduced), even when the conductive film CD serving as the gate electrode GE is deposited in the trench TR3, the voids are not formed. Less likely to occur. Therefore, it is possible to solve the problem as shown in the fourth problem.

  Furthermore, in the MISFET of the fourth embodiment, since the upper length of the gate electrode GE is longer (than the lower length of the gate electrode GE), the volume of the entire gate electrode GE can be increased. The resistance of the electrode GE can be reduced.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

BOX1 Insulating layer BR Barrier conductor film CD Conductive film CNT Contact hole EG End portion EG1, EG2, EG3, EG4 Corner portion EP1, EP2, EP3 Semiconductor layer EP4 Silicon germanium layer EX n ⁻ type semiconductor regions GE, GE101, GE102 Gate electrode GED Dummy gates GI, GI101, GI102 Gate insulating film GIa Insulating film GID Insulating film IL1, IL2, IL3 Insulating film IL101 Interlayer insulating film M1 Wiring ME Metal film MC1 Main conductor film PG Plug PL1 Polysilicon film NW n-type well SD n ⁺ type Semiconductor region SF1, SF1a, SF2 Side surface SIL Metal silicide layer SM1, SM2 Semiconductor layer SN1, SN2, SN101, SN103 Silicon nitride film SN3 Liner film SO1, SO2, SO103 Silicon oxide film SO3 Insulating film SUB S I substrate SUB1 substrate SUB2 semiconductor substrate SW1, SW1a, SW2, SW2a, SW3, SW4, SW4a, SW4b sidewall insulating film TR, TR1, TR2, TR3, TR101 groove UF1, UF2 top WT wiring groove

The step of forming the sidewall insulating film SW2 in step S6 can be performed as follows. That is, first, as shown in FIG. 11, a silicon oxide film SO2 is formed (deposited) over the entire main surface of the SOI substrate SUB by CVD or the like so as to cover the dummy gate GED and the sidewall insulating film SW1. Then, the silicon oxide film SO2 is etched back (anisotropic etching) to leave the silicon oxide film SO2 on the side wall of the dummy gate GED to form the side wall insulating film SW2, as shown in FIG. The silicon oxide film SO2 in the region is removed. As a result, the sidewall insulating film SW2 is formed on the sidewall of the dummy gate GED via the sidewall insulating film SW1. The thickness of the sidewall insulating film SW2 (thickness in a direction substantially perpendicular to the sidewall of the dummy gate GED) can be set to about 3 to 10 nm, for example.

Next, as shown in FIG. 27, an insulating film (interlayer insulating film) IL2 is formed over the entire main surface of the SOI substrate SUB, that is, over the insulating film IL1 in which the gate electrode GE is embedded. As the insulating film IL2 , a silicon oxide insulating film can be used. The insulating film IL2 is formed over the insulating film IL1 so as to cover the upper surface of the gate electrode GE.

In this embodiment, the case where an n-channel MISFET is formed as MISFE T has been described. However, a p-channel MISFET can be formed by reversing the conductivity type. In addition, both an n-channel MISFET and a p-channel MISFET can be formed on the same SOI substrate SUB. The same applies to the following second to fourth embodiments.

Next, as shown in FIG. 56, as in Embodiment 1 above Symbol embodiment, by a surface (upper surface) of the insulating film IL1 are polished by the CMP method, the upper surface of the dummy gate GED (i.e. silicon nitride film SN1 Are exposed (step S12 in FIG. 47).

In the present embodiment, the side wall insulating film SW4a formed on the side wall of the dummy gate GED and located on the semiconductor layer EP2 is removed together with the dummy gate GED in step S13a, and the removed region (trench TR1) is removed. A gate electrode GE is formed. Therefore, the gate electrode GE can be formed not only in the region where the dummy gate GED was present but also in the region where the sidewall insulating film SW4a was present. For this reason, the dimension in the gate length direction of the gate electrode GE can be made larger than the dimension of the dummy gate GED, and part of the gate electrode GE (both ends in the gate length direction) is located on the semiconductor layer EP2. That is, it rides on the semiconductor layer EP2. Therefore, the end of the gate length direction of the gate electrode GE, will be positioned on the semiconductor layer EP 2. At least a part of the n ⁻ type semiconductor region EX is located immediately below the gate electrode GE.

However, in FIG. 64, in order to easily understand which region is the semiconductor layer SM1 and the semiconductor layers EP2 and EP3, the total of the semiconductor layer EP2 and the semiconductor layer EP3 is indicated by dot hatching, and the semiconductor layer SM1 The whole is indicated by hatching with thin diagonal lines. Therefore, in FIG. 64 , the formation region of the n ⁻ type semiconductor region EX and the n ⁺ type semiconductor region SD is not illustrated. Further, in FIG. 65, n ^- -type semiconductor region EX and the n ⁺ -type semiconductor region as SD is easy to understand if it is any region, n ^- -type semiconductor regions EX entirety denoted by the same hatching, n ⁺ -type semiconductor region The same SD is added to the entire SD. Therefore, when FIG. 64 and FIG. 65 are viewed together, the configuration of the semiconductor layers SM1, EP2, and EP3, and the formation region of the n ⁻ type semiconductor region EX and the n ⁺ type semiconductor region SD in the semiconductor layers SM1, EP2, and EP3, Easy to understand. Similarly to FIGS. 1 and 2, in FIGS. 64 and 6 5, for the upper layer of the structure than the above insulating film IL3 and wiring M1, are not shown.

The metal silicide layer SIL forming step in step S10 is basically the same as the fourth embodiment as in the first embodiment, but in the first embodiment, the metal silicide layer SIL is mainly formed in the semiconductor layer EP1. However, in the fourth embodiment, the metal silicide layer SIL is formed in the silicon germanium layer EP4. Similarly to the first embodiment, since the silicon nitride film SN1 is formed on the polysilicon film PL1 of the dummy gate GED, the metal silicide layer is not formed on the surface of the polysilicon film PL1 of the dummy gate GED. Not formed.

Next, as shown in FIG. 75, an insulating film IL1 is formed on the main surface (entire main surface) of the semiconductor substrate SUB2 as in the first embodiment (step S11 in FIG. 67). In other words, so as to cover the dummy gate GED and the sidewall insulating films SW1, SW 2, an insulating film IL1 on the main surface of the semiconductor substrate SUB2. Since the insulating film IL1 has been described in the first embodiment, repeated description thereof is omitted here.

Next, as shown in FIG. 77, the dummy gate GED and the sidewall insulating films SW1, SW 2, is removed by etching (step S13b in FIG. 67).

Next, as shown in FIG. 82, the conductive film CD and the insulating film GIa are left in the trench TR3, and the conductive film CD and the insulating film GIa outside the trench TR3 are removed by a CMP method or the like, so that the gate electrodes GE and A gate insulating film GI is formed (step S16 in FIG. 67). As for step S16, the fourth embodiment is the same as the first embodiment, and therefore, repeated description thereof is omitted here. Step S16 is a step of forming the gate electrode GE in the trench TR1 via the gate insulating film GI. As in the first embodiment, the gate electrode GE may have a stacked structure of a metal film and a polysilicon film or a structure in which different metal films are stacked.

In contrast, in the fourth embodiment, the sidewall insulating film SW2 formed on the sidewall of the dummy gate GED after the formation of the silicon germanium layer EP4 is removed together with the dummy gate GED in step S13b, and then the gate electrode GE is formed. ing. As a result, the gate electrode GE is formed not only in the region where the dummy gate GED is formed, but also in the region where the sidewall insulating film SW2 is formed. For this reason, the end portions (both ends in the gate length direction) of the gate electrode GE run on the silicon germanium layer EP4, and the end portions in the gate length direction of the gate electrode GE are positioned on the silicon germanium layer EP4. Therefore, the overlap between the semiconductor region for source or drain (silicon germanium layer EP4) and the gate electrode GE can be reliably ensured, and the parasitic resistance between the semiconductor region for source or drain and the channel region is suppressed. can do. That is, when the silicon germanium layer EP4 is grown as a p-type doped epitaxial layer and as in the modification of the fourth embodiment, the p ⁻ type semiconductor region EX and the silicon germanium layer EP4 are formed by ion implantation. The parasitic resistance can be suppressed both in the case where the p ⁺ type semiconductor region SD is formed. For this reason, the said 1st subject can be solved.

Claims (11)

A semiconductor device having a MISFET including a gate insulating film, a gate electrode, a first epitaxial layer for source, and a second epitaxial layer for drain,
A plurality of first grooves are formed in the semiconductor substrate;
The first and second epitaxial layers each have a protruding portion that is embedded in the first groove and is higher than the surface of the semiconductor substrate outside the first groove,
The protrusion has an inclined portion that gradually increases in thickness,
A first insulating film is formed on the semiconductor substrate, on the first epitaxial layer and on the second epitaxial layer;
The first insulation so that a second groove opens on the semiconductor substrate between the first and second epitaxial layers, on the inclined portion of the first epitaxial layer, and on the inclined portion of the second epitaxial layer. Formed in the film,
The gate insulating film is formed on a side surface and a bottom surface of the second groove;
The gate electrode is formed so as to fill the second trench through the gate insulating film;
A semiconductor device in which both end portions of the gate electrode in the gate length direction of the MISFET are respectively located on the first and second epitaxial layers. The semiconductor device according to claim 1,
In the second trench, the gate insulating film is formed so as to follow the shape of the inclined portion of the first and second epitaxial layers. The semiconductor device according to claim 2,
In the second trench, the gate electrode is formed so as to follow the shape of the inclined portion of the first and second epitaxial layers. The semiconductor device according to any one of claims 1 to 3,
The gate insulating film is a semiconductor device containing a metal oxide. The semiconductor device according to claim 4,
The gate insulating film includes a silicon oxide film between the semiconductor substrate and the metal oxide between the first and second epitaxial layers. In the semiconductor device according to claim 1,
The gate electrode is a semiconductor device including a metal film. The semiconductor device according to claim 6.
A semiconductor device in which a silicide film is formed on the first and second epitaxial layers. In the semiconductor device according to claim 1,
The semiconductor substrate is silicon;
The channel region of the MISFET is formed in the silicon,
The MISFET is a p-channel MISFET,
The first and second epitaxial layers are each a semiconductor device containing SiGe. The semiconductor device according to claim 8,
A semiconductor device in which a compressive stress of −1.3 GPa or more is generated in the channel region of the MISFET by the first and second epitaxial layers. In the semiconductor device according to claim 1,
The semiconductor substrate is silicon;
The channel region of the MISFET is formed in the silicon,
The MISFET is an n-channel MISFET,
Each of the first and second epitaxial layers is a semiconductor device containing SiC. The semiconductor device according to claim 10.
A semiconductor device in which a tensile stress of 1.3 GPa or more is generated in the channel region of the MISFET by the first and second epitaxial layers.

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