JP2016004858A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a structure which makes it easy to manufacture a semiconductor device including a capacitor with one electrode being connected to a plate electrode and a silicon interlayer film.SOLUTION: A semiconductor device comprises: first contact plugs formed in a semiconductor substrate; a silicon interlayer film formed above the first contact plugs; capacitors which are respectively arranged in through holes formed in the silicon interlayer film and each of which is composed of a lower electrode, a capacitance insulation film and an upper electrode; and a plate electrode formed on the silicon interlayer film. The plate electrode has electric resistivity lower than that of the silicon interlayer film and the capacitors pierce the plate electrode.

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a capacitor and a manufacturing method thereof.

  A DRAM (Dynamic Random Access Memory) is known as an example of a semiconductor device including a capacitor.

The related DRAM realizes the mutually incompatible requirements of reducing the area occupied by the capacitor and increasing the capacitance. Therefore, an Si film that can easily form fine and deep holes compared to the SiO ₂ film is used as an interlayer film. Adopted.

  In a DRAM that employs a Si layer as an interlayer film, a capacitor is formed in a through hole that penetrates the Si interlayer film. The Si interlayer film is used as a part of the upper electrode of the capacitor or a part of the plate electrode connected to the upper electrode. Such a DRAM is described in Patent Document 1 or 2, for example.

JP 2006-245364 A US Pat. No. 6,670,663

  Each of the capacitors described in Patent Documents 1 and 2 is a type of capacitor called a crown type. In this type of capacitor, a capacitive insulating film and an upper electrode are disposed on the inner and outer peripheral sides of a crown-shaped lower electrode, respectively. That is, two upper electrodes, two capacitive insulating films, and one lower electrode must be accommodated in a narrow through hole (occupied area). For this reason, a semiconductor device including a crown type capacitor has a problem that it is difficult to manufacture.

  In order to solve such a problem, the adoption of a capacitor called a concave type is also being studied in a DRAM employing a Si interlayer film. Since the concave type capacitor has one upper electrode, one capacitor insulating film, and one lower electrode, it can be easily arranged in a small exclusive area.

  However, the concave type capacitor has another problem that it is difficult to form a metal film to be a plate electrode. In the case of a crown type capacitor, one of the two capacitive insulating films is configured to cover the upper end of the lower electrode, whereas in the case of a concave type, such a capacitive insulating film does not exist. Because. In other words, in this type of capacitor, the upper end of the lower electrode is exposed on the surface side together with the upper end of the upper electrode, and when attempting to form a metal film (plate electrode) connected to the upper electrode, the upper electrode and the lower electrode are short-circuited. Because it will end up.

  Further, if measures such as addition of processes such as lithography and etching are performed in order to avoid a short circuit between the upper electrode and the lower electrode, the manufacturing process becomes complicated and costs increase. In addition, depending on the accuracy of alignment, there is a case where a short circuit cannot be avoided even if such a process is performed, so that the yield decreases.

  It is conceivable to omit the formation of a metal film (to be a plate electrode) and use a silicon interlayer film (doped with impurities) as a plate electrode. In that case, the silicon interlayer film has a higher electrical power than the metal film. Due to the resistivity, the operation of the semiconductor device becomes unstable.

  A semiconductor device according to an aspect of the present invention includes a first contact plug formed on a semiconductor substrate, a silicon interlayer film formed above the first contact plug, and a through hole formed in the silicon interlayer film. A capacitor comprising a lower electrode, a capacitive insulating film and an upper electrode, and a plate electrode formed on the silicon interlayer film, wherein the plate electrode has a lower electrical resistivity than the silicon interlayer film And the said capacitor has penetrated the said plate electrode, It is characterized by the above-mentioned.

  A semiconductor device according to another aspect of the present invention includes a silicon interlayer film formed on a first insulating film, a plate electrode formed on the silicon interlayer film, the silicon interlayer film and the plate electrode. A capacitor penetrating, the capacitor comprising: a cylindrical first electrode having an outer peripheral surface in contact with the silicon interlayer film and the plate electrode; a capacitor insulating film covering the inner peripheral surface of the first electrode; And a second electrode disposed on the inner peripheral side of the capacitor insulating film and penetrating the first insulating film.

  A method of manufacturing a semiconductor device according to still another embodiment of the present invention includes a step of forming a first contact plug on a semiconductor substrate, a first insulating film on the first contact plug, a first conductive film, A step of laminating a second conductive film having an electrical resistivity lower than that of the first conductive film in this order; and a step of etching the second conductive film and the first conductive film to reach the first insulating film A step of forming a through hole; a step of forming an upper electrode on an inner surface of the first through hole; and the first insulating film positioned at the bottom of the first through hole; Forming a second through hole that exposes a portion; and laminating a capacitor insulating film and a lower electrode on the surfaces of the first contact plug and the upper electrode exposed in the second through hole; , Located at the bottom of the second through-hole Etching the part electrode and the capacitive insulating film to expose a part of the first contact plug again, and electrically connecting the first contact plug exposed at the bottom of the second through hole and the lower electrode. And a step of connecting them to each other.

  According to the present invention, a semiconductor device having a structure including a capacitor penetrating a silicon interlayer film and a plate electrode in contact with an upper electrode of the capacitor can be obtained.

It is sectional drawing which shows schematic structure of the principal part of the semiconductor device which concerns on one embodiment of this invention. FIG. 7 is a cross-sectional view for explaining a step in the method for manufacturing the semiconductor device in FIG. 1. FIG. 3 is a cross-sectional view for explaining a process following the process of FIG. 2. It is sectional drawing for demonstrating the process following the process of FIG. It is sectional drawing for demonstrating the process following the process of FIG. It is sectional drawing for demonstrating the process following the process of FIG. It is sectional drawing for demonstrating the process following the process of FIG. It is sectional drawing for demonstrating the process following the process of FIG. FIG. 9 is a cross-sectional view for explaining a process following the process of FIG. 8. FIG. 10 is a cross-sectional view for explaining a process following the process of FIG. 9. It is sectional drawing for demonstrating the process following the process of FIG. It is sectional drawing for demonstrating the process following the process of FIG. It is sectional drawing for demonstrating the process following the process of FIG.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a cross-sectional view showing a schematic configuration of a main part of the semiconductor device 10 according to the first embodiment of the present invention. Specifically, FIG. 1 shows a part of the cell region 20 of the DRAM and the vicinity of the boundary with the peripheral circuit region 30. A large number of memory cells are two-dimensionally arranged in the cell region 20, and a circuit for controlling the memory cells is formed in the peripheral circuit region 30.

  The illustrated semiconductor device 10 includes a semiconductor substrate 101, a first interlayer insulating film 102, a capacitor contact plug (first contact plug) 104, a stopper film (first insulating film) 108, and a silicon interlayer film (first conductive film) 109. , A plate electrode (second conductive film) 110-1, a mask insulating film 111, a capacitor 119, a cover film 121, a through-hole contact plug (second contact plug) 122, and an upper layer wiring 123.

  The semiconductor substrate 101 is a silicon substrate, for example. Although not shown in FIG. 1, in the cell region 20 and the peripheral circuit region 30 of the semiconductor substrate 101, an element such as a transistor, an element isolation film that electrically isolates elements from each other, and an electric element between any elements are electrically connected. A buried wiring or the like to be connected is formed.

  The first interlayer insulating film 102 is, for example, a silicon oxide film.

  The capacitor contact plug 104 is made of, for example, tungsten. The capacitor contact plug 104 is connected to a source part or a drain part of a cell transistor (not shown) formed on the semiconductor substrate 101. In the figure, four capacitor contact plugs 104 arranged in one direction are shown, but the capacitor contact plugs 104 are formed corresponding to a large number of memory cells arranged two-dimensionally.

  The stopper film 108 is configured as, for example, a stacked film of a first silicon nitride film 105, a silicon oxide film 106, and a second silicon nitride film 107.

  The silicon interlayer film 109 is a silicon film doped with non-doped or impure portions. The silicon film can easily form a through-hole having a larger aspect than the silicon oxide film. Therefore, it is possible to reduce the area occupied by the capacitor 119 having a predetermined or higher capacitance (to increase the degree of integration).

  The plate electrode 110-1 is made of tungsten, for example. The plate electrode 110-1 having an electric resistivity lower than that of the silicon interlayer film 109 makes it possible to stably charge and discharge the capacitor 119.

  The mask insulating film 111 is, for example, a silicon oxide film. The mask insulating film 111 is used as an etching mask when forming a through hole in the silicon interlayer film 109.

  The capacitor 119 is formed in a columnar shape, and has an upper electrode 113-1, a capacitor insulating film 115-1, and a lower electrode 118-1 from the outer peripheral side. For example, titanium nitride can be used as the upper electrode 113-1 and the lower electrode 118-1, and zirconium oxide can be used as the capacitor insulating film 115-1.

  The upper electrode 113-1 has a cylindrical shape (cylindrical shape, square tube shape, etc.), and the outer peripheral surface thereof is in contact with the silicon interlayer film 109 and the plate electrode 110-1. The film 109 and the plate electrode 110-1 are electrically connected.

  The capacitive insulating film 115-1 is formed so as to cover the inner peripheral surface of the upper electrode 113-1. The capacitive insulating film 115-1 is also cylindrical, and a lower electrode 118-1 is embedded on the inner peripheral side thereof. The capacitor insulating film 115-1 and the lower electrode 118-1 are formed not only through the silicon interlayer film 109 but also through the stopper film 108. The lower end of the lower electrode 118-1 is in contact with the capacitor contact plug 104, whereby the lower electrode 118-1 is electrically connected to the capacitor contact plug 104.

  The cover film 121 is, for example, a silicon oxide film. Cover film 121 covers the upper surface of capacitor 119 and embeds peripheral circuit region 30 and has a flat upper surface.

  The through-hole contact plug 122 is made of tungsten, for example, and the upper wiring 123 is made of copper, for example. The through-hole contact plug 122 penetrates the cover film 121 and is connected to the plate electrode 110-1 and electrically connects the plate electrode 110-1 and the upper layer wiring 123.

  Next, a method for manufacturing the semiconductor device 10 shown in FIG. 1 will be described with reference to FIGS.

  First, as shown in FIG. 2, a semiconductor substrate 101 is prepared, and elements such as transistors and elements are electrically separated into the cell region 20 and the peripheral circuit region 30 of the semiconductor substrate 101 using a known method. An element isolation film to be formed, a buried wiring connecting any element, and the like (none of which are shown) are formed. Then, a first interlayer insulating film 102 is formed on the surface of the semiconductor substrate 101 on which elements and the like are formed. As the first interlayer insulating film 102, a silicon oxide film can be used. Hereinafter, the semiconductor substrate 101 having the first interlayer insulating film 102 formed on the surface may be referred to as a semiconductor substrate 103.

  Subsequently, the capacitor contact plug 104 is formed on the semiconductor substrate 103 using a known method. Specifically, a contact hole is formed in the first interlayer insulating film 102, and a conductive film such as a tungsten film is embedded in the formed contact hole to form a capacitor contact plug 104. The capacitor contact plug 104 passes through the first interlayer insulating film 102 and is connected to the source portion or drain portion of the transistor formed on the semiconductor substrate 101.

  Next, as shown in FIG. 3, a first silicon nitride film 105, a silicon oxide film 106, and a second silicon nitride film 107 are stacked in this order on the first interlayer insulating film 102. These films 105 to 107 constitute a stopper film 108 that covers the upper surface of the capacitor contact plug 104.

  The first silicon nitride film 105 and the second silicon nitride film 107 can be formed using, for example, a thermal CVD method, and the silicon oxide film 106 can be formed using, for example, a plasma CVD method. The film thicknesses of the first silicon nitride film 105 and the second silicon nitride film 107 can be 50 nm, for example, and the film thickness of the silicon oxide film 106 can be 100 nm, for example.

  Next, as shown in FIG. 4, a silicon interlayer film 109, a plate electrode film 110, and a mask insulating film 111 are formed in this order on the stopper film 108. The silicon interlayer film 109 can be formed to a thickness of 1500 nm using, for example, a plasma CVD method. The plate electrode film 110 can be formed to a thickness of 80 nm by using, for example, a sputtering method using tungsten as a material. Furthermore, the mask insulating film 111 can be formed to a film thickness of 50 nm using, for example, a thermal CVD method.

  Next, a hard mask and a resist mask (not shown) are formed on the mask insulating film 111, and a predetermined opening pattern is formed on the hard mask using a known lithography method. As the hard mask, for example, an amorphous carbon film can be used. The predetermined opening pattern is a pattern in which an opening is formed at a position corresponding to the capacitor contact plug 104.

  Next, etching is performed using the patterned hard mask as a mask to transfer the opening pattern to the mask insulating film 111. Then, etching is performed using the hard mask and the mask insulating film 111 as a mask to transfer the opening pattern to the plate electrode film 110. Further, the silicon interlayer film 109 is etched to form a hole (first through hole) 112 that penetrates the silicon interlayer film 109 as shown in FIG. 5, and the upper surface of the stopper film 108 is exposed at the bottom of the hole 112. .

  The hard mask disappears during the above steps. If the hard mask remains, an additional step of removing the hard mask is performed.

  Next, as shown in FIG. 6, an upper electrode film 113 that covers the inner surface of the hole 112 is formed. The upper electrode film 113 is formed using, for example, an ALD (Atomic Layer Deposition) method using titanium nitride as a material so that the inner surface of the hole 112 is covered with the upper electrode film 113. The film thickness of the upper electrode film 113 is 8 nm, for example.

  Next, as shown in FIG. 7, the upper electrode film 113 is etched back to remove the upper electrode film 113 formed on the mask insulating film 111 and the upper electrode film 113 formed on the bottom of the hole 112. The upper electrode film 113 covering the inner surface of the hole 112 is used later as the upper electrode 113-1 that is a part of the capacitor 119. The upper electrode 113-1 passes through the plate electrode film 110, and the upper end of the upper electrode 113-1 protrudes to the surface side (upward in the drawing) from the upper surface of the plate electrode film 110. The outer peripheral surface of the upper electrode 113-1 is in contact with and electrically connected to the silicon interlayer film 109 and the plate electrode film 110.

  Subsequently, as shown in the figure, the stopper film 108 exposed in the hole 112 is etched to form a new hole (second through hole) 114 that penetrates the stopper film 108. At least a part of the upper surface of the capacitor contact plug 104 is exposed at the bottom of the new hole 114. Further, the inner surface of the new hole 114 is constituted by the inner peripheral surface of the upper electrode 113-1 and the inner surface of the stopper film 108.

  Next, as illustrated in FIG. 8, an insulating film 115 to be a capacitive insulating film 115-1 is formed so as to cover the inner surface of the hole 114. The insulating film 115 can be formed to a film thickness of 6 nm using, for example, an ALD method using zirconium oxide as a material.

  Subsequently, as shown in FIG. 9, a first lower electrode film 116 is formed so as to cover the entire surface of the insulating film 115. The first lower electrode film 116 is formed with a film thickness of 6 nm by using, for example, an ALD method using titanium nitride as a material. At this stage, the hole 114 is not completely filled, and a void 117 is left on the inner peripheral side of the first lower electrode film 116.

  Next, as shown in FIG. 10, the first lower electrode film 116 is etched back, and further the insulating film 115 is etched back. As a result, a part of the upper surface of the capacitor contact plug 104 is exposed again at the bottom of the void 117 remaining in the hole 114. Further, a part of the insulating film 115 is a capacitive insulating film 115-1 covering the inner peripheral surface of the upper electrode 113-1, and a part 116-1 of the first lower electrode film 116 is a portion of the lower electrode 118-1. As a part, each remains in the hole 114.

  Next, as shown in FIG. 11, the second lower electrode film 118 is formed to a thickness of 10 nm by using, for example, the ADL method. As a result, the void 117 remaining on the inner peripheral side of the first lower electrode film 116 is completely buried. The lower end of the second lower electrode film 118 formed in the void 117 is in contact with and electrically connected to the capacitor contact plug 104. By using the same titanium nitride as that of the first lower electrode 116 as the material of the second lower electrode film 118, a part 116-1 of the first lower electrode film 116 and the second lower electrode film 118 are integrated. In FIG. 11, the second lower electrode film 118 including the part 116-1 of the first lower electrode film 116 is illustrated.

  Next, as shown in FIG. 12, the second lower electrode film 118 is etched back, and the excess second lower electrode film 118 formed on the mask insulating film 111 is removed. This etch back is performed so that the second lower electrode film 118 and the upper electrode 113-1 are completely electrically separated. Thus, the lower electrode 118-1 buried on the inner peripheral side of the capacitive insulating film 115-1 is formed, and as a result, the capacitor 119 composed of the upper electrode 113-1, the capacitive insulating film 115-1 and the lower electrode 118-1. Is formed.

  Next, as shown in FIG. 13, a second interlayer insulating film 120 is formed on the entire surface and processed into a predetermined pattern by lithography. As the second interlayer insulating film 120, for example, a silicon oxide film formed using a plasma CVD method can be used, and the film thickness can be 200 nm. Further, the predetermined pattern can be, for example, a pattern separated in memory mat units.

  Next, the mask insulating film 111, the plate electrode film 110, and the silicon interlayer film 109 are sequentially etched using the patterned second interlayer insulating film 120 as a mask. As a result, the memory mats are individually separated in the cell region 20, and the stopper film 108 is exposed in the peripheral circuit region 30. The plate electrode film 110 is also separated for each memory mat to become the plate electrode 110-1.

  Thereafter, a third interlayer insulating film is formed on the entire surface, and the memory mats and the peripheral circuit region 30 are embedded. As the third interlayer insulating film, a silicon oxide film formed using the same plasma CVD method as that of the second interlayer insulating film 120 can be used, and the film thickness can be 1800 nm. By forming the same film as the second interlayer insulating film 120 as the third interlayer insulating film, they are integrated. Thereafter, the surface of the third interlayer insulating film is planarized by CMP (Chemical Mechanical Polishing) or the like to form the cover film 121.

  Next, as shown in FIG. 1, a through hole is formed at a predetermined position of the cover film 121, and the formed through hole is buried with a conductive material to form a through hole contact plug 122. The formation position of the through hole can be, for example, near the end of the memory mat. Further, tungsten can be used as the conductive material.

  Finally, the upper layer wiring 123 is formed so as to pass over the through-hole contact plug 122. The upper layer wiring 123 can be formed, for example, by forming a metal film made of copper on the cover film 121 and processing the formed metal film into a wiring pattern.

  As described above, the semiconductor device 10 is completed.

  According to the present embodiment, a concave-type capacitor that penetrates the silicon interlayer film can be formed without requiring a step of electrically separating the plate electrode 110-1 and the lower electrode 118-1. . As a result, a semiconductor device capable of realizing high integration of capacitors and stable operation can be manufactured at low cost and with high yield.

  While the present invention has been described with reference to the embodiment, the present invention is not limited to the above embodiment, and various modifications and changes can be made. In particular, the material, film thickness, and film formation method of each film in the above embodiment are merely examples and do not limit the present invention.

DESCRIPTION OF SYMBOLS 10 Semiconductor device 20 Cell area | region 30 Peripheral circuit area | region 101 Semiconductor substrate 102 1st interlayer insulation film 103 Semiconductor base body 104 Capacitance contact plug 105 First silicon nitride film 106 Silicon oxide film 107 Second silicon nitride film 108 Stopper film 109 Silicon interlayer film 110 plate electrode film 110-1 plate electrode 111 mask insulating film 112 hole 113 upper electrode film 113-1 upper electrode 114 hole 115 insulating film 115-1 capacitive insulating film 116 first lower electrode film 116-1 first lower electrode Part of film 117 Void 118 Second lower electrode film 118-1 Lower electrode 119 Capacitor 120 Second interlayer insulating film 121 Cover film 122 Through-hole contact plug 123 Upper layer wiring

Claims (18)

A first contact plug formed on the semiconductor substrate;
A silicon interlayer formed above the first contact plug;
A capacitor that is disposed in a through-hole formed in the silicon interlayer film and includes a lower electrode, a capacitor insulating film, and an upper electrode;
A plate electrode formed on the silicon interlayer film,
The plate electrode has a lower electrical resistivity than the silicon interlayer film, and
The semiconductor device, wherein the capacitor penetrates the plate electrode. The semiconductor device according to claim 1,
The semiconductor device, wherein the first contact plug and the lower electrode are electrically connected. The semiconductor device according to claim 1, wherein
The semiconductor device, wherein the upper electrode and the plate electrode are electrically connected. A semiconductor device according to any one of claims 1 to 3,
A semiconductor device, wherein a second contact plug connected to an upper wiring is connected to the plate electrode. The semiconductor substrate includes a semiconductor substrate and a first interlayer insulating film covering the surface of the semiconductor substrate,
The first contact plug is formed through the first interlayer insulating film,
A first insulating film is provided between the first contact plug and the silicon interlayer film.
The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device. The lower electrode passes through the first insulating film and contacts the first contact plug;
The outer surface of the upper electrode is in contact with the silicon interlayer film and the plate electrode,
The semiconductor device according to claim 5. A silicon interlayer film formed on the first insulating film;
A plate electrode formed on the silicon interlayer film;
A capacitor penetrating the silicon interlayer film and the plate electrode,
The capacitor includes a cylindrical first electrode having an outer peripheral surface in contact with the silicon interlayer film and the plate electrode;
A capacitive insulating film covering the inner peripheral surface of the first electrode;
A semiconductor device comprising: a second electrode disposed on an inner peripheral side of the capacitive insulating film and penetrating through the first insulating film. An interlayer insulating film formed on the semiconductor substrate;
A first contact plug that penetrates the interlayer insulating film, and
The first insulating film is formed on the insulating interlayer film so as to cover the first contact plug,
The second electrode is in contact with the first contact plug through the first insulating film;
The semiconductor device according to claim 7.   9. The semiconductor device according to claim 7, wherein the plate electrode has a lower electrical resistivity than the silicon interlayer film. A cover insulating film covering the plate electrode and the capacitor;
A second contact plug penetrating the cover insulating film and connected to the plate electrode;
A wiring formed on the cover insulating film and connected to the second contact plug;
The semiconductor device according to claim 7, further comprising: Forming a first contact plug on the semiconductor substrate;
Laminating a first insulating film, a first conductive film, and a second conductive film having an electrical resistivity lower than the first conductive film on the first contact plug in this order;
Etching the second conductive film and the first conductive film to form a first through hole reaching the first insulating film;
Forming an upper electrode on the inner surface of the first through hole;
Forming a second through hole penetrating the first insulating film located at the bottom of the first through hole and exposing a part of the first contact plug;
Laminating a capacitor insulating film and a lower electrode on the surfaces of the first contact plug and the upper electrode exposed in the second through hole;
Etching and removing the lower electrode and the capacitor insulating film located at the bottom of the second through hole to expose a part of the first contact plug again;
Electrically connecting the first contact plug exposed at the bottom of the second through hole and the lower electrode;
A method for manufacturing a semiconductor device, comprising: The step of laminating the capacitive insulating film and the lower electrode is performed so as to leave a void in the second through hole,
The step of electrically connecting the first contact plug and the lower electrode is performed so as to embed the void with a conductive material.
The method of manufacturing a semiconductor device according to claim 11.   The method of manufacturing a semiconductor device according to claim 12, wherein the conductive material is made of the same material as the lower electrode. Before forming the first through hole, further comprising a step of forming a mask film having a pattern corresponding to the first through hole on the second conductive film;
After each of the step of forming the upper electrode, the step of forming the second through hole, and the step of electrically connecting the first contact plug and the lower electrode, the upper surface of the mask film is exposed. ,
The method of manufacturing a semiconductor device according to claim 11, 12 or 13. After the step of electrically connecting the first contact plug and the lower electrode, further comprising the step of forming a cover insulating film covering the mask film;
15. The method of manufacturing a semiconductor device according to claim 14, wherein the second contact plug is formed through the cover insulating film and the mask film.   The method of manufacturing a semiconductor device according to claim 15, wherein the inner surface is an exposed surface of the first and second conductive films exposed in the second through hole.   Etching and removing the lower electrode and the capacitor insulating film located at the bottom of the second through hole to expose a part of the first contact plug again removes a part of the lower electrode and the capacitor The method for manufacturing a semiconductor device according to claim 15, further comprising a step of exposing a part of the insulating film.   The step of electrically connecting the first contact plug and the lower electrode is performed by burying a conductive film in a space formed by the etching after removing a part of the capacitive insulating film. 18. A method of manufacturing a semiconductor device according to claim 15, 16 or claim 17.

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