JP2016001680A - Semiconductor device and semiconductor circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which prevents deterioration in characteristics of a transistor, which is caused by high resistance of the transistor on the source side.SOLUTION: A semiconductor device comprises: a first diffusion layer; a second diffusion layer; a first channel region which is sandwiched by the first and second diffusion layers and extends in a first direction; a first gate electrode which is formed on the first channel region via a gate insulation film so as to extend in the first direction; an interlayer insulation film which is formed so as to cover the first diffusion layer, the second diffusion layer and the first gate electrode; a first contact which is formed in the interlayer insulation film to contact the first diffusion layer and formed to have a length in the first direction longer than a length in a second direction orthogonal to the first direction; and a second contact which is formed in the interlayer insulation film to contact the second diffusion layer and formed to have a length in the first direction shorter than a length in the second direction.

Description

  The present invention relates to a semiconductor device and a semiconductor circuit.

  In recent years, in semiconductor memories such as DRAM (Dynamic Random Access Memory) and the like, the progress of miniaturization has been remarkable, and the size of transistors used in semiconductor devices has been reduced year by year. Accordingly, as shown in FIG. 1 of Patent Document 1, the long side of the slit-like via (contact) that connects the source and drain and the metal wiring is arranged in parallel with the extending direction of the gate electrode. Transistor is used. Patent Document 1 discloses a technique for reducing the resistance value of a via and arranging a plurality of vias having a rectangular shape in the transistor width direction to improve a current value that can be passed through the transistor.

Japanese Patent Laying-Open No. 2003-7844 (FIG. 1) Japanese Patent Application No. 2013-160342

  Each disclosure of the above prior art document is incorporated herein by reference. The following analysis was made by the present inventors.

  As described above, since the size of the transistor has been reduced year by year, the area for arranging the via connecting the source and drain of the transistor and the metal wiring is also reduced, and the resistance value of the via has been increased. More specifically, as the miniaturization of the semiconductor device progresses, not only the wiring width of the metal wiring, but also the shape of the via becomes finer, particularly the contact resistance between the via and the diffusion layer increases, This is a cause of high wiring resistance.

  In such a situation where the transistor width is reduced, the influence of the contact resistance of the via on the transistor characteristics is increasing. Specifically, there is a problem that transistor characteristics such as power consumption and operation speed deteriorate due to an increase in contact resistance. Therefore, as disclosed in Patent Document 1, a layout in which a plurality of vias are arranged in the transistor width direction can be one solution to the above problem.

  However, even in the via layout disclosed in Patent Document 1, since the miniaturization is progressing, the contact resistance value is not sufficiently reduced at present. In view of this, it is conceivable that the slit-shaped via disclosed in Patent Document 1 has a longer length in the transistor width direction (see FIG. 23). However, it is difficult to form an extremely long and narrow via as shown in FIG. 23 due to limitations of exposure and etching processes (see FIG. 24).

  Further, it is conceivable to correct the mask shape or the like by OPC (Optical Proximity Correction) when forming the via, but there is a limit to such correction. Furthermore, if the interval between the vias is too short, the exposures interfere with each other, so it is difficult to arrange a large number of vias close to each other. As described above, it is difficult to form a via having a shape with an extreme aspect ratio as intended due to limitations of exposure processing and etching processing as the entire semiconductor device is miniaturized.

  Furthermore, there is a problem that current leaks to the substrate at locations where the via depth is not uniform and becomes a deep hole, and that a short circuit with the gate is likely to occur when the exposure shape is rounded inward. For this reason, not only vias connected to sources and the like, but actually, vias whose shapes are standardized are often used.

  According to the first aspect of the present invention, the first diffusion layer, the second diffusion layer, and the first channel region sandwiched between the first and second diffusion layers and extending in the first direction. A first gate electrode formed on the first channel region so as to extend in the first direction through a gate insulating film, the first diffusion layer, the second diffusion layer, and An interlayer insulating film formed to cover the first gate electrode; and a first contact formed in the interlayer insulating film to contact the first diffusion layer, wherein the first contact A first contact having a length in a direction longer than a length in a second direction orthogonal to the first direction, and the interlayer insulating film formed in contact with the second diffusion layer. A second contact having a length in the first direction shorter than a length in the second direction. A second contact formed, the semiconductor device comprising a are provided.

  According to a second aspect of the present invention, there is provided a semiconductor circuit that includes the semiconductor device described above and forms at least one of a driver circuit, an inverter circuit, a NAND circuit, and a NAND circuit.

  According to each aspect of the present invention, the second contact that contacts the second diffusion layer of the transistor is formed so that the length in the first direction is shorter than the length in the second direction. Provided are a semiconductor device and a semiconductor circuit that contribute to preventing deterioration of characteristics.

2 is a diagram illustrating an example of a plan view of a PMOS transistor according to the first embodiment. FIG. 1 is a block diagram showing an overall configuration of a semiconductor device 1 according to a first embodiment. 3 is an equivalent circuit diagram illustrating an example of a schematic configuration of a column decoder in the semiconductor device according to the first embodiment. FIG. It is a figure which shows an example of the cross-sectional schematic diagram between AA of FIG. It is a figure which shows an example of the top view of the PMOS transistor which concerns on a 1st comparative example. It is a figure which shows an example of the cross-sectional schematic diagram between BB of FIG. FIG. 6 is a diagram for explaining the influence of source-side wiring resistance in the PMOS transistor shown in FIG. 1 and the PMOS transistor shown in FIG. It is a figure which shows an example of the response speed of a transistor. It is a figure for demonstrating the resistance value by the side of a source. It is a figure for demonstrating the resistance value by the side of a source. It is a figure which shows an example of the measurement result of the source side resistance in each point of FIG.9 and FIG.10. It is a figure for demonstrating the direction which supplies power to a source. It is a figure for demonstrating the resistance value by the side of a source. It is a figure which shows an example of the top view of the PMOS transistor which concerns on a 2nd comparative example. It is a figure for demonstrating the response performance in a PMOS transistor. It is a figure for demonstrating the difference in the drain capacity of a transistor. It is a figure which shows an example of the top view of the PMOS transistor which concerns on a 3rd comparative example. It is a schematic diagram of the resistance component of the PMOS transistor which concerns on 1st Embodiment, and the PMOS transistor which concerns on a 3rd comparative example. It is a figure which shows an example of the planar layout figure of an inverter circuit. It is a figure which shows an example of the planar layout figure of an inverter circuit. It is a figure which shows an example of the plane layout figure of a NAND circuit. It is a figure which shows an example of the plane layout figure of a NOR circuit. It is a figure which shows an example of the planar layout of a transistor. It is a figure for demonstrating the restriction | limiting of an exposure process and an etching process.

  First, an outline of an embodiment will be described with reference to FIG. Note that the reference numerals of the drawings attached to the outline are attached to the respective elements for convenience as an example for facilitating understanding, and the description of the outline is not intended to be any limitation.

  The semiconductor device according to an embodiment includes a first diffusion layer (for example, the drain region 54), a second diffusion layer (for example, the source region 53a), and the first and second diffusion layers. A first channel region extending in the first direction, and a first gate electrode (for example, gate 51a) formed on the first channel region so as to extend in the first direction via a gate insulating film And an interlayer insulating film (for example, interlayer insulating film 62 in FIG. 4) formed to cover the first diffusion layer, the second diffusion layer, and the first gate electrode, and in contact with the first diffusion layer. Thus, the first contact formed in the interlayer insulating film, the first contact having a length in the first direction longer than the length in the second direction orthogonal to the first direction ( For example, the via 55) of the drain region 54 is in contact with the second diffusion layer. As described above, the second contact formed in the interlayer insulating film and having a length in the first direction shorter than the length in the second direction (for example, the via of the source region 53a) 57a).

  As shown in FIG. 1, in the semiconductor device according to the embodiment, the contact (via 57) connected to the source region is arranged in a direction orthogonal to the gate. Therefore, a larger number of contacts can be arranged than contacts (vias 55) of the drain region arranged in parallel to the gate. Since many vias are connected to the source region, the resistance value on the source side of the first conductivity type MOS transistor (for example, PMOS transistor) or the second conductivity type MOS transistor (for example, NMOS transistor) can be lowered. By reducing the resistance value on the source side of the MOS transistor, the characteristics of the MOS transistor such as power consumption and operation speed are improved.

  Hereinafter, specific embodiments will be described in more detail with reference to the drawings.

[First Embodiment]
The first embodiment will be described in more detail with reference to the drawings.

  FIG. 2 is a block diagram showing an overall configuration of the semiconductor device 1 according to the first embodiment.

  The semiconductor device 1 shown in FIG. 2 is a DRAM, and external clock terminals CK and / CK, command terminals / RAS, / CAS, / WE, an address terminal ADD, power supply terminals VDD and VSS, and a data input / output terminal DQ are external terminals. I have. In the present specification, a signal having “/” at the beginning of a signal name means an inverted signal of the corresponding signal or a low-active signal. It is a complementary signal.

  The clock input circuit 11 receives external clock signals CK and / CK, generates an internal clock signal, and supplies it to the FIFO circuit 12 and the like.

  A row address strobe signal / RAS, a column address strobe signal / CAS, and a write enable signal / WE are supplied to the command terminals / RAS, / CAS, / WE, respectively. These command signals are supplied to the command decode circuit 14 via the command input circuit 13. The command decode circuit 14 generates various internal commands.

  Various internal commands output from the command decode circuit 14 are supplied to the row decoder 15, column decoders 16a and 16b, the refresh control circuit 17, the mode register 18, the input / output circuit 19, and the like.

  The mode register 18 sets the data supplied from the internal address bus in the mode register 18 when a mode setting command is given from the command decode circuit 14. The mode register 18 supplies a mode signal MODE to the input / output circuit 19.

  The refresh control circuit 17 controls the row decoder 15 so that a refresh address is generated from the row decoder 15 according to the refresh timing when a refresh command is given from the command decode circuit 14.

  The address signal ADD supplied to the address terminal ADD is supplied to the address latch circuit 21 via the address input circuit 20. The address latch circuit 21 is a circuit that latches the address signal ADD in synchronization with the internal clock signal.

  As shown in FIG. 2, the memory cell array 22 is divided into a plurality of memory areas (23a to 23b, etc.), and adjacent to each memory cell area, column decoders 16a to 16b, sense amplifiers (SA; Sense). Amplifier) 24 is arranged.

  The address signal ADD includes a row address that specifies a word line (not shown) and a column address that specifies a bit line (not shown). Of the address signals latched by the address latch circuit 21, the row address is supplied to the row decoder 15, and the column address is supplied to the column decoders 16a and 16b.

  The row decoder 15 is a circuit that selects a word line corresponding to a row address supplied from the address latch circuit 21 among a plurality of word lines.

  The column decoders 16a and 16b are circuits for selecting a bit line corresponding to a column address supplied from the address latch circuit 21 from among a plurality of bit lines. The sense amplifier 24 connected to the selected bit line is electrically connected to a data amplifier (not shown), and the output of the data amplifier is supplied to the FIFO circuit 12.

  The data input / output terminal DQ is a terminal for outputting read data DQ and inputting write data DQ, and is connected to the input / output circuit 19. The input / output circuit 19 is connected to the FIFO circuit 12. During a read operation, a plurality of read data DQ prefetched from the memory cell array 22 to the FIFO circuit 12 is burst output from the data input / output terminal DQ via the input / output circuit 19. During a write operation, a plurality of write data DQ that are burst input to the data input / output terminal DQ are prefetched to the FIFO circuit 12 via the input / output circuit 19 and are simultaneously written to the memory cell array 22.

  The power supply terminals VDD and VSS are terminals to which external voltages VDD and VSS are supplied, respectively, and are connected to the internal power supply generation circuit 25. The internal power supply generation circuit 25 generates a power supply voltage (such as a voltage VPERI) necessary for the inside of the semiconductor device 1 from the external voltages VDD and VSS and supplies it to each unit.

  The above is the overall configuration of the semiconductor device 1 according to the first embodiment.

  In the semiconductor device 1, in order to reduce power consumption, power gating is employed to reduce the subthreshold current during standby. In the first embodiment, power gating is implemented in the column decoders (YDEC) 16a and 16b in FIG. 2, and the configuration of the column decoders (YDEC) 16a and 16b will be described below.

  FIG. 3 is an equivalent circuit diagram showing an example of a schematic configuration of the column decoder 16a in the semiconductor device 1 according to the first embodiment.

  The column decoder 16a shown in FIG. 3 illustrates the case of 4 inputs and 16 outputs. However, the number of input and output signals of the column decoder is not limited to this, and can be configured to an arbitrary number. In FIG. 3, the column decoder 16 a has a power gating power line structure including an SCRC driver 31, a main power line 32, and a pseudo power line 33.

  The column decoder 16a includes a 16-channel decode circuit, and each decode circuit includes a NAND circuit 34, a previous stage inverter circuit 35, and a final stage inverter circuit 36 shown in FIG. That is, FIG. 3 illustrates one channel decoding circuit among 16 channel decoding circuits.

  The input to the column decoder 16a is the column address described above, and FIG. 3 illustrates the case where the column address is 4 bits (each bit is A3, A2, A1, A0). Sixteen combinations of A3 or / A3, A2 or / A2, A1 or / A1, and A0 or / A0 are input to the four input terminals of the NAND circuit 34 of each decoding circuit. In the channel decoding circuit shown in FIG. 3, A3, A2, A1, and A0 are input.

  In this channel, when (A3, A2, A1, A0) = (1, 1, 1, 1), the output of the NAND circuit 34 becomes 0 (L level), and the column selection signal YS_An is activated. . In the case of a decode circuit in which A3, / A2, A1, / A0 is connected to the input terminal of the NAND circuit 34 in a separate channel decode circuit, (A3, A2, A1, A0) = (1, 0, 1 and 0), the output of the NAND circuit 34 becomes 0 (L level), and the column selection signal is activated.

  In this way, one column selection signal is selected and activated from the outputs of the 16-channel decoder circuit in accordance with the 4-bit column address signals A3 to A0.

  Next, the configuration of the circuit of FIG. 3 will be described in more detail.

  The final stage inverter circuit 36 is an inverter circuit in which a PMOS transistor 41 and an NMOS transistor 42 are connected in series between the pseudo power supply line 33 and the main ground line 37. A column selection signal YS_An is output from a connection contact between the PMOS transistor 41 and the NMOS transistor 42.

  The pre-stage inverter circuit 35 is an inverter circuit in which a PMOS transistor 43 and an NMOS transistor 44 are connected in series between the main power supply line 32 and the output terminal of the NAND circuit 34. The connection contact between the PMOS transistor 43 and the NMOS transistor 44 is connected to the input terminal of the final stage inverter circuit 36 (that is, the gates of the PMOS transistor 41 and the NMOS transistor 42). The control signal CtrlA is input to the input terminal of the pre-stage inverter circuit 35 (that is, the gates of the PMOS transistor 43 and the NMOS transistor 44).

  Next, the power gating operation of FIG. 3 will be described.

  In the semiconductor device 1, the power gating control unit 26 shown in FIG. 2 performs control to switch between the normal operation mode and the standby mode. Specifically, the power gating control unit 26 receives, for example, a clock enable signal CKE (not shown), sets the normal operation mode when the clock enable signal CKE is in an active state, and the clock enable signal CKE is not turned on. In the active state, the standby mode is set. This makes it possible to set the power gating to the standby mode when the semiconductor device 1 is in a non-operating state where no clock is supplied. However, the signal for switching between the normal operation mode and the standby mode may be a signal other than the clock enable signal CKE.

  When the power gating control unit 26 sets the normal operation mode, the power gating control unit 26 controls the voltage VPG of the second gate electrode of the SCRC driver 31 configured by the PMOS transistor to L level, Make it conductive. As a result, the power supply VPERI of the main power supply line 32 is supplied to the pseudo power supply line 33. That is, the potential VPERIZ of the pseudo power supply line 33 becomes the potential VPERI.

  Further, when the control signal CtrlA is set to H level in the normal operation mode, the NMOS transistor 44 of the preceding inverter circuit 35 is turned on, and the output signal of the NAND circuit 34 is output from the output signal YS_An− of the preceding inverter circuit 35 via the NMOS transistor 44. 1 is output. Then, the output signal of the NAND circuit 34 is logically inverted by the final stage inverter circuit 36 and output as the output signal YS_An (column selection signal) of the column decoder 16a. Then, any one of the 16-channel decoder circuits is activated, and the corresponding signal line is driven.

  On the other hand, when the power gating control unit 26 sets the standby mode, the power gating control unit 26 controls the voltage VPG of the second gate electrode of the SCRC driver 31 to the H level, and makes the SCRC driver 31 non-conductive. . In this case, the pseudo power supply line 33 is disconnected from the main power supply line 32, and the potential VPERIZ of the pseudo power supply line 33 is in a floating state. In this standby mode, since the power supply voltage is not supplied to the PMOS transistor 41, an effect of suppressing the subthreshold current in the final stage inverter circuit 36 is obtained.

  In the standby mode, when the control signal CtrlA is set to L level, the output signal YS_An-1 of the preceding inverter circuit 35 is fixed to H level. As a result, the NMOS transistor 42 is turned on even though the potential VPERIZ is not supplied to the final stage inverter circuit 36, so that the output YS_An of the final stage inverter circuit 36 can be held at the L level.

  As described above, according to the configuration of FIG. 3, the subthreshold current can be suppressed in the standby mode, and the output signal YS_An can be held at the L level.

  The PMOS transistor and the NMOS transistor that form the inverter circuit such as the SCRC driver 31 and the pre-stage inverter circuit 35 are circuits that want to increase the response speed and suppress current consumption. Therefore, it is desirable to use a transistor having a small resistance value from the transistor to the source wiring in these circuits.

  FIG. 1 is a diagram illustrating an example of a plan view of the PMOS transistor 100 according to the first embodiment. FIG. 4 is a diagram illustrating an example of a schematic cross-sectional view taken along a line AA in FIG. 1.

  The SCRC driver 31 includes the PMOS transistor 100 shown in FIGS.

  The PMOS transistor 100 includes two gate electrodes (gates 51a and 51b). The PMOS transistor 100 is formed in the N-type well 52. The PMOS transistor 100 includes source regions 53a and 53b, which are P + diffusion regions, and a drain region 54.

  The drain region 54 is connected to an upper layer drain wiring (metal wiring) 56 through a via 55. The source regions 53a and 53b are connected to the source wirings 58a and 58b of the upper layer through vias 57a and 57b. The source wiring 58 is connected to a power source that supplies a source potential, and the drain wiring 56 is connected to a drain output destination. In the plan view including FIG. 1, for the sake of easy understanding, the via 57 is illustrated as being formed above the source wiring 58, but the via 57 is actually formed of the source region 53 and the source wiring 58. It is formed between. The same applies to the via 55.

  Both the via 57 connected to the source region 53 and the via 55 connected to the drain region 54 have a rectangular shape. However, the via 57 and the via 55 have different arrangement directions in the source region 53 and the drain region 54, respectively. In the first embodiment, the via 57 and the via 55 have substantially the same shape. That is, the via 57 rotated 90 degrees has the same shape and the same arrangement direction as the via 55. However, the shape of the via 55 and the via 57 is not limited, and these shapes may be different.

  Each of the plurality of vias 57 connected to the source region 53 is arranged so that the long side is orthogonal to the gate 51. On the other hand, each of the plurality of vias 55 connected to the drain region 54 is arranged so that the long side is parallel to the gate 51.

  Referring to FIG. 4, it can be seen that the width of the via 57 connected to the source region 53 is wider than the width of the via 55 connected to the drain region 54.

  Note that a gate insulating film 61 is formed between the N-type well 52 and the gate 51. An interlayer insulating film 62 is formed so as to cover the source region 53, the drain region 54, and the gate 51. The via 57 is formed in the interlayer insulating film 62 so as to be in contact with the source region 53. Similarly, the via 55 is formed in the interlayer insulating film 62 so as to be in contact with the drain region 54.

  As described above, in the PMOS transistor 100 according to the first embodiment, the vias 57 are arranged in an array so that the long side of the rectangular slit via is orthogonal to the gate 51, and the number of vias that can be connected to the source region 53 is determined. It is increasing.

  Since the long side of the via 57 in the source region 53 is arranged so as to be orthogonal to the gate 51, the width of the source region 53 is wider than the width of the drain region 54. For this reason, although the capacitance corresponding to the width of the source region 53 increases, the capacity of the transistor does not matter even if the capacitance on the source side increases.

  In the first embodiment, the PMOS transistor 100 having two gate electrodes has been described. However, in the PMOS transistor having one gate electrode, a via connected to the source region is formed laterally with respect to the gate. By placing it, the same effect as the PMOS transistor 100 can be obtained. Furthermore, also in the NMOS transistor, the resistance value on the source side can be reduced by placing the via connected to the source region laterally with respect to the gate.

  As described above, the via 57 in the source region is arranged so that the long side is orthogonal to the gate 51, so that a larger number of vias than in the case where the via 57 is arranged in parallel to the gate 51. Can be formed. Therefore, it is possible to prevent deterioration in transistor characteristics (quality) due to a low resistance on the source side and a high resistance on the source side. If the semiconductor device is further miniaturized and the via interval can be narrowed in the future, more slit vias can be arranged, and the resistance value on the source side can be further reduced.

<Comparative Example 1>
Next, a comparative example of the PMOS transistor 100 according to the first embodiment will be described.

  FIG. 5 is a diagram illustrating an example of a plan view of the PMOS transistor 101 according to the first comparative example. FIG. 6 is a diagram illustrating an example of a schematic cross-sectional view taken along the line B-B in FIG. 5. In the subsequent drawings including FIG. 5 and FIG. 6, the same components as those in FIG. 1 and FIG.

  A difference between the PMOS transistor 100 shown in FIG. 1 and the PMOS transistor 101 shown in FIG. 5 is that the long side of the via 57 connected to the source region 53 is arranged in parallel to the gate 51. In addition, referring to FIG. 6, it can be seen that the via 57 and the via 55 have the same width.

  Since the long side of the via 57 connected to the source region 53 is parallel to the gate 51, many vias cannot be connected to the source region 53. Specifically, four vias 57 are connected in the PMOS transistor 100 of FIG. 1, whereas only three vias 57 are connected in the PMOS transistor 101 of FIG.

  Accordingly, it can be said that the PMOS transistor 100 of FIG. 1 has a smaller resistance value on the source side because the number of vias 57 connected to the source region 53 is larger. However, in the PMOS transistor 101 of FIG. 5, it is not necessary to place the via 57 horizontally in the source region 53 (the long side is orthogonal to the gate 51), so that the width of the source region 53 can be narrower than that of the PMOS transistor 100.

  FIG. 7 is a diagram for explaining the influence of the source-side wiring resistance in the PMOS transistor 100 shown in FIG. 1 and the PMOS transistor 101 shown in FIG. FIG. 7A corresponds to the PMOS transistor 100, and FIG. 7B corresponds to the PMOS transistor 101 according to the first comparative example.

  In FIG. 7, the parasitic resistance of the source wiring of each transistor is indicated by a dotted line, the parasitic resistance value of the PMOS transistor 100 is R1, and the parasitic resistance value of the PMOS transistor 101 is R2. If the voltage value at both ends of the parasitic resistance in the source wirings of the PMOS transistors 100 and 101 is V, the currents supplied to the respective transistors are I1 = V / R1 and I2 = VDD / R2.

  As described above, since the parasitic resistance value of the PMOS transistor 100 is smaller than that of the PMOS transistor 101 (R1 <R2), the current value flowing through the parasitic resistance is I1> I2. Therefore, if the longer side of the via 57 connected to the source region 53 is orthogonal to the gate 51 as in the PMOS transistor 100 according to the first embodiment, the current supply capability to the transistor is higher. I can say that. That is, in the first embodiment, the resistance value can be lowered while suppressing variations in the parasitic resistance in the source wiring, so that a decrease in the current value supplied to the transistor can be suppressed. That is, deterioration of transistor characteristics can be prevented. Further, when the resistance value on the source side is reduced, the amount of current supplied to the transistor is increased, and the response speed of the transistor (gate charging time) is improved (see FIG. 8).

  Next, it will be described that the resistance value on the source side is lower in the PMOS transistor 100 according to the first embodiment than in the PMOS transistor 101 according to the first comparative example, regardless of the measurement point. The measurement point of the resistance value on the source side is 7 points as shown in FIGS. The measurement points shown in FIGS. 9 and 10 are the points P1 to P7 that divide the vertical direction (gate direction) of the source region 53a into six.

  FIG. 11 is a diagram illustrating an example of a measurement result of the source-side resistance at each point in FIGS. 9 and 10. In FIG. 11, the wiring resistance value W and the diffusion resistance value F between the points of the PMOS transistor 100 and the PMOS transistor 101 are illustrated.

  Referring to FIG. 11, it can be seen that both the wiring resistance value W and the diffusion resistance value F are lower in the PMOS transistor 100 according to the first embodiment than in the PMOS transistor 101 according to the first comparative example.

  Next, regardless of which direction power is supplied to the source of the transistor, the PMOS transistor 100 according to the first embodiment is closer to the source side than the PMOS transistor 101 according to the first comparative example. Explain that the resistance value is low.

  As shown in FIG. 12, when power is supplied to the source from two directions above the transistor (direction A), side of the transistor (direction B), and below the transistor (direction C), as shown in FIG. Consider the change in resistance on the source side. 12A corresponds to the PMOS transistor 100 according to the first embodiment, and FIG. 12B corresponds to the PMOS transistor 101 according to the first comparative example. Also, the resistance measurement points on the source side are points P1 to P7 shown in FIGS.

  Referring to FIG. 13, the diffusion resistance value F is equal to that of the PMOS transistor 100 according to the first embodiment than that of the PMOS transistor 101 according to the first comparative example, regardless of which of the three directions power is supplied. It turns out that it is low.

<Comparative Example 2>
Next, a second comparative example will be described.

  As in the PMOS transistor 100 according to the first embodiment, not only the via 57 connected to the source region 53 but also the via 55 connected to the drain region 54 may be arranged orthogonal to the gate 51. . Specifically, as shown in FIG. 14, in the PMOS transistor 102 according to the second comparative example, the via 55 connected to the drain region 54 is also arranged orthogonal to the gate 51.

  The response performance of the PMOS transistor 101 (all vias parallel to the gate) shown in FIG. 5 and the PMOS transistor 102 (all vias orthogonal to the gate) shown in FIG. 14 are compared. FIG. 15 is a diagram for explaining the response performance of the PMOS transistor 101 and the PMOS transistor 102. FIG. 15A corresponds to the PMOS transistor 101 according to the first comparative example, and FIG. 15B corresponds to the PMOS transistor 102 according to the second comparative example.

  In FIG. 15, the parasitic resistance and parasitic capacitance of the source wiring of each transistor are illustrated by dotted lines. The parasitic resistance value of the source wiring of the PMOS transistor 101 is R1, and the parasitic resistance value of the source wiring of the PMOS transistor 102 is R2. The parasitic resistance value of the drain wiring of the PMOS transistor 101 is R3, and the parasitic resistance value of the drain wiring of the PMOS transistor 102 is R4. The parasitic capacitance value of the drain of the PMOS transistor 101 is C1, and the parasitic capacitance value of the drain of the PMOS transistor 102 is C2. The on-resistances of the PMOS transistors 101 and 102 are Ron.

  As shown in FIG. 14, by arranging the via 55 connected to the drain region 54 so as to be orthogonal to the gate 51, the area of the diffusion layer increases, and the junction capacitance increases. As a result, the drain parasitic capacitance C2 in the PMOS transistor 102 increases (see FIG. 16).

  For example, the on-resistance Ron = 4.6 kΩ. Further, it is assumed that the parasitic capacitance C1 of the PMOS transistor 101 is 0.47 [fF], and the parasitic capacitance C2 of the PMOS transistor 102 is 0.54 [fF]. In this case, the time constant of the PMOS transistor 101 is τ1 = 2.16 [ps], the time constant of the PMOS transistor 102 is τ2 = 2.48 [ps], and the signal of τ2 is delayed from τ1.

  On the drain side, the on-resistance Ron of the transistor is larger than the parasitic resistance values R3 and R4 of the drain wiring, and it can be said that the parasitic resistance values R3 and R4 have little influence on the response performance of the transistor. However, if the vias 55 of the drain region 54 are also placed horizontally, the increase in junction capacitance has a large effect on the response performance, which affects the signal charge speed. As an index when measuring the performance of an electronic circuit including a transistor, it is important how much delay the signal can be responded to (can be charged with a signal).

  Therefore, with respect to the via 55 connected to the drain region 54, the long side is not perpendicularly arranged with respect to the gate 51 as shown in FIG. 14, but with respect to the gate 51 so as not to increase the junction capacitance. The arrangement in which the long sides are parallel has better characteristics. Therefore, only the via 57 connected to the source region 53 is horizontally (orthogonal) with respect to the gate 51, and the PMOS transistor 100 according to the first embodiment has all the vias horizontally with respect to the gate. The quality is higher than that of the PMOS transistor 102.

<Comparative Example 3>
Next, a third comparative example will be described.

  In order to reduce the resistance value on the source side, the source region may be enlarged and the vias arranged in the enlarged source region may be arranged in two rows. Specifically, as shown in FIG. 17, the PMOS transistor 103 according to the third comparative example has a configuration in which the vias 57 connected to the source region 53 are vertically arranged in two rows. In FIG. 17, the source wiring is not shown for ease of understanding, but actually the source wiring 58 exists so as to cover the via 57.

  Consider resistance values on the source side of the PMOS transistor 100 according to the first embodiment and the PMOS transistor 103 according to the fourth comparative example. Referring to FIG. 17, in the PMOS transistor 103 according to the fourth comparative example, since the diffusion layer resistance between the vias 57 in the adjacent columns is added, the entire resistance value on the source side is shown in FIG. Than to rise.

  FIG. 18 is a schematic diagram of resistance components of the PMOS transistor 100 according to the first embodiment and the PMOS transistor 103 according to the third comparative example. FIG. 18A corresponds to the PMOS transistor 100 according to the first embodiment, and FIG. 18B corresponds to the PMOS transistor 103 according to the third comparative example. In FIG. 18B, black circle points P1 to P6 shown within a dotted line frame mean connection points of vias 57-1 to 57-6 shown in FIG. For example, the via 57-1 in FIG. 17 is connected to the source wiring at a point P1 in FIG.

  Referring to FIG. 18, in FIG. 18B, the diffusion layer resistance F1 between the via 57-1 and the via 57-4, the diffusion layer resistance F2 between the via 57-2 and the via 57-5, and the via 57- 3 and the diffusion layer resistance F3 between the via 57-6 are added. Therefore, the influence of the added diffusion layer resistance increases as the distance from the gate 51 increases. For example, even if the number of vias connected to the source region 53 is increased, the improvement effect is limited.

  Further, since the area of the source region 53 is increased, the response performance of the transistor is deteriorated as described in the second comparative example, which is not preferable.

  As described above, the via arrangement of the PMOS transistor 100 according to the first embodiment is more advantageous than the via arrangement described in the first to third comparative examples.

<Application example>
In the first embodiment, the SCRC driver 31 used in the power gating circuit has been described as the application destination of the PMOS transistor 100 in which the long side of the via 57 connected to the source region 53 is arranged orthogonal to the gate 51. However, the application destination of the PMOS transistor 100 is not limited to these, and it is preferable to use it for a buffer circuit with high power consumption, a circuit that requires quick response performance (a transistor for which a waveform is to be raised quickly), or the like. .

  FIG. 19 is a diagram illustrating an example of a planar layout diagram of the inverter circuit. When the inverter circuit shown in FIG. 19A is realized, the via arrangement described in the first embodiment is applied to each of the PMOS transistor 201 and the NMOS transistor 202.

  Referring to FIG. 19B, the via 301 connected to the source region of the PMOS transistor 201 is arranged so that the long side is orthogonal to the gate. Similarly, the via 302 connected to the source region of the NMOS transistor 202 is arranged so that the long side is orthogonal to the gate. The inverter circuit having such a configuration is preferably used for a circuit with high power consumption or a circuit that requires high response performance.

  Alternatively, as shown in FIG. 20B, even when a single transistor is formed by a plurality of gates (in the case of a W-size divided layout), the vias 301 and 302 connected to the source region are gated. If the long sides are arranged so as to be orthogonal to each other, an effect of reducing the resistance value on the source side can be obtained.

  Further, when improving the performance of a NAND circuit (NAND) or a NOR circuit (NOR), as shown in FIGS. 21 and 22, it is connected to the source region of a transistor whose performance is to be improved. It is preferred to place the vias horizontally (perpendicular to the gate) rather than vertically (parallel to the gate).

  FIG. 21 is a diagram illustrating an example of a planar layout diagram of the NAND circuit. In FIG. 21, vias 303 and 304 are connected to the source regions of the PMOS transistors 203 and 204 so that the long sides are orthogonal to the gate. On the other hand, for the NMOS transistor, a via 305 is connected to the source region of the NMOS transistor 205 so that the long side is orthogonal to the gate.

  FIG. 22 is a diagram illustrating an example of a planar layout diagram of the NOR circuit. In FIG. 22, a via 307 is connected to the source region of the PMOS transistor 207 so that the long side is orthogonal to the gate. On the other hand, regarding the NMOS transistor, vias 309 and 310 are connected to the source regions of the NMOS transistors 209 and 210 so that the long side is orthogonal to the gate.

  Since the performance of a transistor in which a via connected to the source region is placed laterally with respect to the gate is improved, it is considered that the characteristics of the circuit can be improved by applying such a transistor to many logic circuits. However, since a laterally long via is arranged in the source region, the source region is expanded in the lateral direction, and the area of the transistor is increased. Therefore, if the number of transistors increases, the influence on the substrate area increases. Therefore, in order to reduce the impact on the area while improving the characteristics of the transistor, a circuit that consumes more current than a normal logic element, such as a power gating circuit (including an SCRC circuit), a buffer circuit, and an operation speed are emphasized. It is preferable to apply to a circuit limitedly. In this case, a transistor in which a vertically long contact is provided for both the source and drain and a transistor in which the source is horizontally long and the drain is provided with a vertically long contact coexist.

  Each disclosure of the cited patent documents and the like cited above is incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. In addition, various combinations or selections of various disclosed elements (including each element in each claim, each element in each embodiment or example, each element in each drawing, etc.) within the scope of the entire disclosure of the present invention. Is possible. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea. In particular, with respect to the numerical ranges described in this document, any numerical value or small range included in the range should be construed as being specifically described even if there is no specific description.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 11 Clock input circuit 12 FIFO circuit 13 Command input circuit 14 Command decode circuit 15 Row decoder 16a, 16b Column decoder 17 Refresh control circuit 18 Mode register 19 Input / output circuit 20 Address input circuit 21 Address latch circuit 22 Memory cell array 23a, 23b Memory area 24 Sense amplifier 25 Internal power generation circuit 26 Power gating controller 31 SCRC driver 32 Main power line 33 Pseudo power line 34 NAND circuit 35 Previous stage inverter circuit 36 Final stage inverter circuit 37 Main ground lines 41, 43, 100 to 103 201, 203, 204, 207, 208 PMOS transistor 42 44, 202, 205, 206, 209, 210 NMOS transistors 51, 51a, 51b Gate 52 Well (N-type diffusion layer)
53, 53a, 53b Source region 54 Drain regions 55, 57, 57-1 to 57-6, 57a, 57b, 301 to 310 Via 56 Drain wiring 58, 58a, 58b Source wiring 61 Gate insulating film 62 Interlayer insulating film

Claims (7)

A first diffusion layer;
A second diffusion layer;
A first channel region sandwiched between the first and second diffusion layers and extending in a first direction;
A first gate electrode formed on the first channel region so as to extend in the first direction via a gate insulating film;
An interlayer insulating film formed to cover the first diffusion layer, the second diffusion layer, and the first gate electrode;
A first contact formed in the interlayer insulating film so as to be in contact with the first diffusion layer, wherein a length in the first direction is in a second direction perpendicular to the first direction; A first contact formed longer than the length;
A second contact formed in the interlayer insulating film so as to contact the second diffusion layer, wherein the length in the first direction is shorter than the length in the second direction. A second contact;
A semiconductor device comprising:   The semiconductor device according to claim 1, wherein the number of the second contacts is larger than the number of the first contacts.   The semiconductor device according to claim 1, wherein a shape of the first contact and a shape of the second contact are the same. A first metal wiring connected to the first contact;
A second metal wiring connected to the second contact;
The semiconductor device according to claim 1, further comprising:   5. The semiconductor device according to claim 1, wherein a length of the second diffusion layer in the second direction is longer than a length of the first diffusion layer in the second direction. 6. A third diffusion layer;
A second channel region sandwiched between the first and third diffusion layers and extending in the first direction;
A second gate electrode formed on the second channel region so as to extend in the first direction via a gate insulating film;
A third contact formed in the interlayer insulating film so as to contact the third diffusion layer, wherein the length in the first direction is shorter than the length in the second direction. A third contact;
The semiconductor device according to claim 1, further comprising:   A semiconductor circuit comprising the semiconductor device according to claim 1 and comprising at least one of a driver circuit, an inverter circuit, a negative logical product circuit, and a negative logical sum circuit.