JP2015233296A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce an area of a semiconductor integrated circuit device comprising an A/D converter which performs conversion processing on an inputted analog signal into a digital signal by performing digital correction processing.SOLUTION: A semiconductor integrated circuit device comprises first and second A/D converters. In a first mode, a first test signal is inputted in common to the first and second A/D converters, and a first correction coefficient for the first A/D converter and a second correction coefficient for the second A/D converter are calculated. In a second mode, the first A/D converter performs first digital correction processing using the first correction coefficient, thereby performing A/D conversion processing on a first analog signal into a first digital signal, and the second A/D converter performs second digital correction processing using the second correction coefficient, thereby performing A/D conversion processing on a second analog signal into a second digital signal.

Description

  More particularly, the present invention relates to a semiconductor integrated circuit device for communication processing having an AD converter (Analog Digital Converter).

  Each of Non-Patent Documents 1 to 4 discloses an AD converter (ADC). The ADC includes an AD converter (ADCU) that receives an analog signal and a digital correction unit (DCU) that receives the output of the ADCU. By using the ADCU and the DCU in this way, a high-speed, high-accuracy and low power consumption ADC is obtained.

T. T. et al. Oshima, et al. , “Fast non-linear linearization of pipelined A / D converters,” IEEE 2008 Midwest Symposium on Circuits and Systems, Session C2L-C-1. 2008. T. T. et al. Oshima, et al. "23-mW 50-MS / s 10-bit pipeline A / D converter with linear LMS foreground calibration," 2009 International Symposium on Circuits and Systems. 960-963, May 2009. J. et al. Mcneill, et al. , “A split-ADC architecture for deterministic digital calibration of a 16b 1MS / s ADC,” IEEE 2005 International Solid-State Circuits Conf. 276-277, Feb. 2005. W. Liu et al. "A 12b 22.5 / 45 MS / s 3.0 mW 0.059 mm2 CMOS SAR ADC achieving over 90 dB SFDR," IEEE 2010 International Solid-State Circuits Conference, pp. 380-381, Feb. 2010.

  Regarding the Non-Patent Document 1 to Non-Patent Document 4, the inventor examined the configuration and operation of the ADC disclosed therein. First, prior to the study, the inventor rewrote the ADCs described in Non-Patent Literature 1 to Non-Patent Literature 4 as shown in the configuration diagrams of FIGS. That is, FIGS. 1 to 4 are reference drawings rather than prior art drawings. Hereinafter, FIGS. 1 to 4 are referred to as Reference FIGS. 1 to 4, respectively.

  The ADC 11 shown in FIG. 1 includes a reference AD conversion unit (RADCU) 13, an ADCU 12, a DCU 14, and an error calculation unit (ECU) 15.

  An analog signal (Input) is input to both the RADC 12 and the ADCU 12. Here, the RADC 13 performs analog / digital conversion (AD conversion) processing at a low speed and high accuracy as compared with the ADCU 12, and the ADCU 12 performs high speed and low accuracy AD conversion processing as compared with the RADCU 13.

  A predetermined clock (CK) to be a reference for AD conversion processing is input to the ADCU 12, and a predetermined clock (CK) to be a reference for AD conversion processing is input to the RADC 13 by a frequency divider (DIV) 18. The divided clock is input. A digital output as a result of AD conversion processing by the ADC 12 is input to the DCU 14. The DCU 14 digitally corrects the digital output using the correction coefficient to output a digital signal (Output) as a result of AD conversion processing of the ADC 11 for the analog signal (Input).

  The ECU 15 calculates the difference between the digital signal from the DCU 14 and the digital output signal from the RADC 13 and outputs the difference to the DCU 14 as a conversion error (e). Based on this conversion error (e), the DCU 14 searches for a correction coefficient by the LMS algorithm. Here, the LMS algorithm is an abbreviation for the Last Means Square algorithm, and is one of adaptive control methods. The LMS algorithm estimates Wi from a large number of samples of Di and A with respect to what is known that A = ΣWi · Di holds when the input data is Di, the output is A, and the coefficient is Wi.

  In the ADC 11, background correction is possible. Here, the background correction means that a correction coefficient is calculated by simultaneously performing calculation of a correction coefficient for digital correction processing and AD conversion processing using the calculated correction coefficient. Further, the output result of the high-speed and low-accuracy ADCU 12 is digitally corrected by the DCU 14 to obtain a high-speed and high-precision digital output signal (Output).

  However, it is necessary to provide both the ADC 12 and the RADC 13 in the semiconductor integrated circuit device, which increases the number of design steps, increases the design cost, increases the cost due to the increased area, and prevents the semiconductor integrated circuit device from being downsized. A point is generated.

  The ADC 21 shown in FIG. 2 includes a switching circuit SC, a reference digital / analog (DA) converter (RDACU) 23, an ADCU 22, a DCU 24, and an error calculator (ECU) 25.

  When the switch SW1 of the switching circuit SC is OFF and the switch SW2 is ON, a digital test signal (TestInput) is input to the RDACU 23 and subjected to DA conversion processing, and an analog test signal as a DA conversion result from the RDACCU 23 is input to the ADCU 22. AD conversion processing is performed. Here, the RDACU 23 performs low-speed and high-precision DA conversion processing as compared with the ADC 22, and the ADC 22 performs high-speed and low-precision AD conversion processing as compared with the RDAC 23. A predetermined clock (CK) for serving as a reference for AD conversion processing is input to the ADCU 22, and a predetermined clock (CK) for serving as a reference for DA conversion processing is input to the RDACU 23 by a frequency divider (DIV) 28. The divided clock is input. The ECU 25 calculates the difference between the digital signal that is the result of the digital correction processing performed by the DCU 24 and the digital test signal (TestInput), and outputs the difference to the DCU 24 as a conversion error (e). Based on this conversion error (e), the DCU 24 searches for a correction coefficient by the LMS algorithm.

  When the switch SW1 of the switching circuit SC is on and the switch SW2 is off, an analog signal (Input) is input to the ADCU 24. A digital output as a result of AD conversion processing in the ADCU 22 is input to the DCU 24. The DCU 24 digitally corrects the digital output using the correction coefficient to output a digital signal (Output) as a result of AD conversion processing of the ADC 21 for the analog signal (Input). Here, the DCU 24 uses a correction coefficient obtained when the switch SW1 of the switching circuit SC is off and the switch SW2 is on.

  The ADC 21 performs foreground correction. Here, the foreground correction is a mode in which a first mode for calculating a correction coefficient for digital correction processing and a second mode for performing AD conversion processing using the calculated correction coefficient are temporally separated. This means that the correction coefficient is calculated. The first mode is when the switch SW1 of the switching circuit SC is off and the switch SW2 is on, and the second mode is when the switch SW1 of the switching circuit SC is on and the switch SW2 is off. Furthermore, the output result of the high-speed and low-precision ADCU 22 is digitally corrected by the DCU 24, whereby a high-speed and high-precision digital output signal (Output) is obtained.

  However, it is necessary to provide both the ADCU 22 and the RDACU 23 in the semiconductor integrated circuit device, and there is a problem that an increase in design man-hours, an increase in design cost, an increase in cost due to an increase in area, and a reduction in size reduction of the semiconductor integrated circuit device A point is generated.

  The ADC 31 illustrated in FIG. 3 includes a first AD conversion unit (ADCU (1)) 32a, a second AD conversion unit (ADCU (2)) 32b, a first digital correction unit (DCU (1)) 34a, A second digital correction unit (DCU (2)) 34b, an error calculation unit (ECU) 35, and an output signal addition averaging unit (OAAU) 36 are included.

  An analog signal (Input) is input to both the ADCU (1) 32a and the ADCU (2) 32b. The first dither signal (Dither1) is input to the ADCU (1) 32a, and the second dither signal (Dither2) having a different sign and the same absolute value as the Dither1 is input to the ADCU (2) 32b. Here, the dither signal is a DC offset applied voltage and is used for effectively calculating a correction coefficient. In each of the ADCU (1) 32a and the ADCU (2) 32b, the digital output as a result of AD conversion processing is input to the DCU (1) 34a and the DCU (2) 34b, respectively.

  Each of the DCU (1) 34a and the DCU (2) 34b outputs the result of digitally correcting the digital output using the correction coefficient to the OAAU 36. The OAAU 36 adds the outputs from the DCU (1) 34a and DCU (2) 34b, divides them by 2, and averages them, and outputs a digital signal (Output) as an AD conversion processing result of the ADC 31 for the analog signal (Input).

  The ECU 35 calculates the difference between the digital signal from the DCU (1) 34a and the digital signal from the DCU (2) 34b and outputs the difference to the dither difference unit (DDU) 37. In the DDU 37, a value obtained by subtracting 2α from the output from the ECU 35 is output to the DCU (1) 34a and the DCU (2) 34b as a conversion error (e). Here, 2α = Dither1-Dihter2. Based on the conversion error (e), the DCU (1) 34a and the DCU (2) 34b search for correction coefficients by the LMS algorithm.

  The ADC 31 can perform background correction. The reason is that the dither signal component is canceled by the OAAU 36 because Dither1 and Dither2 have different signs and have the same absolute value. Further, the output results of the high-speed and low-precision ADCU (1) 32a and ADCU (2) 32b are digitally corrected by the DCU (1) 34a and DCU (2) 34b, thereby obtaining a high-speed and high-precision digital output signal (Output). It is done.

  However, an AD conversion unit and a digital correction unit are required as a pair, such as ADCU (1) 32a and ADC (2) U32b and DCU (1) 34a and DCU (2) 34b, and an AD conversion unit and a digital correction unit are required. As compared with the configuration having only one, there is a problem in that the cost increases with the increase in area and the miniaturization of the semiconductor integrated circuit device is hindered.

  The ADC 41 shown in FIG. 4 includes an ADCU 42, a DCU (1) 44a and a DCU (2) 44b, a delay unit (Delay) 49, an error calculation unit (ECU) 45, and an output signal adding and averaging unit (OAAU). ) 46 and a dither difference unit (DDU) 47.

  An analog signal (Input) is input to the ADCU 42. Further, the AD converter 42 is configured to receive the first dither signal (Dither1) and the second dither signal (Dither2) having the same sign and different absolute value as the Dither1.

  The operation of the ADCU 42 will be described with reference to the AD conversion unit sequence (ADCUsequence) in FIG. The analog signal (Input) is sampled in the sampling period (S). The analog signal (Input) sampled in the subsequent first AD conversion period (A / D1) and Dither1 added to the ADCU 42 are subjected to AD conversion processing by the ADCU 42, and the first AD conversion result (A / D1R) is output. Further, the analog signal (Input) sampled in the subsequent second AD conversion period (A / D2) and Dither2 added to the ADCU 42 are subjected to AD conversion processing in the ADCU 42, and the second AD conversion result ( A / D2R) is output. Delay 49 delays A / D1R by the second AD conversion period (A / D2) and outputs it to DCU (1) 44a. As a result, the timing at which A / D1R is input to DCU (1) 44a and the timing at which A / D2R is input to DCU (2) are the same.

  Each of DCU (1) 44a and DCU (2) 44b outputs the result of digitally correcting each of A / D1R and A / D2R to the OAAU 46 using a correction coefficient. The output from the DCU (1) 43 and the DCU (2) 44b is added and divided and divided by 2, and the OAAU 46 uses the digital signal (Output) as the AD conversion processing result of the ADCU 41 for the analog signal (Input). Output.

  The ECU 45 calculates the difference between the A / D1R from the DCU (1) 44a and the A / D2R from the DCU (2) 44b and outputs the difference to the dither difference unit (DDU) 47. In the DDU 47, a value obtained by subtracting 2α from the output from the ECU 45 is output to the DCU (1) 44a and the DCU (2) 44b as a conversion error (e). Based on the conversion error (e), the DCU (1) 44a and the DCU (2) 44b search for correction coefficients by the LMS algorithm.

  The ADC 41 can perform background correction. The reason is that the dither signal component is canceled by the OAAU 46 because Dither1 and Dither2 have different signs and have the same absolute value. Further, the output result of the high-speed and low-precision ADCU 42 is digitally corrected by the digital correction units DCU (1) 44a and DCU (2) 44b, whereby a high-speed and high-precision digital output signal (Output) is obtained.

  However, the DCU (1) 44a and the DCU (2) 44b are required in pairs, and an increase in cost due to an increase in area and a semiconductor integrated circuit device compared to a configuration in which only one AD conversion unit and one digital correction unit are provided. The problem of hindering miniaturization occurs.

  A semiconductor integrated circuit device according to an embodiment includes first and second AD converters. In the first mode, the first test signal is input to both the first and second AD converters in common, and the first correction coefficient for the first AD converter and the second correction for the second AD converter. A coefficient is calculated. In the second mode, the first AD converter performs the first digital correction process using the first correction coefficient to convert the first analog signal to the first digital signal, and the second AD converter performs the second correction. A second analog signal is converted into a second digital signal by performing a second digital correction process using the coefficient.

  According to the embodiment, the semiconductor integrated circuit device has a small area.

It is the block diagram which rewritten the AD converter described in the nonpatent literature 1. It is the block diagram which rewrote the AD converter described in the nonpatent literature 2. It is the block diagram which rewrote the AD converter described in the nonpatent literature 3. It is the block diagram which rewritten the AD converter described in the nonpatent literature 4, and the operation | movement diagram for this block diagram. 1 is a configuration diagram of a communication system including a semiconductor integrated circuit device according to a first embodiment. 3 is an operation diagram of a communication system including the semiconductor integrated circuit device according to the first embodiment. FIG. 3 is a configuration diagram of a digital correction unit for IQ signal according to Embodiment 1. FIG. 4 is a configuration diagram of an inter-IQ correction unit according to Embodiment 1. FIG. FIG. 3 is a configuration diagram of a charge sharing AD conversion unit, which is an embodiment of an I signal AD conversion unit and a Q signal AD conversion unit. It is a block diagram of a charge redistribution type AD converter that is an embodiment of an AD converter for I signal and an AD converter for Q signal. It is a block diagram of a charge redistribution type AD converter that is an embodiment of an AD converter for I signal and an AD converter for Q signal. It is a modification of a semiconductor integrated circuit device. It is one Example of the test signal generation circuit for AD converters for producing | generating the test signal for AD converters. It is one Example of the test signal generation circuit for AD converters for producing | generating the test signal for AD converters. It is one Example of the test signal generation circuit for AD converters for producing | generating the test signal for AD converters. FIG. 6 is a configuration diagram of a communication system including a semiconductor integrated circuit device according to a second embodiment.

  First, the present inventor has a configuration (hereinafter referred to as “basic configuration”) for providing a high-speed, high-precision, low-power AD converter as an AD converter used in a semiconductor integrated circuit device for communication processing. Thought.

  In other words, the basic configuration is an AD converter for I signal that performs an AD conversion process by digitally correcting an analog I signal that has been AD converted, and an AD converter that performs an analog conversion of an analog Q signal by performing an AD conversion process. It has an AD converter for Q signal that performs conversion processing.

  In this basic configuration, it was considered that either digital correction processing requires background correction or foreground correction.

  First, when foreground correction is applied as digital correction processing to obtain a semiconductor integrated circuit device having the above-described basic configuration, for each of the I signal AD converter and the Q signal AD converter to be used, Any of the four ADCs 11, 21, 31, and 41 described is considered to be applicable. Assuming that the circuit is applied, a circuit having a large area that is used only in the first mode is required, and a reduction in the area of the semiconductor integrated circuit device is hindered. The reason is as follows.

  When any of ADCs 11, 21, 31, and 41 is applied to the basic configuration described above, two ADCs are required for the I signal and the Q signal. When the ADC 11 shown in FIG. 1 is applied, two RADCUs 13 are not necessary in the second mode in which the conversion error (e) does not need to be obtained. Therefore, the two RADCUs 13 are circuits used only in the first mode. In the case where the ADC 21 shown in FIG. 2 is applied, two RDACCUs 23 are not necessary in the second mode in which the conversion error (e) does not need to be obtained. The two RDACCUs 23 are circuits used only in the first mode. When the ADC 31 shown in FIG. 3 is applied, there are four ADCUs and DCUs, but two ADCUs and two DCUs of these are circuits that are not used in the first mode. In the second mode in which the conversion error (e) does not need to be obtained, it is sufficient that the ADC for the I signal has one ADCU and one DCU, and the ADC for the Q signal has one ADCU and one DCU. This is because it is only necessary. In the case where the ADC 41 shown in FIG. 4 is applied, the DCU (1) 44a or the DCU (2) 44b is not necessary in the second mode in which the conversion error (e) does not need to be obtained. The reason is that in the second mode, the input of the dither signal is stopped with respect to the ADCU 42, and the output of the DCU (1) 44a or DCU (2) 44b is used as it is as the output of the ADC 41 instead of the output from the OAAU 47. This is because the operation of DCU (1) 44a or DCU (2) 44 can be stopped. Therefore, the DCU (1) 43 or DCU (2) 44b is a circuit used only in the first mode.

  As described above, the area of the circuit described as not necessary in the second mode is large, which hinders the reduction of the area of the semiconductor integrated circuit device.

  Furthermore, as an additional problem, when applying the foreground correction to obtain a semiconductor integrated circuit device having the above-described premise configuration, for each of the I signal AD converter and the Q signal AD converter to be used, When any of ADCs 11, 21, 31, and 41 is applied, there are the following problems. In the first mode, a circuit having a large area that is used only in the first mode operates and a circuit having a large area that is also used in the second mode also operates, which hinders reduction in power consumption of the semiconductor integrated circuit device. The reason is as follows.

  As described above, two ADCUs are required. Therefore, when the ADC 12 shown in Reference FIG. 1 is applied, two RADCUs, ADCUs, and DCUs each operate in the first mode. In the case where the ADC 21 shown in FIG. 2 is applied, two RDACUs, ADCUs, and DCUs each operate in the first mode. In the case where the ADC 31 shown in FIG. 3 is applied, four ADCUs and four DCUs each operate in the first mode. Therefore, power consumption increases. In particular, RADCU, RDACCU, and ADCU are analog circuits, and an operational amplifier is often used to obtain good performance. However, since this operational amplifier is composed of a circuit that consumes a large amount of power, the power consumption in the first mode is low. growing. When the ADC 41 shown in FIG. 4 is applied, two ADCUs and four DCUs operate in the first mode. Therefore, power consumption increases. Further, at least in the first mode, AD conversion processing in the ADCU is required twice for every sampling of the analog signal in order to obtain the conversion error (e). Therefore, AD conversion processing in the ADCU is required at high speed, and power consumption increases in the first mode. In particular, an ADCU using an operational amplifier needs to operate the operational amplifier at a high speed. As the operational amplifier increases in high-speed operation, power consumption increases accordingly, which hinders low power consumption.

  Next, the ADCs 11, 31, and 41 can perform background correction. For example, consider a case where the background correction is applied to the semiconductor integrated circuit device having the basic configuration described above, and ADCs 11, 31, and 41 are applied as the AD converter for I signal and the AD converter for Q signal. In this case, the power consumption is hindered as follows.

  In the background correction, there is no first mode or second mode. Therefore, when AD conversion processing is performed, the following is always performed.

  Two ADCUs are required for the I signal and the Q signal. Therefore, when the ADC 11 shown in FIG. 1 is applied, the two RADCUs, the two ADCCUs, and the two DCUs always operate during AD conversion processing. When the ADC 31 shown in the reference FIG. 3 is applied, four ADCUs and four DCUs always operate during AD conversion processing. Therefore, the power consumption is larger than that of the foreground correction type semiconductor integrated circuit device having the first mode and the second mode. In particular, as described above, power consumption during AD conversion processing of RADCU, RDACCU, and ADCU becomes a problem. When the ADC 41 shown in FIG. 4 is applied, two ADCUs and four DCUs always operate during AD conversion processing. Therefore, the power consumption is larger than that of the foreground correction type semiconductor integrated circuit device having the first mode and the second mode. Further, as described above, at the time of AD conversion processing, AD conversion processing in the ADCU is required twice for every sampling of the analog signal in order to obtain the conversion error (e). Therefore, AD conversion processing in the ADCU is required at high speed, and power consumption increases.

  In view of the above, regarding the following two configurations and functions, it is performance-wise to apply any of the four ADCs 11, 21, 31, and 41 as the AD converter for I signal and the AD converter for Q signal. It becomes good.

(1) An I-signal AD converter that performs AD conversion processing by performing digital correction processing on an analog I signal converted from AD, and AD conversion processing by performing digital correction processing on an analog Q signal that has been converted from AD. Semiconductor integrated circuit device having Q signal AD converter to perform (2) Foreground correction of I signal AD converter and Q signal AD converter However, semiconductor having I signal AD converter and Q signal AD converter It can be seen that there are still problems in reducing the area and power consumption of integrated circuit devices.

  When any of the four ADCs 11, 21, 31, 41 is combined with the basic configuration described above, a circuit having a large area for calculating the correction coefficient even if any one of the background correction and the foreground correction is applied. This is because power consumption due to the addition of a circuit having a large area hinders the reduction in area and power consumption of the semiconductor integrated circuit device.

  In view of the above matters, embodiments to be described later have been derived.

  In the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other, and one is related to a part or all of the other, a modified example, an application example, a detailed description, a supplementary description, and the like. Also, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), particularly when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including operation, timing chart, operation step, etc.) are indispensable unless otherwise specified and considered to be clearly essential in principle. It is not a thing. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc., of components, etc., the shape is substantially the same unless otherwise specified or otherwise apparent in principle. And the like are included. The same applies to the above numbers and the like (including the number, numerical value, quantity, range, etc.).

  Hereinafter, embodiments will be described in detail with reference to the drawings. Note that in all the drawings for explaining the embodiments, portions or members having the same function are denoted by the same or related reference numerals, and repeated description thereof is omitted. Also, in the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

(Embodiment 1)
Hereinafter, a configuration of a semiconductor integrated circuit device according to the present embodiment and a communication system including the semiconductor integrated circuit device, and an operation of the semiconductor integrated circuit device and a communication system including the semiconductor integrated circuit device will be described in detail. FIG. 5 is a configuration diagram of a communication system including a semiconductor integrated circuit device. FIG. 6 is an operation diagram of a communication system including a semiconductor integrated circuit device. FIG. 7 is a block diagram of the digital correction unit for I and Q signals in the semiconductor integrated circuit device. FIG. 8 is a configuration diagram of the inter-IQ correction unit in the semiconductor integrated circuit device.

1. Configuration First, the configuration of a semiconductor integrated circuit device according to the present embodiment and a communication system including the semiconductor integrated circuit device will be described with reference to FIG.

(1) Communication system The communication system of the present embodiment includes an antenna ANT, a semiconductor integrated circuit device RFIC for wireless communication, and a baseband processing unit BBU. The antenna ANT receives a high frequency signal HFS as a communication signal from the outside. The semiconductor integrated circuit device RFIC for wireless communication is a portion surrounded by a two-dot chain line in the figure, and demodulates the high frequency signal HFS into a baseband signal. The baseband processing unit BBU receives the baseband signal, performs digital processing, and performs communication signal analysis and data processing. The semiconductor integrated circuit device RFIC is compatible with GSM (Global System Mobile Communication), WCDMA (Wide Band CDMA), and LTE (Long Term Evolution).

(2) Semiconductor Integrated Circuit Device The semiconductor integrated circuit device RFIC includes an analog circuit R-AC, an AD converter I-ADC, an AD converter Q-ADC, a digital processing unit DOU, and an analog circuit T-AC. The analog circuit R-AC is a part surrounded by a chain line in FIG. The analog circuit R-AC receives the high frequency signal HFS via the antenna ANT, and generates the analog I signal R-IA and the analog Q signal R-QA whose phase is shifted by 90 degrees from the analog I signal R-IA. To do. The analog I signal R-IA and the analog Q signal R-QA are said to be orthogonal, but in reality, they are not exactly 90 degrees apart due to variations such as process variations. The AD converter I-ADC is a portion surrounded by a chain line in the figure, receives the analog I signal R-IA, and performs an AD conversion process to generate a digital I signal R-ID. The AD converter Q-ADC is a portion surrounded by a one-dot chain line in the figure, receives the analog Q signal R-QA, and performs an AD conversion process to generate a digital Q signal R-QD. The digital processing unit DOU receives the digital I signal R-ID and the digital Q signal R-QD, performs digital processing, generates a baseband signal, and outputs the baseband signal to the baseband processing unit BBU. The analog circuit T-AC is a portion surrounded by a chain line in FIG. The analog circuit T-AC receives the digital I signal T-ID and the digital Q signal T-QD based on the baseband signal from the baseband processing unit BBU from the digital processing unit DOU, performs modulation processing, and outputs an output high-frequency signal. Is generated.

  The analog I signal is an analog I signal, and the analog Q signal is an analog Q signal. The digital I signal is a digital I signal, and the digital Q signal is a digital Q signal. Further, the I signal is an in-phase signal (In phase signal), and the Q signal is a quadrature signal (Quadrature phase signal).

  Here, the analog circuit T-AC excluding the analog circuit R-AC, AD converter I-ADC, AD converter Q-ADC, digital processing unit DOU, and power amplifier PA described later is on the first semiconductor substrate. Formed. The power amplifier PA is formed on the second semiconductor substrate. The first and second semiconductor substrates are sealed in one package to form a semiconductor integrated circuit device RFIC. The power amplifier PA may be separated from the semiconductor integrated circuit device RFIC without the second second semiconductor substrate. Further, the baseband processing unit BBU is a semiconductor integrated circuit device different from the semiconductor integrated circuit device RFIC, and the antenna ANT is also a circuit device different from the semiconductor integrated circuit device RFIC.

(A) Analog circuit for reception The analog circuit R-AC includes a transmission / reception changeover switch TR-SW, a low noise amplifier LNA, a mixer RI-MIX, a filter I-FIL, and a filter Q-FIL. The analog circuit R-AC includes an I variable amplifier I-PGA, a variable amplifier Q-PGA, a clock pulse generator CPG, and a loop switch L-SW. The transmission / reception selector switch TR-SW is used to input a necessary signal component of the high-frequency signal HFS via the antenna ANT into the analog circuit R-AC. The transmission / reception selector switch TR-SW cuts off unnecessary signal components from the analog circuit T-AC so as not to be input to the analog circuit R-AC. The low noise amplifier LNA amplifies the high frequency signal HFS from the transmission / reception selector switch TR-SW with low noise at a magnification specified by the baseband processing unit BBU. The mixer RI-MIX performs high-frequency signal HFS from the low-noise amplifier LNA and performs down-conversion such that the first mixer signal having a predetermined frequency is converted to a low frequency by mixing the analog I A signal R-IA is generated. The mixer RQ-MIX is a high-frequency signal with respect to the high-frequency signal HFS from the low-noise amplifier LNA, and converts the frequency to a low frequency by mixing a second mixer signal having a predetermined frequency and a phase different from the first mixer signal by 90 degrees. Such down conversion is performed to generate an analog Q signal R-QA. The filter I-FIL receives the analog I signal R-IA from the reception I mixer RI-MIX, and outputs the analog I signal R-IA by passing the frequency in the band designated by the baseband processing unit BBU. The filter Q-FIL receives the analog Q signal R-QA from the mixer RQ-MIX, and outputs the analog Q signal R-QA by passing the frequency in the band specified by the baseband processing unit BBU. The variable amplifier I-PGA receives the analog I signal I-QA from the filter I-FIL and outputs an analog I signal R-IA amplified at a magnification specified by the baseband processing unit BBU. The variable amplifier Q-PGA receives the analog Q signal R-QA from the filter Q-FIL, and outputs an analog Q signal R-QA amplified at a magnification specified by the baseband processing unit BBU. The clock pulse generator CPG is a phase locked loop PLL for generating the first mixer signal and the second mixer signal, and the first and second high-frequency signals that are in phase with a predetermined clock according to the output from the phase locked loop PLL. And a voltage controlled oscillator VCO that generates a second mixer signal.

(B) AD converter for I signal and AD converter for Q signal (b) Configuration The AD converter I-ADC includes a test input terminal TIT, a switching circuit I-SC, an AD converter I-ADCU, and digital And a correction unit DCUI & Q.

  The AD converter Q-ADC includes a test input terminal TIT, a switching circuit Q-SC, an AD conversion unit Q-ADCU, and a digital correction unit DCUI & Q. The test input terminal TIT and the digital correction unit DCUI & Q are shared with the AD converter I-ADC.

(B) AD conversion test operation When the switch SWI1 of the switching circuit I-SC is ON and the switch SWI2 is OFF, the switch SWQ1 of the switching circuit Q-SC is ON and the switch SWQ2 is OFF, the operation is as follows. In the present embodiment, this operation is referred to as an AD conversion test operation. In this specification as a whole, an operation of generating a correction coefficient for AD conversion using the test signal ADC-TS is referred to as an AD conversion test operation.

  The test signal ADC-TS is input to the AD conversion unit I-ADCU via the switching circuit I-SC, and is input to the AD conversion unit Q-ADCU via the switching circuit Q-SC. The AD converter I-ADCU receives the first dither signal Dither1 in addition to the test signal ADC-TS, performs AD conversion on these inputs, and outputs the result to the digital corrector DCUI & Q. The AD conversion unit Q-ADCU receives the second dither signal Dither2 in addition to the test signal ADC-TS, performs AD conversion on these inputs, and outputs the result to the digital correction unit DCUI & Q.

The digital correction unit DCUI & Q has a correction coefficient setting register I-ADCCCSRES and a correction coefficient setting register Q-ADCCCSRES. The correction coefficient setting register I-ADCCCCSRES stores correction coefficients for digital correction processing for the AD converter I-ADC. The correction coefficient setting register Q-ADCCCSRES stores correction coefficients for digital correction processing for the AD converter Q-ADC. The digital correction unit DCUI & Q holds a correction result obtained by digitally correcting the output from the AD conversion unit I-ADCU and a correction result obtained by digitally correcting the output from the AD conversion unit Q-ADCU. Based on these stored correction results, the correction coefficient I-ADCCC to be stored in the correction coefficient setting register I-ADCCCCSRES is determined and stored. Here, the correction coefficient I-ADCCC is _{W i} shown in FIG. Further, the correction coefficient Q-ADCCC to be stored in the correction coefficient setting register Q-ADCCCSRES is determined and stored. Here, the correction coefficient Q-ADCCC is U _i shown in FIG.

(Ha) AD conversion actual operation When the switch SWI1 of the switching circuit I-SC is OFF and the switch SWI2 is ON, the switch SWQ1 of the switching circuit Q-SC is OFF and the switch SWQ2 is ON, the operation is as follows. In this embodiment, the operation at this time is referred to as an AD conversion actual operation. In this specification as a whole, an operation for performing AD conversion processing on a reception analog signal from a reception analog circuit using an AD conversion correction coefficient obtained during an AD conversion test operation is referred to as an AD conversion actual operation.

  The analog I signal R-IA is input to the AD conversion unit I-ADCU via the switching circuit I-SC, and the analog Q signal R-QA is input to the AD conversion unit Q-ADCU via the switching circuit Q-SC. . An analog I signal R-IA is input to the AD conversion unit I-ADCU, and this input is subjected to AD conversion processing, and the result is output to the digital correction unit DCUI & Q. An analog Q signal R-QA is input to the AD conversion unit Q-ADCU, and this input is subjected to AD conversion processing, and the result is output to the digital correction unit DCUI & Q. The digital correction unit DCUI & Q digitally corrects the output from the AD conversion unit I-ADCU using the correction coefficient I-ADCCC stored in the correction coefficient setting register I-ADCCCCSRES. The digital correction unit DCUI & Q outputs a digital I signal R-ID as an AD conversion processing result in the AD converter I-ADC. The digital correction unit DCUI & Q performs digital correction processing on the output from the AD conversion unit Q-ADCU using the correction coefficient Q-ADCCC stored in the correction coefficient setting register Q-ADCCCCSRES. The digital correction unit DCUI & Q outputs a digital Q signal R-QD as an AD conversion processing result in the AD converter Q-ADC.

(C) Digital processing unit The digital processing unit DOU includes an inter-IQ correction unit I / QCU, a calibration signal generation circuit I / QCU-CSG, and a frequency setting register ADC-FSRES. The digital processing unit DOU further includes a period setting register ADC-PSRES, a frequency setting register I / QC-FSRES, a period setting register I / QC-PSRES, and a mode setting register MRES. The IQ correction unit I / QCU detects and corrects mismatches in gain, phase, and DC offset due to the path from the mixer RI-MIX to the variable amplifier I-PGA in the analog circuit R-AC. Further, the inter-IQ correction unit I / QCU detects and corrects a mismatch in gain, phase, and DC offset caused by a path from the mixer RQ-MIX to the variable amplifier Q-PGA. The calibration signal generation circuit I / QCU-CSG generates a test signal I / QC-TS for calculating a correction coefficient for the inter-IQ correction unit I / QCU.

  The inter-IQ correction unit I / QCU has a correction coefficient setting register II / QCUCCRES which stores a correction coefficient II / QCUCC for processing the digital I signal R-ID. Here, the correction coefficients II / QCUCC are the coefficients H11, H12, and kI shown in FIG. Further, the inter-IQ correction unit I / QCU also has a correction coefficient setting register Q-I / QCUCCSRS that stores correction coefficients Q-I / QCUCC for processing the digital Q signal R-QD. Here, the correction coefficients QI / QCUCC are the coefficients H21, H22, and kQ shown in FIG.

(D) Analog circuit for transmission The analog circuit T-AC includes a DA converter I-DAC, a DA converter Q-DAC, a low-pass filter I-LPF, and a low-pass filter Q-LPF. Further, the analog circuit T-AC includes a mixer TI-MIX, a mixer TQ-MIX, an output adding unit T-OAU, and a power amplifier PA. The DA converter I-DAC is based on the baseband signal from the baseband processing unit BBU, receives the digital I signal T-ID output from the digital processing unit DOU, performs DA conversion processing, and performs an analog I signal T-IA. Is generated. The DA converter Q-DAC is based on the baseband signal from the baseband processing unit BBU, receives the digital Q signal T-QD output from the digital processing unit DOU, performs DA conversion processing, and performs an analog Q signal T-QA. Is generated. The low-pass filter I-LPF receives the analog I signal T-IA from the DA converter I-DAC and outputs the analog I signal T-IA through a signal in a lower frequency region than the frequency specified by the baseband processing unit BBU. The low-pass filter Q-LPF receives the analog Q signal T-QA from the DA converter Q-DAC and outputs the analog Q signal T-QA through a signal in a lower frequency region than the frequency specified by the baseband processing unit BBU. The mixer TI-MIX performs up-conversion such that the analog I signal T-IA from the low-pass filter I-LPF is a high-frequency signal and is converted to a high frequency by mixing a third mixer signal having a predetermined frequency. Output. The mixer TQ-MIX is a high-frequency signal with respect to the analog I signal T-IA from the low-pass filter I-LPF, and mixes a fourth mixer signal having a predetermined frequency and a phase that is 90 degrees different from the third mixer signal. Upconverts the signal to frequency and outputs it. The output adding unit T-OAU adds the outputs from the mixer TI-MIX and the mixer TQ-MIX to generate a transmission high-frequency signal for communication. The power amplifier PA amplifies the output from the output adding unit T-OAU.

  The clock pulse generator CPG, the loop switch L-SW, and the transmission / reception selector switch TR-SW are shared with the analog circuit R-AC. The output from the power amplifier PA is cut in a predetermined frequency region so that noise is not input to the analog circuit R-AC by the transmission / reception selector switch TR-SW. The high frequency signal HFS via the antenna ANT is also cut in a predetermined frequency region so that noise is not input to the power amplifier by the transmission / reception selector switch TR-SW. The signal component of the high-frequency signal for transmission that has passed through the transmission / reception selector switch TR-SW by the output from the power amplifier PA is transmitted to the outside via the antenna ANT.

(E) IQ correction test operation When calculating the correction coefficient II / QCUCC and the correction coefficient QI / QCUCC, the following operation is performed. In the present embodiment, this operation is referred to as an inter-IQ correction test operation. In this specification as a whole, the operation for calculating the correction coefficient for IQ correction based on the output from the calibration signal generation circuit I / QCU-CSG is referred to as the IQ correction test operation.

  The loop switch L-SW is turned ON. A calibration signal I-CS is output from the calibration signal generation circuit I / QCU-CSG to the DA converter I-DAC. The calibration signal Q-CS is output from the calibration signal generation circuit I / QCU-CSG to the DA converter Q-DAC. A / D conversion production operation is performed. As a result, it operates as follows.

  A calibration signal I-CS and a calibration signal Q-CS are output to the analog circuit T-AC. The calibration signal I-CS and the calibration signal Q-CS are subjected to various conversion processes by the analog circuit T-AC. Then, the results of various conversion processes are input from the output adding unit T-OAU to the analog circuit R-AC via the loop switch L-SW. This input is input to the mixer RI-MIX and the mixer RQ-MIX of the analog circuit R-AC, and various conversion processes are performed. As a result of the various conversion processes, the analog I signal R-IA is output to the AD converter I-ADC, and the analog Q signal R-QA is output to the AD converter Q-ADC. The AD converter I-ADC and AD converter Q-ADC perform an AD conversion actual operation, and output the digital I signal R-ID and the digital Q signal R-QD to the inter-IQ correction unit I / QCU. The inter-IQ correction unit I / QCU corrects the digital I signal R-ID and the digital Q signal R-QD, and calculates a correction coefficient II / QCUCC and a correction coefficient Q-I / QCUCC based on the correction result. .

(F) IQ correction actual operation Using the correction coefficient I-I / QCUCC and the correction coefficient Q-I / QCUCC obtained in the IQ correction test operation, the above-described gain, phase, and DC offset mismatch are detected. When detecting and correcting, it operates as follows. In this embodiment, the operation at this time is referred to as an inter-IQ correction actual operation. Throughout this specification, an operation for performing a digital correction process on a digital signal received from an AD converter and generating a corrected digital signal using the correction coefficient for IQ correction obtained in the test operation for IQ correction. Is the IQ correction actual operation.

  The loop switch L-SW is turned OFF. The calibration signal generation circuit I / QCU-CSG is disabled. A / D conversion production operation is performed. As a result, it operates as follows.

  Upon receiving the high frequency signal HFS via the antenna ANT, the analog circuit R-AC generates an analog I signal R-IA and an analog Q signal R-QA. The AD converter I-ADC receives the analog I signal R-IA and performs an AD conversion process to generate a digital I signal R-ID. The AD converter Q-ADC receives the analog Q signal R-QA and performs AD conversion processing to generate a digital Q signal R-QD. The inter-IQ correction unit I / QCU receives the digital I signal R-ID and the digital Q signal R-QD, detects the mismatch in gain, phase, and DC offset as described above, and performs digital correction processing. The mismatch is detected by using the correction coefficient II / QCUCC and the correction coefficient QI / QCUCC obtained during the IQ correction test operation. As a result, the inter-IQ correction unit I / QCU generates a correction digital I signal CID and a correction digital Q signal CQD. The digital processing unit DOU performs necessary digital processing on the corrected digital I signal CID and the corrected digital Q signal CQD to generate a baseband signal and transmits it to the baseband processing unit BBU. If digital processing is unnecessary, no digital processing is performed. In that case, the corrected digital I signal CID and the corrected digital Q signal CQD are demodulated baseband signals.

2. Operation of Communication System The operation of the communication system including the semiconductor integrated circuit device will be described with reference to FIG.

(1) Operation Sequence As an operation sequence, there are an initial sequence period ISP that occurs after activation of the communication system, a no-signal period NSP that occurs after the initial sequence period, and a received signal processing period RSP that occurs after the no-signal period. The repetition period, which is a set of the second no-signal period NSP2 and the received signal processing period RSP2, is repeated at a constant period.

  The initial sequence period ISP is a period for performing a reset operation of flip-flops in the communication system, a power-on process in the communication system, and a calibration process for canceling various offsets of each element circuit in the communication system. Circuits that perform typical calibration processing are an analog circuit R-AC and an analog circuit T-AC. The circuits for performing the calibration process are a low noise amplifier LNA, a filter I-FIL, a filter Q-FIL, a variable amplifier I-PGA, a variable amplifier Q-PGA, and a clock pulse generator CPG. In addition, circuits for performing the calibration process are a DA converter I-DAC, a DA converter Q-DAC, a low-pass filter I-LPF, a low-pass filter Q-LPF, and a power amplifier PA.

  The no-signal period NSP is a period during which the external high frequency signal HFS does not come.

  The received signal processing period (normal operation period) RSP is a period during which the external high-frequency signal HFS is down-converted and demodulated into a baseband signal.

(2) Operation mode The operation mode is determined by setting a value in the mode setting register MRES of the digital processing unit DOU by the baseband processing unit BBU. In each of the transmission / reception systems, the operation mode is set so that the I signal path and the Q signal path are the same.

  The operation modes include an ADC correction mode ADC-CM, an IQCU correction mode I / QCU-CM, and a received signal processing mode RSPM. The ADC correction mode ADC-CM is a mode for calculating a correction coefficient I-ADCCC and a correction coefficient Q-ADCCC which are correction coefficients for AD conversion processing. The IQCU correction mode I / QCU-CM is a mode for calculating a correction coefficient I-I / QCUCC and a correction coefficient Q-I / QCUCC, which are correction coefficients for the inter-IQ correction unit I / QCU. The reception signal processing mode RSPM is a mode in which a high-frequency signal HFS from the outside is down-converted and demodulated into a baseband signal.

  There are modes other than the operation modes described above, and those not applied to the operation modes described above are collectively referred to as other modes OM. In the other mode OM immediately after the communication system is activated, a flip-flop reset operation in the communication system and a power-on process in the communication system are executed.

  In the ADC correction mode ADC-CM, an AD conversion test operation is executed. In the IQCU correction mode I / QCU-CM, an AD conversion actual operation is executed and an IQ correction test operation is executed. In the received signal processing mode RSPM, the AD conversion actual operation is executed and the inter-IQ correction actual operation is executed.

  In the figure, the ADC correction mode ADC-CM is set in the initial sequence period ISP. Further, the ADC correction mode ADC-CM and the IQCU correction mode I / QCU-CM are set in the no-signal periods NSP and NSP2. In addition, the reception signal processing mode RSPM is set in the reception signal processing periods RSP and RSP2.

(3) Register The digital processing unit DOU includes a frequency setting register ADC-FSRES, a period setting register ADC-PSRES, a frequency setting register I / QC-FSRES, and a period setting register I / QC-PSRES.

  The frequency setting register ADC-FSRES can set whether or not there is an AD conversion test operation in the initial sequence period ISP. Furthermore, it is possible to set whether or not there is an AD conversion test operation for every non-signal period NSP, or whether or not there is an AD conversion test operation for every M non-signal periods NSP. Here, M is a natural number of 2 or more.

  The period setting register ADC-PSRES can set how long the AD conversion test operation is executed in the initial sequence period ISP. Further, it is possible to set how long the AD conversion test operation in the non-signal period NSP is executed.

  The frequency setting register I / QC-FSRES can set whether or not there is an IQ correction test operation in the initial sequence period ISP. Furthermore, it is possible to set whether there is an IQ correction test operation every non-signal period NSP or whether there is an IQ correction test operation every N non-signal periods. Here, N is a natural number of 2 or more.

  The period setting register I / QC-PSRES can set how long the inter-IQ correction test operation is executed in the initial sequence period ISP. Further, it is possible to set how long the IQ correction test operation in the non-signal period NSP is executed.

  When both the ADC correction mode ADC-CM and the IQCU correction mode I / QCU-CM are executed in the initial sequence period ISP, the ADC correction mode ADC-CM is always executed first. Thereafter, the IQCU correction mode I / QCU-CM is executed. Even in each non-signal period NSP, when both the ADC correction mode ADC-CM and the IQCU correction mode I / QCU-CM are executed, the ADC correction mode ADC-CM is always executed first. Thereafter, the IQCU correction mode I / QCU-CM is executed.

  The graph at the bottom of the figure is an example showing how the temperature or power supply voltage value changes with time, and the second graph from the bottom is the correction coefficient value or IQ for the AD converter. It is an example showing how the correction coefficient value for the interim correction unit I / QCU changes with time.

3. Digital Correction Unit for I and Q Signals The digital correction unit for I and Q signals in the semiconductor integrated circuit device will be described with reference to FIG.

(1) Configuration The digital correction unit DCUI & Q is a part surrounded by a chain line in FIG. The digital correction unit DCUI & Q includes a correction coefficient setting register I-ADCCCSRES and a digital correction unit I-DCU. The digital correction unit DCUI & Q includes a correction coefficient setting register Q-ADCCCSRES and a digital correction unit Q-DCU. Further, the digital correction unit DCUI & Q includes an error calculation unit ECU, a dither difference unit DDU, and a correction coefficient search unit ADC-CSU. The digital correction unit I-DCU receives an AD conversion unit output I-ADCCUO that is an output from the AD conversion unit I-ADCU. The digital correction unit I-DCU outputs a digital I signal R-ID by performing digital correction processing according to the correction coefficient I-ADCCC stored in the correction coefficient setting register I-ADCCCSRES. The digital correction unit Q-DCU receives an AD conversion unit output Q-ADCCUO which is an output from the AD conversion unit Q-ADCU. The digital correction unit Q-DCU outputs a digital Q signal R-QD by performing digital correction processing according to the correction coefficient Q-ADCCC stored in the correction coefficient setting register Q-ADCCCSRES. The error calculation unit ECU takes a difference in output between the digital correction unit I-DCU and the digital correction unit Q-DCU. The dither difference unit DDU outputs a conversion error e by subtracting 2α from the output from the error calculation unit ECU. The correction coefficient search unit ADC-CSU receives the conversion error e from the dither difference unit DDU. Then, the correction coefficient search unit ADC-CSU calculates the correction coefficient I-ADCCC and the correction coefficient Q-ADCCC by a predetermined algorithm such as an LMS algorithm according to the conversion error e.

(2) Digital correction processing The AD conversion unit output I-ADCUO from the AD conversion unit I-ADCU is set to Di. The correction coefficient I-ADCCC is set to Wi. At that time, a value like the following formula (1) is output from the digital correction unit I-DCU as a digital I signal R-ID. Here, i is 0 to N-1, and i represents a bit of a digital output signal such as an i-th AD converter output I-ADCCUO or an AD converter output Q-ADCCUO. N is a natural number of 2 or more and represents the number of bits.

  The AD conversion unit output Q-ADCCUO from the AD conversion unit Q-ADCU is set to Di. The correction coefficient Q-ADCCC is Ui. At that time, a value like the following formula (2) is output from the digital correction unit Q-DCU as a digital Q signal R-QD.

  In the following description, a digital output from the AD conversion unit I-ADCU or the AD conversion unit Q-ADCU is referred to as a digital output Di.

(3) AD conversion test operation The following operations are executed during the AD conversion test operation. The test signal ADC-TS is commonly input from the test input terminal TIT to the AD conversion unit I-ADCU and the AD conversion unit Q-ADCU. The digital correction unit I-DCU receives the digital output Di from the AD conversion unit I-ADCU. Then, the digital correction unit I-DCU performs a digital correction process according to the correction coefficient I-ADCCC stored in the correction coefficient setting register I-ADCCCSRES, thereby outputting a digital I signal R-ID to the error calculation unit ECU. The digital correction unit Q-DCU receives the digital output Di from the AD conversion unit Q-ADCU. Then, the digital correction unit Q-DCU performs digital correction processing according to the correction coefficient Q-ADCCC stored in the correction coefficient setting register Q-ADCCCSRES, and outputs a digital Q signal R-QD to the error calculation unit ECU. The error calculation unit ECU subtracts the digital Q signal R-QD from the digital I signal I-QD, and outputs the result to the dither difference unit DDU. The dither difference unit DDU subtracts 2α from the output from the error calculation unit ECU, and outputs the resulting conversion error e to the correction coefficient search unit ADC-CSU. Here, 2α = first dither signal Dither1−second dither signal Dither2. The correction coefficient search unit ADC-CSU calculates the correction coefficient I-ADCCC by a predetermined algorithm such as an LMS algorithm according to the conversion error e and the correction coefficient I-ADCCC. Here, the correction coefficient I-ADCCC is stored in advance in the correction coefficient setting register I-ADCCCCSRES (denoted as Wi in the figure). The correction coefficient search unit ADC-CSU calculates the correction coefficient Q-ADCCC by a predetermined algorithm such as an LMS algorithm according to the conversion error e and the correction coefficient Q-ADCCC. Here, the correction coefficient Q-ADCCC is stored in advance in the correction coefficient setting register Q-ADCCCSRES (denoted as Ui in the figure). The newly calculated correction coefficient I-ADCCC (denoted as Wi (NEW) in the figure) is newly stored in the correction coefficient setting register I-ADCCCCSRES. Also, the newly calculated correction coefficient Q-ADCCC (described as Ui (NEW) in the figure) is newly stored in the correction coefficient setting register Q-ADCCCSRES. Further, the next test signal ADC-TS is commonly input from the test input terminal TIT to the AD converter I-ADC and the AD converter Q-ADC. As a result, the value of the correction coefficient setting register I-ADCCCSRES and the value of the correction coefficient setting register Q-ADCCCSRES are updated. Such an update operation is repeated during the AD conversion test operation.

(4) AD conversion production operation The following operations are executed during the AD conversion production operation. An analog I signal R-IA from the analog circuit R-AC is input to the AD converter I-ADC, and an analog Q signal R-QA is input to the AD converter Q-ADC. An AD conversion unit output I-ADCCUO (digital output Di) is output from the AD conversion unit I-ADCU, and an AD conversion unit output Q-ADCCUO (digital output Di) is output from the AD conversion unit Q-ADCU. The digital correction unit I-DCU receives the digital output Di from the AD conversion unit I-ADCU. The digital correction unit I-DCU outputs a digital I signal R-ID to the inter-IQ correction unit I / QCU by performing digital correction processing according to the correction coefficient I-ADCCC. The correction coefficient I-ADCCC is obtained during the AD conversion test operation and is stored in the correction coefficient setting register I-ADCCCCSRES. The digital correction unit Q-DCU receives the digital output Di from the AD conversion unit Q-ADCU. The digital correction unit Q-DCU outputs a digital Q signal R-QD to the inter-IQ correction unit I / QCU by performing digital correction processing according to the correction coefficient Q-ADCCC. The correction coefficient Q-ADCCC is obtained in the AD conversion test operation and is stored in the correction coefficient setting register Q-ADCCCSRES.

  In FIG. 7, an area 71 surrounded by an alternate long and short dash line is an area that does not operate during the AD conversion actual operation and operates only during the AD conversion test operation.

4). Inter-IQ Correction Unit The inter-IQ correction unit in the semiconductor integrated circuit device will be described with reference to FIG.

(1) Configuration The inter-IQ correction unit I / QCU is a portion surrounded by a one-dot chain line in FIG. The inter-IQ correction unit I / QCU includes a correction coefficient setting register I / QCUCCRES, a digital correction unit II / QCU, a correction coefficient setting register QI / QCUCCRES, a digital correction unit QI / QCU, and a correction coefficient search unit. I / QCU-CSU. The digital correction unit II / QDCU performs digital correction processing on the digital I signal R-ID and the digital Q signal R-QD in accordance with the correction coefficient II / QCUCC, and outputs a corrected digital I signal CID. The correction coefficient II / QCUCC is stored in the correction coefficient setting register II / QCUCSRES. The digital I signal R-ID is a signal from the AD converter I-ADC. The digital Q signal R-QD is a signal from the AD converter Q-ADC. The digital correction unit Q-I / QDCU performs digital correction processing on the digital I signal R-ID and the digital Q signal R-QD according to the correction coefficient Q-I / QCUCC, and outputs a corrected digital Q signal CQD. The correction coefficient Q-I / QCUCC is stored in the correction coefficient setting register Q-I / QCUCCRES. The digital I signal R-ID is a signal from the AD converter I-ADC. The digital Q signal R-QD is a signal from the AD converter Q-ADC. The correction coefficient search unit I / QCU-CSU searches for the correction coefficient I-I / QCUCC and the correction coefficient Q-I / QCUCC by a predetermined algorithm such as an LMS algorithm according to the correction digital I signal CID and the correction digital Q signal CQD. . The correction digital I signal CID is a signal from the digital correction unit II / QCU. The correction digital Q signal CQD is a signal from the digital correction unit Q-I / QDCU.

  By the digital correction processing of the digital correction unit I / I / QDCU, detection of the mismatch of gain, phase, or DC offset with respect to the digital Q signal R-QD of the digital I signal R-ID and correction are executed. Here, the mismatch in gain, phase or DC offset is caused by the path from the mixer RI-MIX to the variable amplifier I-PGA and the path from the mixer RQ-MIX to the variable amplifier Q-PGA in the analog circuit R-AC. It is. By the digital correction processing of the digital correction unit Q-I / QDCU, detection of the mismatch of gain, phase or DC offset with respect to the digital I signal R-ID of the digital Q signal R-QD and correction are executed. Here, this is caused by the path from the mixer RI-MIX to the variable amplifier I-PGA and the path from the mixer RQ-MIX to the variable amplifier Q-PGA in the analog circuit R-AC.

(2) Digital correction processing The digital correction unit II / QDCU performs digital correction processing on the digital I signal R-ID and the digital Q signal R-QD in accordance with the correction coefficient II / QCUCC to obtain a corrected digital I signal. Output CID.

  The digital correction unit Q-I / QDCU performs digital correction processing on the digital I signal R-ID and the digital Q signal R-QD according to the correction coefficient Q-I / QCUCC, and outputs a corrected digital Q signal CQD.

  Here, the digital I signal R-ID, the digital Q signal R-QD, the corrected digital I signal CID, and the corrected digital Q signal CQD have the relationship of the following expression (3).

Here, H ₁₁ and H ₂₂ are values close to 1, and are coefficients for correcting an amplitude mismatch between the digital I signal R-ID and the digital Q signal R-QD. H ₁₂ and H ₂₁ are values close to 0 and are coefficients for correcting a phase mismatch between the digital I signal R-ID and the digital Q signal R-QD. kI and kQ are coefficients for removing DC offsets of the digital I signal R-ID and the digital Q signal R-QD, respectively.

(3) IQ correction test operation The following operations are executed during the IQ correction test operation. Also, during the IQ correction test operation, the AD conversion actual operation is executed.

  The digital correction unit II / QCU performs digital correction processing on the digital I signal R-ID from the AD converter I-ADC and the digital Q signal R-QD from the AD converter Q-ADC. Here, the digital correction processing is performed according to correction coefficients II / QCUCC (denoted as H11, H12, and kI in the figure) stored in the correction coefficient setting register II / QCUCCRES. Then, the digital correction unit II / QDCU outputs the correction digital I signal CID to the correction coefficient search unit I / QCU-CSU.

  The digital correction unit Q-I / QDCU performs digital correction processing on the digital I signal R-ID from the AD converter I-ADC and the digital Q signal R-QD from the AD converter Q-ADC. Here, the digital correction processing is performed in accordance with correction coefficients QI / QCUCC (denoted as H21, H22, and kQ in the figure) stored in the correction coefficient setting register QI / QCUCCSRS. Then, the digital correction unit Q-I / QDCU outputs the corrected digital Q signal CQD to the correction coefficient search unit I / QCU-CSU.

  The correction coefficient search unit I / QCU-CSU searches for the correction coefficient II / QCUCC and the correction coefficient QI / QCUCC by a predetermined algorithm such as an LMS algorithm. Here, the search includes a correction digital I signal CID from the digital correction unit II / QDCU, a correction digital Q signal CQD from the digital correction unit QI / QCU, a correction coefficient II / QCUCC, and a correction. This is done according to the factor Q-I / QCCUCC. The correction coefficient II / QCUCC used for the search is previously stored in the correction coefficient setting register II / QCUCCRES. Further, the correction coefficient QI / QCUCC used for the search is previously stored in the correction coefficient setting register QI / QCUCCRES. The searched correction coefficient II / QCUCC (denoted as H11, H12, kI (New) in the figure) is newly stored in the correction coefficient setting register II / QCUCCRES. Further, the correction coefficient Q-I / QCCUCC (denoted as H21, H22, kQ (New) in the figure) is newly stored in the correction coefficient setting register Q-I / QCUCCRES.

  Next, the digital I signal R-ID and the digital Q signal R-QD are input to the digital correction unit II / QCU and the digital correction unit QI / QCU. As a result, the values of the correction coefficient setting register Q-I / QCUCCRES and the correction coefficient setting register Q-I / QCUCCRES are updated. Such an update operation is repeated during the IQ correction test operation.

(4) IQ correction actual operation The following operations are executed during the IQ correction actual operation. Further, the AD conversion actual operation is executed during the IQ correction actual operation.

  The digital correction unit II / QCU performs digital correction processing on the digital I signal R-ID from the AD converter I-ADC and the digital Q signal R-QD from the AD converter Q-ADC. Here, the digital correction process is performed in accordance with the correction coefficient II / QCUCC obtained in the IQ correction test operation and stored in the correction coefficient setting register II / QCUCCRES. Then, the digital correction unit II / QDCU outputs the corrected digital I signal CID to the inside of the digital processing unit DOU, and the digital processing unit DOU outputs the baseband signal to the baseband processing unit BBU.

  The digital correction unit Q-I / QDCU performs digital correction processing on the digital I signal R-ID from the AD converter I-ADC and the digital Q signal R-QD from the AD converter Q-ADC. Here, the digital correction processing is performed in accordance with the correction coefficient Q-I / QCUCC which is obtained during the IQ correction test operation and stored in the correction coefficient setting register Q-I / QCUCCRES. The digital correction unit Q-I / QDCU outputs a corrected digital Q signal CQD inside the digital processing unit DOU. Then, the digital processing unit DOU outputs the baseband signal to the baseband processing unit BBU.

5. Summary According to one aspect of the present embodiment, the following operational effects can be obtained.

  (1) ADC correction mode In ADC-CM (first mode), the test signal ADC- is commonly used for the AD converter I-ADC (first AD converter) and the AD converter Q-ADC (second AD converter). By inputting TS (first test signal), a correction coefficient I-ADCCC (first correction coefficient) and a correction coefficient Q-ADCCC (second correction coefficient) are calculated. Here, the ADC correction mode (first mode) corresponds to the first mode in the foreground correction. Further, in the IQ correction mode I / QCU-CM (third mode) or the received signal processing mode RSPM (second mode), the correction coefficient I-ADCCC (first mode) obtained in the ADC correction mode ADC-CM (first mode). By performing digital correction processing using one correction coefficient), the AD converter I-ADC (first AD converter) performs AD conversion processing on the analog I signal R-IA (first analog signal), and the digital I signal R -Output ID (first digital signal). Here, the received signal processing mode (second mode) corresponds to the second mode in the foreground correction. Similarly, in the IQ correction mode I / QCU-CM (third mode) or the received signal processing mode RSPM (second mode), the correction coefficient Q-ADCCC (first mode) obtained in the ADC correction mode ADC-CM (first mode) By performing digital correction processing using the two correction coefficients, the AD converter Q-ADC (second AD converter) performs AD conversion processing on the analog Q signal R-QA (second analog signal), and the digital Q signal R -Output QD (second digital signal). Here, mode information including the first mode, the second mode, and the third mode is stored in the mode setting information storage circuit (mode setting register MRES).

  By having the configuration or function of (1), the AD converter I-ADC (first conversion circuit) and the AD converter Q-ADC (second conversion circuit) are in the ADC correction mode (first mode) ADC-CM. Is used to calculate a correction coefficient I-ADCCC (first correction coefficient) and a correction coefficient Q-ADCCC (second correction coefficient). Similarly, the AD converter I-ADC (first AD converter) and the AD converter Q-ADC (second AD converter) are IQ correction mode I / QCU-CM (third mode) or received signal processing mode RSPM (first In the second mode, the analog I signal R-IA (first analog signal) and the analog Q signal R-QA (second analog signal) are used for AD conversion operation. Therefore, it becomes unnecessary to obtain the correction coefficient I-ADCCC (first correction coefficient) and the correction coefficient Q-ADCCC (second correction coefficient) with an additional circuit having a large area, thereby reducing the area of the semiconductor integrated circuit device. Further, since there is no additional circuit with a large area, the additional circuit with a large area does not operate in the ADC correction mode ADC-CM (first mode), so that power consumption can be reduced.

  (2) In the configuration or function of (1) above, in the ADC correction mode ADC-CM (first mode), the first dither signal Dither1 (for the AD converter I-ADC (first AD converter)) The first predetermined voltage) is input, and the second dither signal Dither2 (second predetermined voltage) is input to the AD converter Q-ADC (second AD converter).

  By having the configuration or function of (2) above, in the ADC correction mode ADC-CM (first mode) by the first dither signal Dither1 (first predetermined voltage) and the second dither signal Dither2 (second predetermined voltage), The upper bits of the correction coefficient I-ADCCC (first correction coefficient) and the correction coefficient Q-ADCCC (second correction coefficient) are searched from different states. Therefore, the correction coefficient I-ADCCC (first correction coefficient) and the correction coefficient Q-ADCCC (second correction coefficient) can be reliably and quickly searched.

  (3) The configuration or function of (1) above, in the ADC correction mode ADC-CM (first mode), the output from the AD converter I-ADC (first AD converter) and the AD converter Q- Based on the conversion error e (difference output) based on the difference from the output from the ADC (second converter), the correction coefficient I-ADCCC (first correction coefficient) and the correction coefficient Q-ADCCC (second correction coefficient) Is calculated.

  By having the configuration or function of (3) above, in the ADC correction mode ADC-CM (first mode), the output from the AD converter I-ADC (first AD converter) and the AD converter Q-ADC ( Based on the conversion error e (difference output) based on the difference from the output from the second AD converter), the correction coefficient I-ADCCC (first correction coefficient) and the correction coefficient Q-ADCCC (second correction coefficient) are Both are calculated. Both the correction coefficient I-ADCCC (first correction coefficient) and the correction coefficient Q-ADCCC (second correction coefficient) are obtained based on the common conversion error e (difference output). The correction coefficient I-ADCCC (first correction coefficient) and the correction coefficient Q-ADCCC (second correction coefficient) in the IQ correction mode I / QCU-CM (third mode) or the received signal processing mode RSPM (second mode) The AD converter I-ADC (first converter) and the AD converter Q-ADC (second converter) execute an AD conversion operation. Both the correction coefficient I-ADCCC (first correction coefficient) and the correction coefficient Q-ADCCC (second correction coefficient) are obtained based on the common conversion error e (difference output), and the correction coefficient I thus obtained is calculated. Since the ADCCC (first correction coefficient) and the correction coefficient Q-ADCCC (second correction coefficient) are used, the output of the AD converter I-ADC (first AD converter) and the AD converter Q-ADC (first The conversion gain mismatch with the output of the two AD converters is reduced.

  Here, a problem when there is a conversion gain mismatch will be described. In the orthogonal modulation method, data is modulated into both an I signal and a Q signal. The demodulator performs a predetermined digital operation by combining the I signal and the Q signal. At this time, if the amplitudes of the I signal and the Q signal are deviated from each other, the amplitude of the demodulated waveform obtained after the above combination calculation is small (generally, “eye opening degree is small”). Here, the magnitude of the amplitude corresponds to the gain. The demodulated waveform is an analog waveform that is still expressed in multiple bits at this stage. Even when the phase shift amount and the DC offset voltage application amount are shifted from each other between the I signal and the Q signal, the eye opening degree is similarly reduced. Determination of demodulated data is performed by determining whether the value is positive or negative at the timing when the demodulated waveform has the maximum amplitude. Therefore, if the amplitude of the demodulated waveform is small, the sign of the value is reversed when there is noise of an opposite sign having a larger absolute value than that, resulting in erroneous determination of data. Therefore, it is necessary to reduce the conversion gain mismatch in order to avoid erroneous determination of this data.

  When the ADCs shown in FIGS. 1 to 4 are applied to the AD converter I-ADC and the AD converter Q-ADC, a conversion error e is generated between the I signal AD converter and the Q signal AD converter. In the meantime, the conversion gain mismatch becomes large. The reason is that the circuit for calculating the conversion error e by the AD converter for I signal and the circuit for calculating the conversion error e by the AD converter for Q signal are completely separate circuits. It is. Note that the ADC of Reference FIG. 1 or Reference FIG. 2 has a small conversion gain error because there are RADCU and RDACCU with high absolute accuracy. However, an increase in area, power consumption, design man-hours, and costs associated with mounting RADCU and RDACCU are inevitable. The ADCs in FIGS. 3 and 4 do not have a circuit corresponding to RADCU or RDACCU with high absolute accuracy. Therefore, particularly when the ADC as shown in FIG. 3 and FIG. 4 is applied to the AD converter I-ADC and the AD converter Q-ADC, the conversion error e is an I signal AD converter and a Q signal AD converter. And the conversion gain mismatch becomes large.

  Note that if the correction between the I signal and the Q signal as performed in the inter-IQ correction unit I / QCU is performed, the amplitude of the demodulated waveform becomes sufficiently large, and erroneous determination of data is less likely to occur.

  According to another aspect of the present embodiment, the following effects can be obtained.

  (4) An analog circuit R-AC that receives the high-frequency signal HFS and generates an analog I signal R-IA (first analog signal) and an analog Q signal R-QA (second analog signal); and an analog I signal R-IA First AD converter (corresponding to AD converter I-ADC) that performs AD conversion processing by receiving and digitally correcting and generating digital I signal R-ID, and receiving analog Q signal R-QA and AD converting A second AD converter (corresponding to the AD converter Q-ADC) that generates a digital Q signal R-QD by performing processing; The first AD converter and the second AD converter perform foreground correction. The execution period of the first mode of foreground correction is the same for the first AD converter and the second AD converter. In addition, the execution period of the second mode of foreground correction is the same for the first AD converter and the second AD converter.

  By having the configuration or function of (4), there are the following advantages. The first AD converter and the second AD converter perform conversion processing on the analog I signal R-IA and the analog Q signal R-QA obtained by converting one high-frequency signal HFS by the analog circuit R-AC. To do. Therefore, the execution period of the first mode may be the same for the first AD converter and the second D converter, and the execution period of the second mode may be the same for the first AD converter and the second D converter. Absent. The first AD converter and the second D converter have the same execution period of the first mode, and the execution period of the second mode is also the same, so that the setting sequence of the first mode and the second mode is common. Easy to do. Furthermore, AD conversion correction coefficients in the first mode and AD conversion processing in the second mode can be effectively performed.

  There is a temperature sensor AD converter for signal processing from the temperature sensor and a wireless communication AD converter for signals from the wireless communication antenna, and each of the temperature sensor AD converter and the wireless communication AD converter is digitally corrected. Consider a case where there is a semiconductor integrated circuit device that performs AD conversion processing by performing processing and performs foreground correction. Since the signal from the temperature sensor and the signal from the wireless communication antenna operate independently from each other, the timing at which the AD converter for the temperature sensor performs AD conversion processing on the signal from the temperature sensor, and the AD converter for wireless communication However, the timing at which AD conversion processing is performed on the signal from the wireless communication antenna is completely different. Therefore, the first mode and the second mode are completely different between the temperature sensor AD converter and the wireless communication AD converter. In the case of the configuration or function (4), the analog circuit R-AC generates the analog I signal R-IA and the analog Q signal R-QA from one high-frequency signal HFS. It can be the same between one AD converter and the second AD converter.

  When the configuration or function of (1) is combined with the configuration or function of (4), there are the following advantages. Since the first mode is the same between the AD converter I-ADC and the AD converter Q-ADC, the test signal ADC- is shared by the AD converter I-ADC and the AD converter Q-ADC in the first mode. TS can be input. When the first mode and the second mode are different between the AD converter I-ADC and the AD converter Q-ADC, the first mode is common to the AD converter I-ADC and the AD converter Q-ADC. When the test signal ADC-TS is inputted to either of them, either one of the AD converters cannot operate in the second mode.

  When the configuration or function of (1) is combined with the configuration or function of (4), there are the following merits. Since the first mode is the same between the AD converter I-ADC (first AD converter) and the AD converter Q-ADC (second AD converter), the AD converter I-ADC in the first mode. And a correction coefficient I-ADCCC (first correction coefficient) and a correction coefficient Q-ADCCC (second correction coefficient) are calculated based on a conversion error e based on a difference from the output of the AD converter and the output of the AD converter Q-ADC. Can be done. When the first mode and the second mode are different between the AD converter I-ADC and the AD converter Q-ADC, the difference from the output of the AD converter I-ADC and the output of the AD converter Q-ADC. It is impossible to obtain the conversion error e based on

  (5) In the configuration or function of (4) above, after the AD conversion correction coefficients of the first and second AD converters are obtained in the first mode, the IQ correction mode I / QC-CM (first In the three modes, the correction coefficient for IQ correction is calculated as follows. The IQ correction unit I / QCU (digital error correction circuit) receives the digital I signal R-ID (first digital signal) from the first AD converter operating in the second mode, and receives the digital Q signal R-QD ( The second digital signal) is received from the second AD converter operating in the second mode, so that the digital I signal R-ID (first digital signal) and the digital Q signal R-QD (second digital signal) are received. By performing digital correction processing, the correction coefficient II / QCUCC (third correction coefficient) and the correction coefficient QI / QCUCC (fourth correction coefficient) are calculated.

  By having the configuration or function of (5), there are the following merits. Since the AD conversion correction coefficient is obtained in the first mode, the AD converter correction coefficient optimum for the first and second AD converters can be used in the second mode. Therefore, in the IQ correction mode I / QC-CM (third mode), since the outputs of the first and second AD converters are optimized, the correction coefficient II / QCUCC (third correction coefficient) and The correction coefficient QI / QCUCC (fourth correction coefficient) can be obtained more correctly.

  (6) In the configuration or function of (4), the first and second AD converters are configured to be operable in the first mode in the initial sequence period, and the first and second AD converters are configured in the first signal period. The second AD converter is configured to be operable in the first mode. The reception signal period (normal operation period) and the no-signal period are alternately repeated periodically. The period of operation in the first mode is also referred to as the first test operation period.

  Satisfying the configuration (6) or function has the following advantages. In the initial sequence period, the first and second AD converters operate in the first mode, whereby AD conversion correction coefficients reflecting static variations such as process variations can be acquired. Even during the no-signal period, the first and second AD converters operate in the first mode, and as shown in FIG. 6, the optimal AD conversion correction coefficient that follows fluctuations in temperature and power supply voltage is acquired. it can.

  (7) The configuration or function of (4) above, wherein the inter-IQ correction unit I / QCU (digital error correction circuit) operates in the IQ correction mode I / QC-CM (third mode) in the initial sequence period. The inter-IQ correction unit I / QCU (digital error correction circuit) is configured to be operable in the IQ correction mode I / QC-CM (third mode) even in the no-signal period. The reception signal period (normal operation period) and the no-signal period are alternately repeated periodically. The period of operation in the third mode is also referred to as the second test operation period.

  By having the configuration or function of (7), there are the following merits. Correction that reflects static variation such as process variation by the inter-IQ correction unit I / QCU (digital error correction circuit) operating in the IQ correction mode I / QC-CM (third mode) during the initial sequence period A coefficient I-ADCCC (first correction coefficient) and a correction coefficient Q-ADCCC (second correction coefficient) can be acquired. Even during the no-signal period, the inter-IQ correction unit I / QCU (digital error correction circuit) operates in the IQ correction mode I / QC-CM (third mode). An optimum correction coefficient I-ADCCC and correction coefficient Q-ADCCC following the voltage fluctuation can be acquired.

  (8) In the configuration or function of (4) and (6), the frequency setting register ADC-FSRES and the period setting register ADC-PSRES are provided.

  By having the configuration or function of (8), there are the following merits. By setting the frequency setting register ADC-FSRES and the period setting register ADC-PSRES in accordance with the characteristics of a communication system such as a mobile phone incorporating a baseband unit BBU, a semiconductor integrated circuit device RFIC, and an antenna ANT, The AD conversion correction coefficient can be obtained with appropriate accuracy and power consumption.

  (9) In the configuration or function of the above (4) and (7), a frequency setting register I / QC-FSRES and a period setting register I / QC-PSRES are provided.

  By having the configuration or function of (9), there are the following merits. By setting the frequency setting register I / QC-FSRES and the period setting register I / QC-PSRES in accordance with the characteristics of the communication system such as a mobile phone incorporating the baseband unit BBU, the semiconductor integrated circuit device RFIC, and the antenna ANT. The correction coefficient II / QCUCC (third correction coefficient) and the correction coefficient QI / QCUCC (fourth correction coefficient) can be obtained with appropriate accuracy and power consumption suitable for the communication system. The frequency setting register ADC-FSRES, the period setting register ADC-PSRES, the frequency setting register I / QC-FSRES, and the period setting register I / QC-PSRES are collectively referred to as a period setting storage circuit.

6). AD converter (Example 1)
FIG. 9 shows a charge share type AD converter as an example of the AD converter I-ADCU and AD converter Q-ADCU of the present embodiment.

  In the present embodiment, the communication system handles single-phase signals, but there is no problem even as a communication system handling differential signals. The AD conversion unit CS-ADCU (area surrounded by a chain line) shown in the figure is based on the premise that the communication system of this embodiment handles differential signals, and each element circuit performs differential input / output. It has become.

(1) Configuration The AD conversion unit CS-ADCU includes a switch NP-SW, a capacitor NP-SHC, and a switch NP-CSSW. Further, the AD conversion unit CS-ADCU includes a switch RP-SW, a capacitor RP-SHC, and a switch RP-CSSW. Further, the AD conversion unit CS-ADCU includes a comparator CS-CMP, a control unit CS-CTRL, and a bit cell BCell. The AD converter CS-ADCU receives one of the outputs of the variable amplifier I-PGA and the variable amplifier Q-PGA. The AD conversion unit CS-ADCU receives a reception analog differential signal composed of an analog signal NP-RA and an analog signal RP-RA in an inverted relationship with the analog signal NP-RA. Here, the analog signal NP-RA is one of a non-inverted signal output from the variable amplifier I-PGA and a non-inverted signal output from the variable amplifier Q-PGA. The analog signal RP-RA is one of an inverted signal of the output of the variable amplifier I-PGA and an inverted signal of the output of the variable amplifier Q-PGA.

  Switch NP-SW receives analog signal NP-RA. Switch RP-SW receives analog signal RP-RA. The capacitor NP-SHC samples and holds the analog signal NP-RA. The capacitor RP-SHC samples and holds the analog signal RP-RA. A switch NP-CSW for sharing charge between the capacitor NP-SHC and the bit cell BCell is connected to the capacitor NP-SHC. A switch RP-CSW for sharing charge between the capacitor RP-SHC and the bit cell BCell is connected to the capacitor RP-SHC.

  A node NPCS-N is provided between the non-inverting input terminal of the comparator CS-CMP and the capacitor NP-SHC. A node RPCS-N is provided between the inverting input terminal of the comparator CS-CMP and the capacitor RP-SHC. Comparator CS-CMP compares the voltage between node NPCS-N and node RPCS-N.

  The control unit CS-CTRL receives the comparison result of the comparator CS-CMP, generates a digital output Di of the AD conversion unit CS-ADCU, outputs it to the digital correction unit DCUI & Q, and controls the bit cell BCell.

The bit cell BCell is a portion surrounded by a one-dot chain line in the figure, and has a bit cell of 1 for the number of bits of the digital output Di. That is, the bit cell BCell has a dither signal bit cell DBCell and bit cells (other bit cells) corresponding to the number of bits of the digital output Di. The dither signal bit cell DBCell has a capacitance C _alpha for the dither signal, a switch CA-SW1, a switch CA-SW2, a switch DC-SW3. Further, the dither signal bit cell DBCell includes two switches SW4a and SW4b and two switches SW5a and SW5b. The connection relationship is as shown in FIG. Capacitance value of the dither signal capacitors C _alpha has a capacitance value in accordance with a voltage value to be applied at the dither signal.

The other bit cells have N cells, and the structure is basically the same as that of the dither signal bit cell DBCell, except that the switch DC-SW3 is not provided. Furthermore there is a bit cell capacitor Ci in place of the dither signal capacitors C _alpha, the bit cell capacitance Ci satisfies the following relationship.
(Ii) 0 ≦ k ≦ N−1, k is 0 or a natural number, N is a natural number greater than or equal to 2 (b) The capacity value of the bit cell capacity C _{k + 1} of the (k + 1) th bit cell is equal to the bit cell capacity C _k of the _kth bit cell. Double the capacity value The N−1th bit cell BCell corresponding to the maximum bit of the digital output Di is the maximum bit cell MSBCell, and the 0th bit cell BCell corresponding to the minimum bit is the minimum bit cell LSBCell. . The bit cell BCell is supplied with the ground voltage GND and the power supply voltage VDD.

(2) Operation (a) AD conversion test operation The operation when the AD conversion test operation is executed will be described below.

  At the first timing, the analog signal NP-RA and the analog signal RP-RA are sampled in the capacitor NP-SHC and the capacitor RP-SHC, respectively. Then, the switch CA-SW1 and the switch CA-SW2 are turned ON in order to charge the bit cell capacitance Ci of all the bit cells BCell with the electric charge corresponding to between the power supply voltage VDD and the ground voltage GND.

At a second timing after the first timing, the switch NP-SW, the switch RP-SW, and the switch CA-SW1 and the switch CA-SW2 of the dither signal bit cell DBCell are turned off. Then, the switch NP-CSSW, the switch RP-CSSW, and the switch SW4a and the switch SW4b of the dither signal bit cell DBCell are turned ON. This ON, the OFF control, to connect the one ends and capacity NP-SHC dither signal capacitors C _alpha to the node NPCs-N. To connect the one end of the other end and the capacitance RP-SHC dither signal capacitors C _alpha to the node RPCS-N. Thereby, the charge in the charge the capacitor NP-SHC dither signal within the capacity C _alpha is charge distribution is charge share to the node NPCs-N. The charge of the charge and the capacitance RP-SHC dither signal within the capacity C _alpha is charge distribution in the charge sharing by the node RPCS-N. The voltage of node NPCS-N to which charge has been distributed is compared with the voltage of node RPCS-N to which charge has been distributed by comparator CS-CMP. For example, the comparator CS-CMP outputs 1 if the comparison result is positive and outputs 0 if the comparison result is negative. Based on the comparison result, the control unit CS-CTRL determines the (N−1) th digital output _DN−1 that is the maximum bit.

At the third timing after the second timing, the switch of the maximum bit cell MSBCell is controlled based on the digital output _DN-1 . When _DN-1 is 1, the switches SW5a and SW5b are turned ON. As a result, the charge amount in the bit cell capacity CN _-1 of the maximum bit cell MSBCell is subtracted from the charge amount of the node NPCS-N. Further, the charge amount in the bit cell capacitor CN _-1 of the maximum bit cell MSBCell is subtracted from the charge amount of the node RPCS-N. When _DN-1 is 0, the switches SW4a and SW4b are turned ON. As a result, the amount of charge in the bit cell capacity Ci of the maximum bit cell MSBCell is added to the node NPCS-N. Further, the charge amount in the bit cell capacity CN _-1 of the maximum bit cell MSBCell is added to the node RPCS-N. As a result, charge distribution is performed at the node NPCS-N, and charge distribution is performed at the node RPCS-N. The voltage of node NPCS-N to which charge is distributed and the voltage of node RPCS-N to which charge is distributed are compared by comparator CS-CMP. For example, the comparator CS-CMP outputs 1 if the comparison result is positive and outputs 0 if the comparison result is negative. Based on the comparison result, the control unit CS-CTRL determines the (N−2) th digital output _DN−2 .

Hereinafter by repeating these operations to determine to digital output D _0.

  When the dither voltage to be applied is to be inverted (when the second dither signal Dither2 is applied), the switch SW4a and the switch SW4b of the dither signal bit cell DBCell may be turned ON at the second timing.

(B) AD conversion production operation The operation during the AD conversion production operation is basically the same as that during the AD conversion test operation. However, since the dither signal bit cell DBCell is not used, the switch CA-SW2 and the switch DC-SW3 are turned on. Operate as is.

  By operating in this way, the AD conversion operation is performed with the dither signal component superimposed in the AD conversion test operation, and the AD conversion operation is performed without the dither signal component in the AD conversion actual operation.

(3) Summary Since it is a successive approximation ADCU, low power consumption of several mW or less is possible at 50 MS / s or less. Unlike the charge redistribution type ADCU (second embodiment) described later, since the frequency of access to the reference voltage is low, there is an advantage that generation of the reference voltage can be facilitated.

7). AD converter (Example 2)
FIG. 10 shows a charge redistribution AD converter that is an example of the AD converter I-ADCU and the AD converter Q-ADCU according to the present embodiment.

(1) Configuration The AD conversion unit CRD-ADCU includes a switch CS-SW, N + 2 bit cells BCell2, a comparator CRD-CMP, and a control unit CRD-CTRL. It is configured to receive one of the outputs of the variable amplifier I-PGA and the variable amplifier Q-PGA, and receives the analog signal RA. Here, the analog signal RA represents one of the analog I signal R-IA and the analog Q signal R-QA. The switch CS-SW selects whether or not the ground voltage GND is supplied to the bit cell capacitance Ci of each bit cell BCell via the charge holding node CH-N. The comparator CRD-CMP compares the voltage of the charge holding node CH-N connected to each bit cell BCell with the ground voltage GND voltage. The control unit CRD-CTRL performs digital output based on the comparison result of the comparator CRD-CMP. Determine Di. And it outputs to digital correction part DCUI & Q, and controls each bit cell BCell.

Each bit cell BCell is as follows. Dither signal bit cell DBCell2 has a dither signal capacitors C _alpha and the first switch CRD-SW1 and the second switch CRD-SW2 and the third switch CRD-SW3. The capacitance C _alpha for the dither signal is a predetermined capacitance value, and is for producing a voltage value of alpha corresponding to the dither signal. The first switch CRD-SW1 selects whether through a positive reference voltage + _{V R.} The second switch CRD-SW2 selects whether through a negative reference voltage -V _R. The third switch CRD-SW3 selects whether or not the ground voltage GND is passed.

  The connection relationship between the switches and capacitors of the dither signal bit cell DBCell2 is as shown in FIG.

The structure of the other bit cell BCell2 is basically the same as that of the dither signal bit cell DBCell2, except for the following points. Respect third switch CRD-SW3, in the dither signal bit cell DBCell2, provided the ground voltage GND as a switch for selecting whether or not the dither signal capacitors C _alpha receives. However, the other bit cell BCell is provided as a switch for selecting whether or not the bit cell capacitor Ci receives the received analog signal RA. Furthermore there is a bit cell capacitor Ci in place of the dither signal capacitors C _alpha, the bit cell capacitance Ci satisfies the following relationship.
(Ii) 0 ≦ k ≦ N−1, k is 0 or a natural number, N is a natural number greater than or equal to 2 (b) The capacity value of the bit cell capacity C _{k + 1} of the (k + 1) th bit cell is equal to the bit cell capacity C _k of the _kth bit cell. Double the capacity value The bit cell corresponding to the maximum bit of the digital output Di is the maximum bit cell MSBCell2, and there are two bit cells corresponding to the minimum bit, respectively for the first minimum bit cell LSB1Cell and the second minimum bit This is the cell LSB2Cell.

  Unlike the other bit cell BCell2, the second minimum bit cell LSB2Cell does not have the second switch CRD-SW2.

(2) Operation (a) AD conversion test operation The operation when the AD conversion test operation is executed will be described below.

The switch CS-SW and the third switch CRD-SW3 are turned on for all the bit cells BCell at the first timing. Thereafter, while sampling the received analog signal RA to the charge holding node CH-N, applies the ground voltage GND to the capacitor dither signal C _alpha.

At the second timing after the first timing, the switch CS-SW and the third switch CRD-SW3 are turned OFF. Thereafter, the first switch CRD-SW1 of the maximum bit cell MSBCell2 is turned ON, and the second switches CRD-SW2 of the remaining bit cells BCell2 are turned ON. The voltage obtained by adding the voltage corresponding to the analog signal RA and the voltage corresponding to the dither signal to the charge holding node CH-N and subtracting the voltage corresponding to the maximum bit cell MSBCell2 is generated. The sign of this voltage is determined by the comparator CRD-CMP. As a result, the control unit CRD-CTRL determines that the maximum bit of the digital output Di is digital output D _N-1 = 0 if positive, and digital output D _N-1 = 1 if negative.

At the third timing after the second timing, when the digital output D _N-1 = 1, the control unit CRD-CTRL controls the first switch CRD-SW1 of the maximum bit cell MSBCell2 while being ON. When the digital output D _N−1 = 0, the first switch CRD-SW1 of the maximum bit cell MSBCell2 is turned OFF, and the second switch CRD-SW2 of the maximum bit cell MSBCell2 is turned ON. Next, the second switch CRD-SW2 is turned off while the first switch CRD-SW1 of the N-2th bit cell BCell2 is turned on. The comparator CRD-CMP determines the sign of the voltage generated at the charge holding node CH-N. As a result, the control unit CRD-CTRL determines that the second bit from the top of the digital output Di is digital output D _N−2 = 0 if positive, and digital output D _N−2 = 1 if negative. Thereafter, the digital output Di is determined by repeating to the minimum bit. As a result, the digital output Di is generated in a form including the dither signal component.

(B) AD conversion actual operation The operation during the AD conversion actual operation will be described below. Although it is basically the same as that in the AD conversion test operation, the dither signal bit cell DBCell2 is operated with the third switch CRD-SW3 being turned on at the first to third timings. As a result, the digital output Di is generated without including the dither signal component. The dither signal bit cell DBCell2 is used during the AD conversion test operation, but the dither signal bit cell DBCell2 is not used during the AD conversion actual operation.

(3) Summary Since it is a successive approximation ADCU, low power consumption of several mW or less is possible at 50 MS / s or less.

  In the first embodiment, the buffer circuit (not shown) is used only when the analog signal NP-RA and the analog signal RP-RA are sampled into the capacitor NP-SHC and the capacitor RP-SHC at the first timing at the first timing, respectively. The analog signal NP-RA and the analog signal RP-RA are input to the capacitor NP-SHC and the capacitor RP-SHC at the first timing. Therefore, since no buffer circuit is used at the second timing or the third timing, power consumption is reduced.

In the second embodiment, the switch CS-SW and the third switch CRD-SW3 are turned on for all the bit cells BCell at the first timing. Then, using a buffer circuit (not shown) when the while sampling the analog signal RA to the charge holding node CH-N, applies the ground voltage GND to the dither signal capacitors C _alpha. Furthermore it is necessary to use a buffer circuit (not shown) each time applying a positive reference voltage + V _R and negative reference voltage -V _R in each bit cell BCell, power consumption is increased as compared with Example 1.

  In the first embodiment, the charges held in the node NPCS-N and the node RPCS-N at the first timing are not stored at the second timing or the third timing, and therefore cannot be reused.

  In the second embodiment, the charge held in the charge holding node CH-N at the first timing is stored at the second timing or the third timing, and can be reused.

8). AD converter (Example 3)
FIG. 11 shows a pipelined AD conversion unit which is an example of the AD conversion unit I-ADCU and the AD conversion unit Q-ADCU of the present embodiment.

(1) Configuration The pipeline AD converter PL-ADCU has the following configuration. It is configured to receive one of the outputs of the variable amplifier I-PGA and the variable amplifier Q-PGA, and receives the analog signal RA. Have each stage Stage, what those corresponding to the maximum bit _{D N-1} digital output Di and stage STAGEn-1, just as with the name and code for each bit, corresponding to the minimum bit _{D 0} The stage is Stage0. Each stage Stagei satisfies the following relationship.
(Ii) 0 ≦ k ≦ N−1, k is 0 or a natural number, N is a natural number greater than or equal to 2 (b) k + 1-th stage outputs stage output SO to k-th stage (ha) k-th stage is k The digital output _Dk corresponding to the second bit is output. Stage Stage N-1 includes an AD conversion unit PA-ADCU, a dither signal adding unit DAU, and a DA conversion unit PL-DACU. Further, the stage StageN-1 has a digital output difference unit DODU and a stage output amplification unit SOAU. The AD conversion unit PA-ADCU receives the analog signal RA and performs AD conversion processing on a ternary (binary or OK) digital value. The dither signal adding unit DAU adds the output of the AD conversion unit PA-ADCU (this output is output bN _-1 ) and the dither signal (α). The DA conversion unit PL-DACU performs DA conversion processing on the output from the dither signal addition unit DAU. The digital output difference unit DODU subtracts the output from the DA conversion unit PL-DACU from the analog signal RA. The stage output amplification unit SOAU amplifies the output from the digital output difference unit DODU and outputs the stage output SO to the next stage StageN-2. Further, the output of the dither signal adding unit DAU becomes the digital output _DN-1 .

  The other stage Stage is basically the same as stage StageN-1, but receives the stage output SO from the preceding stage Stage instead of receiving the received analog signal RA. There is no dither signal adding unit DAU, and the digital output difference unit DODU directly receives the output of the AD conversion unit PA-ADCU. The output of the AD converter PA-ADCU becomes the digital output Di.

(2) Operation (a) AD Conversion Test Operation During the AD conversion test operation, the reception analog signal RA is input to the stage StageN-1 and the dither signal is input, so that the stage output SO is changed to the next stage StageN-2. To stage Stage0 by repeating in the same manner. As a result, a digital output Di is generated and output to the digital correction unit DCUI & Q.

(B) AD Conversion Production Operation In the AD conversion production operation, basically the same operation as that in the AD conversion test operation is performed, but the dither signal cannot be added to the stage StageN-1.

  Therefore, in the AD conversion test operation, the digital output Di is generated in a form including the dither signal component, and in the AD conversion actual operation, the digital output Di is generated in a form not including the dither signal component.

(3) Summary Pipeline type ADCU can operate at 50 MS / s to several hundred MS / s. In the case of a pipeline type ADCU, since there are many types of correction coefficients such as an operational amplifier gain, nonlinearity, and capacitance mismatch, it is effective to apply a dither signal having a more complicated pattern. Further, the search for the correction coefficient can be accelerated by increasing the amplitude of the test signal.

9. Digital correction unit for I and Q signals (Modification 1)
FIG. 12 shows a modification of the semiconductor integrated circuit device RFIC of the present embodiment.

(1) Configuration It has a correction coefficient averaging unit I-ADCCCAU for averaging the correction coefficient I-ADCCC used in the digital correction unit DCUI & Q. A correction coefficient averaging unit Q-ADCCCAU is provided for averaging the correction coefficient Q-ADCCC used in the digital correction unit DCUI & Q.

  The correction coefficient averaging unit I-ADCCCAU includes a correction coefficient sampling unit ADCCCSU, a correction coefficient integration unit ADCCCIU, a correction coefficient averaging unit ADCCCAVEEU, and a correction coefficient accuracy setting register I-ADCCCASRES. The correction coefficient sampling unit ADCCCSU multiplies the correction coefficient I-ADCCC by the X sample period between the sampling start time SST representing the sampling start time and the sampling end time SET representing the sampling end time. Here, X is a positive integer. Thus, the correction coefficient I-ADCCC is sampled X times in the X sample period, and the correction coefficient I-ADCCC is masked by multiplying the correction coefficient I-ADCCC outside the X sample period by 0. . Here, the correction coefficient I-ADCCC is stored in the correction coefficient setting register I-ADCCCSRES. The correction coefficient integration unit ADCCCIU includes a correction coefficient adding unit ADCCCAU and a correction coefficient delay unit ADCCCU, and outputs the sum of the sample values of the X correction coefficient I-ADCCC as an output. Here, the correction coefficient adding unit ADCCCAU adds the correction coefficient I-ADCCC from the correction coefficient sampling unit ADCCCSU and the previous correction coefficient I-ADCCC. The correction coefficient delay unit ADCCCU outputs the correction coefficient I-ADCCC from the correction coefficient adding unit ADCCCAU to be delayed by one sample period and returned to the correction coefficient adding unit ADCCCAU. The correction coefficient averaging unit ADCCCAVEU divides the output from the correction coefficient integration unit ADCCC IU by X. As a result, the average value of the correction coefficient I-ADCCC in the X sample period is output to the correction coefficient setting register I-ADCCCCSRES. The correction coefficient accuracy setting register I-ADCCCASRES sets the calculation accuracy of the correction coefficient I-ADCCC by setting the value of X.

  The correction coefficient averaging unit Q-ADCCCAU is basically the same as the correction coefficient averaging unit I-ADCCCAU. However, the correction coefficient Q-ADCCC is handled instead of the correction coefficient I-ADCCC, and input / output is performed with respect to the correction coefficient setting register Q-ADCCCSRES. Further, a correction coefficient accuracy setting register Q-ADCCCASRES is provided instead of the correction coefficient accuracy setting register I-ADCCCASRES.

(2) Operation In the AD conversion test operation, the correction coefficient I-ADCCC and the correction coefficient Q-ADCCC are updated as needed. At this time, in the I signal system and the Q signal system, the digital correction units I-DCU and Q-DCU use the correction coefficients I-ADCCC and Q-ADCCC stored in the correction coefficient setting registers I-ADCCCSRES and Q-ADCCCSRES. Perform digital correction. Then, the correction coefficient search unit ADC-CSU searches for the correction coefficients I-ADCCC and Q-ADCCC based on the conversion error e obtained from the result of the digital correction processing. Then, a search loop in which the correction coefficients I-ADCCC and Q-ADCCC in the correction coefficient setting registers I-ADCCCSRES and Q-ADCCCCSRES are updated based on the search result is operated. In parallel with the operation of this search loop, the correction coefficient averaging unit I-ADCCCAU and the correction coefficient averaging unit Q-ADCCCAU operate. At this time, the correction coefficient averaging unit ADCCCAVEU stops operating and does not output to the correction coefficient setting register. When the operation of the search loop stops, the correction coefficient averaging unit ADCCCAVEEU performs division processing to average the AD converter correction coefficients, and outputs the result to the correction coefficient setting registers I-ADCCCSRES and Q-ADCCCCSRES. Against.

(3) Summary When an algorithm such as the LMS algorithm is used, the above-described search loop control for calculating the correction coefficients I-ADCCC and Q-ADCCC is performed in order to quickly converge the correction coefficients I-ADCCC and Q-ADCCC. The control loop gain, which is a gain, is increased. Then, even after convergence, the control loop gain oscillates greatly. The control loop gain after convergence oscillates even under the influence of thermal noise and quantization noise. The influence of this vibration can be reduced by averaging the correction coefficients I-ADCCC and Q-ADCCC. Note that a circuit for averaging correction coefficients I-ADCCC and Q-ADCCC is not arranged in the search loop. Here, the circuits for the averaging process are the correction coefficient averaging unit I-ADCCCAU and the correction coefficient averaging unit Q-ADCCCAU. This is because the search loop is slowed down. Therefore, a circuit for averaging the correction coefficients I-ADCCC and Q-ADCCC is arranged outside this search loop. As an operation, when the search loop is operating, the correction coefficient averaging unit ADCCCAVEEU has stopped operating, and no output is made to the correction coefficient setting registers I-ADCCCSRES and Q-ADCCCCSRES, and the search loop operation has stopped. In some cases, the correction coefficient averaging unit ADCCCAVEEU performs division processing to average the correction coefficients I-ADCCC and Q-ADCCC, and performs the result on the correction coefficient setting registers I-ADCCCSRES and Q-ADCCCSRES. This makes it possible to perform the averaging process of the correction coefficients I-ADCCC and Q-ADCCC while speeding up the response of the search loop operation.

  When X of the correction coefficient accuracy setting registers I-ADCCCASRES and Q-ADCCCASRES is increased, the averaging effect is increased by increasing the number of samples, and high-precision correction coefficients I-ADCCC and Q-ADCCC can be obtained. When X is small, the accuracy is low, but since the number of samples is small, the time for averaging the correction coefficients I-ADCCC and Q-ADCCC can be shortened. Further, when the value of X is limited to a power of 2, the correction coefficient averaging unit ADCCCAVEEU can be operated not by division operation but by bit shift operation.

10. Test signal generation circuit for AD converter (Embodiment 4)
FIG. 13 shows an example of the test signal generation circuit ADC-TSGC for generating the test signal ADC-TS used in the semiconductor integrated circuit device RFIC of the present embodiment.

  A test signal generation circuit ADC-TSGC is surrounded by a dotted line shown in FIG. The test signal generation circuit ADC-TSGC has a digital waveform generation unit DWGU and a DA converter DWGU-DAC. The DA converter DWGU-DAC receives the output of the digital waveform generation unit DWGU and performs DA conversion to generate the test signal ADC-TS. The test signal generation circuit ADC-TSGC is provided in the semiconductor integrated circuit device RFIC.

  The output of the digital waveform generator DWGU is preferably a triangular wave having an amplitude close to the full scale (voltage range in which AD conversion is possible) of the AD converter I-ADC and AD converter Q-ADC, and a sufficiently low frequency. This is so that when the test signal ADC-TS is sampled by the AD converter I-ADC and the AD converter Q-ADC, the sampled voltage has a sufficiently diverse pattern. This is because the search for all correction coefficients I-ADCCC and correction coefficient Q-ADCCC is normally converged.

  The test signal ADC-TS output from the DA converter DWGU-DAC may have large noise and distortion. In the digital correction process, in order to search the correction coefficient I-ADCCC and the correction coefficient Q-ADCCC with high accuracy, the AD converter I-ADC and the AD converter Q-ADC may sample strictly equal input voltages. is important. Even if the test signal ADC-TS includes noise and distortion, the AD converter I-ADC and AD conversion are performed because the AD converter I-ADC and the AD converter Q-ADC simultaneously sample including noise and distortion. The sampling voltage of the device Q-ADC is kept exactly the same. Therefore, since the noise and distortion of the DA converter DWGU-DAC can be tolerated, the DA converter DWGU-DAC can be easily designed.

11. Test signal generation circuit for AD converter (Example 5)
FIG. 14 shows an example of the test signal generation circuit ADC-TSGC2 for generating the test signal ADC-TS used in the semiconductor integrated circuit device RFIC of the present embodiment.

(1) Configuration The test signal generation circuit ADC-TSGC2 is surrounded by a dotted line shown in FIG. The test signal generation circuit ADC-TSGC2 has a charge pump CP and an analog integrator AI. The charge pump CP receives a clock signal CLK such as (1) shown in FIG. The analog integrator AI receives the output of the charge pump CP and outputs a test signal ADC-TS as shown in (4) in FIG. The test signal generation circuit ADC-TSGC2 is provided in the semiconductor integrated circuit device RFIC.

  The charge pump CP includes an upper current source UIS, a P-type MOS transistor PMOS, an N-type MOS transistor NMOS, and a lower current source BIS. From the power supply voltage VDD to the ground voltage GND, a plurality of components are arranged in the connection relationship as shown in the figure, and this arrangement is an upper current source UIS, a P-type MOS transistor PMOS, an N-type MOS transistor. The order is NMOS and lower current source BIS. That is, the source terminal of the P-type MOS transistor PMOS is connected to the upper current source UIS, and the source terminal of the N-type MOS transistor NMOS is connected to the lower current source BIS. Further, the drain terminal of the P-type MOS transistor PMOS and the drain terminal of the N-type MOS transistor NMOS are connected. The gates of the P-type MOS transistor PMOS and the N-type MOS transistor NMOS receive a clock signal CLK as shown in (1) in FIG. When the clock signal CLK is at a high level, a current flows through the lower current source BIS through the path (3) shown in FIG. When the clock signal CLK is at a low level, a current flows through the upper current source UIS through the path (2) shown in FIG.

  The analog integrator AI has an operational amplifier OP-A, a feedback capacitor (capacitor) OPA-FC, and a feedback resistor OPA-FR. The operational amplifier OP-A receives a voltage half of the power supply voltage VDD at the non-inverting input terminal and the output of the charge pump CP at the inverting input terminal. The feedback capacitor OPA-FC is connected in parallel between the inverting input terminal of the operational amplifier OP-A and the output. The feedback resistor OPA-FR is connected in parallel with the feedback capacitor OPA-FC.

(2) Operation The test signal generation circuit ADC-TSGC2 operates as follows. When the test signal generation circuit ADC-TSGC2 receives the clock signal CLK, the charge pump CP operates, and a current flows through the feedback capacitor OPA-FC through paths (1) and (2) shown in FIG. When a current flows through a path such as (2) shown in the figure, the test signal ADC-TS changes so as to decrease. When a current flows through a path such as (3) shown in the figure, the test signal ADC-TS changes so as to increase. As a result, the test signal ADC-TS having a triangular wave shape as shown in (4) shown in the figure is output as the output of the analog integrator AI, and the test signal generation circuit ADC-TSGC2 outputs the test signal ADC-TS. The feedback resistor OPA-FR is a high resistance for direct current feed for making the test signal ADC-TS have a waveform that operates with an amplitude centered on the power supply voltage VDD / 2. The frequency of the clock signal CLK becomes the frequency of the triangular wave as the test signal ADC-TS.

  The clock signal CLK has a sufficiently low frequency by dividing the sampling clock for the AD converter I-ADC and the AD converter Q-ADC. The amplitude of the triangular wave is set by the current value of the upper side current source UIS and the lower side current source BIS and the capacitance value of the feedback capacitor OPA-FC, and close to the full scale of the AD converter I-ADC and AD converter Q-ADC. It shall have the amplitude of. These ensure that the search for the correction coefficient I-ADCCC and the correction coefficient Q-ADCCC can converge reliably. As in the fourth embodiment, the test signal ADC-TSGC2 is acceptable even if noise or distortion is included in the test signal ADC-TS. Therefore, the design of the test signal generation circuit ADC-TSGC2 is easy.

12 Test signal generation circuit for AD converter (Embodiment 6)
FIG. 15 shows an example of the test signal generation circuit ADC-TSGC3 for generating the test signal ADC-TS used in the semiconductor integrated circuit device RFIC of the present embodiment.

(1) Configuration The test signal generation circuit ADC-TSGC3 is surrounded by a dotted line shown in FIG. As in the fifth embodiment, the test signal generation circuit ADC-TSGC3 includes a charge pump CP and an analog integrator AI. Further, the test signal generation circuit ADC-TSGC3 includes an AD converter I-ADC and an AD converter Q-ADC, an AD converter output averaging unit (averaging circuit) IQADC-OAU, and a charge pump control circuit CPCC. A charge pump CP that receives a clock signal CLK as in (1) and outputs a current. An analog integrator AI that receives the output of the charge pump CP and outputs the test signal ADC-TS as in (4). An AD converter I-ADC and an AD converter Q-ADC that receive the output of the charge pump. The AD converter output averaging unit IQADC-OAU receives two outputs from the AD converter I-ADC and the AD converter Q-ADC, and averages and outputs the two outputs. The charge pump control circuit CPCC receives an output from the AD converter output averaging unit IQADC-OAU and generates a clock signal CLK input to the charge pump CP. Here, the test signal generation circuit ADC-TSGC3 is configured as a loop circuit including these components. The test signal generation circuit ADC-TSGC3 is provided in the semiconductor integrated circuit device RFIC.

(2) Operation The operation of the test signal generation circuit ADC-TSGC during the AD conversion test operation will be described. As described in the sixth embodiment, when a current flows through the paths (2) and (3) shown in the figure, the test signal ADC-TS like (4) shown in the figure is converted into the AD converter I. -Input to ADC and AD converter Q-ADC. The first dither signal Dither1 is input to the AD converter I-ADC, and the second dither signal Dither2 is input to the AD converter Q-ADC. These dither signal components are canceled by the AD converter output averaging unit IQADC-OAU, and a signal such as (5) shown in FIG. The output of the AD converter output averaging unit IQADC-OAU is obtained by subjecting the test signal ADC-TS to AD conversion processing. The charge pump control circuit CPCC receives a signal such as (5) shown in FIG. The charge pump control circuit CPCC outputs a high level signal when a signal such as (5) shown in the figure falls below the first threshold voltage Vth1. The charge pump control circuit CPCC outputs a low-level signal when it exceeds a second threshold voltage Vth2 that is larger than the first threshold voltage Vth1. As a result, a clock signal CLK such as (1) shown in the figure is generated and output to the charge pump CP. The test signal generation circuit ADC-TSGC3 as a loop circuit constitutes a triangular wave transmitter, and the correction signals I-ADCCC and Q-ADCCC are generated by using the test signal ADC-TS as a triangular wave.

  Compared to the fifth embodiment, since the amplitude of the triangular wave can be managed by the first threshold voltage Vth1 and the second threshold voltage Vth2, it is saturated due to variations in the upper current source UIS, the lower current source BIS, and the feedback capacitance OPA-FC. The point that can avoid the risk is excellent.

  The frequency of the triangular wave in the sixth embodiment is determined by the first threshold voltage Vth1, the second threshold voltage Vth2, the upper current source UIS, the lower current source BIS, and the feedback capacitor OPA-FC, and is sampled as in the fifth embodiment. Not an integer number of clocks. Therefore, the frequency of the triangular wave can be made independent of the frequency of the sampling clock for the AD converter I-ADC and the AD converter Q-ADC. Thereby, the sampling voltage of the triangular wave in the AD converter I-ADC and the AD converter Q-ADC has various patterns, which is advantageous in that it is advantageous for searching for the correction coefficients I-ADCCC and Q-ADCCC.

13. Other Modifications (1) Dither Signal In this embodiment, the first dither signal Dither1 input to the AD conversion unit I-ADCU is absolute with the second dither signal Dither2 input to the AD conversion unit Q-ADCU. The values are equal and the signs are reversed. Therefore, if the first dither signal Dither1 = α, the second dither signal Dither2 = −α. However, such a relationship is not necessarily required, and the first dither signal Dither1 = 2α and the second dither signal Dither2 = 0 may be used, or the first dither signal Dither1 = 0 and the second dither signal Dither2 = 2α may be used. Thus, either one of the first and second dither signals may be 0 and the other may be 2α.

(2) Mismatch In this embodiment, the IQ correction unit I / QCU has a path from the mixer RI-MIX to the variable amplifier I-PGA in the analog circuit R-AC, and from the mixer RQ-MIX to the variable amplifier Q-PGA. It is best to detect and correct the mismatch in gain, phase, and DC offset due to the path. However, it is also possible to detect and correct at least one (or two) mismatch among gain, phase, and DC offset.

(3) Calibration processing In the present embodiment, calibration processing is performed on the following circuits of the analog circuit R-AC and the analog circuit T-AC in the initial sequence period.
(A) Analog circuit R-AC
Low noise amplifier LNA, filter I-FIL, filter Q-FIL, variable amplifier I-PGA, variable amplifier Q-PGA, clock pulse generator CPG
(B) Analog circuit T-AC
DA converter I-DAC, DA converter Q-DAC, low-pass filter I-LPF, low-pass filter Q-LPF, power amplifier PA
The calibration processing for these element circuits is not limited to the initial sequence period, and may be executed in the ADC correction mode ADC-CM. In particular, when calibration processing is performed during regular periods of no signal, calibration processing results corresponding to temperature fluctuations and power supply voltage fluctuations of these element circuits are obtained, and high accuracy of demodulation processing and modulation processing is obtained. Can be achieved. Further, the frequency and time of calibration processing may be set for each element circuit. In this case, since there is an optimal calibration frequency and time for each element circuit, it is possible to improve the accuracy of demodulation processing and modulation processing and optimize power consumption. It should be noted that the calibration of these element circuits, particularly the calibration process of each element circuit of the analog circuit R-AC, is preferably performed before the IQ correction mode I / QC-CM. The reason is that the IQ correction unit I / QCU is a gain or phase caused by a path from the mixer RI-MIX to the variable amplifier I-PGA and a path from the mixer RQ-MIX to the variable amplifier Q-PGA in the analog circuit R-AC. DC offset mismatch is detected and corrected. Therefore, various offsets of each element circuit existing in the path from the mixer RI-MIX to the variable amplifier I-PGA and each element circuit existing in the path from the mixer RQ-MIX to the variable amplifier Q-PGA are optimally corrected. This is because the detection and correction processing of the mismatch of the gain, phase, and DC offset in the IQ correction unit I / QCU cannot be performed with high accuracy.

(4) IQ correction test signal In the present embodiment, the calibration signal generation circuit I / QCU-CSG applies the test signal I / QC- to the low-pass filter I-LPF or the low-pass filter Q-LPF of the analog Q signal T-QA. It is configured to output TS. However, since the test signal I / QC-TS only has to pass through the path from the mixer RI-MIX to the variable amplifier I-PGA and the path from the mixer RQ-MIX to the variable amplifier Q-PGA, the low noise amplifier LNA and the mixer RI- The test signal I / QC-TS may be directly input between the MIX and the mixer RQ-MIX. Since the loop switch L-SW needs to pass the test signal I / QC-TS through the path from the mixer RI-MIX to the variable amplifier I-PGA and the path from the mixer RQ-MIX to the variable amplifier Q-PGA. In addition, it is provided in a place as shown in FIG. The switching circuit I-SC and the switching circuit Q-SC are configured such that each element circuit has an offset by passing a path from the mixer RI-MIX to the variable amplifier I-PGA or a path from the mixer RQ-MIX to the variable amplifier Q-PGA. 5 is provided in a place as shown in FIG. 5 so that the variation of the A does not affect the AD conversion test operation. The order of the arrangement of the filter and the variable amplification amplifier in the path between the mixer RI-MIX and the AD converter I-ADC and the path between the mixer RQ-MIX and the AD converter Q-ADC may be reversed. There may be a plurality of filters and variable amplifiers, and the filters and variable amplifiers may be alternately arranged.

(5) ADC
In the configuration or function of 5 (4) to (9) above, the first AD converter may be the AD converter I-ADC described in FIG. 5, and the second AD converter is shown in FIG. 5. The AD converter Q-ADC described may be used. The first AD converter may be the ADC of any one of Reference FIGS. 1 to 4 provided between the analog circuit R-AC and the digital processing unit DOU. In this case, the analog signal (Input) of the ADC of Reference FIGS. 1 to 4 is input from the output of the variable amplifier I-PGA for I signal, and the digital signal (Output) of the ADC of Reference FIGS. This is input to the input unit that receives the digital I signal R-ID of the inter-IQ correction unit I / QCU. The second AD converter may be the ADC of any one of Reference FIGS. 1 to 4 provided between the analog circuit R-AC and the digital processing unit DOU. In this case, the analog signal (Input) of the ADC of Reference FIGS. 1 to 4 is input from the output of the variable amplifier Q-PGA, and the digital signal (Output) of the ADC of Reference FIGS. 1 to 4 is corrected between IQs. Input to the input unit that receives the digital Q signal R-QD of the unit I / QCU. In short, the ADC of the I signal path may be any ADC that generates the digital I signal R-ID by performing AD conversion processing by receiving the analog I signal R-IA and performing digital correction processing. Similarly, the ADC of the Q signal path may be an ADC that receives the analog Q signal R-QA and performs digital correction processing to perform AD conversion processing to generate the digital Q signal R-QD. In addition, when applying any ADC of Reference FIG. 1, Reference FIG. 3 and Reference FIG. 4 to the first AD converter, the switching circuit I-SC is set to any of Reference FIG. 1, Reference FIG. 3 and Reference FIG. It may be configured to connect to the front stage of the ADC so that the input of the AD converter test signal and the output of the variable amplifier I-PGA can be switched between the first mode and the second mode. In the case where the ADC of any one of Reference FIG. 1, Reference FIG. 3 and Reference FIG. 4 is applied to the second AD converter, the switching circuit Q-SC is connected to the ADC of any one of Reference FIG. 1, Reference FIG. What is necessary is just to set it as the structure which connects to the front | former stage and can switch the input of the test signal for AD converters, and the output of variable amplifier Q-PGA between 1st mode and 2nd mode.

(Embodiment 2)
Hereinafter, the configuration of a semiconductor integrated circuit device according to the present embodiment, a communication system including the semiconductor integrated circuit device, and the semiconductor integrated circuit device will be described in detail with reference to the drawings. FIG. 16 is a configuration diagram of a communication system including a semiconductor integrated circuit device.

  Although there are the same parts as the communication system of the first embodiment, there are some different points, which will be mainly described.

  In the first embodiment, the number of antennas is one, but in the present embodiment, there are two antennas, and accordingly, there are two reception analog circuits. Further, the configuration of the AD converter for the I and Q signals at the subsequent stage is changed. Furthermore, the configuration of the digital processing unit has been changed.

1. Communication System The communication system of the present embodiment is different from that of the first embodiment in that the configuration includes a first antenna ANT1, a second antenna ANT2, a semiconductor integrated circuit device RFIC2, and a baseband processing unit BBU. The first antenna ANT1 receives a first high frequency signal HFS1 as a communication signal from the outside. The second antenna ANT2 receives the second high-frequency signal HFS2, which is the same type of signal as the first high-frequency signal HFS1, and is a physically separated signal. The baseband processing unit BBU is the same as that in the first embodiment.

2. Semiconductor Integrated Circuit Device (1) Configuration The semiconductor integrated circuit device RFIC2 includes a first analog circuit R-AC1, a second analog circuit R-AC2, and an AD converter R-ADC that are different from those in the first embodiment. . Furthermore, the semiconductor integrated circuit device RFIC2 includes a digital processing unit DOU2 and an analog circuit T-AC2.

  The first analog circuit R-AC1 is surrounded by a chain line shown in FIG. The first analog circuit R-AC1 receives the first high-frequency signal HFS1 via the first antenna ANT1, and the analog I signal L1R-IA and the analog Q signal whose phases are shifted by 90 degrees from the analog I signal L1R-IA. L1R-QA is generated. The second analog circuit R-AC2 is surrounded by a chain line shown in FIG. The second analog circuit R-AC2 receives the second high-frequency signal HFS2 via the second antenna ANT2, and the analog Q signal L2R-IA and the analog Q signal whose phases are shifted by 90 degrees from the analog I signal L2R-IA. L2R-QA is generated. The AD converter R-ADC is surrounded by a chain line shown in FIG. The AD converter R-ADC receives the analog I signal L1R-IA and performs AD conversion on this signal to generate a digital I signal L1R-ID. Further, the AD converter R-ADC receives the analog Q signal L1R-QA and AD-converts this signal to generate a digital Q signal L1R-QD. Further, the AD converter R-ADC receives the analog I signal L2R-IA and AD-converts this signal to generate a digital I signal L2R-ID. Further, the AD converter R-ADC receives the analog Q signal L2R-QA and AD-converts this signal to generate a digital Q signal L2R-QD.

  Regarding the analog circuit for reception, the analog circuit R-AC of the first embodiment has the loop switch L-SW, but instead, the first analog circuit R-AC1 and the analog circuit T-AC of the present embodiment. Then, it is a loop switching circuit L-SC. In the IQ correction test operation, the loop switching circuit L-SC connects the output of the output adding unit T-OAU and the inputs of the receiving mixers of the first analog circuit R-AC1 and the second analog circuit R-AC2. This connection is disconnected in the correction operation between IQs. The loop switching circuit L-SC and the clock pulse generator CPG are shared by the analog circuit T-AC2, the first analog circuit R-AC1, and the second analog circuit R-AC2. The transmission / reception selector switch TR-SW is shared by the analog circuit T-AC2 and the first analog circuit R-AC1, and is not shared by the second analog circuit R-AC2. The output of the analog circuit T-AC2 is transmitted to the outside via the first antenna ANT1 via the transmission / reception selector switch TR-SW. The first mixer signal is output to the first analog circuit R-AC1 and the second analog circuit R-AC2, and the second mixer signal is output to the first analog circuit R-AC1 and the second analog circuit R-AC2. Other than these, there is no particular structural difference between the analog circuit R-AC of the first embodiment, the first analog circuit R-AC1, and the second analog circuit R-AC2. Needless to say, since the input signal is changed as described above, the signal processed internally is also changed along with this change.

  The AD converter R-ADC has a switching circuit ADC-SC. The switching circuit ADC-SC outputs a common test signal ADC-TS to the subsequent AD conversion unit during the AD conversion test operation. In the AD conversion actual operation, the switching circuit ADC-SC converts the analog I signal L1R-IA, the analog Q signal L1R-QA, the analog I signal L2R-IA, and the analog Q signal L2R-QA to the AD conversion corresponding to each subsequent stage. To the output. The AD converter R-ADC includes an AD conversion unit L1I-ADCU, an AD conversion unit L2I-ADCU, and digital correction units DCUIL1 & L2. The AD converter R-ADC includes an AD conversion unit L1Q-ADCU, an AD conversion unit L2Q-ADCU, and digital correction units DCUQL1 & L2.

  The digital correction units DCUIL1 & L2 include a correction coefficient setting register L1I-ADCCCSRES and a correction coefficient setting register L2I-ADCCCSRES. The correction coefficient setting register L1I-ADCCCCSRES is for storing a correction coefficient for digital correction processing for the digital output from the AD conversion unit L1I-ADCU. The correction coefficient setting register L2I-ADCCCCSRES is for storing a correction coefficient for digital correction processing for the digital output from the AD conversion unit L21I-ADCU.

  The digital correction units DCUQL1 & L2 include a correction coefficient setting register L1Q-ADCCCSRES and a correction coefficient setting register L2Q-ADCCCSRES. The correction coefficient setting register L1Q-ADCCCCSRES is for storing a correction coefficient for digital correction processing for the digital output from the AD conversion unit L1Q-ADCU. The correction coefficient setting register L2Q-ADCCCSRES is for storing a correction coefficient for digital correction processing for the digital output from the AD conversion unit L21Q-ADCU.

  The digital processing unit DOU2 and the analog circuit T-AC2 will be described later.

(2) Operation (a) AD conversion test operation The AD conversion test operation is performed as follows. The test signal ADC-TS is input to the AD conversion unit L1I-ADCU through the switching circuit ADC-SC, input to the AD conversion unit L1Q-ADCU, input to the AD conversion unit L2I-ADCU, and the AD conversion unit L2Q-ADCU. Is input.

  The AD conversion unit L1I-ADCU receives the first dither signal Dither1 in addition to the test signal ADC-TS, performs AD conversion on these inputs, and outputs the result to the digital correction units DCUIL1 & L2. The AD converter L2I-ADCU receives the second dither signal Dither2 in addition to the test signal ADC-TS, performs AD conversion on these inputs, and outputs the result to the digital correction units DCUIL1 & L2.

  The AD converter L1Q-ADCU receives the first dither signal Dither1 in addition to the test signal ADC-TS, AD-converts these inputs, and outputs the result to the digital correctors DCUQL1 & L2. The AD converter L2Q-ADCU receives the second dither signal Dither2 in addition to the test signal ADC-TS, AD-converts these inputs, and outputs the result to the digital correctors DCUQL1 & L2.

  The digital correction units DCUIL1 & L2 obtain a correction result obtained by digitally correcting the digital output from the AD conversion unit L1I-ADCU and a correction result obtained by digitally correcting the digital output from the AD conversion unit L2I-ADCU. Based on the obtained correction results, the correction coefficient L1I-ADCCC to be stored in the correction coefficient setting register L1I-ADCCCSRES is determined and stored, and the correction coefficient L2I− to be stored in the correction coefficient setting register L2I-ADCCCSRES ADCCC is determined and stored.

  The digital correction units DCUQL1 & L2 obtain a correction result obtained by digitally correcting the digital output from the AD conversion unit L1Q-ADCU and a correction result obtained by digitally correcting the digital output from the AD conversion unit L2Q-ADCU. Based on the obtained correction results, a correction coefficient L1Q-ADCCC to be stored in the correction coefficient setting register L1Q-ADCCCSRES is determined and stored, and the correction coefficient L2Q- to be stored in the correction coefficient setting register L2Q-ADCCCSRES. ADCCC is determined and stored.

(B) A / D conversion production operation The A / D conversion production operation operates as follows. The analog I signal L1R-IA is input to the AD conversion unit L1I-ADCU via the switching circuit ADC-SC, and the analog I signal L2R-IA is input to the AD conversion unit L2I-ADCU via the switching circuit ADC-SC. . The analog Q signal L1R-QA is input to the AD conversion unit L1Q-ADCU via the switching circuit ADC-SC, and the analog Q signal L2R-QA is input to the AD conversion unit L2Q-ADCU via the switching circuit ADC-SC. .

  An analog I signal L1R-IA is input to the AD conversion unit L1I-ADCU, and this input is subjected to AD conversion processing, and the result is output to the digital correction units DCUIL1 & L2. An analog I signal L2R-IA is input to the AD conversion unit L2I-ADCU, and this input is subjected to AD conversion processing, and the result is output to the digital correction units DCUIL1 & L2. An analog Q signal L1R-QA is input to the AD conversion unit L1Q-ADCU, and this input is subjected to AD conversion processing and the result is output to the digital correction units DCUQL1 & L2. An analog Q signal L2R-QA is input to the AD conversion unit L2Q-ADCU, and this input is subjected to AD conversion processing, and the result is output to the digital correction units DCUQL1 & L2.

  The digital correction units DCUIL1 & L2 perform digital correction processing on the output from the AD conversion unit L1I-ADCU using the correction coefficient L1I-ADCCC stored in the correction coefficient setting register L1I-ADCCCCSRES, thereby performing AD correction in the AD converter R-ADC. The digital I signal L1R-ID is output as the conversion processing result. The digital correction units DCUIL1 & L2 perform digital correction processing on the output from the AD conversion unit L2I-ADCCU using the correction coefficient L2I-ADCCC stored in the correction coefficient setting register L2I-ADCCCCSRES, thereby performing AD correction in the AD converter R-ADC. The digital I signal L2R-ID is output as the conversion processing result.

  The digital correction units DCUQL1 & L2 perform digital correction processing on the output from the AD conversion unit L1Q-ADCU using the correction coefficient L1Q-ADCCC stored in the correction coefficient setting register L1Q-ADCCCCSRES, so that the AD in the AD converter R-ADC The digital Q signal L1R-QD is output as the conversion processing result. The digital correction units DCUQL1 & L2 perform digital correction processing on the output from the AD conversion unit L2Q-ADCU using the correction coefficient L2Q-ADCCC stored in the correction coefficient setting register L2Q-ADCCCCSRES, so that the AD in the AD converter R-ADC The digital Q signal L2R-QD is output as the conversion processing result.

  The internal configuration and operation of each AD converter are the same as those of the AD converter of the first embodiment. The internal configuration and operation of each digital correction unit are basically the same as those of the digital correction unit of the first embodiment, but the correction coefficient setting register for AD conversion is the same as that of the first embodiment as described above. It has been replaced with the one of the form. Therefore, except for the replaced part, it is based on what is described in FIG. 7 of the first embodiment and its description part. Needless to say, since the input signal is changed as described above, the signal processed internally is also changed along with this change.

3. Digital Processing Unit (1) Configuration Unlike the first embodiment, the digital processing unit DOU2 includes an inter-IQ correction unit L1I / QCU and an inter-IQ correction unit L2I / QCU. The inter-IQ correction unit L1I / QCU has gain, phase, and DC offset caused by the path from the mixer of the I signal system to the variable amplifier and the path from the mixer of the Q signal system to the variable amplifier in the analog circuit R-AC1. Detect mismatches. Then, the IQ correction unit L1I / QCU corrects the detected mismatch and outputs a corrected digital I signal L1-CID and a corrected digital Q signal L1-CQD. The inter-IQ correction unit L2I / QCU has gain, phase, and DC offset caused by the path from the I signal system mixer to the variable amplifier and the path from the Q signal system mixer to the variable amplifier in the analog circuit R-AC2. Detect mismatches. Then, the IQ correction unit L2I / QCU corrects the detected mismatch and outputs a corrected digital I signal L2-CID and a corrected digital Q signal L2-CQD. The digital processing unit DOU2 performs necessary digital processing on these corrected digital signals to generate a baseband signal and transmits it to the baseband processing unit BBU. The digital processing unit DOU2 does not perform any digital processing if unnecessary. In this case, these corrected digital signals become demodulated baseband signals.

  The inter-IQ correction unit L1I / QCU includes a correction coefficient setting register L1I-I / QCUCCRES and a correction coefficient setting register L1Q-I / QCUCCRES. The correction coefficient setting register L1I-I / QCUCCRES stores the correction coefficient L1I-I / QCUCC for processing the digital I signal L1R-ID. The correction coefficient setting register L1Q-I / QCUCCRES stores the correction coefficient L1Q-I / QCUCC for processing the digital Q signal L1R-QD.

  The inter-IQ correction unit L2I / QCU includes a correction coefficient setting register L2I-I / QCUCCRES and a correction coefficient setting register L2Q-I / QCUCCRES. The correction coefficient setting register L2I-I / QCUCCRES stores the correction coefficient L2I-I / QCUCC for processing the digital I signal L2R-ID. The correction coefficient setting register L2Q-I / QCUCCRES stores the correction coefficient L2Q-I / QCUCC for processing the digital Q signal L2R-QD.

  The internal configuration of each IQ correction unit is basically the same as the IQ correction unit of the first embodiment. However, the correction coefficient setting register for correction between IQs is replaced from that of the first embodiment to that of the present embodiment as described above. Therefore, except for the replaced part, it is based on what is described in FIG. 8 of the first embodiment and its description part. Needless to say, since the input signal is changed as described above, the signal processed internally is also changed along with this change.

(2) Operation The inter-IQ correction test operation and the inter-IQ correction actual operation of each inter-IQ correction unit are basically the same as the operation of the inter-IQ correction unit of the first embodiment. However, the received digital signal input to the IQ correction unit and the correction digital signal output from the IQ correction unit are replaced with those of the present embodiment as described above from the first embodiment. Further, the correction coefficient for IQ correction is changed from that of the first embodiment to that of the present embodiment as described above. Needless to say, since the input signal is changed as described above, the signal processed internally is also changed along with this change.

(3) AD conversion processing mode (a) Path 1 & 2 correction mode The digital processing unit DOU2 is further provided with an AD conversion processing mode register ADCMRES. In the present embodiment, the AD conversion processing of the AD converter R-ADC described so far has the following form. An analog I signal L1R-IA that is an I signal of path 1 that has passed through the first analog circuit R-AC1 from the first antenna ANT1, and a path 2 that has passed through the second analog circuit R-AC2 from the second antenna ANT2. Using the analog I signal L2R-IA, which is an I signal, a correction coefficient for AD conversion is calculated during an AD conversion test operation. Then, the digital I signal L1R-ID and the digital I signal L2R-ID are generated by performing AD conversion processing using the AD conversion correction coefficient obtained during the AD conversion test operation during the AD conversion actual operation. Similarly, the AD conversion processing of the AD converter R-ADC described so far has the following form. The analog Q signal L1R-QA, which is the Q signal of the path 1 that has passed through the first analog circuit R-AC1 from the first antenna ANT1, and the path 2 that has passed through the second analog circuit R-AC2 from the second antenna ANT2. Using the analog I signal L2R-QA, which is a Q signal, a correction coefficient for AD conversion is calculated during an AD conversion test operation. Then, the AD conversion processing is performed using the AD conversion correction coefficient obtained during the AD conversion test operation during the AD conversion actual operation, thereby generating the digital Q signal L1R-QD and the digital Q signal L2R-QD. In this case, the path 1 & 2 correction mode is set in the AD conversion processing mode register ADCMRES. The baseband processing unit BBU can set the mode of the AD conversion processing mode register ADCMRES.

(B) IQ correction mode When the IQ correction mode is set in the AD conversion processing mode register ADCMRES, the AD converter R-ADC performs the following operation. An analog I signal L1R-IA that is an I signal of path 1 that has passed through the first analog circuit R-AC1 from the first antenna ANT1, and a path 1 that has passed through the first analog circuit R-AC1 from the first antenna ANT1. Using the analog Q signal L1R-QA, which is a Q signal, a correction coefficient for AD conversion is calculated during an AD conversion test operation. Then, the digital I signal L1R-ID and the digital Q signal L1R-QD are generated by performing AD conversion processing using the AD conversion correction coefficient obtained during the AD conversion test operation during the AD conversion actual operation. Similarly, the AD conversion processing of the AD converter R-ADC takes the following form. An analog I signal L2R-IA that is an I signal of path 2 that has passed through the second analog circuit R-AC2 from the second antenna ANT2, and a path 2 that has passed through the second analog circuit R-AC2 from the second antenna ANT2. A correction coefficient for AD conversion is calculated using the analog I signal L2R-QA, which is a Q signal, during an AD conversion test operation. Then, the digital I signal L2R-ID and the digital Q signal L2R-QD are generated by performing AD conversion processing using the AD conversion correction coefficient obtained during the AD conversion test operation during the AD conversion actual operation.

In order to achieve the operation when the inter-IQ correction mode is set in the AD conversion processing mode register ADCMRES, the AD conversion correction coefficients stored in the signal input / output and AD conversion correction coefficient setting registers are as follows: Changed to
(Ii) The output of the AD conversion unit L1I-ADCU is input to the digital correction unit DCUQL1 & L2. (B) The output of the AD conversion unit L2Q-ADCU is input to the digital correction unit DCUIL1 & L2. (Ha) correction coefficient setting register L2Q-ADCCCCSRES The correction coefficient L1I-ADCCC is stored in (ii) The correction coefficient L2Q-ADCCC is stored in the correction coefficient setting register L1I-ADCCCCSRES (ho) The digital Q signal L2R-QD is output from the digital correction unit DCUIL1 & L2, and this output The digital Q signal L2R-QD is input to the IQ correction unit L2I / QCU (to) the digital correction unit DCUQL1 & L2 outputs the digital I signal L1R-ID, and the output digital I signal L1R-ID is IQ Input to interval correction unit L1I / QCU Also in AD conversion test operation and AD conversion production operation is, the correction coefficient for AD conversion to be stored in the correction coefficient setting register for signal input and output and the AD conversion is changed in accordance with these changes. Also in the AD converter R-ADC, since the input signal is changed as described above, the signal processed inside is also changed in accordance with this change.

4). Others Note that the operation of the communication system including the semiconductor integrated circuit device RFIC2 of the present embodiment conforms to FIG. 6 of the first embodiment and the description thereof.

Regarding the analog circuit T-AC2, there is a difference from the first embodiment regarding the clock pulse generator CPG and the loop switching circuit L-SC as described above. Other than that, it conforms to FIG. 5 of the first embodiment and its description.
5. Summary According to the present embodiment, the following effects can be obtained.
(1) In the ADC correction mode ADC-CM (corresponding to the first mode in the foreground correction), the AD conversion unit L1I-ADCU, the AD conversion unit L1Q-ADCU, the AD conversion unit L2I-ADCU, and the AD conversion unit L2Q-ADCU A test signal ADC-TS is input in common. The correction coefficient L1I-ADCCC and the correction coefficient L2I-ADCCC are calculated by digitally processing the outputs from the AD conversion unit L1I-ADCU and the AD conversion unit L2I-ADCU by the digital correction units DCUIL1 & L2. The correction coefficient L1Q-ADCCC and the correction coefficient L2Q-ADCCC are calculated by the digital correction units DCUQL1 & L2 performing digital correction processing on the outputs from the AD conversion unit L1Q-ADCU and the AD conversion unit L2Q-ADCU. Further, in the IQ correction mode I / QCU-CM or the received signal processing mode RSPM (corresponding to the second mode in the foreground correction), the correction coefficient L1I-ADCCC and the correction coefficient L2I-ADCCC obtained in the ADC correction mode ADC-CM. The digital I signal L1R-IA is AD converted and the digital I signal L1R-ID is output, and the analog I signal L2R-IA is AD converted to the digital I signal L2R-ID. Is output. Digital correction processing is performed using the correction coefficient L1Q-ADCCC and the correction coefficient L2Q-ADCCC obtained in the ADC correction mode ADC-CM, whereby the analog Q signal L1R-QA is subjected to AD conversion processing, and the digital Q signal L1R- QD is output, the analog Q signal L2R-QA is AD converted, and a digital Q signal L2R-QD is output.

  By having the configuration or function of (1), the AD conversion unit L1I-ADCU, the AD conversion unit L2I-ADCU, and the digital correction unit DCUIL1 & L2 are the correction coefficient L1I-ADCCC and the correction coefficient L2I− in the ADC correction mode ADC-CM. Used to calculate ADCCC. Further, in the IQ correction mode I / QCU-CM or the reception signal processing mode RSPM, the analog I signal L1R-IA and the analog I signal L2R-IA are also used for AD conversion operation. Further, the AD conversion unit L1Q-ADCU, the AD conversion unit L2Q-ADCU, and the digital correction unit DCUQL1 & L2 are used to calculate the correction coefficient L1Q-ADCCC and the correction coefficient L2Q-ADCCC in the ADC correction mode ADC-CM. In the IQ correction mode I / QCU-CM or the reception signal processing mode RSPM, the analog Q signal L1R-QA and the analog Q signal L2R-QA are also used for AD conversion operation. Therefore, it is not necessary to obtain the correction coefficient L1I-ADCCC, the correction coefficient L2I-ADCCC, the correction coefficient L1Q-ADCCC, and the correction coefficient L2Q-ADCCC with an additional circuit having a large area, thereby reducing the semiconductor integrated circuit device. Further, since there is no additional circuit with a large area, the additional circuit with a large area does not operate in the ADC correction mode ADC-CM, so that power consumption can be reduced.

  (2) The configuration or function of (1) above, wherein in the ADC correction mode ADC-CM, a conversion error based on a difference between an output from the AD conversion unit L1I-ADCU and an output from the AD conversion unit L2I-ADCU Based on the above, a correction coefficient L1I-ADCCC and a correction coefficient L2I-ADCCC are calculated. In the ADC correction mode ADC-CM, the correction coefficient L1Q-ADCCC and the correction coefficient L2Q-ADCCC are based on the conversion error based on the difference between the output from the AD conversion unit L1Q-ADCU and the output from the AD conversion unit L2Q-ADCU. Is calculated.

  By having the configuration or function of (2) above, in the ADC correction mode ADC-CM, based on the conversion error based on the difference between the output from the AD conversion unit L1I-ADCU and the output from the AD conversion unit L2I-ADCU. Thus, both the correction coefficient L1I-ADCCC and the correction coefficient L2I-ADCCC are calculated. Both the correction coefficient L1I-ADCCC and the correction coefficient L2I-ADCCC are obtained based on a common conversion error. Both the correction coefficient L1Q-ADCCC and the correction coefficient L2Q-ADCCC are calculated based on the conversion error based on the difference between the output from the AD conversion unit L1Q-ADCU and the output from the AD conversion unit L2Q-ADCU. Both the correction coefficient L1Q-ADCCC and the correction coefficient L2Q-ADCCC are obtained based on a common conversion error. In the IQ correction mode I / QCU-CM or the reception signal processing mode RSPM, the AD converter R-ADC executes an AD conversion operation using the correction coefficient L1I-ADCCC and the correction coefficient L2I-ADCCC. The AD converter R-ADC performs an AD conversion operation using the correction coefficient L1Q-ADCCC and the correction coefficient L2Q-ADCCC. Since both the correction coefficient L1I-ADCCC and the correction coefficient L2I-ADCCC are obtained based on the common conversion error, and the correction coefficient L1I-ADCCC and the correction coefficient L2I-ADCCC thus obtained are used, the digital I signal Conversion gain mismatch between L1R-ID and digital I signal L2R-ID is reduced. Similarly, both the correction coefficient L1Q-ADCCC and the correction coefficient L2Q-ADCCC are obtained based on a common conversion error, and the correction coefficient L1Q-ADCCC and the correction coefficient L2Q-ADCCC thus obtained are used, so that the digital Q Conversion gain mismatch between signal L1R-QD and digital Q signal L2R-QD is reduced.

  (3) In the configuration or function of (2) above, when the path 1 & 2 correction mode is set in the AD conversion processing mode register ADCMRES, the configuration or function of (1) and (2) described above operates. . When the inter-IQ correction mode is set in the AD conversion processing mode register ADCMRES, the signal input / output and AD conversion correction coefficients stored in the AD conversion correction coefficient setting register are the above-described 3. (3) It is changed as (ii) to (f) in (b). An inter-IQ correction unit L1I / QCU and an inter-IQ correction unit L2I / QCU are provided.

By having the configuration or function of (3), the following situation occurs.
(Ii) Gain, phase, and direct current caused by the path from the I signal system mixer to the variable amplifier and the path from the Q signal system mixer to the variable amplifier in the analog circuit R-AC1 by the IQ correction unit L1I / QCU (4) The mismatch between the offset mismatch detection process and the correction process is sufficient. (B) The path from the mixer of the I signal system to the variable amplifier in the analog circuit R-AC2 by the IQ correction unit L2I / QCU, and the Q signal (1) The digital I signal L1R-ID and the digital I signal L2R-ID are sufficiently reduced by the detection processing and correction processing of the mismatch of gain, phase, and DC offset due to the path from the system mixer to the variable amplifier. Gain mismatch between and digital Q signal L1R-QD and conversion between digital Q signal L2R-QD The gain mismatch hinders the high accuracy of the demodulation operation for generating the baseband signal. In the above situations (i) to (ha), the correction mode between paths 1 and 2 is set in the AD conversion processing mode register ADCMRES. It becomes possible.

  When the conversion gain mismatch reduction due to the operation of the inter-IQ correction unit L1I / QCU or the inter-IQ correction unit L2I / QCU is insufficient, the inter-IQ correction mode is set in the AD conversion processing mode register ADCMRES as follows: There are advantages. A baseband signal is generated by reducing a conversion gain mismatch between the digital I signal L1R-ID and the digital Q signal L1R-QD and a conversion gain mismatch between the digital I signal L2R-ID and the digital Q signal L2R-QD. Therefore, it is possible to improve the accuracy of the demodulation operation.

  Note that the AD conversion units in Examples 1 to 3 of the first embodiment can be appropriately applied to the AD conversion unit of the second embodiment. In the second embodiment, the communication system handles single-phase signals, but there is no problem as a communication system handling differential signals. The AD converter correction coefficient averaging unit of the first modification of the first embodiment can be appropriately applied as a circuit connected to the digital correction units DCUIL1 & L2 and the digital correction units DCUQL1 & L2 of the second embodiment. The test signal generation circuit ADC-TSGC of Examples 4 to 6 of the first embodiment can be appropriately applied to the second embodiment as a circuit for generating the test signal ADC-TS.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

11, 21, 31, 41 AD converter (ADC)
13 AD converter for reference (RADCU)
12, 22, 42 AD converter (ADCCU)
14, 24 Digital Correction Unit (DCU)
15, 25 Error calculator (ECU)
16 divider (DIV)
SC switching circuit SW1, SW2 switch 23 DA conversion unit for reference (RDACU)
32a First AD converter (ADCU (1))
32b Second AD converter (ADCU (2))
34a, 44a First digital correction unit (DCU (1))
34b, 44b Second digital correction unit (DCU (2))
37, 47 Dither difference unit (DDU)
36, 46 Output signal addition averaging unit (OAAU)
49 Delay part (Delay)
ADCUSequence AD conversion unit sequence S Sampling period A / D1 First AD conversion period A / D1R First AD conversion result A / D2 Second AD conversion period A / D2R Second AD conversion result HFS High frequency signal ANT Antenna RFIC Semiconductor integrated circuit device BBU Baseband processing unit R-IA Analog I signal R-QA Analog Q signal R-AC Analog circuit I-ADC AD converter Q-ADC AD converter DOU Digital processing unit R-ID Digital I signal R-QD Digital Q signal T-AC Analog circuit TR-SW Transmission / reception selector switch LNA Low noise amplifier RI-MIX Mixer RQ-MIX Mixer I-FIL Filter Q-FIL Filter I-PGA Variable amplifier Q-PGA Variable amplifier PLL Phase locked loop VCO Voltage controlled oscillator CPG Clock Pulse generator L-SW Loop switch I-SC switching circuit SWI1, SWI2 Switch I-ADCU AD conversion unit DCUI & Q Digital correction unit Q-SC switching circuit SWQ1, SWQ2 Switch Q-ADCU AD conversion unit TIT Test input terminal ADC-TS Test Signal Dither1 First dither signal Dither2 Second dither signal I-ADCCC correction coefficient I-ADCCCCSRES correction coefficient setting register Q-ADCCC correction coefficient Q-ADCCCCSRES correction coefficient setting register I / QCU Inter-Q correction unit I / QCU-CSG Calibration signal Generation circuit I / QC-TS Test signal ADC-FSRES Frequency setting register ADC-PSRES Period setting register I / QC-FSRES Frequency setting register I / QC-PSRES Period setting register MRES mode setting register T-ID digital I signal I-DAC DA converter T-QD digital Q signal Q-DAC DA converter T-IA analog I signal I-LPF low-pass filter T-QA analog Q signal Q-LPF low-pass filter TI-MIX Mixer TQ-MIX Mixer T-OAU Output adding unit PA Power amplifier I-CS Calibration signal Q-CS Calibration signal II / QCUCC Correction coefficient II / QCUCCCSR Correction coefficient setting register QI / QCUCC correction coefficient I / I / QCUCCRES correction coefficient setting register CID correction digital I signal CQD correction digital Q signal ISP initial sequence period NSP, NSP2 no signal period RSP, RSP2 reception signal processing period ADC-CM ADC correction mode I / QCU-CM IQ correction mode RSPM Received signal processing mode OM Other mode I-ADCCUO AD converter output Q-ADCCUO AD converter output I-DCU Digital correction unit Q-DCU Digital correction unit ADC-CSU Correction coefficient search unit Di Digital output I / I / QDCU IQ digital correction unit Q-I / QDQ IQ digital correction unit I / QCU-CSU coefficient search unit CS-ADCU AD conversion unit NP-RA Analog signal RP-RA Analog signal NP-SW Switch RP- SW switch NP-SHC capacity RP-SHC capacity NP-CSW switch RP-CSW switch RP-SHC capacity CS-CMP comparator NPCS-N node RPCS-N node CS-CTRL control unit BCell, BCell2 bit cell DBCell, DBCell2 Dither signal bit cell C _α Dither signal capacity CA-SW1 Switch CA-SW2 Switch DC-SW3 Switch SW4a, SW4b Switch SW5a, SW5b Switch Ci Bit cell capacity MSBCell, MSBCell2 Maximum bit cell LSBCell, LSBCell2 Minimum bit cell GND Ground voltage VDD power supply voltage CRD-ADCU AD conversion unit RA analog signal CH-node charge holding node CS-SW switch CRD-CMP comparator CRD-CTRL control unit + _{V R} positive reference voltage CRD-SW1 first switch -V of _R negative Reference voltage CRD-SW2 Second switch CRD-SW3 Third switch LSB1Cell First minimum bit cell LSB2Cell Second minimum bit cell PL-ADCU Pipeline AD conversion unit Stage Stage PA-ADCU AD conversion unit DAU Dither signal addition unit PL-DACU DA conversion unit DODU Digital output difference unit SOAU Stage output amplification unit SO Stage output I-ADCCCAU correction coefficient averaging unit Q-ADCCCAU correction coefficient average SST Sampling start time SET Sampling end time ACCCSU Correction coefficient sampling part ADCCCAU Correction coefficient addition part ADCCDU Correction coefficient delay part ADCCC IU Correction coefficient integration part
ADCCCAVEEU Correction coefficient averaging unit I-ADCCCASRES Correction coefficient accuracy setting register Q-ADCCCASRES Correction coefficient accuracy setting register ADC-TSGC Test signal generation circuit DWGU Digital waveform generation unit DWGU-DAC DA converter CP Charge pump AI Analog integrator UIS Upper current Source PMOS P-type MOS transistor NMOS N-type MOS transistor BIS Lower current source OP-A Operational amplifier OPA-FC Feedback capacitor OPA-FR Feedback resistor IQADC-OAU AD converter output averaging unit CPCC Charge pump control circuit Vth1 First threshold voltage Vth2 Second threshold voltage HFS1 First high frequency signal ANT1 First antenna HFS2 Second high frequency signal ANT2 Second antenna L1R-IA Analog I signal L1R-QA Analog Q signal R -AC1 First analog circuit L2R-IA Analog I signal L2R-QA Analog Q signal R-AC2 Second analog circuit L1R-ID Digital I signal L1R-QD Digital Q signal L2R-ID Digital I signal L2R-QD Digital Q signal R -ADCU AD converter L-SC Loop switching circuit ADC-SC switching circuit L1I-ADCU AD conversion unit L1Q-ADCU AD conversion unit L2I-ADCU AD conversion unit L2Q-ADCU AD conversion unit DCUIL1 & L2 Digital correction unit DCUQL1 & L2 Digital correction unit L1I- ADCCCSRES correction coefficient setting register L2I-ADCCCSRES correction coefficient setting register L1Q-ADCCCSRES correction coefficient setting register L2Q-ADCCCSRES correction coefficient setting register L1I-ADCCC correction coefficient L2 I-ADCCC correction coefficient L1Q-ADCCC correction coefficient L2Q-ADCCC correction coefficient L1-CID correction digital I signal L1-CQD correction digital Q signal L1I / QCU IQ correction unit L2-CID correction digital I signal L2-CQD correction digital Q signal L2I / QCU IQ correction unit L1I-I / QCUCC correction coefficient L1I-I / QCUCCSRES correction coefficient setting register L1Q-I / QCUCC correction coefficient L1Q-I / QCUCCCSRES correction coefficient setting register L2I-I / QCUCC correction coefficient L2I-I / QCUCCRESS correction coefficient setting register L2Q-I / QCUCC correction coefficient L2Q-I / QCUCCRESS correction coefficient setting register

Claims (7)

A first AD converter that receives a first analog signal, performs a first digital correction process, and outputs a first digital signal;
A second AD converter that receives a second analog signal having a phase different from that of the first analog signal, performs a second digital correction process, and outputs a second digital signal;
A first correction coefficient storage circuit for storing correction coefficients for the first and second AD converters;
Receiving the first and second digital signals and correcting the first digital signal based on the phase, gain and DC offset mismatch between the first and second analog signals to generate a digital demodulated first signal; And a digital error correction circuit for correcting the second digital signal to generate a digital demodulated second signal, and a mode setting information storage circuit for storing mode information,
When the first mode is set in the mode setting information storage circuit, a first test signal is input to the first and second AD converters in common, so that the first digital correction processing is performed. A correction coefficient and a second correction coefficient for the second digital correction process are calculated,
When the second mode is set in the mode setting information storage circuit, the first AD converter converts the first analog signal to the first analog signal using the first correction coefficient stored in the first correction coefficient storage circuit. A semiconductor integrated circuit which converts the second analog signal into the second digital signal by using the second correction coefficient stored in the first correction coefficient storage circuit by the second AD converter. apparatus. The digital error correction circuit is provided with the second correction coefficient storage circuit,
When the third mode is set in the mode setting information storage circuit, the digital error correction circuit uses the third correction coefficient for the first error correction of the first digital signal and the second correction of the second digital signal. By obtaining the fourth correction coefficient for the two-error correction, the third correction coefficient and the fourth correction coefficient are stored in the second correction coefficient storage circuit,
When the second mode is set in the mode setting information storage circuit, the digital demodulation first signal and the digital demodulation second signal are used by using the third and fourth correction coefficients in the digital error correction circuit. The semiconductor integrated circuit device according to claim 1, wherein: An IQ signal generation circuit that receives an externally modulated high-frequency signal and outputs an I signal that is the first analog signal and a Q signal that is the second analog signal;
A first switching circuit that receives the I signal and the first test signal and switches between the output of the I signal and the output of the first test signal;
A second switching circuit that receives the Q signal and the first test signal and switches between the output of the Q signal and the output of the first test signal;
The first AD converter receives the I signal and outputs a third digital signal, and receives the third digital signal and performs the first digital correction process on the third digital signal. A first digital correction circuit for outputting the first digital signal;
The second AD converter receives the fourth digital signal and performs the second digital correction process on the fourth digital signal by receiving a fourth digital signal and receiving a fourth digital signal by inputting the Q signal. A second digital correction circuit for outputting the second digital signal;
When the first mode is set in the mode setting information storage circuit, the first test signal is output from the first and second switching circuits, and the first and second AD converters share the first mode. When one test signal is input, a difference output based on the difference between the first digital signal from the first digital correction unit and the second digital signal from the second digital correction unit is calculated, Based on the difference output, the first correction coefficient for the first digital correction circuit and the second correction coefficient for the second digital correction circuit are calculated,
2. The semiconductor according to claim 1, wherein when the second mode is set in the mode setting information storage circuit, the I signal is output from the first switching circuit and the Q signal is output from the second switching circuit. Integrated circuit device. The first test operation period corresponding to the first mode is assigned to an initial sequence period for performing various initial settings of the semiconductor integrated circuit device itself and calibrating the IQ signal generation circuit,
A normal operation period for converting the high-frequency signal into a baseband signal corresponding to the second mode is provided after the initial sequence period,
4. The semiconductor integrated circuit device according to claim 3, wherein there are a plurality of second test operation periods corresponding to the third mode, and each of the plurality of second test operation periods is provided before each of the plurality of normal operation periods. . The first test operation period and the second test operation period are also assigned to a no-signal period in which the input of the high-frequency signal from the outside is interrupted,
The no-signal period and the normal operation period are alternately repeated periodically.
5. The semiconductor integrated circuit device according to claim 4, wherein the second test operation period exists between the first test operation period and the normal operation period.   6. The semiconductor integrated circuit device according to claim 5, further comprising a period setting storage circuit that sets an occurrence frequency and a length of each of the first test operation period and the second test operation period.   The period setting storage circuit can set how long the first test operation period is in the initial sequence period, and whether there is the first test operation period for each non-signal period. It is possible to set whether there is the first test operation period for each non-signal period (N is a natural number of 2 or more), and how long the first test operation period is in the non-signal period. It is possible to set whether there is the second test operation period for each non-signal period or whether there is the second test operation period for each of the N non-signal periods. The semiconductor integrated circuit device according to claim 6, wherein a length of the second test operation period can be set.

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