JP2015230987A - Compound semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve a highly reliable and high-withstand-voltage compound semiconductor device which has a comparatively simple configuration in the compound semiconductor device having both of a Schottky structure and an MIS structure.SOLUTION: A compound semiconductor device includes: a compound semiconductor layer 2; and a gate electrode 7 formed upward of the compound semiconductor layer 2. The gate electrode 7 includes: a first portion 7A which is in Schottky contact with the surface of the compound semiconductor layer 2; and a second portion 7Ba which embeds a recess 2C formed on the surface of the compound semiconductor layer 2 via an insulation film 6.

Description

  The present invention relates to a compound semiconductor device and a manufacturing method thereof.

  Nitride semiconductors have been studied for application to high breakdown voltage and high output semiconductor devices utilizing characteristics such as high saturation electron velocity and wide band gap. For example, the band gap of GaN that is a nitride semiconductor is 3.4 eV, which is larger than the band gap of Si (1.1 eV) and the band gap of GaAs (1.4 eV), and has a high breakdown electric field strength. Therefore, GaN is extremely promising as a material for a semiconductor device for a power supply that obtains high voltage operation and high output.

  As semiconductor devices using nitride semiconductors, many reports have been made on field effect transistors, particularly high electron mobility transistors (HEMTs). For example, in a GaN-based HEMT (GaN-HEMT), AlGaN / GaN.HEMT using GaN as an electron transit layer and AlGaN as an electron supply layer has attracted attention. In AlGaN / GaN.HEMT, strain caused by the difference in lattice constant between GaN and AlGaN is generated in AlGaN. A high-concentration two-dimensional electron gas (2DEG) is obtained by the piezoelectric polarization generated thereby and the spontaneous polarization of AlGaN. Therefore, it is expected as a high-efficiency power device for high-efficiency switching elements, electric vehicles and the like.

JP 2008-166469 A JP 2011-181922 A

  In a semiconductor device using a nitride semiconductor, research and development of a semiconductor device with higher withstand voltage and higher reliability is underway in order to cope with an increase in operating voltage expected in the future as well as high-frequency characteristics.

  For example, a GaN-HEMT having an overhanging T-shaped gate electrode that embeds an opening formed in an insulating film on a substrate has been developed. In this GaN-HEMT, the fine gate portion of the gate electrode comes into Schottky contact with the substrate to form a Schottky structure. At the same time, an insulating film is interposed between the overgate portion of the gate electrode and the substrate, and the overgate portion has a MIS (Metal-Insulator-Semiconductor) structure. That is, the GaN-HEMT has a Schottky structure at the fine gate portion of the gate electrode and an MIS structure at the over gate portion.

  In the T-shaped gate electrode, it has been found that the overgate portion having the MIS structure tends to have a deeper threshold (the threshold value shifts in the negative direction) than the fine gate portion having the Schottky structure. . During device operation, the depletion layer is not formed better as the threshold value of the overgate portion is deeper. Therefore, a sufficient off-effect cannot be obtained, and the electric field stress received at the end of the fine gate portion is increased due to the influence, and breakage / destruction is likely to occur. As a result, low breakdown voltage is caused and reliability is lowered, which is regarded as a problem.

  The present invention has been made in view of the above problems, and in a compound semiconductor device having both a Schottky structure and an MIS structure, a highly reliable compound semiconductor device having a relatively simple structure and high reliability, and a method for manufacturing the compound semiconductor device. The purpose is to provide.

  One aspect of the compound semiconductor device includes a compound semiconductor layer and an electrode formed above the compound semiconductor layer, the electrode being in a Schottky contact with the surface of the compound semiconductor layer, and And a second portion embedded in the concave portion formed on the surface of the compound semiconductor layer with an insulating film interposed therebetween.

One aspect of a method for manufacturing a compound semiconductor device includes a step of forming a recess on a surface of the compound semiconductor layer, a step of forming an insulating film on the compound semiconductor layer so as to cover an inner wall of the recess,
Removing a part of the insulating film to expose a part of the surface of the compound semiconductor layer adjacent to the recess; and embedding the recess through the insulating film; Forming an electrode above the compound semiconductor layer so as to cover a part of the surface.

  According to the above aspects, in a compound semiconductor device having both a Schottky structure and an MIS structure, a highly reliable compound semiconductor device with a relatively simple structure and high reliability is realized.

It is a schematic sectional drawing which shows the manufacturing method of AlGaN / GaN * HEMT by 1st Embodiment to process order. FIG. 2 is a schematic cross-sectional view illustrating the AlGaN / GaN HEMT manufacturing method according to the first embodiment in the order of steps, following FIG. 1. FIG. 3 is a schematic cross-sectional view illustrating the AlGaN / GaN HEMT manufacturing method according to the first embodiment in the order of steps, following FIG. 2. It is a characteristic view which shows the relationship between the thickness of the insulating film (SiN) in a MIS structure, and a threshold value. It is a schematic sectional drawing which shows the main processes of the manufacturing method of AlGaN / GaN * HEMT by 2nd Embodiment. It is a connection diagram which shows schematic structure of the power supply device by 3rd Embodiment. It is a connection diagram which shows schematic structure of the high frequency amplifier by 4th Embodiment.

(First embodiment)
In this embodiment, a nitride semiconductor AlGaN / GaN HEMT is disclosed as a compound semiconductor device.
1 to 3 are schematic cross-sectional views showing the method of manufacturing the AlGaN / GaN HEMT according to the first embodiment in the order of steps.

First, as shown in FIG. 1A, a compound semiconductor multilayer structure 2 is formed on, for example, a Si substrate 1 as a growth substrate. As the growth substrate, an SiC substrate, a sapphire substrate, a GaAs substrate, a GaN substrate, or the like may be used instead of the Si substrate. Further, the conductivity of the substrate may be semi-insulating or conductive.
The compound semiconductor multilayer structure 2 includes a buffer layer 2a, an electron transit layer 2b, an intermediate layer 2c, an electron supply layer 2d, and a cap layer 2e.

  In the completed AlGaN / GaN HEMT, two-dimensional electron gas (2DEG) is generated near the interface between the electron transit layer 2b and the electron supply layer 2d (more precisely, the intermediate layer 2c) during the operation. This 2DEG is generated based on the difference in lattice constant between the compound semiconductor (here, GaN) of the electron transit layer 2b and the compound semiconductor (here, AlGaN) of the electron supply layer 2d.

Specifically, the following compound semiconductors are grown on the Si substrate 1 by, for example, metal organic vapor phase epitaxy (MOVPE). Instead of the MOVPE method, a molecular beam epitaxy (MBE) method or the like may be used.
On the Si substrate 1, AlN is about 5 nm thick, i (Intensive Undoped) -GaN is about 1 μm thick, i-AlGaN is about 5 nm thick, and n-AlGaN is about 30 nm thick. , N-GaN is sequentially grown to a thickness of about 3 nm. Thereby, the buffer layer 2a, the electron transit layer 2b, the intermediate layer 2c, the electron supply layer 2d, and the cap layer 2e are formed. As the buffer layer 2a, AlGaN may be used instead of AlN, or GaN may be grown at a low temperature.

As growth conditions for AlN, a mixed gas of trimethylaluminum (TMA) gas and ammonia (NH ₃ ) gas is used as a source gas. As a growth condition for GaN, a mixed gas of trimethylgallium (TMG) gas and NH ₃ gas is used as a source gas. As growth conditions for AlGaN, a mixed gas of TMA gas, TMG gas, and NH ₃ gas is used as a source gas. The presence / absence and flow rate of trimethylaluminum gas as an Al source and trimethylgallium gas as a Ga source are appropriately set according to the compound semiconductor layer to be grown. The flow rate of ammonia gas, which is a common raw material, is about 100 ccm to 10 LM. The growth pressure is about 50 Torr to 300 Torr, and the growth temperature is about 1000 ° C. to 1200 ° C.

When growing GaN and AlGaN as n-type, for example, SiH ₄ gas containing Si as an n-type impurity is added to the source gas at a predetermined flow rate, and Si is doped into GaN and AlGaN. The doping concentration of Si is about 1 × 10 ¹⁸ / cm ^{3 to} about 1 × 10 ²⁰ / cm ³ , for example, about 5 × 10 ¹⁸ / cm ³ .

Subsequently, as shown in FIG. 1B, an element isolation structure 3 is formed. In FIG. 2A and subsequent figures, illustration of the element isolation structure 3 is omitted.
Specifically, for example, argon (Ar) is implanted into the element isolation region of the compound semiconductor multilayer structure 2. Thereby, the element isolation structure 3 is formed in the compound semiconductor multilayer structure 2 and the surface layer portion of the Si substrate 1. An active region is defined on the compound semiconductor stacked structure 2 by the element isolation structure 3.
The element isolation may be performed by using, for example, an STI (Shallow Trench Isolation) method instead of the above-described implantation method. At this time, for example, a chlorine-based etching gas is used for the dry etching of the compound semiconductor multilayer structure 2.

Subsequently, as shown in FIG. 1C, the source electrode 4 and the drain electrode 5 are formed.
Specifically, first, electrode recesses 2 </ b> A and 2 </ b> B are formed at the planned formation positions (electrode formation planned positions) of the source electrode and the drain electrode on the surface of the compound semiconductor multilayer structure 2.
A resist is applied to the surface of the compound semiconductor multilayer structure 2. The resist is processed by lithography, and an opening that exposes the surface of the compound semiconductor multilayer structure 2 corresponding to the electrode formation planned position is formed in the resist. Thus, a resist mask having the opening is formed.

Using this resist mask, the electrode formation planned position of the cap layer 2e is removed by dry etching until the surface of the electron supply layer 2d is exposed. As a result, electrode recesses 2A and 2B that expose the electrode formation scheduled position on the surface of the electron supply layer 2d are formed. As an etching condition, using a chlorine-based gas of the inert gas and Cl ₂ and the like such as Ar as an etching gas, for example, Cl ₂ flow rate 30 sccm, 2 Pa pressure, the RF input power and 20W. The electrode recesses 2A and 2B may be formed by etching partway through the cap layer 2e, or may be formed by etching up to the electron supply layer 2d.
The resist mask is removed by ashing or the like.

A resist mask for forming the source electrode and the drain electrode is formed. Here, for example, a two-layer resist having a cage structure suitable for the vapor deposition method and the lift-off method is used. This resist is applied onto the compound semiconductor multilayer structure 2 to form openings for exposing the electrode recesses 2A and 2B. Thus, a resist mask having the opening is formed.
Using this resist mask, Ta / Al, for example, is deposited as an electrode material on the resist mask including the inside of the opening exposing the electrode recesses 2A and 2B, for example, by vapor deposition. The thickness of Ta is about 20 nm, and the thickness of Al is about 200 nm. The resist mask and Ta / Al deposited thereon are removed by a lift-off method. Thereafter, the Si substrate 1 is heat-treated in a nitrogen atmosphere, for example, at a temperature of about 400 ° C. to 1000 ° C., for example, about 600 ° C., and the remaining Ta / Al is brought into ohmic contact with the electron supply layer 2d. If an ohmic contact with the Ta / Al electron supply layer 2d is obtained, heat treatment may be unnecessary. Thus, the source electrode 4 and the drain electrode 5 are formed in which the electrode recesses 2A and 2B are embedded with a part of the electrode material.

Subsequently, as shown in FIG. 2A, an electrode recess 2 </ b> C for the gate electrode is formed in the compound semiconductor multilayer structure 2.
Specifically, first, a resist is applied to the surface of the compound semiconductor multilayer structure 2. The resist is processed by lithography, and an opening is formed in the resist to expose the surface of the compound semiconductor multilayer structure 2 corresponding to the gate electrode formation planned position (electrode formation planned position). Thus, a resist mask having the opening is formed.

Using this resist mask, parts of the cap layer 2e and the electron supply layer 2d at the electrode formation scheduled position are removed by dry etching. As a result, the electrode recess 2C dug from the surface of the cap layer 2e to a part of the electron supply layer 2d is formed. As an etching condition, using a chlorine-based gas of the inert gas and Cl ₂ and the like such as Ar as an etching gas, for example, Cl ₂ flow rate 30 sccm, 2 Pa pressure, the RF input power and 20W. The electrode recess 2C needs to be formed so that its bottom surface is positioned above 2DEG so as not to block a part of 2DEG.
The resist mask is removed by ashing or the like.

Subsequently, as shown in FIG. 2B, a protective insulating film 6 is formed.
Specifically, for example, SiN is deposited as an insulating material on the compound semiconductor multilayer structure 2 so as to cover the inner wall surface of the electrode recess 2C. SiN is deposited by a CVD method, for example, to a film thickness of about 20 nm to 60 nm, here about 40 nm. Thereby, the protective insulating film 6 for protecting the surface of the compound semiconductor multilayer structure 2 and forming the T-shaped gate electrode is formed.

Subsequently, as shown in FIG. 2C, an opening 6 a is formed in the protective insulating film 6.
Specifically, the protective insulating film 6 is processed by lithography and dry etching. Thus, an opening 6a is formed in the protective insulating film 6 so as to be adjacent to the side surface on the source electrode 4 side of the electrode recess 2C and to expose a part of the surface of the protective insulating film 6. At this time, the protective insulating film 6 is also removed from the upper portion of the side surface of the electrode recess 2C on the source electrode 4 side, and remains up to substantially the same height as the side surface of the electrode recess 2C on the source electrode 4 side. In this case, the removed portion of the protective insulating film 6 also becomes a part of the opening 6a.

Subsequently, as shown in FIG. 3A, the portion of the protective insulating film 6 on the bottom surface of the electrode recess 2C is thinned.
Specifically, first, a resist is applied to the surface of the compound semiconductor multilayer structure 2. The resist is processed by lithography, and an opening 11a that exposes a portion of the bottom surface of the electrode recess 2C of the protective insulating film 6 is formed in the resist. Thus, the resist mask 11 having the opening 11a is formed.

Using the resist mask 11, the portion of the protective insulating film 6 exposed from the opening 11 on the bottom surface of the electrode recess 2C is thinned by dry etching. The thinned portion of the protective insulating film 6 is referred to as a thinned portion 6b. In the present embodiment, the thinned portion 6b is thinner than the other portions of the protective insulating film 6, and is adjusted to a thickness of about 5 nm to 20 nm, for example, about 15 nm.
The resist mask 11 is removed by ashing or the like.

Subsequently, as shown in FIG. 3B, a gate electrode 7 is formed.
Specifically, first, a resist mask for forming a gate is formed.
Each of the lower layer resist and the upper layer resist is applied and formed on the entire surface by, eg, spin coating. Openings are formed in the upper resist by ultraviolet exposure. Next, using the upper layer resist as a mask, the lower layer resist is wet-etched with an alkaline developer to form an opening in the lower layer resist. As described above, a resist mask composed of the lower layer resist having an opening and the upper layer resist having an opening is formed. In this resist mask, an opening formed by connecting two openings is defined as a communication opening.

Next, the gate electrode 7 is formed.
Specifically, gate metal (Ni: film thickness of about 10 nm / Au: film thickness of about 300 nm) is deposited on the entire surface including the inside of the communication opening using the resist mask as a mask. As a result, the opening 6a of the protective insulating film 6 is buried with the gate metal in Schottky contact with the surface of the compound semiconductor multilayer structure 2, and the electrode recess 2C is buried with the gate metal via the protective insulating film 6. Is formed.
The resist mask is removed by a lift-off method by infiltrating the Si substrate 1 together with unnecessary gate metal into N-methyl-pyrrolidinone heated to 80 ° C., for example.

  The gate electrode 7 is an overhanging T-shaped gate electrode in which a lower fine gate portion 7A and an upper overgate portion 7B are integrally formed. The fine gate portion 7A is a first portion, and fills the opening 6a of the protective insulating film 6 with gate metal to form a Schottky structure. The over gate portion 7B has a buried portion 7Ba which is a second portion buried in the electrode recess 2C with a gate metal through the protective insulating film 6, and is wider above the fine gate portion 7A. It is formed. The over gate portion 7B forms a MIS structure via the compound semiconductor multilayer structure 2 and the protective insulating film 6 on the source electrode 4 side, and the buried portion 7Ba includes the compound semiconductor multilayer structure 2 and the thinned portion 6b on the drain electrode 5 side. A MIS structure is formed.

  After that, the AlGaN / GaN HEMT according to the present embodiment is formed through various processes such as formation of wirings connected to the source electrode 4, the drain electrode 5, and the gate electrode 7.

  In an AlGaN / GaN HEMT having a conventional T-shaped gate electrode, the threshold value is deeper in the overgate portion having the MIS structure than in the fine gate portion having the Schottky structure. For this reason, the depletion layer generated under the MIS structure is extremely shallow and insufficient as compared with the depletion layer generated in the Schottky structure, and the Schottky structure is not assisted by the depletion layer of the MIS structure by a threshold difference when a negative bias voltage is applied. All electric fields will be received. As a result, compared to the end portion on the drain electrode side of the over gate portion, an extremely strong electric field concentration occurs at the end portion on the drain electrode side of the fine gate portion.

  In the present embodiment, the over-gate portion 7B of the T-shaped gate electrode 7 has, on the drain electrode 5 side, an embedded portion 7Ba in which the electrode recess 2C formed in the compound semiconductor multilayer structure 2 is embedded with gate metal. Yes. In this configuration, the depletion layer generated under the MIS structure extends and deepens due to the presence of the embedded portion 7Ba, and 2DEG is reliably reduced at the site under the MIS structure. As a result, the threshold difference between the Schottky structure and the MIS structure is reduced, and the electric field concentration is distributed to the end of the overgate portion on the drain electrode side, and is correspondingly relaxed at the end of the fine gate portion on the drain electrode side. The As a result, off-leakage and gate leakage are reduced, and a highly reliable high breakdown voltage AlGaN / GaN HEMT is realized.

  Furthermore, in this embodiment, the protective insulating film 6 is thinner than the other portions in the portion on the bottom surface of the electrode recess 2C. As shown in FIG. 4, the thinner the thinned portion 6b of the protective insulating film 6, the shallower the threshold of the MIS structure (the threshold shifts in the positive direction). Therefore, the threshold difference between the Schottky structure and the MIS structure is reduced, and the electric field concentration is relaxed, which contributes to higher reliability and higher breakdown voltage.

  As described above, in the present embodiment, a highly reliable device configuration with a high reliability and a relatively simple configuration is realized in the AlGaN / GaN HEMT having both the Schottky structure and the MIS structure.

(Second Embodiment)
The present embodiment discloses an AlGaN / GaN HEMT configuration and manufacturing method as in the first embodiment, but differs in the configuration of the gate electrode. In addition, about the same thing as the structural member of 1st Embodiment, the same code | symbol is attached | subjected and detailed description is abbreviate | omitted.
FIG. 5 is a schematic cross-sectional view showing the main steps of the AlGaN / GaN HEMT manufacturing method according to the second embodiment.

  In the present embodiment, as in the first embodiment, first, the steps of FIGS. 1A to 2B are performed. At this time, the protective insulating film 6 for protecting the surface of the compound semiconductor multilayer structure 2 and forming a T-shaped gate electrode is formed.

Subsequently, as illustrated in FIG. 5A, an opening 6 c is formed in the protective insulating film 6.
Specifically, the protective insulating film 6 is processed by lithography and dry etching. Thus, an opening 6c is formed in the protective insulating film 6 so as to be adjacent to the side surface on the source electrode 4 side of the electrode recess 2C and to expose a part of the surface of the protective insulating film 6. At this time, in the protective insulating film 6, the upper part of the side surface on the source electrode 4 side of the electrode recess 2C remains, and the upper part protrudes from the upper end of the side surface.

Subsequently, as shown in FIG. 5B, the portion of the protective insulating film 6 on the bottom surface of the electrode recess 2C is thinned.
Specifically, first, a resist is applied to the surface of the compound semiconductor multilayer structure 2. The resist is processed by lithography, and an opening 11a that exposes a portion of the bottom surface of the electrode recess 2C of the protective insulating film 6 is formed in the resist. Thus, the resist mask 11 having the opening 11a is formed.

Using the resist mask 11, the portion of the protective insulating film 6 exposed from the opening 11 on the bottom surface of the electrode recess 2C is thinned by dry etching. The thinned portion of the protective insulating film 6 is referred to as a thinned portion 6b. In the present embodiment, the thinned portion 6b is thinner than the other portions of the protective insulating film 6, and is adjusted to a thickness of about 5 nm to 20 nm, for example, about 15 nm.
The resist mask 11 is removed by ashing or the like.

Subsequently, as shown in FIG. 5C, the gate electrode 12 is formed.
Specifically, first, a resist mask for forming a gate is formed.
Each of the lower layer resist and the upper layer resist is applied and formed on the entire surface by, eg, spin coating. Openings are formed in the upper resist by ultraviolet exposure. Next, using the upper layer resist as a mask, the lower layer resist is wet-etched with an alkaline developer to form an opening in the lower layer resist. As described above, a resist mask composed of the lower layer resist having an opening and the upper layer resist having an opening is formed. In this resist mask, an opening through which two openings communicate is defined as a communication opening.

Next, the gate electrode 12 is formed.
Specifically, gate metal (Ni: film thickness of about 10 nm / Au: film thickness of about 300 nm) is deposited on the entire surface including the inside of the communication opening using the resist mask as a mask. As a result, the opening 6 c of the protective insulating film 6 is buried with the gate metal in Schottky contact with the surface of the compound semiconductor multilayer structure 2 and the electrode recess 2 C is buried with the gate metal via the protective insulating film 6. Is formed.
The resist mask is removed by a lift-off method by infiltrating the Si substrate 1 together with unnecessary gate metal into N-methyl-pyrrolidinone heated to 80 ° C., for example.

  The gate electrode 12 is an overhanging T-shaped gate electrode in which a lower fine gate portion 12A and an upper overgate portion 12B are integrally formed. The fine gate portion 12A is a first portion and has a Schottky structure in which the opening 6a of the protective insulating film 6 is filled with gate metal. The over gate portion 12B has a buried portion 12Ba which is a second portion buried in the electrode recess 2C with the gate metal through the protective insulating film 6, and is wider above the fine gate portion 12A. It is formed. The overgate portion 12B forms a MIS structure via the compound semiconductor multilayer structure 2 and the protective insulating film 6 on the source electrode 4 side, and the buried portion 12Ba includes the compound semiconductor multilayer structure 2 and the thinned portion 6b on the drain electrode 5 side. Through the MIS structure.

  In this embodiment, the over-gate portion 12B of the T-shaped gate electrode 12 has a buried portion 12Ba in which the electrode recess 2C formed in the compound semiconductor multilayer structure 2 is embedded with the gate metal on the drain electrode 5 side. Yes. In this configuration, the depletion layer generated under the MIS structure extends and deepens due to the presence of the embedded portion 12Ba, and 2DEG is reliably reduced at the site under the MIS structure. As a result, the threshold difference between the Schottky structure and the MIS structure is reduced, and the electric field concentration is distributed to the end of the overgate portion on the drain electrode side, and is correspondingly relaxed at the end of the fine gate portion on the drain electrode side. The As a result, off-leakage and gate leakage are reduced, and a highly reliable high breakdown voltage AlGaN / GaN HEMT is realized.

  Furthermore, in this embodiment, the protective insulating film 6 is thinner than the other portions in the portion on the bottom surface of the electrode recess 2C. As the thickness of the thinned portion 6b of the protective insulating film 6 becomes thinner, the threshold value of the MIS structure becomes shallower (the threshold value shifts in the positive direction). Therefore, the threshold difference between the Schottky structure and the MIS structure is reduced, and the electric field concentration is relaxed, which contributes to higher reliability and higher breakdown voltage.

  Furthermore, in the present embodiment, the protective insulating film 6 has the upper portion of the side surface on the source electrode 4 side of the electrode recess 2C remaining, and the upper portion protrudes from the upper end of the side surface. In the gate electrode 12, the fine gate portion 12A and the embedded portion 12Ba of the overgate portion 12B are separated by the upper portion, and the two are distinguished from each other by the upper portion. With this configuration, the opening 6c of the protective insulating film 6 is surely secured to the intended size due to the presence of the upper portion, and the fine gate portion 12A can be formed with a width almost as designed.

  As described above, in the present embodiment, a highly reliable device configuration with a high reliability and a relatively simple configuration is realized in the AlGaN / GaN HEMT having both the Schottky structure and the MIS structure.

(Third embodiment)
In the present embodiment, a power supply device to which one kind of AlGaN / GaN HEMT selected from the first and second embodiments is applied is disclosed.
FIG. 6 is a connection diagram illustrating a schematic configuration of the power supply device according to the third embodiment.

The power supply device according to the present embodiment includes a high-voltage primary circuit 21 and a low-voltage secondary circuit 22, and a transformer 23 disposed between the primary circuit 21 and the secondary circuit 22. The
The primary circuit 21 includes an AC power supply 24, a so-called bridge rectifier circuit 25, and a plurality (four in this case) of switching elements 26a, 26b, 26c, and 26d. The bridge rectifier circuit 25 includes a switching element 26e.
The secondary side circuit 22 includes a plurality of (here, three) switching elements 27a, 27b, and 27c.

  In the present embodiment, the switching elements 26a, 26b, 26c, 26d, and 26e of the primary circuit 41 are one type of AlGaN / GaN HEMT selected from the first and second embodiments. On the other hand, the switching elements 27a, 27b, and 27c of the secondary circuit 22 are normal MIS • FETs using silicon.

  In the present embodiment, an AlGaN / GaN HEMT having a relatively simple structure and high reliability is applied to a high voltage circuit in an AlGaN / GaN HEMT having both a Schottky structure and an MIS structure. As a result, a highly reliable high-power power supply circuit is realized.

(Fourth embodiment)
In the present embodiment, a high-frequency amplifier to which one kind of AlGaN / GaN HEMT selected from the first and second embodiments is applied is disclosed.
FIG. 7 is a connection diagram illustrating a schematic configuration of the high-frequency amplifier according to the fourth embodiment.

The high-frequency amplifier according to the present embodiment includes a digital predistortion circuit 31, mixers 32a and 32b, and a power amplifier 33.
The digital predistortion circuit 31 compensates for nonlinear distortion of the input signal. The mixer 32a mixes an input signal with compensated nonlinear distortion and an AC signal. The power amplifier 33 amplifies the input signal mixed with the AC signal, and has one type of AlGaN / GaN HEMT selected from the first and second embodiments. In FIG. 7, for example, by switching the switch, the output side signal is mixed with the AC signal by the mixer 32 b and sent to the digital predistortion circuit 31.

  In the present embodiment, an AlGaN / GaN HEMT having a relatively simple structure and high reliability is applied to a high-frequency amplifier in an AlGaN / GaN HEMT having both a Schottky structure and an MIS structure. As a result, a high-reliability, high-voltage high-frequency amplifier is realized.

(Other embodiments)
In the first to fourth embodiments, AlGaN / GaN.HEMT is exemplified as the compound semiconductor device. As a compound semiconductor device, besides the AlGaN / GaN.HEMT, the following HEMT can be applied.

・ Other HEMT examples 1
In this example, InAlN / GaN.HEMT is disclosed as a compound semiconductor device.
InAlN and GaN are compound semiconductors that can have a lattice constant close to the composition. In this case, in the first to fourth embodiments described above, the electron transit layer is formed of i-GaN, the intermediate layer is formed of i-InAlN, the electron supply layer is formed of n-InAlN, and the cap layer is formed of n-GaN. In this case, since the piezoelectric polarization hardly occurs, the two-dimensional electron gas is mainly generated by the spontaneous polarization of InAlN.

  According to this example, in the AlGaN / GaN HEMT having both the Schottky structure and the MIS structure, similar to the AlGaN / GaN HEMT described above, a highly reliable InAlN / GaN. HEMT is realized.

・ Other HEMT examples 2
In this example, InAlGaN / GaN.HEMT is disclosed as a compound semiconductor device.
GaN and InAlGaN are compound semiconductors in which the latter can make the lattice constant smaller by the composition than the former. In this case, in the first to fourth embodiments described above, the electron transit layer is formed of i-GaN, the intermediate layer is formed of i-InAlGaN, the electron supply layer is formed of n-InAlGaN, and the cap layer is formed of n-GaN.

  According to this example, similarly to the AlGaN / GaN HEMT described above, in the AlGaN / GaN HEMT having both the Schottky structure and the MIS structure, the InAlGaN / GaN. HEMT is realized.

  Hereinafter, various aspects of the compound semiconductor device, the manufacturing method thereof, the power supply device, and the high-frequency amplifier will be collectively described as appendices.

(Appendix 1) a compound semiconductor layer;
An electrode formed above the compound semiconductor layer,
The electrode has a first portion that is in Schottky contact with the surface of the compound semiconductor layer, and a second portion that fills a recess formed in the surface of the compound semiconductor layer with an insulating film interposed therebetween. Compound semiconductor device.

  (Supplementary note 2) The compound semiconductor device according to supplementary note 1, wherein a portion of the insulating film formed on the bottom surface of the concave portion is thinner than other portions.

  (Supplementary Note 3) The insulating film is formed such that a portion separating the first portion and the second portion is formed at the same height as a portion in contact with the first portion of the compound semiconductor layer. The compound semiconductor device according to appendix 1 or 2, which is characterized.

  (Additional remark 4) The said insulating film has projected the upper part rather than the part which contacts the said 1st part of the said compound semiconductor layer, and the part which separates the said 1st part and the said 2nd part is characterized by the above-mentioned. The compound semiconductor device according to appendix 1 or 2,

(Additional remark 5) The process of forming a recessed part in the surface of a compound semiconductor layer,
Forming an insulating film on the compound semiconductor layer so as to cover the inner wall of the recess;
Removing a part of the insulating film to expose a part of the surface of the compound semiconductor layer adjacent to the recess;
And forming the electrode above the compound semiconductor layer so as to cover the part of the exposed surface of the compound semiconductor layer while embedding the recess through the insulating film. Device manufacturing method.

  (Additional remark 6) After the process of removing a part of said insulating film, it further includes the process of thinning the part formed on the bottom face of the said recessed part of the said insulating film before the process of forming the said electrode. Item 6. The method for manufacturing a compound semiconductor device according to appendix 5.

  (Supplementary Note 7) In the step of removing a part of the insulating film, a part of the surface of the compound semiconductor layer is exposed, and the concave portion of the insulating film is formed so as to have the same height as the part of the surface. The method for manufacturing a compound semiconductor device according to appendix 5 or 6, wherein a portion protruding from the side surface is removed.

  (Appendix 8) In the step of removing a part of the insulating film, the insulating film is left so as to protrude from one side surface of the recess adjacent to a part of the exposed surface of the compound semiconductor layer. The manufacturing method of the compound semiconductor device of Additional remark 5 or 6 to do.

(Supplementary note 9) A power supply circuit including a transformer and a high-voltage circuit and a low-voltage circuit across the transformer,
The high-voltage circuit has a transistor,
The transistor is
A compound semiconductor layer;
An electrode formed above the compound semiconductor layer,
The electrode has a first portion that is in Schottky contact with the surface of the compound semiconductor layer, and a second portion that fills a recess formed in the surface of the compound semiconductor layer with an insulating film interposed therebetween. Power supply circuit.

(Appendix 10) A high frequency amplifier that amplifies and outputs an input high frequency voltage,
Has a transistor,
The transistor is
A compound semiconductor layer;
An electrode formed above the compound semiconductor layer,
The electrode has a first portion that is in Schottky contact with the surface of the compound semiconductor layer, and a second portion that fills a recess formed in the surface of the compound semiconductor layer with an insulating film interposed therebetween. High frequency amplifier.

DESCRIPTION OF SYMBOLS 1 Si substrate 2 Compound semiconductor laminated structure 2a Buffer layer 2b Electron travel layer 2c Intermediate layer 2d Electron supply layer 2e Cap layer 2A, 2B, 2C Electrode recess 3 Element isolation structure 4 Source electrode 5 Drain electrode 6 Protective insulating films 6a, 6c , 11a Opening 6b Thinned portion 7, 12 Gate electrode 7A, 12A Fine gate portion 7B, 12B Over gate portion 7Ba, 12Ba Embedded portion 11 Resist mask 21 Primary side circuit 22 Secondary side circuit 23 Transformer 24 AC power supply 25 Bridge rectifier circuit 26a, 26b, 26c, 26d, 26e, 27a, 27b, 27c Switching element 31 Digital predistortion circuit 32a, 32b Mixer 33 Power amplifier

Claims (8)

A compound semiconductor layer;
An electrode formed above the compound semiconductor layer,
The electrode has a first portion that is in Schottky contact with the surface of the compound semiconductor layer, and a second portion that fills a recess formed in the surface of the compound semiconductor layer with an insulating film interposed therebetween. Compound semiconductor device.   2. The compound semiconductor device according to claim 1, wherein a portion of the insulating film formed on the bottom surface of the recess is thinner than other portions.   The insulating film is formed such that a portion separating the first portion and the second portion is formed at the same height as a portion in contact with the first portion of the compound semiconductor layer. Item 3. The compound semiconductor device according to Item 1 or 2.   2. The insulating film is characterized in that a portion separating the first portion and the second portion protrudes upward from a portion in contact with the first portion of the compound semiconductor layer. Or the compound semiconductor device of 2. Forming a recess in the surface of the compound semiconductor layer;
Forming an insulating film on the compound semiconductor layer so as to cover the inner wall of the recess;
Removing a part of the insulating film to expose a part of the surface of the compound semiconductor layer adjacent to the recess;
And forming the electrode above the compound semiconductor layer so as to cover the part of the exposed surface of the compound semiconductor layer while embedding the recess through the insulating film. Device manufacturing method.   The method further includes a step of thinning a portion of the insulating film formed on the bottom surface of the recess after the step of removing a part of the insulating film and before the step of forming the electrode. A method for manufacturing a compound semiconductor device according to claim 5.   In the step of removing a part of the insulating film, a part of the surface of the compound semiconductor layer is exposed and protrudes from one side surface of the recess of the insulating film so as to have the same height as the part of the surface. 7. The method of manufacturing a compound semiconductor device according to claim 5, wherein the portion is removed.   6. The step of removing a part of the insulating film leaves the insulating film so as to protrude from one side surface of the recess adjacent to a part of the exposed surface of the compound semiconductor layer. Or the manufacturing method of the compound semiconductor device of 6.

Images