JP2015228588A - Video processing apparatus, control method of the same, and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a video processing apparatus and a video processing method, capable of preventing increase of an unnecessary memory capacity and a memory band.SOLUTION: A video processing apparatus 10 is so configured that an input part 11, with respect to an input video signal, selectively performs a plurality of video processing functions such as a selection function for outputting to a first video processing part 12, a function for combining a plurality of divided input video signals, and a function for serializing the input video signals, and selects video processing of accessing in accordance with a desired video processing function, and, on the basis of the selected video processing, the first video processing part 12, a layout part 13, and a second video processing part 14 perform video processing through a memory 16.

Description

  The present invention relates to a video processing apparatus that writes an intermediate frame to a memory at the time of video processing, and more particularly to a control technique for changing a place where a synchronization timing is replaced according to video processing to be performed.

  2. Description of the Related Art In recent years, there are cases where a video processing apparatus performs a plurality of different processes using the same video processing processor as the development cost of video processing LSI (Large Scale Integration) increases. For example, there is a case where one video processing apparatus performs video processing using the same video processing LSI in order to provide video to different output devices such as a liquid crystal monitor and a projector. In this case, the video processing apparatus is suitable for each output device using the same LSI by switching between video processing common to each output device and separate video processing according to the characteristics of the output device. Video processing can be performed. For example, when the output device is a projector, the video processing apparatus performs a geometric deformation process for deforming the output video according to the shape of the projection target. However, when the output device is a liquid crystal monitor, such a process is necessary. do not do. Conversely, when the output device is a liquid crystal monitor, the video processing device performs backlight control processing according to the display characteristics for each region, but when the output device is a projector, such processing is not necessary. As described above, the video processing apparatus realizes commonality of LSIs by switching processing for each target output device.

  Further, as the resolution of the display panel of the output device is increased, the memory bandwidth required for video processing in one video processing device is increasing. For example, consider a case where the display resolution is expanded from Full-HD (Full-High-Definition: 1920 × 1080 pixels) to 4K2K (4096 × 2160 pixels). In this case, when the video processing apparatus performs processing using the same LSI, a memory band slightly more than four times is required. Thus, the memory bandwidth required for video processing in the video processing device is increasing.

  In addition, with the improvement of the resolution of the display panel of the output device and the enhancement of the video processing of the video processing device, there is also a function for laying out a plurality of input video signals on one screen on one video processing device. Often installed. For example, Patent Document 1 proposes an apparatus that temporarily stores a plurality of frame data (input signals) in a memory and combines them into one screen in accordance with the timing output from the timing generation unit. According to Japanese Patent Application Laid-Open No. 2004-228620, image synthesis with reduced frequency of frame skipping (frame dropping) is realized when synthesizing a plurality of frame data that are not synchronized with each other. However, in Patent Document 1, when a plurality of signals are combined on one screen, since a combining process using a frame memory is performed, the memory band increases. Thus, with the advancement of video processing, the required memory bandwidth is steadily increasing.

JP 2009-265319 A

  The video processing device that processes the input video and outputs the video to the display panel of the output device replaces the input synchronization timing with the internal synchronization timing and the internal synchronization timing with the output synchronization timing when outputting the video. Is often implemented. Here, since the output synchronization timing is determined by the characteristics of the panel of the output device that outputs the video, the resolution and frame rate of the output signal output from the video processing device differ depending on the output device. The internal synchronization timing varies depending on the input / output synchronization timing and the function to be performed. In general, the video processing device performs the transfer from the input synchronization timing to the internal synchronization timing in the video processing unit that performs the first memory access, and performs the transfer from the internal synchronization timing to the output synchronization timing for the last memory access. This is performed by the video processing unit to be performed.

  On the other hand, the location where the memory access is performed in the video processing apparatus varies depending on the output device, the panel type, the function to be performed, and the like. On the other hand, when the video processing apparatus always performs the above-described replacement process at the same location, depending on the function to be performed, memory access is performed only for the purpose of timing replacement, not for the purpose of direct video processing. . As a result, there is a problem that unnecessary memory capacity and memory bandwidth are increased.

  The present invention has been made in view of the above problems, and an object thereof is to prevent an increase in memory capacity and memory bandwidth.

  As a means for achieving the above object, the video processing apparatus of the present invention has the following configuration. That is, a selection of a plurality of video processing means for performing video processing on the input video signal and a video processing means for accessing the memory among the plurality of video processing means according to a desired video processing function And the video processing means selected by the selection means performs the video processing via access to the memory.

  An increase in memory capacity and memory bandwidth can be prevented.

The block diagram which shows schematic structure of the video processing circuit by 1st embodiment. The figure which shows the operation | movement of the input part at the time of a division | segmentation video input. The block diagram which shows the operation | movement of 1 screen display with the projector in 1st embodiment. The block diagram which shows the operation | movement of 1 screen display with the monitor in 1st embodiment. The block diagram which shows the operation | movement of a layout display with the monitor in 1st embodiment. The figure which shows the image processing outline | summary of a layout display with the monitor in 1st embodiment. The block diagram which shows schematic structure of the conventional video processing circuit. The block diagram which shows schematic structure of the video processing circuit by 2nd embodiment. The block diagram which shows the operation | movement of 1 screen display in 2nd embodiment. The block diagram which shows the operation | movement of the layout display in 2nd embodiment. The figure which shows schematic structure of the video processing system by 3rd embodiment.

  Embodiments according to the present invention will be described below with reference to the accompanying drawings. The following embodiments do not limit the present invention related to the scope of claims, and all combinations of features described in the present embodiments are essential to the solution means of the present invention. Not necessarily.

<First embodiment>
Configuration of Video Processing Circuit The configuration of the video processing circuit constituting the video processing device in the first embodiment will be described below. FIG. 1 is a block diagram showing a schematic configuration of a video processing circuit 10 in the present embodiment. In the present embodiment, the video processing circuit 10 is described as including an interface capable of inputting four systems of video signals, but is not limited thereto. The video processing circuit 10 includes an input interface such as HDMI (registered trademark) (High-Definition Multimedia Interface), DVI (Digital Visual Interface), and DisplayPort for input. Alternatively, the video processing circuit 10 may be configured to be able to input an encoded stream signal such as MPEG (Moving Picture Experts Group) decoded by a decoder (not shown).

  The video signal input to the video processing circuit 10 is first input to the input unit 11. The input unit 11 has a frame memory access unit (not shown) and has the following three functions. As a first function, the input unit 11 has a selection function of selecting one of the four input video signals and outputting it to the first video processing unit 12. As a second function, the input unit 11 has a function of combining a plurality of divided input video signals. FIG. 2 is a diagram illustrating a combining operation of input video signals. As shown in FIG. 2, for example, when four input video signals are video signals obtained by dividing one video signal, the input unit 11 stores the four video signals in the memory 16 via the bus 15. To do. At that time, the input unit 11 combines the four videos into one video on the memory 16. Thereafter, the input unit 11 reads out from the memory 16 as one video signal in synchronization with the synchronization signal SyncA generated and supplied by the synchronization signal generation unit 17, and outputs it to the first video processing unit 12.

  As a third function, the input unit 11 has a function of serializing an input video signal. When the four input video signals are independent and separate video signals, and the four-screen layout display corresponding to these video signals is realized, the input unit 11 stores each video signal in the memory 16 via the bus 15. To store. Thereafter, the input unit 11 reads the four input images alternately from the memory 16 for each frame (in serialization) in synchronization with the synchronization signal SyncA supplied from the synchronization signal generation unit 17, and adds a separate identification code to each. Then, the data is output to the first video processing unit 12. The input unit 11 selectively performs these first to third functions.

  The first video processing unit 12 performs video processing via the memory 16. In the present embodiment, the first video processing unit 12 can perform IP conversion (interlace / progressive conversion) and resolution conversion processing. The video signal input to the first video processing unit 12 is written into the memory 16 via a frame memory access unit (not shown). Thereafter, when the video signal is an interlaced signal, the first video processing unit 12 reads out the video signals of a plurality of frames stored in the memory 16 in accordance with the synchronization signal SyncB generated and supplied by the synchronization signal generation unit 17. IP conversion processing is performed. When four video signals are input to the video processing circuit 10, the first video processing unit 12 may perform separate processing according to the identification code added by the third function of the input unit 11. I can do it. The first video processing unit 12 converts the video signal into a desired resolution by performing resolution conversion processing after conversion to a progressive signal. When reducing the effective area of the input video when performing the resolution conversion process, the first video processing unit 12 outputs an effective area having a lower rate than the input rate.

  The video signal output from the first video processing unit 12 is input to the first route selection unit 18. The first route selection unit 18 is configured by a selection circuit that selects a route A that bypasses a layout unit 13 to be described later and a route B that passes through the layout unit 13, and switches between these routes according to an instruction from a control unit (not shown). .

  The layout unit 13 has a function of laying out a plurality of input video signals on one screen. For example, when four video signals are input to the video processing circuit 10, the layout unit 13 can lay out these video signals on one screen. In this case, the four input videos are stored in the memory 16 via a frame memory access unit (not shown) and the bus 15, respectively. After that, the layout unit 13 receives designation of the composite coordinates from a control unit (not shown), and synchronizes with the synchronization signal SyncC generated and supplied by the synchronization signal generation unit 17, and outputs four video signals at predetermined coordinates on the output screen. Lay out and output. When the first route selection unit 18 selects the route A, the layout unit 13 stops the process.

  The second route selection unit 19 includes a selection circuit that selects a route C that bypasses a second video processing unit 14 (to be described later) and a route D that passes through the second video processing unit 14, and is instructed by a control unit (not shown). To switch these paths. The video signal output from the second path selection unit 19 is output from the video processing circuit 10, connected to an external output device (not shown), and displayed on the display panel of the output device. Here, as a display panel, a direct-view panel such as liquid crystal, plasma, or organic EL (Electro-Luminescence), or a reflector panel for projector such as LCOS (Liquid crystal on silicon) or DLP (Digital Light Processing) may be used. I can do it.

  The second video processing unit 14 performs video processing via the memory 16 on the input video signal. In the present embodiment, the second video processing unit 14 can perform a geometric deformation process. The second video processing unit 14 performs a geometric deformation process on the input video signal to a shape designated by a control unit (not shown), and the processed video signal is connected to a frame memory access unit (not shown) and a bus. 15 to the memory 16 via Thereafter, the second video processing unit 14 reads out and outputs the video signal from the memory 16 in synchronization with the synchronization signal SyncD generated and supplied by the synchronization signal generation unit 17. When the second route selection unit 19 selects the route C, the second video processing unit 14 stops the process.

  The synchronization signal generation unit 17 generates the synchronization signals SyncA to D for controlling the access timing to the memory 16 for the input unit 11, the first video processing unit 12, the layout unit 13, and the second video processing unit 14. ,Send. The synchronization signal generation unit 17 can generate separate synchronization signals SyncA to SyncD according to functions. When the synchronization signal generation unit 17 generates a synchronization signal for one system of input signals, the synchronization signal generation unit 17 acquires the synchronization signal from the video signal input to the input unit 11 and outputs the input signal to the display panel. The phase of the acquired synchronization signal is adjusted so that the signal is locked.

  Next, the operation of the video processing circuit 10 according to the present embodiment will be described in relation to the first to third functions of the input unit 11 described above. In the video processing circuit 10 according to the present embodiment, necessary video processing is selected by a selection control unit (not shown) according to a desired video processing function, and an operation corresponding to the selection is performed.

● One screen display on the projector (Embodiment of the first function)
As an example of the case where the input unit 11 performs the first function, the configuration of the video processing circuit 10 when the output target is a projector (projector) will be described. FIG. 3 is a block diagram showing a configuration of the video processing circuit 10 when one screen display is performed on the display panel of the projector. The first video signal input to the video processing circuit 10 is input to the input unit 11. The input unit 11 operates as a selector of an input signal that is a first function, and outputs the first video signal to the first video processing unit 12. At the same time, the input unit 11 outputs a synchronization signal included in the first video signal to the synchronization signal generation unit 17. The synchronization signal generation unit 17 determines whether or not the synchronization timing of the synchronization signal of the input video signal satisfies the constraint on the synchronization timing of a display panel (not shown).

  For example, consider a case where the input signal is a 1920 × 1080 pixel, 60i (60 is vertical frequency, i is interlaced) signal, the display panel is 1920 × 1080 pixel, and the operating frequency is 95 Hz to 125 Hz. In this case, the synchronization signal generation unit 17 generates and outputs a synchronization signal of 1920 × 1080 pixels and a frequency of 60 Hz for SyncB, and a synchronization signal of 1920 × 1080 pixels and a frequency of 120 Hz for SyncD. Here, since the input unit 11 and the layout unit 13 that do not perform the access processing to the memory 16 do not use the synchronization signals SyncA and SyncC, the synchronization signal generation unit 17 does not necessarily output the synchronization signals SyncA and SyncC. .

  The first video processing unit 12 stores the video signal input from the input unit 11 in the memory 16. Thereafter, the first video processing unit 12 reads the video signals of a plurality of frames stored in the memory 16 in synchronization with the synchronization signal SyncB input from the synchronization signal generation unit 17, and performs IP conversion processing. After the IP conversion process, the first video processing unit 12 outputs the video signal to the first route selection unit 18.

  The first path selection unit 18 selects whether the video signal input from the first video processing unit 12 is input to the layout unit 13 or bypassed. In the embodiment of this function, the layout process is unnecessary because there is one input. Therefore, a control unit (not shown) sets a route A for the first route selection unit 18. In response to this, the first route selection unit 18 bypasses the layout unit 13 and outputs the video signal input from the first video processing unit 12 to the second route selection unit 19. The second route selection unit 19 selects whether the video signal input from the first route selection unit 18 is input to the second video processing unit 14 or bypassed. Here, since the output to the projector is assumed in the embodiment of this function, it is necessary to use the second video processing unit 14 capable of performing geometric deformation processing. Therefore, a control unit (not shown) sets the route of the second route selection unit 19 to the route D. In response to this, the second route selection unit 19 outputs the video signal input from the first route selection unit 18 to the second video processing unit 14.

  The second video processing unit 14 performs geometric deformation on the input video signal and stores the processing result in the memory 16. Thereafter, the second video processing unit 14 reads the video signal from the memory 16 at the SyncD timing generated by the synchronization signal generating unit 17 and output to a display panel (not shown), and outputs the video signal to the projector. . As described above, in the embodiment of the first function, the second video processing unit 14 indicated by the oblique lines in FIG. 3 performs the replacement to the output synchronization timing.

● Displays 4 inputs on a monitor on a single screen (second function embodiment)
Next, as an example of the case where the input unit 11 performs the second function, the configuration of the video processing circuit 10 when the output target is a monitor will be described. FIG. 4 is a block diagram showing a configuration of the video processing circuit 10 when a four-input one-screen display is performed on the display panel of the monitor. The first to fourth video signals shown in FIG. 4 are divided from one video signal into different signal lines as shown in FIG. The input unit 11 combines the input first to fourth video signals on the memory 16 using the second function. At the same time, the input unit 11 transfers the synchronization signal included in the first to fourth video signals to the synchronization signal generation unit 17.

  The synchronization signal generation unit 17 selects a reference synchronization signal from a plurality of input synchronization signals, and generates synchronization signals SyncA to SyncD based on the selection. Here, consider a case where the input signals are 2048 × 1080 pixels and 60i, respectively, the display panel is 3840 × 2160 pixels, and the operating frequency is 47 to 65 Hz. In this case, the synchronization signal generation unit 17 generates and outputs a synchronization signal of 4096 × 2160 pixels and a frequency of 60 Hz for SyncA and B, and a synchronization signal of 3840 × 2160 pixels and a frequency of 60 Hz for SyncD. In the embodiment of the second function, the layout unit 13 does not access the memory and does not use the synchronization signal, so the synchronization signal generation unit 17 does not necessarily output SyncC.

  The input unit 11 reads the combined input video from the memory 16 in synchronization with SyncA input from the synchronization signal generation unit 17 and inputs the input video to the first video processing unit 12. The first video processing unit 12 stores the input video signal in the memory 16. Thereafter, the first video processing unit 12 performs IP conversion using video signals for a plurality of frames stored in the memory 16 in synchronization with the synchronization signal SyncB input from the synchronization signal generation unit 17. Further, since the resolution of the input video signal is larger than the resolution of the display panel, the first video processing unit 12 performs a reduction process according to the resolution of the display panel. Here, when the first video processing unit 12 reduces the size while maintaining the aspect, the output resolution is reduced to 3840 × 2025 pixels. After the processing, the first video processing unit 12 outputs a video signal to the first route selection unit 18.

  In the embodiment of this function, the first route selection unit 18 does not need layout processing because the input is one system. Therefore, a control unit (not shown) sets a route A for the first route selection unit 18. In response to this, the first route selection unit 18 bypasses the layout unit 13 and outputs the video signal input from the first video processing unit 12 to the second route selection unit 19. The video signal input to the second path selection unit 19 is 135 lines (2160 pixels (resolution of the display panel) −2025 pixels (of the first video processing unit 12) in the vertical direction by the reduction processing of the first video processing unit 12. It reaches the second path selection unit 19 as a video signal with a missing line of output resolution)). For such a signal, the second video processing unit 14 performs a replacement process at an output synchronization timing suitable for the output display panel.

  The second video processing unit 14 performs image expansion processing on the input signal by adding black regions to the 135-line region that is insufficient in the vertical direction, for example, and stores it in the memory 16. In the embodiment of this function, since the output device is not a projector, the second video processing unit 14 does not perform the geometric deformation process described above. Thereafter, the second video processing unit 14 reads out from the memory 16 in synchronization with the synchronization signal SyncD generated by the synchronization signal generation unit 17 and outputs it to a panel (not shown). As described above, in the embodiment of the second function, the second video processing unit 14 indicated by the oblique lines in FIG. 4 is replaced with the output synchronization timing.

● Display multiple images on the monitor (third function embodiment)
Next, as an example of the case where the input unit 11 performs the third function, the output target is a monitor, and video signals input as a plurality of different input signals are laid out and displayed on the display panel of the monitor The configuration of the video processing circuit 10 will be described. FIG. 5 is a block diagram showing a configuration of the video processing circuit 10 when the layout display is performed on the display panel of the monitor. FIG. 6 is a diagram showing an outline of image processing of the video processing circuit 10 when layout display is performed on the display panel of the monitor. As shown in FIG. 6, the first to fourth video signals are different video signals having different resolutions and frame frequencies, and are input to the input unit 11. The input unit 11 uses the third function to sequentially write each input video signal to the memory 16.

  In the embodiment of this function, the synchronization signal generation unit 17 generates a synchronization signal synchronized with the operating frequency of the display panel without using the synchronization signal included in the input video signal. Here, the display panel has 3840 × 2160 pixels and the operating frequency is 60 Hz. In the embodiment of this function, the video processing circuit 10 needs to process four different video signals in one video processing path between the input unit 11 and the layout unit 13. Therefore, the synchronization signal generation unit 17 alternately converts the first to fourth video signals in a time-division manner at a frame rate of 240 Hz, which is four times the operating frequency of the display panel, between the input unit 11 and the layout unit 13. To process. Therefore, the synchronization signal generation unit 17 generates a synchronization signal having a frequency of 240 Hz for Sync A and B, and generates and outputs a synchronization signal of 60 Hz that is the same as the synchronization signal of the display panel for Sync C. In the embodiment of this function, since the second video processing unit 14 does not use SyncD, the synchronization signal generation unit 17 does not necessarily need to output SyncD.

  The input unit 11 synchronizes with the SyncA input from the synchronization signal generation unit 17, reads the first to fourth video signals from the memory 16 alternately with the frames, and outputs them to the first video processing unit 12. When the synchronizing signal of the input video signal has a shorter period than the synchronizing signal of the display panel, the input unit 11 synchronizes by reading by skipping frames. On the other hand, when the synchronization signal of the input video signal has a longer period than the synchronization signal of the display panel, the input unit 11 synchronizes by reading the same frame a plurality of times. The input unit 11 outputs the video signal read from the memory 16 to the first video processing unit 12.

  The first video processing unit 12 performs IP conversion processing and resolution conversion processing separately on the input first to fourth video signals. At this time, the first video processing unit 12 stores the input video signal in the memory 16, and reads out the frame alternately from the memory 16 in synchronization with the synchronization signal SyncB generated by the synchronization signal generation unit 17. Perform resolution conversion processing. The first video processing unit 12 outputs the video signal to the first route selection unit 18 after processing.

  In the embodiment of this function, the first route selection unit 18 lays out four input screens on one screen. Therefore, a control unit (not shown) sets a route B for the first route selection unit 18. In response to this, the first route selection unit 18 outputs the video signal input from the first video processing unit 12 to the layout unit 13. The layout unit 13 stores the input first to fourth video signals in the memory 16, respectively. Thereafter, the layout unit 13 reads out each video signal from the memory 16 in synchronization with the synchronization signal SyncC generated by the synchronization signal generation unit 17. Then, the layout unit 13 lays out each video on the coordinates designated by a control unit (not shown) and outputs the video to the second route selection unit 19 as a video signal of one screen.

  The second path selection unit 19 selects whether the video signal input from the layout unit 13 is input to the second video processing unit 14 or bypassed. Here, the synchronization signal SyncC used in the layout unit 13 is a display panel synchronization signal, and the second video processing unit 14 does not need to perform geometric deformation and transfer to the output synchronization timing. Therefore, the control unit (not shown) sets the route of the second route selection unit 19 to the route C. In response to this, the second route selection unit 19 outputs the video signal input from the layout unit 13 to a monitor which is an output device (not shown).

Effects of the present embodiment Here, effects of the present embodiment with respect to a conventional video processing circuit will be described. FIG. 7 shows a configuration of a conventional video processing circuit 70. In the conventional video processing circuit, the process of changing the output synchronization timing to the output device is fixedly performed by the second video processing unit 74 at the last stage. In such a conventional video processing circuit 70, when the layout process described above is performed, the layout unit 73 needs to perform the layout, and then the second video processing unit 74 needs to change the output synchronization timing. It was. As a result, memory access by the second video processing unit 74 occurs as compared with the embodiment at the time of layout processing described above. Therefore, in the conventional video processing circuit 70, it is necessary to configure the circuit with a memory having a larger memory capacity and memory bandwidth. On the other hand, in this embodiment, since it is possible to transfer to the output synchronization timing and generate the synchronization timing at a plurality of memory access locations, the function can be realized with fewer memory accesses compared to the conventional method. . Therefore, the superiority of this embodiment over the prior art is clear.

<Second embodiment>
Configuration of Video Processing Circuit Hereinafter, the configuration of the video processing circuit constituting the video processing device in the second embodiment will be described. In addition, description is abbreviate | omitted regarding the same location as 1st embodiment. FIG. 8 is a block diagram showing a schematic configuration of the video processing circuit 80 in the present embodiment. In the video processing circuit 80, the first to fourth video signals are input to the input unit 81. The input unit 81 has the following two functions. As a first function, the input unit 11 has a function of outputting the input first to fourth video signals to the first video processing unit 82 as they are. As a second function, the input unit 11 combines the input signals into one via the memory 86, and synchronizes with SyncA generated by the synchronization signal generation unit 87 to the first video processing unit 82. Has a function to output. The input unit 11 selectively performs these first to second functions.

  The first video processing unit 82 has four memory write paths for the four input video signals, and stores the input video in the memory 86. Thereafter, the data is read from the memory 86 in synchronization with the synchronization signal SyncB, IP conversion processing and resolution conversion processing are performed, and output to the first path selection unit 88. The subsequent processing is the same as in the first embodiment.

● Display 4 inputs on a single screen (second function embodiment)
A configuration of the video processing circuit 80 when the input unit 11 performs the second function will be described. FIG. 9 is a block diagram showing the configuration of the video processing circuit 80 when performing one-screen display. When displaying the first to fourth video signals divided into different signal lines from one video signal on one screen, the input unit 81 uses the second function and displays each input video signal on one screen. Join. The input unit 81 arranges and stores the input first to fourth video signals so as to be combined on the memory 86 via the bus 85.

  As in the first embodiment, the synchronization signal generation unit 87 generates synchronization signals SyncA to D synchronized with the input signal, and controls the replacement of the read timing from the memory 86 and the output synchronization timing. The input unit 81 synchronizes with the synchronization signal SyncA input from the synchronization signal generation unit 87, reads the combined video signal from the memory 86, and outputs it to the first video processing unit 82. Thereafter, as in the first embodiment, the second video processing unit 84 indicated by hatching in FIG. 9 carries out the replacement to the output synchronization timing, and outputs a video signal to a display panel of an output device (not shown).

● Multiple video layout display (first function embodiment)
Next, the configuration of the video processing circuit 80 when the input unit 11 performs the first function will be described. FIG. 10 is a block diagram showing a configuration of the video processing circuit 80 when a plurality of videos are displayed in layout. When the first to fourth video signals, which are different independent video signals, are combined and displayed on one screen, the input unit 81 does not perform screen combination unlike the case of displaying one screen. In the example of FIG. 8, the video processing circuit 80 can perform four independent processes until the first video processing unit 82 writes to the memory 86, so the input unit 81 is the same as in the first embodiment. Therefore, there is no need to change the processing order to time-division alternating processing. Therefore, as shown in FIG. 10, the input unit 81 inputs four images input using the first function to the first image processing unit 82. The first video processing unit 82 writes the input four video signals into the memory 86 separately.

  In the embodiment of this function, the synchronization signal generation unit 87 operates free-running in synchronization with the output panel timing without being synchronized with the input signal. In the embodiment of this function, since the input unit 81 and the second video processing unit 84 do not access the memory 86, the synchronization signal generation unit 87 may not generate the synchronization signals SyncA and D. For the layout unit 83 that implements the replacement of the synchronization signal to the panel, the synchronization signal generation unit 87 generates a synchronization signal for the output panel as SyncC. In addition, there is only one image processing circuit between the first video processing unit 82 and the layout unit 83. In order to perform video processing for four inputs, image processing is performed at a vertical synchronization frequency four times that of SyncC. There is a need to. Therefore, the synchronization signal SyncB output to the first video processing unit 82 is generated at a vertical synchronization frequency four times the output synchronization timing SyncC.

  The first video processing unit 82 reads out the first to fourth video signals from the memory 86 alternately in frame in synchronization with the synchronization signal SyncB input from the synchronization signal generation unit 87, and outputs the processed signals to the layout unit 83. The layout unit 83 stores the four input video signals in the memory 86. Thereafter, it is read at the timing of the output synchronization timing SyncC, and the four screens are synthesized in accordance with the layout instruction of the control unit (not shown) and output from the video processing circuit.

Effects of this Embodiment In the conventional video processing circuit shown in FIG. 7, the internal operation timing replacement process is fixedly performed at the input unit 71 in the forefront stage. In the present embodiment, the location where the input signal is stored in the memory is variable according to the function to be implemented, and a plurality of locations to be replaced with the internal operation timing are provided, so that the image from the first embodiment to the first video processing unit is provided. Processing circuitry increases. However, in this embodiment, the layout function can be realized with fewer memory accesses. Therefore, when the circuit scale of the video processing circuit is a problem, the circuit configuration of the first embodiment is used, and when the memory bandwidth is a problem, the second embodiment is used. A layout function can be realized.

<Third embodiment>
In this embodiment, a configuration of a system including the video processing circuit described in the first to second embodiments will be described. FIG. 11 is a diagram showing a video processing system according to the present embodiment. In FIG. 11, a video processing circuit 90 corresponds to the video processing circuit described in the first to second embodiments. The camera 91 transmits the video signal obtained by the shooting process to the video processing circuit 90. In FIG. 11, one camera 91 is used, but a plurality of cameras 91 may be used. The selection control unit 94 selects the necessary video processing using the projector 92 or the monitor 93 as the number and type of video signals input to the video processing circuit 90 and the output target, and is described in the first to second embodiments. Different video processing. Note that the video processing circuit 90 may include the selection control unit 94.

  As described above, according to the embodiment described above, it is possible to suitably control the place where the timing change of the input signal is performed according to the video processing to be performed. Thereby, it is possible to suppress the increase in memory cost and realize a desired function.

<Other embodiments>
The present invention can also be realized by executing the following processing. That is, software (program) that realizes the functions of the above-described embodiments is supplied to a system or apparatus via a network or various storage media, and a computer (or CPU, MPU, or the like) of the system or apparatus reads the program. It is a process to be executed.

10 video processing circuit, 11 input unit, 12 first video processing unit, 13 layout unit, 14 second video processing unit, 15 bus, 16 memory, 17 synchronization signal generation unit, 18 first path selection unit, 19 second path Select part

Claims (14)

A video processing device,
A plurality of video processing means for performing video processing on the input video signal;
Selecting means for selecting a video processing means for accessing the memory among the plurality of video processing means according to a desired video processing function;
The video processing apparatus, wherein the video processing means selected by the selection means performs the video processing via access to the memory.   The video processing apparatus according to claim 1, further comprising a bypass unit that bypasses video processing by the video processing unit that is not selected by the selection unit among the plurality of video processing units. A first synchronization signal indicating an output timing to the outside is generated, and the first synchronization signal is supplied to the last video processing means among the video processing means selected by the selection means. A synchronization signal generating means;
The video processing apparatus according to claim 1, wherein the video processing means at the last stage performs the video processing via access to the memory according to an output timing to the outside.   The last-stage video processing means writes the result of performing geometric deformation processing on the input video signal to the memory, reads the result from the memory according to the output timing to the outside, and outputs the result to the outside The video processing apparatus according to claim 3, wherein:   The last-stage video processing means writes the result of image expansion processing on the input video signal to the memory, reads the result from the memory according to the output timing to the outside, and outputs the result to the outside The video processing apparatus according to claim 3, wherein:   The last-stage video processing means writes a plurality of the input video signals to the memory, reads out the written video signals from the memory according to the output timing to the outside, lays out and outputs them to the outside. The video processing apparatus according to claim 3. A second synchronization signal that generates a second synchronization signal indicating an internal operation timing, and supplies the second synchronization signal to the first-stage video processing means among the video processing means selected by the selection means. A signal generating means;
The video processing apparatus according to claim 1, wherein the video processing unit in the forefront stage performs the video processing via access to the memory in accordance with the internal operation timing.   The foremost video processing means writes the input video signal into the memory, reads out from the memory according to the internal operation timing, and outputs it to the next video processing means selected by the selection means. The video processing apparatus according to claim 7.   The video processing apparatus according to claim 8, wherein the input video signal is a plurality of signals divided from one signal.   When the input video signal is a plurality of separate signals, the first-stage video processing means writes the plurality of video signals to the memory and reads them from the memory for serialization according to the internal operation timing. 9. The video processing apparatus according to claim 8, wherein   The foremost video processing means writes the result of IP conversion (interlace / progressive conversion) to the input video signal into the memory, reads out from the memory in accordance with the internal operation timing, and the selection means 8. The video processing apparatus according to claim 7, wherein the video processing apparatus outputs to the next selected video processing means.   The first-stage video processing means writes the result of resolution conversion of the input video signal to the memory, reads out from the memory according to the internal operation timing, and selects the next selected by the selection means The video processing apparatus according to claim 7, wherein the video processing apparatus outputs the video processing means. A method for controlling a video processing apparatus,
A plurality of video processing steps for performing video processing on the input video signal;
A selection step of selecting a video processing step for accessing the memory among the plurality of video processing steps according to a desired video processing function,
The method of controlling a video processing apparatus, wherein the video processing is performed through access to the memory in the video processing step selected in the selection step.   The program for functioning a computer as each means of the video processing apparatus of any one of Claims 1 thru | or 12.

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