JP2015227982A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display device excellent in display quality.SOLUTION: The display device comprises: an insulation substrate; gate wiring; source wiring intersecting with the gate wiring; a semiconductor layer formed of polysilicon, and including a first impurity region that includes a first high concentration region and a first low concentration region having lower impurity concentration than that of the first high concentration region, and that is electrically connected to the source wiring, a second impurity region, and a channel region positioned between the first impurity region and the second impurity region, facing the gate wiring, formed in an L-shape, and having inner edge and outer edge channel lengths equal to each other; and a pixel electrode electrically connected to the second impurity region. A boundary between the first high concentration region and the first low concentration region includes a curve part having the edge length of the first low concentration region along the inner edge of the channel region as curvature radius.

Description

  Embodiments described herein relate generally to a display device.

  In recent years, display devices including thin film transistors have been put into practical use. Examples of the display device include a liquid crystal display device and an organic electroluminescence (EL) display device. As an example of a thin film transistor applied to a display device, a technique is known which is a thin film transistor having a double gate electrode structure and includes a light shielding film for preventing light irradiation to a bonding surface.

  In recent display devices for portable terminals, there is an increasing demand for miniaturization and high definition, and the pixel size tends to be reduced. When a thin film transistor that requires a relatively large installation area is provided in a pixel, the area contributing to display per pixel is reduced by the amount of the thin film transistor installed. For this reason, in order to obtain sufficient luminance or transmittance, it is required to expand the area contributing to the display of each pixel.

  On the other hand, when a light-shielding film that shields light toward the semiconductor layer is provided, a parasitic capacitance is generated between the light-shielding film and the semiconductor layer. However, as the area of the light-shielding film facing the semiconductor layer increases, the parasitic capacitance increases. Become. In a thin film transistor arranged in the vicinity of an intersection between a gate wiring and a source wiring, in a layout in which at least a part of the semiconductor layer overlaps with the source wiring, the potential of the semiconductor layer on the side electrically connected to the source wiring is It changes according to the video signal supplied to. For this reason, the potential of the light shielding film capacitively coupled to the semiconductor layer changes according to the video signal. The light shielding film also faces the semiconductor layer on the side electrically connected to the pixel electrode. For this reason, the pixel potential written and held in the pixel electrode becomes unstable due to the potential change of the light shielding film. Therefore, in each pixel electrically connected to the same source wiring, the pixel potential held is disturbed in accordance with the video signal supplied to the source wiring, which may cause deterioration in display quality.

JP 2001-284594 A

  An object of the present embodiment is to provide a display device with good display quality.

According to this embodiment,
A semiconductor layer formed of an insulating substrate, a gate wiring, a source wiring crossing the gate wiring, and polysilicon, and having a lower impurity concentration than the first high concentration region and the first high concentration region. A first impurity region including a low-concentration region and electrically connected to the source wiring; a second impurity region; and the gate electrode positioned between the first impurity region and the second impurity region. A semiconductor layer having a channel region formed in an L shape and having an inner channel length equal to an outer channel length, and a pixel electrode electrically connected to the second impurity region; The boundary between the first low concentration region and the first high concentration region includes a curved portion having an edge length of the first low concentration region along the inner edge of the channel region as a radius of curvature. Display device It is provided.

According to this embodiment,
A semiconductor layer formed of an insulating substrate, a linearly extending gate wiring, a first source wiring and a second source wiring intersecting with the gate wiring, and polysilicon, and parallel to the first source wiring A first impurity region extending opposite to the first source line and electrically connected to the first source line, and located between the first source line and the second source line. A semiconductor layer comprising: a second impurity region extending in parallel with one impurity region; and a channel region located between the first impurity region and the second impurity region and facing the gate wiring; A display device including a pixel electrode electrically connected to two impurity regions is provided.

FIG. 1 is a diagram schematically showing a configuration and an equivalent circuit of a display panel PNL constituting the display device of the present embodiment. FIG. 2 is a cross-sectional view schematically showing the configuration of the display panel PNL including the pixel PX shown in FIG. FIG. 3 is a diagram showing an equivalent circuit of the switching element SW shown in FIG. FIG. 4 is a plan view schematically showing a configuration example of the switching element SW applicable to the display device of the present embodiment. FIG. 5 is an enlarged plan view of the semiconductor layer SC in the switching element shown in FIG. 6 is a cross-sectional view schematically showing a structure in which the switching element SW shown in FIG. 4 is cut along the line AB. FIG. 7 is a plan view schematically showing another configuration example of the switching element SW applicable to the display device of the present embodiment. FIG. 8 is a plan view schematically showing another configuration example of the switching element SW applicable to the display device of the present embodiment.

  Hereinafter, the present embodiment will be described in detail with reference to the drawings. In each figure, the same reference numerals are given to components that exhibit the same or similar functions, and duplicate descriptions are omitted.

  FIG. 1 is a diagram schematically showing a configuration and an equivalent circuit of a display panel PNL constituting the display device of the present embodiment. Here, a liquid crystal display device will be described as an example of a display device.

  That is, the liquid crystal display device includes an active matrix type transmissive display panel PNL. The display panel PNL includes an array substrate AR, a counter substrate CT arranged to face the array substrate AR, and a liquid crystal layer LQ held in a cell gap between the array substrate AR and the counter substrate CT. Yes. The array substrate AR and the counter substrate CT are bonded together with a sealing material. Such a display panel PNL is provided with an active area ACT for displaying an image inside surrounded by a sealing material. The active area ACT is composed of a plurality of pixels PX arranged in a matrix.

  The array substrate AR includes gate lines G (G1 to Gn), source lines S (S1 to Sm), and the like in the active area ACT. Each gate line G is drawn outside the active area ACT and connected to the gate driver GD. Each source line S is drawn outside the active area ACT and connected to the source driver SD.

  Each pixel PX includes a switching element SW, a pixel electrode PE, a common electrode CE, and the like. The switching element SW is formed of a thin film transistor (TFT) and is electrically connected to the gate line G and the source line S. The pixel electrode PE is electrically connected to the switching element SW in each pixel PX. The common electrode CE is connected to the power supply unit VS. The common electrode CE is formed in common over the plurality of pixels PX in the active area ACT and faces each pixel electrode PE. A control signal for on / off control of the switching element SW is supplied to the gate line G. A video signal is supplied to the source wiring S. When the switching element SW is turned on based on a control signal supplied to the gate line G, the switching element SW writes a pixel potential corresponding to the video signal supplied to the source line S to the pixel electrode PE. A voltage is applied to the liquid crystal layer LQ by the potential difference between the common electrode CE having the common potential and the pixel electrode PE having the pixel potential, and the alignment of the liquid crystal molecules included in the liquid crystal layer LQ is controlled.

  The storage capacitor CS holds a voltage applied to the liquid crystal layer LQ for a certain period, and is composed of a pair of electrodes opposed via an insulating film. For example, the storage capacitor CS includes a first electrode having the same potential as the pixel electrode PE, a second electrode having the same potential as the common electrode CE, and an insulating film interposed between the first electrode and the second electrode. Has been.

  The detailed configuration of the display panel PNL is omitted here, but in a mode that mainly uses a vertical electric field such as a TN (Twisted Nematic) mode, an OCB (Optically Compensated Bend) mode, and a VA (Vertical Aligned) mode. The pixel electrode PE is provided on the array substrate AR, while the common electrode CE is provided on the counter substrate CT. Further, in a mode that mainly uses a lateral electric field such as an IPS (In-Plane Switching) mode and an FFS (Fringe Field Switching) mode, both the pixel electrode PE and the common electrode CE are provided on the array substrate AR.

  FIG. 2 is a cross-sectional view schematically showing the configuration of the display panel PNL including the pixel PX shown in FIG. Here, as an example of the display mode, a pixel structure of the display panel PNL to which the horizontal electric field mode is applied will be described. In the figure, only the main parts necessary for the explanation are shown.

  The array substrate AR is formed using a transparent first insulating substrate 10 such as a glass substrate or a resin substrate. The array substrate AR has a common electrode CE, a pixel electrode PE, a first insulating film 11, a second insulating film 12, a third insulating film 13, and a fourth insulating film on the side of the first insulating substrate 10 facing the counter substrate CT. 14, a fifth insulating film 15, a first alignment film AL1, and the like.

  The first insulating film 11 is disposed on the inner surface of the first insulating substrate 10. The second insulating film 12 is disposed on the first insulating film 11. The third insulating film 13 is disposed on the second insulating film 12. The fourth insulating film 14 is disposed on the third insulating film 13. The first insulating film 11, the second insulating film 12, and the third insulating film 13 are formed using an inorganic material such as silicon nitride or silicon oxide, for example. The fourth insulating film 14 is formed using an organic material such as an acrylic resin.

  The common electrode CE is disposed on the fourth insulating film 14. The common electrode CE is formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The common electrode CE is covered with the fifth insulating film 15. The fifth insulating film 15 is formed using an inorganic material such as silicon nitride.

  Each of the pixel electrodes PE is disposed on the fifth insulating film 15 and faces the common electrode CE. A slit SL facing the common electrode CE is formed in the pixel electrode PE. The pixel electrode PE is made of, for example, a transparent conductive material such as ITO or IZO. The pixel electrode PE is covered with the first alignment film AL1. The first alignment film AL1 also covers the fifth insulating film 15. The first alignment film AL1 is formed of a material exhibiting horizontal alignment and is disposed on the surface in contact with the liquid crystal layer LQ of the array substrate AR.

  On the other hand, the counter substrate CT is formed using a transparent second insulating substrate 20 such as a glass substrate or a resin substrate. The counter substrate CT includes a black matrix (light shielding member) BM, color filters CF1 to CF3, an overcoat layer OC, a second alignment film AL2, and the like on the side of the second insulating substrate 20 facing the array substrate AR.

  The black matrix BM is disposed on the inner surface of the second insulating substrate 20. The black matrix BM is formed along the boundary of the pixels and is located immediately above the wiring portion such as the gate wiring, the source wiring, and the switching element. The black matrix BM is formed of a black resin material or a light shielding metal material.

  Each of the color filters CF1 to CF3 is disposed on the inner surface of the second insulating substrate 20. As an example, the color filter CF1 is formed of a resin material colored in green. The color filter CF2 is formed of a resin material colored in blue. The color filter CF3 is formed of a resin material colored in red. The end portions of the color filters CF1 to CF3 overlap the black matrix BM.

  The overcoat layer OC covers the color filters CF1 to CF3. The overcoat layer OC is formed of a transparent resin material. The overcoat layer OC is covered with the second alignment film AL2. The second alignment film AL2 is formed of a material exhibiting horizontal alignment, and is disposed on the surface in contact with the liquid crystal layer LQ of the counter substrate CT.

  The array substrate AR and the counter substrate CT as described above are arranged so that the first alignment film AL1 and the second alignment film AL2 face each other. At this time, a predetermined cell gap is formed between the array substrate AR and the counter substrate CT. The liquid crystal layer LQ is composed of a liquid crystal composition including liquid crystal molecules sealed between the first alignment film AL1 of the array substrate AR and the second alignment film AL2 of the counter substrate CT.

  A backlight BL is disposed on the back side of the display panel PNL having such a configuration. The backlight BL irradiates light toward the display panel PNL.

  A first optical element OD1 including a first polarizing plate PL1 is disposed on the outer surface of the first insulating substrate 10. On the outer surface of the second insulating substrate 20, the second optical element OD2 including the second polarizing plate PL2 is disposed. The first absorption axis of the first polarizing plate PL1 and the second absorption axis of the second polarizing plate PL2 are, for example, orthogonal to each other.

  FIG. 3 is a diagram showing an equivalent circuit of the switching element SW shown in FIG. Although the switching element SW in the illustrated example has a single gate structure, the structure of the switching element SW is not limited to the illustrated example.

  In the illustrated example, in the switching element SW, when the potential of the one end side terminal connected to the source line S is Vs and the potential of the other end side terminal connected to the pixel electrode PE is Vd, the relationship of Vd> Vs is satisfied. The state in FIG. 6 corresponds to the case where the positive electrode charge is held in the pixel electrode PE, and the state in the relationship of Vd <Vs corresponds to the case where the negative electrode charge is held in the pixel electrode PE. .

  The switching element SW includes a semiconductor layer SC. The semiconductor layer SC is made of, for example, polysilicon. The semiconductor layer SC has a first impurity region R1, a second impurity region R2, and a channel region CN. The channel region CN is located between the first impurity region R1 and the second impurity region R2. The gate electrode WG is opposed to the channel region CN.

  Both the first impurity region R1 and the second impurity region R2 correspond to regions where impurities are implanted into the semiconductor layer SC. The first impurity region R1 is located on one end side (source wiring side) of the switching element SW. The first impurity region R1 has a first high concentration region RH1 and a first low concentration region RL1. The first low concentration region RL1 has a lower impurity concentration than the first high concentration region RH1. The first low concentration region RL1 is located between the channel region CN and the first high concentration region RH1. The second impurity region R2 is located on the other end side (pixel electrode side) of the switching element SW. The second impurity region R2 has a second high concentration region RH2 and a second low concentration region RL2. The second low concentration region RL2 has a lower impurity concentration than the second high concentration region RH2. The second low concentration region RL2 is located between the channel region CN and the second high concentration region RH2.

  When positive field charge is held in the pixel electrode PE, the first impurity region R1 on the source wiring side becomes a source region, and the second impurity region R2 on the pixel electrode side becomes a drain region. When a negative field charge is held in the pixel electrode PE, the first impurity region R1 on the source wiring side becomes a drain region, and the second impurity region R2 on the pixel electrode side becomes a source region.

  Next, a configuration example of the switching element SW according to the present embodiment will be described.

  FIG. 4 is a plan view schematically showing a configuration example of the switching element SW applicable to the display device of the present embodiment.

  The gate line G1 extends along the first direction X. The source line S1 and the source line S2 respectively extend along the second direction Y and intersect the gate line G1. The switching element SW is located near the intersection of the gate line G1 and the source line S1, and is electrically connected to the gate line G1 and the source line S1. The switching element SW in the illustrated example is a single-gate thin film transistor having one gate electrode WG.

  The semiconductor layer SC of the switching element SW is formed in a substantially L shape. The first impurity region R1, the channel region CN, and the second impurity region R2 are arranged in this order. The first impurity region R1 extends in parallel with the source line S1, and extends linearly along the second direction Y in the illustrated example. The second impurity region R2 extends in a direction different from the first impurity region R1, and in the illustrated example, extends in a straight line along the first direction X. The channel region CN is formed in an L shape bent at about 90 degrees. That is, the channel region CN has a portion that is connected to the first impurity region R1 and extends along the second direction Y, and a portion that is connected to the second impurity region R2 and extends along the first direction X. doing. In the channel region CN, when the channel length is the distance from the boundary with the first impurity region R1 to the boundary with the second impurity region R2, the channel length L1 of the inner edge CNI of the channel region CN is equal to the outer edge CNO of the channel region CN. Is equivalent to the channel length L2.

  In the XY plane, a part of the semiconductor layer SC extending in the second direction Y, that is, a part of the first impurity region R1 and the channel region CN substantially overlaps with the source line S1. Further, a portion of the semiconductor layer SC extending in the first direction X, that is, the other portion of the second impurity region R2 and the channel region CN does not overlap with the source line S1. In other words, the source line S1 is opposed to a portion extending in the second direction Y of the semiconductor layer SC. Further, the source line S1 is disposed at a position shifted from a position facing the portion extending in the first direction X of the semiconductor layer SC.

  The gate electrode WG is opposed to the channel region CN. The gate electrode WG is, for example, a part of the gate wiring G1. In the illustrated example, the gate electrode WG is connected to one edge portion of the gate wiring G1 extending linearly in the first direction X.

  The source line S1 is electrically connected to one end side of the semiconductor layer SC, that is, the first impurity region R1 through the contact hole CH1. In the illustrated example, the source line S1 is opposed to at least a part of the gate electrode WG. That is, a part of the gate electrode WG is located between the semiconductor layer SC and the source wiring S1.

  The relay electrode RE is opposed to the second impurity region R2. In the illustrated example, the relay electrode RE further faces the gate line G1. Such a relay electrode RE is electrically connected to the other end side of the semiconductor layer SC, that is, the second impurity region R2 through the contact hole CH2.

  The pixel electrode PE indicated by a one-dot chain line in the drawing is located between the source line S1 and the source line S2. Further, the pixel electrode PE is opposed to the relay electrode RE. That is, the relay electrode RE is located between the semiconductor layer SC and the pixel electrode PE. Such a pixel electrode PE is electrically connected to the relay electrode RE through the contact hole CH3.

  In the example shown in the figure, a region where light leakage is prominently generated in the semiconductor layer SC is shielded by the light shielding film LS. In other words, the light shielding film LS is disposed so as to face a region of the semiconductor layer SC where light leakage occurs remarkably, that is, a region including the boundary between the channel region CN and the second impurity region R2. In the illustrated example, the light shielding film LS extends across the channel region CN and the second impurity region R2, and includes one end LSA facing the channel region CN and the other end facing the second impurity region R2. LSB. That is, the light shielding film LS is opposed to the region on the pixel electrode side of the channel region CN and the region adjacent to the channel region CN of the second impurity region R2 in the semiconductor layer SC. On the other hand, the light shielding film LS does not face the first impurity region R1. Further, the light shielding film LS is formed in an island shape, and is disposed at a position shifted from a position facing the source line S1. For this reason, the light shielding film LS does not form an undesired parasitic capacitance with the source line S1 or with the region on the source line side of the semiconductor layer SC. Further, the light shielding film LS is arranged at a position shifted from a position facing the portion extending in the first direction X of the gate wiring G1. For this reason, the light shielding film LS does not form an undesired parasitic capacitance with the gate wiring G1.

  FIG. 5 is an enlarged plan view of the semiconductor layer SC in the switching element shown in FIG.

  The contact hole CH1 is formed at a position overlapping the first high concentration region RH1. The contact hole CH2 is formed at a position overlapping the second high concentration region RH2.

  In the semiconductor layer SC, a boundary BC1 between the channel region CN and the first low-concentration region RL1 is, for example, at a position overlapping with an edge on one end side of the gate electrode WG. In addition, the boundary BC2 between the channel region CN and the second low concentration region RL2 is, for example, at a position overlapping the edge on the other end side of the gate electrode WG. In the illustrated example, the boundary BC1 extends in a direction intersecting the first direction X and the second direction Y in a portion extending in the second direction Y of the semiconductor layer SC. Further, the boundary BC2 extends in parallel with the second direction Y in the portion extending in the first direction X of the semiconductor layer SC.

  In the first impurity region R1, the boundary BR1 between the first high concentration region RH1 and the first low concentration region RL1 has a straight line portion LN parallel to the boundary BC1 and a curved line portion CV connected to the straight line portion LN. . The radius of curvature of the curved portion CV corresponds to the edge length L11 of the first low concentration region RL1 along the inner edge CNI of the channel region CN. That is, the curved part CV is a part (arc) of a circumference centered on the intersection of the boundary BC1 and the inner edge CNI and having the edge length L11 as a radius. The shortest distance between the straight line portion LN and the boundary BC1, that is, the distance L12 from the boundary BC1 to the straight line portion LN along the normal direction of the boundary BC1 is equal to the edge length L11. In short, the distance between the boundary BC1 and the boundary BR1 is substantially constant.

  In the second impurity region R2, a boundary BR2 between the second high concentration region RH2 and the second low concentration region RL2 extends in parallel with the second direction Y and is parallel to the boundary BC2. That is, the distance between the boundary BC2 and the boundary BR2 is constant.

  6 is a cross-sectional view schematically showing a structure in which the switching element SW shown in FIG. 4 is cut along the line AB. Here, illustration of the pixel electrode is omitted.

  The light shielding film LS is located between the first insulating substrate 10 and the semiconductor layer SC. In the illustrated example, the light shielding film LS is disposed on the inner surface of the first insulating substrate 10 and is covered with the first insulating film 11. Such a light shielding film LS is formed using a metal material such as molybdenum (Mo), tungsten (W), aluminum (Al), titanium (Ti), silver (Ag), for example.

  The semiconductor layer SC is disposed on the first insulating film 11 and is covered with the second insulating film 12. The second insulating film 12 corresponds to a first interlayer insulating film that covers the semiconductor layer SC. In the semiconductor layer SC, from one end side to the other end side, the first high concentration region RH1 and the first low concentration region RL1, the channel region CN, and the second high concentration region of the second impurity region R2 in the first impurity region R1. The region RH2 and the second low concentration region RL2 are arranged in this order. The channel region CN is located immediately above the one end portion LSA of the light shielding film LS. The second impurity region R2 is located immediately above the other end portion LSB of the light shielding film LS. In the illustrated example, the second low concentration region RL2 is located immediately above the other end LSB.

  The gate electrode WG that is a part of the gate wiring G <b> 1 is disposed on the second insulating film 12 and covered with the third insulating film 13. The gate electrode WG is located immediately above the channel region CN. The third insulating film 13 corresponds to a second interlayer insulating film that covers the gate electrode WG.

  The source line S1 and the relay electrode RE are disposed on the third insulating film 13 and covered with the fourth insulating film 14. The source line S1 and the relay electrode RE can be collectively formed using the same material. The source line S1 is electrically connected to the first impurity region R1 through a contact hole CH1 that penetrates the second insulating film 12 and the third insulating film 13. The relay electrode RE is electrically connected to the second impurity region R2 through a contact hole CH2 penetrating the second insulating film 12 and the third insulating film 13. In the illustrated example, the source line S1 is in contact with the first high concentration region RH1, and the relay electrode RE is in contact with the second high concentration region RH2.

  The pixel electrode is in contact with the relay electrode RE through a contact hole that penetrates the fourth insulating film 14.

  The gate wiring G1 including the gate electrode WG, the source wiring S1, and the relay electrode RE are made of a metal material such as molybdenum (Mo), tungsten (W), aluminum (Al), titanium (Ti), silver (Ag), for example. It is formed using.

  According to the present embodiment, the switching element SW disposed in each pixel PX is configured by a thin film transistor having a single gate structure. In the semiconductor layer SC, the channel region CN is formed in an L shape, and the channel length L1 of the inner edge CNI is equal to the channel length L2 of the outer edge CNO. For this reason, it is possible to alleviate local current concentration inside the channel region CN in the semiconductor layer SC.

  In order to make the channel lengths of the inner edge CNI and the outer edge CNO equal in the bent channel region CN, the semiconductor layer SC is formed between the first impurity region R1 located on the source wiring side and the channel region CN. The boundary BC1 extends in a direction different from the extending direction of the impurity region R1 (the second direction Y in the above example). In such a semiconductor layer SC, the first impurity region R1 has a first low concentration region RL1 and a first high concentration region RH1, and a boundary between the first low concentration region RL1 and the first high concentration region RH1. BR1 includes a curved portion CV having an edge length of the first low concentration region RL1 along the inner edge CNI of the channel region CN as a curvature radius. That is, in the first low concentration region RL1, the distance from the boundary BC1 between the channel region CN and the first low concentration region RL1 to the boundary BR1 between the first low concentration region RL1 and the first high concentration region RH1 is substantially constant. It is. For this reason, it is possible to alleviate local current concentration even in the first low-concentration region RL1 in the semiconductor layer SC. As a result, even if the switching element SW is downsized due to high definition and the like, it is possible to suppress deterioration of the electrical characteristics of the switching element SW.

  Further, according to the present embodiment, a part of the semiconductor layer SC of the switching element SW is opposed to the source line S. That is, since a part of the switching element SW is located in a region overlapping with a wiring that does not contribute to display, even if the pixel size is reduced due to high definition or the like, Reduction of the area contributing to display is suppressed. Therefore, sufficient luminance or transmittance can be obtained in each pixel PX.

  Further, the other end connected to the pixel electrode PE of the switching element SW does not face the source line S. In particular, the second impurity region R2 of the semiconductor layer SC is disposed at a position shifted from a position facing the source line S. Therefore, capacitive coupling between the semiconductor layer SC on the pixel electrode side and the source wiring S is prevented, and the potential on the pixel electrode side of the switching element SW is stabilized regardless of the video signal supplied to the source wiring S. It becomes possible. For this reason, it is possible to suppress the disturbance of the pixel potential held in the pixel electrode PE. Therefore, it is possible to obtain a good display quality.

  In addition, according to the present embodiment, the semiconductor layer SC of the switching element SW is opposed to the light shielding film LS disposed on the back surface side (that is, the side on which the backlight is disposed). The light-shielding film LS includes a region in the semiconductor layer SC where light leakage occurs significantly, particularly a region including a boundary between a channel region located on the pixel electrode side and an impurity region (second impurity region in the above example). It arrange | positions so that it may oppose. For this reason, it becomes possible to block the backlight light toward the region where light leakage is likely to occur in the semiconductor layer SC. Therefore, light leakage in the switching element SW can be suppressed. As a result, it is possible to suppress malfunction of the switching element SW due to light leakage and fluctuation of the pixel potential held by the pixel electrode PE.

  Next, another configuration example of the switching element SW will be described.

  FIG. 7 is a plan view schematically showing another configuration example of the switching element SW applicable to the display device of the present embodiment.

  The illustrated configuration example is different from the configuration example illustrated in FIG. 4 in that the gate wiring G1 including the gate electrode WG extends linearly and the semiconductor layer SC is formed in a crank shape. Note that the switching element SW is formed of a single-gate thin film transistor, as in the above example.

  In the illustrated example, the gate line G1 extends in the first direction X, and the source line S1 and the source line S2 each extend in the second direction Y. Note that the source wiring S1 and the source wiring S2 do not necessarily extend linearly, and may be bent so as to cross obliquely with respect to the second direction Y.

  Focusing on the switching element SW located between the source wiring S1 and the source wiring S2, the semiconductor layer SC has a first impurity region R1, a channel region CN, and a second impurity region R2. The first impurity region R1 may have a first high concentration region and a first low concentration region, as in the above example. Similarly, the second impurity region R2 may have a second high concentration region and a second low concentration region, as in the above example.

  The first impurity region R1 extends in parallel with the source line S1 and faces the source line S1. That is, the first impurity region R1 extends in the second direction Y, and the whole of the first impurity region R1 overlaps the source line S1 in the XY plane. Such a first impurity region R1 is electrically connected to the source line S1 through the contact hole CH1.

  The second impurity region R2 is located between the source line S1 and the source line S2, and extends substantially parallel to the first impurity region R1. That is, the second impurity region R2 is disposed at a position where the entirety of the second impurity region R2 does not overlap with the source line S1 and the source line S2 in the XY plane. Further, the second impurity region R2 is located on the opposite side of the first impurity region R1 with the gate wiring G1 interposed therebetween, and is further displaced from the same straight line where the first impurity region R1 extends. ing. Such a second impurity region R2 is electrically connected to the relay electrode RE through the contact hole CH2. In the illustrated example, the relay electrode RE does not face any of the gate line G1, the source line S1, and the source line S2.

  The channel region CN is connected to the first impurity region R1 on one end side (source wiring S1 side) and is connected to the second impurity region R2 on the other end side (source wiring S2 side). The channel region CN is bent at about 90 degrees with respect to the first impurity region R1 and the second impurity region R2, and extends in the first direction X. Such a channel region CN is opposed to the gate electrode WG which is a part of the gate wiring G1. Of the gate wiring G1, at least the gate electrode WG is desirably formed wider than the width along the second direction Y of the channel region CN. Accordingly, it is possible to secure a margin for misalignment with the semiconductor layer SC when forming the gate wiring G1 after forming the semiconductor layer SC. In the illustrated example, the gate line G1 is formed to have a certain width.

  In such a channel region CN, the channel length L21 of one edge CNA is equal to the channel length L22 of the other edge CNB.

  The light shielding film LS is disposed so as to face the region including the boundary between the channel region CN and the second impurity region R2. In the illustrated example, the light shielding film LS faces the region on the relay electrode side of the channel region CN and the region adjacent to the channel region CN of the second impurity region R2 in the semiconductor layer SC. On the other hand, the light shielding film LS does not face the first impurity region R1. Further, the light shielding film LS is formed in an island shape, and is disposed at a position shifted from a position facing the source wiring S1 and the source wiring S2.

  According to such a configuration example, the switching element SW disposed in each pixel PX is configured by a single-gate thin film transistor, and the channel region CN of the semiconductor layer SC has a gate wiring extending linearly. Opposing to G1, the first impurity region R1 extends in parallel with the source wiring S1 and opposes the source wiring S1. That is, since many portions of the switching element SW are located in a region overlapping with wiring that does not contribute to display, even if the pixel size is reduced due to high definition or the like, The reduction of the area contributing to the display is suppressed. Therefore, sufficient luminance or transmittance can be obtained in each pixel PX.

  Further, the gate wiring G1 including the gate electrode WG has a linearly extending shape, and can be easily processed. In addition, since at least the gate electrode WG of the gate wiring G1 is formed wider than the width along the second direction Y of the channel region CN, the semiconductor layer SC when the gate wiring G1 is formed is formed. A margin for misalignment can be secured.

  The semiconductor layer SC is formed in a crank shape, and in the channel region CN, the channel length L21 of one edge CNA thereof is equal to the channel length L22 of the other edge CNB. For this reason, it is possible to alleviate local current concentration inside the channel region CN in the semiconductor layer SC. As a result, even if the switching element SW is downsized due to high definition and the like, it is possible to suppress deterioration of the electrical characteristics of the switching element SW.

  Further, the other end connected to the pixel electrode PE of the switching element SW does not face the source line S1 and the source line S2. In particular, the second impurity region R2 of the semiconductor layer SC is disposed at a position shifted from the position facing the source line S1 and the source line S2. For this reason, as in the above configuration example, it is possible to suppress the disturbance of the pixel potential held in the pixel electrode PE. Therefore, it is possible to obtain a good display quality.

  Further, the light shielding film LS is disposed so as to face a region including a boundary between the channel region and the impurity region located on the pixel electrode side. For this reason, similarly to the above configuration example, it is possible to suppress light leakage in the switching element SW. As a result, it is possible to suppress malfunction of the switching element SW due to light leakage and fluctuation of the pixel potential held by the pixel electrode PE.

  FIG. 8 is a plan view schematically showing another configuration example of the switching element SW applicable to the display device of the present embodiment.

  The illustrated configuration example is different from the configuration example illustrated in FIG. 7 in that the semiconductor layer SC is formed in a U shape.

  The first impurity region R1 extends in parallel with the source line S1 and faces the source line S1. That is, the first impurity region R1 extends in the second direction Y, and the whole of the first impurity region R1 overlaps the source line S1 in the XY plane.

  The second impurity region R2 is located between the source line S1 and the source line S2, and extends substantially parallel to the first impurity region R1. That is, the second impurity region R2 is disposed at a position where the entirety of the second impurity region R2 does not overlap with the source line S1 and the source line S2 in the XY plane. The second impurity region R2 is located on the same side as the first impurity region R1 with respect to the gate wiring G1, and is disposed in parallel with the first impurity region R1.

  The channel region CN is connected to the first impurity region R1 on one end side (source wiring S1 side) and is connected to the second impurity region R2 on the other end side (source wiring S2 side). The channel region CN is bent at about 90 degrees with respect to the first impurity region R1 and the second impurity region R2, and extends in the first direction X. Such a channel region CN is opposed to the gate electrode WG which is a part of the gate wiring G1.

  The light shielding film LS is disposed so as to face the region including the boundary between the channel region CN and the second impurity region R2.

  In such a configuration example, the same effect as the configuration example shown in FIG. 6 can be obtained. In the illustrated example, the semiconductor layer SC is formed in a U shape, and in the channel region CN, the channel length of one edge CNA is longer than the channel length of the other edge CNB, but the angle of the channel region CN is By removing and rounding, the channel length of the edge CNA can be shortened, and the difference from the channel length of the edge CNB can be reduced.

  Although the liquid crystal display device has been described as an example of the display device in the above embodiment, the present embodiment can be applied to other display devices such as an organic EL display device.

  As described above, according to the present embodiment, it is possible to provide a display device with good display quality.

  In addition, this invention is not limited to the said embodiment itself, In the stage of implementation, it can change and implement a component within the range which does not deviate from the summary. Further, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, you may combine suitably the component covering different embodiment.

PNL ... display panel AR ... array substrate CT ... counter substrate LQ ... liquid crystal layer SW ... switching element WG ... gate electrode SC ... semiconductor layer CN ... channel region R1 ... first impurity region R2 ... second impurity region LS ... light shielding film

Claims (6)

An insulating substrate;
Gate wiring,
A source wiring crossing the gate wiring;
A first semiconductor layer formed of polysilicon and including a first high concentration region and a first low concentration region having an impurity concentration lower than that of the first high concentration region and electrically connected to the source line. An impurity region, a second impurity region, and a channel length of an inner edge and an outer edge of the outer edge are formed between the first impurity region and the second impurity region, and are formed in an L shape facing the gate wiring. A channel region having a channel length equivalent to the channel length;
A pixel electrode electrically connected to the second impurity region,
The boundary between the first low-concentration region and the first high-concentration region includes a curved portion having a curvature radius that is an edge length of the first low-concentration region along the inner edge of the channel region.   The display device according to claim 1, wherein the source wiring is disposed at a position facing the first impurity region and shifted from a position facing the second impurity region. An insulating substrate;
A gate line extending in a straight line;
A first source line and a second source line intersecting the gate line;
A semiconductor layer formed of polysilicon, extending in parallel with the first source line and facing the first source line and electrically connected to the first source line; A second impurity region located between the first source line and the second source line and extending in parallel with the first impurity region; and located between the first impurity region and the second impurity region. A semiconductor layer having a channel region facing the gate wiring;
A pixel electrode electrically connected to the second impurity region;
A display device comprising:   The display device according to claim 3, wherein the semiconductor layer is formed in a crank shape or a U shape.   The display device according to claim 4, wherein in the channel region, the channel length of one edge thereof is equal to the channel length of the other edge.   6. The light-shielding film according to claim 1, further comprising a light shielding film located between the insulating substrate and the semiconductor layer and facing a region including a boundary between the channel region and the second impurity region. The display device described.

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