JP2015225522A - System and failure processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a system and a failure processing method that can stop a portion where a failure has occurred without causing operation stop of the whole system in the case where the failure has occurred at the portion constituting the system.SOLUTION: A system includes: control means for controlling the whole system; a switch for communicating with the control means in accordance with a communication standard of PCI Express; a device for communicating with the switch in accordance with the communication standard PCI Express; and a monitoring unit that communicates with the switch in accordance with a predetermined communication standard, monitors if there is a failure in the device, transmits information for controlling the switch to the switch via communication in accordance with the predetermined communication standard if a failure is detected, and thereby restrains transfer of information on the failure to the control means from the switch via communication in accordance with the communication standard PCI Express.

Description

  The present invention relates to a system and a failure processing method.

  In Patent Document 1, in a computer system in which a server chassis having at least one server and an IO slot expansion device equipped with a PCIe switch are connected by a PCIe cable, the server includes: an arithmetic unit; The IO slot expansion device has a PCIe switch, an IO slot expansion device controller connected to the PCIe switch, and a PCI card slot connected to the PCIe switch. The PCI card slot includes a PCI card having an HBA and an HBA port, the HBA has an identifier area for holding an identifier assigned to each HBA port, and the PCIe switch includes a PCIe switch register. The IO slot expansion device controller has the HBA port of the PCI card mounted in the PCI card slot An allocation identifier table for managing allocated identifiers, and a PCIe switch register update control unit. The PCIe switch register update control unit receives power on the IO slot expansion device, and the IO slot expansion device controller The assigned identifier table having is copied to the identifier storage area of the PCIe switch register, and the HBA identifier update control unit included in the interface receives the power-on of the server, and the PCIe switch via the PCIe cable An allocation identifier table replicated in the identifier storage area of the register is acquired, the acquired allocation identifier table is stored in the storage unit of the server, and the PCI card slot is stored in the storage unit from the allocation identifier table stored in the storage unit. And the HBA port on the PCI card Against reference identifiers, the identifier recorded in the identifier area of the HBA, the computer system and updates the assignment identifier referenced from the allocation identifier table stored in the storage unit is disclosed.

JP 2012-150623 A

  An object of the present invention is to provide a system and a failure processing method capable of stopping a site where a failure has occurred without causing an operation stop of the entire system when a failure occurs in a site constituting the system. is there.

  In order to achieve the above object, the system according to claim 1 includes a control unit that controls the entire system, a switch that communicates with the control unit according to a PCI Express communication standard, and a communication between the switch and PCI Express. A device that communicates with a standard is communicated with the switch according to a predetermined communication standard, and monitors whether or not the device has a failure. When a failure is detected, the communication is performed according to the predetermined communication standard. By transmitting information for controlling the switch via communication to the switch, it is possible to prevent information relating to the failure from being transferred from the switch to the control means via communication according to the PCI Express communication standard. And a monitoring unit.

  According to a second aspect of the present invention, in the first aspect of the present invention, the monitoring unit and the device are connected via a transmission line that transmits a predetermined signal, and the monitoring unit is configured to perform the predetermined determination. The information for controlling the switch is transmitted to the switch through communication according to the communication standard, and then a signal for stopping the device is transmitted through the transmission path.

  According to a third aspect of the present invention, in the first or second aspect of the present invention, the device is configured so that the monitoring unit controls the switch via communication according to the predetermined communication standard. Before transmitting a signal for stopping the device via the transmission path after transmitting the information to the switch, the log information is collected in advance and communicated to the control means via communication according to the PCI Express communication standard. To be sent.

  The invention according to claim 4 is the invention according to any one of claims 1 to 3, wherein the information for controlling the switch is a PCI Express that stores register information of the switch. This is information for enabling Uncorrectable Error MASK of the AER register stored in the standardized configuration register.

The invention according to claim 5 is the invention according to any one of claims 1 to 4, wherein the predetermined communication standard is an I ² C communication standard.

  The invention according to claim 6 is the invention according to any one of claims 1 to 5, wherein the device includes a temperature control unit that controls its own temperature, and the failure of the device is This is a failure of the temperature control unit.

  On the other hand, in order to achieve the above object, the failure processing method according to claim 7 monitors the presence of a failure of a device that communicates with a switch and a PCI Express communication standard and communicates with the switch in advance. A step of detecting a failure of the device by a monitoring unit that communicates according to a standard; and a step of transmitting information for the monitoring unit to control the switch via communication according to the predetermined communication standard. And the step of inhibiting the information related to the failure from being transferred from the switch to the control means for controlling the entire system via the communication according to the PCI Express communication standard by the information for controlling the switch. Is included.

  According to the first and seventh aspects of the present invention, when a failure occurs in a part constituting the system, there is an effect that the part in which the failure occurs is stopped without causing an operation stop of the entire system. can get.

  According to the second aspect of the present invention, the monitoring unit does not stop the device via the transmission line after transmitting information for controlling the switch to the switch via communication according to a predetermined communication standard. In comparison, the effect is obtained that the failed device is disconnected from the system.

  According to the third aspect of the present invention, the monitoring unit transmits information for controlling the switch via communication according to a predetermined communication standard, and then transmits a signal for stopping the device via the transmission path. Compared with the case where the device collects predetermined log information and does not send it to the control means via communication according to the PCI Express communication standard, the control means logs information such as failure contents before the device is stopped. Is obtained.

  According to the fourth aspect of the present invention, the uncorrectable error MASK of the AER register stored in the configuration register standardized by PCI Express that stores the register information of the switch is enabled as information for controlling the switch. Compared with the case where the information is not used, the system down is more easily suppressed.

According to the fifth aspect of the present invention, there is no information for controlling the switch via a more general communication path than in the case where the I ² C communication standard is not used as the predetermined communication standard. The effect of being transmitted to the switch is obtained.

  According to the sixth aspect of the invention, it is possible to obtain an effect that an excessive temperature rise of the device is suppressed as compared with a case where the failure of the device is not the failure of the temperature control unit of the device itself.

It is a schematic block diagram which shows an example of a structure of the computer which concerns on embodiment. It is a schematic block diagram which shows an example of a structure of the accelerator board | substrate which concerns on embodiment. It is a figure for demonstrating the operation | movement at the time of the failure occurrence of the computer based on a prior art. It is a figure for demonstrating the procedure of the failure processing method of the computer which concerns on embodiment. It is a figure for demonstrating the operation | movement at the time of the failure generation of the computer which concerns on embodiment. It is a figure for demonstrating the configuration register of a PCIe switch which concerns on embodiment, and an AER register.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following description, an example in which the system according to the present invention is applied to a computer that executes image processing or the like provided in association with an image forming apparatus will be described. An image formed by the image forming apparatus is usually processed by software operating on a CPU (Central Processing Unit) of the image forming apparatus and supplied to the image forming unit of the image forming apparatus.

  On the other hand, in a high-speed image forming apparatus, apart from processing by software, hardware specialized for an image processing function (device: hereinafter, “device” is not limited to a dedicated circuit such as an ASIC, for example. A printed wiring board on which such a dedicated circuit is mounted may also be referred to as a “device.”), That is, the dedicated hardware may be expanded to accelerate the processing. In that case, a computer having an extended hardware for image processing may be provided separately from the image forming apparatus. In the following description of the system according to the present embodiment, an example in which the present invention is applied to such a computer will be described.

  Various means such as USB (Universal Serial Bus) are applied as means for expanding the hardware, but in the computer according to the present embodiment, PCI Express (registered trademark) (Peripheral Component Interconnect Express, hereinafter referred to as “PCIe”). An example in which the hardware is expanded according to the communication standard is described. That is, in the computer according to the present embodiment, at least a part of each part constituting the computer is connected via the PCIe communication standard. Note that the computer in this embodiment is a concept including hardware and an operating system (hereinafter also referred to as “OS”), and means hardware that operates under the control of the OS.

  Here, in the PCIe communication standard, data transmission devices are connected point-to-point by a pair of serial transmission lines capable of transmitting data at 2.5 Gbps (bit per second) or 5.0 Gbps, The data communication network has a tree structure with the root complex as a vertex. In the PCIe communication standard, data transmission between devices can be speeded up by parallelizing a plurality of lanes. In the PCIe communication standard, data transmission between connected devices is performed using packets.

  FIG. 1 is a schematic configuration diagram showing an example of a configuration of a computer 10 as a system according to the present embodiment. As shown in FIG. 1, the computer 10 includes a main CPU 12, a DDR (Double Data Rate) memory 14, a root complex (indicated as “Root Complex” in FIG. 1) 16, and accelerator boards 20 and 22. Yes. In addition to the configuration shown in FIG. 1, the computer 10 is provided with a substrate and the like for connection to the image forming apparatus.

  As shown in FIG. 1, in the computer 10 according to the present embodiment, a system used for a main complex 12 that controls the operation of the entire apparatus, a variety of processes of the main CPU 12, and the like in a root complex 16 positioned at the top of the tree structure. A DDR memory 14 as a memory is connected. The main CPU 12 is loaded with an OS that controls the entire computer 10.

  Further, accelerator boards 20 and 22 as devices used for realizing an image processing function such as image compression and decompression are connected to the root complex 16. The root complex is a method for reading setting information of each device from the configuration space of each device compliant with the PCIe standard connected via a communication path based on the PCIe communication standard, assigning an address space to each device, It is a communication device that controls the transfer of data to each of the devices. The root complex 16 of the computer 10 according to the present embodiment controls allocation of address space to the accelerator boards 20 and 22 and data transfer, that is, packet transfer and the like.

As shown in FIG. 1, the accelerator board 20 includes a PCIe switch (indicated as “PCIe Switch” in FIG. 1) 18, and N DRPs (Dynamically Reconfigurable Processors) connected to the PCIe switch 18.
Dynamic reconfigurable processor) 28-1 to DRP 28-N and DDR memory 30-1 to DDR memory 30-N. In the following, when each of DRP 28-1 to DRP-N is not distinguished, it is expressed as “DRP 28”, and when each of DDR memory 30-1 to DDR memory 30-N is not distinguished, “DDR memory”. 30 ”.

  The PCIe switch 18 is a communication device that connects two or more ports and routes packets between the ports. That is, the PCIe switch 18 controls data transfer between the root complex 16 and the DRP 28, that is, packet transfer. Further, the PCIe switch 18 includes a configuration register that stores its own information and status, as will be described later.

Further, the PCIe switch 18 according to the present embodiment has an AER (Advanced Error Reporting) function. For example, when a failure occurs in the computer 10, information on the failure is recorded in the AER register. What is the AER register?
This is a 32-bit register standardized as an option of the PCIe communication standard, and constitutes a part of the configuration register.

  The DRP 28 is a processor that executes an image processing function. The DRP 28 is equipped with a dedicated circuit as hardware and firmware that executes control of image processing and the like (hereinafter sometimes referred to as “FW”). The DDR memory 30 is a memory used for executing the FW.

  Similarly to the accelerator substrate 20, the accelerator substrate 22 includes a PCIe switch 24, and a member (not shown) that executes an image processing function such as DRP is connected to the PCIe switch 24. In the computer 10 according to the present embodiment, an example in which two accelerator boards 20 and 22 are connected to the root complex 16 will be described as an example. However, the present invention is not limited to this, and an accelerator board is required. Three or more sheets may be provided according to the image processing capability.

  FIG. 2 is a configuration diagram showing a more detailed configuration of the accelerator substrate 20 according to the present embodiment. As shown in FIG. 2, the accelerator board 20 includes a PCIe switch 18, DRP 28-1, 28-2, CPLD (Complex Programmable Logic Device) 32, a fan (indicated as “FAN” in FIG. 2) 34, a temperature sensor ( In FIG. 2, it is configured including “TEMP”. 2 illustrates an example in which two DRPs are connected to the PCIe switch 18, and the illustration of the DDR memories 14 and 30 and the route complex 16 in FIG. 1 is omitted. Yes.

  The fan 34 shown in FIG. 2 is a fan for cooling the DRP 28-1 (hereinafter simply referred to as “DRP 28”) mounted on the accelerator board 20, and suppresses the temperature rise of the DRP 28 as a heating element. doing. The temperature sensor 36 is disposed in contact with or around the DRP 28 and detects the temperature of the DRP 28.

  The CPLD 32 mainly controls the fan 34 so that the temperature of the DRP 28 falls within a predetermined range based on the temperature detected by the temperature sensor 36. The CPLD 32 monitors the occurrence of a failure such as an abnormality of the fan 34, that is, an operation stop of the fan 34. That is, the CPLD 32 controls the temperature of the DRP 28 by controlling the operation of the fan 34 and functions as a monitoring / control unit that monitors the occurrence of a failure in the fan 34.

  In the accelerator board 20, the main CPU 12 and the PCIe switch 18 and the PCIe switch 18 and the DRP 28 are connected via a PCIe interface, that is, connected by a PCIe communication path. Further, the DRP 28 and the CPLD 32, the CPLD 32 and the fan 34, and the CPLD 32 and the temperature sensor 36 are connected via an interface based on a level (amplitude) signal such as a CMOS interface or a TTL interface. That is, they are connected by a transmission path for transmitting level signals. In the accelerator substrate 20 according to the present embodiment, as an example, a transmission path using a CMOS interface is employed.

As shown in FIG. 2, in the computer 10 according to the present embodiment, I ² C (Inter-Integrated Circuit) communication is performed between the PCIe switch 18 and the CPLD 32, unlike a connection via only a general PCIe interface. They are connected by a standard communication path. Therefore, between the PCIe switch 18 and the CPLD 32,
Communication is performed through a path different from the communication via the PCIe interface and the signal transmission through the transmission path. Details of the communication path according to the I ² C communication standard will be described later.

  By the way, when the hardware is expanded according to a predetermined communication standard, if a serious failure of the hardware itself (for example, fear of excessive temperature rise of the hardware) is detected by some method, the main CPU, etc. In some cases, it is desired to immediately reset (stop) the hardware after notifying the host system of the failure. However, in the system according to the related art, when the hardware in which the failure has occurred is immediately stopped, the OS may hang up and the system may be down.

  An example of the case where the above system failure occurs will be described with reference to FIG. FIG. 3 is a diagram for explaining the operation when a failure occurs in the computer 10 according to the related art.

The accelerator board 20a of the computer 10 according to the prior art shown in FIG. 3 is obtained by deleting the communication path according to the I ² C communication standard in the accelerator board 20 according to the present embodiment shown in FIG. Reference numerals are assigned and explanations thereof are omitted. In the following, a case where the failure that has occurred is an operation stop of the fan 34 will be described as an example. Note that [1] to [5] shown in FIG. 3 correspond to positions where the operations of the following steps [1] to [5] occur.

[1]: The CPLD 32 detects the operation stop of the fan 34 (hereinafter sometimes referred to as “Fan-Fail”).
[2]: The CPLD 32 notifies the DRP 28 of Fan-Fail.
[3]: The FW of DRP 28 notifies Fan-Fail to the main CPU 12, that is, the OS as the host system.
[4]: The CPLD 32 resets the DRP 28, that is, stops the operation. This is because the temperature control of the DRP 28 becomes impossible because the operation of the fan 34 is stopped, and the temperature of the DRP 28 may rise abnormally.
[5]: When the main CPU 12 receives a packet containing an uncorrectable error (hereinafter sometimes referred to as “Uncorrectable Error”), the OS hangs up (the main CPU 12 stops and the system goes down) Occur).

  Here, the reason why the OS hangs up in step [5] will be described.

  Between the DRP 28 and the PCIe switch 18, the existence of each other is confirmed while transmitting and receiving packets on the normal PCIe interface. However, when the DRP 28 is reset, a packet on the PCIe interface cannot be transmitted or received suddenly (a link break occurs between the DRP 28 and the PCIe switch 18), so that the PCIe switch 18 is in the downstream (downstream) direction. The absence is detected, that is, so-called Surprise Down Error is detected.

When the PCIe switch 18 detects a surprise down error, the PCIe switch 18 transfers a packet having the contents of the uncorrectable error to the main CPU 12. Uncorrectable Error is an error that occurs when the error that has occurred cannot be corrected by hardware,
Also, since the processing method is unknown, the OS hangs up.

  As described above, in the accelerator substrate 20a according to the related art, the OS may hang up when a failure occurs. When the OS hangs up, not only does the operation of the computer 10 stop, but it also becomes impossible to collect log information (history of processing contents in the computer 10, history of warnings, etc.) of each device connected in the computer 10. Therefore, the cause of the OS hanging up cannot be clarified, and the coping method is unknown.

Therefore, in the present invention, a device that detects a failure transmits information based on the failure to the PCIe switch via a communication path based on the I ² C communication standard, which is a communication path different from the communication path based on the PCIe communication standard. Then, the uncorrectable error MASK of the AER register of the PCIe switch is forcibly rewritten by the information based on the failure so as to enable the MASK. As a result, the Uncorrectable Error message packet is not transferred from the PCIe switch to the host system, so that OS hang-up or system down is avoided.

  Next, referring to FIG. 4 to FIG. 6, a failure processing method in the case where a failure (Fan-Fail) of the operation stop of the fan 34 occurs in the computer 10 as the system according to the present embodiment, and the computer 10 The operation will be described.

  FIG. 4 shows a procedure of a failure processing method when Fan-Fail occurs in the computer 10 according to the present embodiment, and FIG. 5 shows a computer in which an operation corresponding to each step of the failure processing method occurs. The site | part in 10 is shown. That is, [1] to [5] in FIG. 5 correspond to steps S1 to S5 shown in FIG.

  Referring to FIGS. 4 and 5, in step S1, CPLD 32 detects Fan-Fail of fan 34 via a transmission path using a CMOS interface.

  In the next step S2, the CPLD 32 notifies the DRP 28 of Fan-Fail via a transmission path using a CMOS interface.

In the next step S3, the CPLD 32 forcibly rewrites the Uncorrectable Error MASK register of the corresponding AER register of the PCIe switch 18 via the I ² C port to enable MASK. Specifically, the rewrite information is transmitted by designating an address (for example, 0xFBC) in the AER register of Uncorrectable Error MASK, and all-F is forcibly written in Uncorrectable Error MASK. As a result, the transfer of the Uncorrectable Error message packet to the main CPU 12 by the PCIe switch 18 is prohibited.

  Here, the AER register will be described in more detail with reference to FIG. FIG. 6 is a diagram illustrating an example of the configuration of the PCIe switch 18 according to the present embodiment.

As shown in FIG. 6, the PCIe switch 18 includes a plurality (three in the example shown in FIG. 6) of ports P1, P2, and P3 (hereinafter collectively referred to as “port P”), and the PCIe switch 18 is provided for each port. Configuration registers (hereinafter sometimes simply referred to as configuration registers) C1, C2, and C3 (hereinafter collectively referred to as “configuration registers C”) are provided. Further, as described above, the PCIe switch 18 includes the interface 40 of the I ² C communication standard for performing communication with the CPLD 32.

  When a failure occurs, each of the plurality of ports P detects the failure and records failure information in the configuration register C. More specifically, fault information is recorded in an AER register that is a part of the configuration register C. Here, the failure information is information indicating the content of the failure. For example, when a link disconnection with the device connected to the port P occurs, “Surprise Down Error” is recorded in the AER register. Further, each of the plurality of ports transmits an Uncorrectable Error message packet to the main CPU 12 when a failure corresponding to an uncorrectable error is detected.

  4 and 5 again, in the next step S4, the FW of the DRP 28 notifies the OS of Fan-Fail via the PCIe interface.

  In the next step S5, the CPLD 32 resets the DRP 28 via the transmission path using the CMOS interface, that is, stops the operation. At this time, since the Uncorrectable Error MASK of the AER register of the PCIe switch 18 is enabled in Step S3, the Uncorrectable Error message packet is not transferred to the main CPU 12. In the state in which the computer 10 according to the present embodiment is operating normally, the Uncorrectable Error MASK is disabled, that is, the Uncorrectable Error message packet is transmitted to the main CPU 12.

  With the above procedure, the DRP 28 is disconnected from the system, and the temperature rise of the DRP 28 due to the stop of the operation of the fan 34 is avoided. In addition, since the CPU 12 does not receive the Uncorrectable Error packet, the OS does not hang up (the system goes down).

  Here, although the case where the DRP 28 is reset has been described in the above embodiment, a step of collecting log information in addition to resetting the DRP 28 may be added. In this case, for example, a step of “collecting a log that requires FW of the DRP 28 and sending it to the main CPU 12 as a host system” may be added between the step S4 and the step S5.

In the above embodiment, an example in which the CPLD 32 uses the I ² C port to forcibly rewrite the uncorrectable error MASK register of the corresponding AER register of the PCIe switch 18 to enable MASK in step S3. However, this is not a limitation. For example, a register rewrite driver for the PCIe switch 18 may be installed in the main CPU 12 so that the main CPU 12 rewrites the Uncorrectable Error MASK register. In this case, after the main CPU 12 completes the rewriting or additionally collects the log information, the register rewriting and the log information collection are notified to the CPLD 32, and the CPLD 32 then resets the DRP 28. .

  In the above-described embodiment, the present invention has been described by exemplifying a case where a failure related to temperature control occurs in a computer that executes image processing or the like. The present invention may be applied to a case where a serious failure, for example, an abnormality occurs in a laser output of a drawing portion by a laser of an image forming apparatus.

  In the above embodiment, the case where the case where the fan 34 stops operating is described as an example. However, the present invention is not limited to this. For example, the temperature of the temperature sensor 36 exceeds a predetermined threshold. You may apply to the form which detects this as a fault.

10 Computer 12 Main CPU
14, 30 DDR memory 16 Root complex 20, 20a, 22 Accelerator board 18, 24 PCIe switch 28 DRP
32 CPLD
34 Fan 36 Temperature sensor 40 I ² C interface C1, C2, C3 Configuration registers P1, P2, P3 ports

Claims (7)

Control means for controlling the entire system;
A switch capable of communicating with the control means according to a PCI Express communication standard;
A device capable of communicating with the switch according to a PCI Express communication standard;
The switch communicates with the switch according to a predetermined communication standard, monitors whether or not the device has a failure, and controls the switch via communication according to the predetermined communication standard when a failure is detected. A monitoring unit that suppresses transfer of information regarding the failure from the switch to the control unit via communication according to a PCI Express communication standard by transmitting information to the switch;
Including system. The monitoring unit and the device are connected by a transmission path that transmits a predetermined signal,
2. The monitoring unit transmits a signal for stopping the device via the transmission path after transmitting information for controlling the switch to the switch via communication according to the predetermined communication standard. The system described in. The device transmits a signal for stopping the device via the transmission line after the monitoring unit transmits information for controlling the switch via communication according to the predetermined communication standard. The system according to claim 1 or 2, wherein previously collected log information is collected and transmitted to the control means via communication according to a communication standard of PCI Express. The information for controlling the switch is information for enabling Uncorrectable Error MASK of an AER register stored in a configuration register standardized by PCI Express that stores register information of the switch. The system according to any one of claims 1 to 3. The system according to claim 1, wherein the predetermined communication standard is an I ² C communication standard. The system according to any one of claims 1 to 5, wherein the device includes a temperature control unit that controls its own temperature, and the failure of the device is a failure of the temperature control unit. Monitoring the presence or absence of a failure of a device that communicates with a switch and a PCI Express communication standard, and detecting a failure of the device by a monitoring unit that communicates with the switch according to a predetermined communication standard;
Transmitting the information for controlling the switch to the switch through communication according to the predetermined communication standard by the monitoring unit;
Suppressing the information related to the failure from being transferred from the switch to a control unit that controls the entire system through communication based on a PCI Express communication standard, based on information for controlling the switch;
Failure handling method.

Images