JP2015216697A - Diversity receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique for minimizing the number of pins and the size of a diversity operation memory according to the reduction of a reception chip size, in an OFDM receiver applied to terrestrial digital broadcast.SOLUTION: A diversity receiver 100 includes: a data receiver unit for receiving a bit stream from a transmitter; a deinterleaver unit 118 for generating deinterleaving data by deinterleaving the bit stream; and a diversity processing unit 120 for calculating a minimized number of diversity data transfer lines on the basis of the output bits of the deinterleaving data, an output clock frequency and a diversity transfer clock frequency, and for performing communication with a mutually different diversity processing unit using the number of diversity data transfer lines.

Description

  The present invention relates to an ISDB-T (Integrated Services Digital Broadcasting-Terrestrial) mobile broadcast diversity receiver.

  It will be clarified that the content described below merely provides background information relevant to the present invention and does not constitute prior art.

  As a method for transferring digital signals, a modulation method called an Orthogonal Frequency Division Multiplexing (OFDM) method (hereinafter referred to as OFDM method) is used. In the OFDM method, a large number of orthogonal subcarriers are set within a transfer band, and data is assigned to the amplitude and phase of each subcarrier by PSK (Phase Shift Keying) or QAM (Quadrature Amplitude Modulation). A modulation method.

  Since the OFDM scheme divides the transfer band into a number of subcarriers, the band per subcarrier is narrowed and the modulation speed is reduced, but the overall transfer speed is not different from a general modulation system. In addition, according to the OFDM scheme, since a large number of subcarriers are transferred in parallel, the symbol rate becomes slow, and the time length of the multipath relative to the time length of the symbol is increased. Can be shortened, and has a feature of being resistant to multipath interference.

  Therefore, such an OFDM system is often applied to terrestrial digital broadcasting that is strongly affected by multipath interference. For terrestrial digital broadcasting employing such an OFDM system, for example, standards such as DVB-T (Digital Video Broadcasting-Terrestrial), ISDB-T (Integrated Services Digital Broadcasting-Terrestrial), ISDB-TSB (ISDBT Sound Broadcasting), etc. There is.

  However, a technique capable of minimizing the number of pins and a technique capable of minimizing the size of the diversity operation memory are required because the receiver chip size is reduced in the OFDM receiver.

  In implementing a diversity receiver, the present invention minimizes the number of pins (Pin Count) connecting the receiver chip and the receiver chip, thereby minimizing the internal memory size of the receiver chip. The purpose is to provide.

  According to an aspect of the present invention, a data reception unit that receives a bitstream from a transmission device, a deinterleaver unit that generates deinterleaving data obtained by deinterleaving the bitstream, And calculating the number of diversity data transfer lines minimized based on the output bit, output clock frequency, and diversity transfer clock frequency of the deinterleaving data, and communicating with different diversity processing units using the number of diversity data transfer lines. A diversity receiving apparatus including a diversity processing unit for performing the processing is provided.

  The diversity processing unit of the diversity receiving apparatus can calculate the number of diversity data transfer lines based on a value obtained by dividing the product of the output bit of the deinterleaving data and the output clock frequency by the diversity transfer clock frequency.

  At least two different diversity processing units of the diversity receiver are connected to each other, and a plurality of slaves for transferring a diversity transfer signal between them, and a diversity transfer signal finally combined from the last slave among the plurality of slaves One of the plurality of slaves can transmit data in the order of the master from the first slave.

  The diversity processing unit of the diversity receiver may insert a symbol start signal between valid periods of the deinterleaving data that is output data of the deinterleaver unit to set the diversity control transfer period to one line. it can.

  The diversity processor of the diversity receiver can transfer system information including symbol index information to the data line of the next cycle of the symbol start signal.

  The diversity processing unit of the diversity receiver performs a synchronization to match the start positions of the symbols of the input data, a received signal decoder unit for decoding the serialized data according to the number of diversity data transfer lines, and a data valid section And a transfer signal encoder for determining whether to transfer data depending on whether the slave or the master is set.

  The diversity processing unit of the diversity receiving apparatus can transfer the diversity transfer signal in real time in symbol units without additional data buffering for diversity transfer according to the data output section of the deinterleaver unit.

  The diversity processing unit of the diversity receiver can determine a synchronization memory size used for diversity combining based on a delay threshold between a symbol start signal and a data valid interval.

  The diversity processing unit of the diversity receiving device, when an exception operation occurs in any one of the plurality of slaves or the master and initialization by reset occurs, the reset generation time point indicates the effective section of diversity processing. It avoids the need for additional control logic due to the loss of data or control signals in symbol units that are regenerated and processed in symbol units to avoid.

  The diversity receiver includes a demapper that outputs demodulated data obtained by demodulating the deinterleaved data, and a decoder that generates decoded data obtained by decoding the demodulated data. Further can be included.

  According to another aspect of the present invention, a data receiving unit that receives a bit stream from a transmission device, a deinterleaver unit that generates deinterleaving data obtained by deinterleaving the bitstream, and the deinterleaving data Diversity data transfer by calculating a demapper that outputs demodulated demodulated data, and the output bit of the demodulated data, the output clock frequency of the deinterleaving data, the diversity transfer clock frequency based on the diversity transfer clock frequency, and the diversity data transfer Provided is a diversity receiver including a diversity processor that performs communication with different diversity processors using the number of pins.

  The diversity processing unit of the diversity receiver calculates the number of diversity data transfer pins based on a value obtained by dividing the product of the output bit of the demodulated data and the output clock frequency of the deinterleaving data by the diversity transfer clock frequency. Can do.

  The diversity receiver can further include a decoding unit that generates decoded data obtained by decoding the demodulated data.

  According to the present invention, when implementing a diversity receiver, the number of pins connecting the receiving chip and the receiving chip can be minimized, and the operation memory size inside the receiving chip can be minimized.

  Further, according to the present invention, there is an effect that the stability of the receiving chip can be ensured without complicated control logic when diversity is combined.

FIG. 2 is a block diagram schematically illustrating a diversity receiving apparatus in which two or more ISDB-T single receiving chips according to an embodiment of the present invention are connected. FIG. 6 is a diagram illustrating timing of a diversity interface according to an embodiment of the present invention. It is a block block diagram which shows roughly the diversity process part according to embodiment of this invention. It is a figure which shows the timing which regenerates the reset signal which initializes the receiving chip according to embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  The present embodiment is for a diversity receiver 100 for ISDB-T (Integrated Services Digital Broadcasting-Terrestrial) mobile broadcast.

  Diversity receiving apparatus 100 is an apparatus that improves reception performance by receiving mutually independent channels in a radio frequency environment. Diversity receiving apparatus 100 is an apparatus that can select and use only a receiving chip having a good reception state among a plurality of receiving chips, or can combine data of each receiving chip to obtain better receiving performance. is there. At least two ISDB-T single receiving chips in the diversity receiver 100 are connected to perform communication.

  The diversity receiving apparatus 100 minimizes data pins and control pins using the structure of the internal diversity processing unit 120 and the clock operation of the receiver, and enables real-time diversity coupling in OFDM symbol units to minimize internal memory. Can do. In other words, when the diversity receiver 100 connects two or more single receiving chips to each other, the number of dedicated pins allocated for communication is minimized by reducing the size of the receiving chip, thereby minimizing the size of the diversity operation memory. Can be

  In addition, since the diversity receiving apparatus 100 operates with two or more receiving chips connected to each other, if a problem occurs in a specific receiving chip during diversity operation, a reset is generated so as to avoid an effective section of diversity processing. The stability of the diversity receiver 100 is guaranteed by adjusting the time. The diversity receiving apparatus 100 can guarantee the stability of the receiving chip without complicated control logic in the diversity processing unit by using the reset signal control of the receiving chip.

  FIG. 1 is a block configuration diagram schematically illustrating a diversity receiving apparatus in which two or more ISDB-T single receiving chips according to an embodiment of the present invention are connected.

  The diversity receiving apparatus 100 according to the present embodiment is implemented with a plurality of slaves 110 and 130 and one master 150. Here, the plurality of slaves 110 and 130 and one master 150 are respectively an RF processing unit 112, an OFDM signal processing unit 114, a channel compensation unit 116, a deinterleaver unit 118, a diversity processing unit 120, a demapper 122, and a channel. A decoding unit 124 is included.

  The slave and master structures in the diversity receiver 100 will be described. At least two different diversity processing units are connected to each other, and the two or more diversity processing units transfer a diversity transfer signal between them. 130 and a plurality of slaves 110 and 130, and a master 150 that acquires a diversity transfer signal finally combined from the last slave (eg, slave-1 130). Among the plurality of slaves 110 and 130, data is transmitted in the order of the master 150 from the first slave (for example, slave-0 110).

  The RF processing unit 112 receives analog data (bit stream) from a transmitter (transmitting apparatus) using the provided channel-specific receiving antenna. That is, the RF processing unit 112 receives a bit stream from the transmitter. Thereafter, the analog-digital converter converts the analog data received from the RF processing unit 112 into digital data, and then transfers the digital data to the OFDM signal processing unit 114. At this time, the data (bit stream) received from the RF processing unit 112 by the analog-digital converter has an analog format. The analog-digital converter represents an analog signal in the form of “0” and “1” in order to represent the signal digitally.

  The OFDM signal processing unit 114 generates processing data obtained by performing Fast Fourier Transform (FFT) on the bit stream received from the RF processing unit 112. The channel compensation unit 116 generates compensation data obtained by performing channel estimation and channel compensation on the processing data received from the OFDM signal processing unit 114. The channel compensator 116 may perform channel compensation using a channel equalization process.

  The deinterleaver unit 118 generates deinterleaving data in which the order of the data sequence of the compensation data received from the OFDM signal processing unit 114 is rearranged in a certain unit (for example, a column and a row of blocks). The deinterleaver unit 118 makes it possible to recover the lost bit by locally expressing the effect even if an intermediate bit of the data string due to instantaneous noise is lost.

  The diversity processing unit 120 includes (i) a communication chip for performing communication with different diversity processing units, (ii) a memory for storing data, and (iii) a micro for executing and controlling a program. A processor can be provided.

  The diversity processing unit 120 according to the present embodiment can be located between the deinterleaver unit 118 and the demapper 122. When the diversity processing unit 120 is located between the deinterleaver unit 118 and the demapper 122, the diversity processing unit 120 outputs the output bit, output clock frequency, and diversity transfer clock of the deinterleaving data received from the deinterleaver unit 118. The number of diversity data transfer lines minimized is calculated based on the frequency, and communication is performed with different diversity processing units using the number of diversity data transfer lines. At this time, the diversity processing unit 120 calculates the number of diversity data transfer lines by rounding up a value obtained by dividing the product of the output bit of the deinterleaving data and the output clock frequency by the diversity transfer clock frequency.

  Diversity processing section 120 inserts a symbol start signal between valid sections of deinterleaving data, which is output data of deinterleaver section 118, and sets a diversity control transfer section (symbol start signal + output data valid section) as one. Set to line. The diversity processing unit 120 transfers system information including symbol index information to the data line of the next cycle of the symbol start signal.

  The diversity processing unit 120 decodes the data serialized according to the number of diversity data transfer lines, performs synchronization to match the start positions of the symbols of the input data, and copes with a delay between data valid intervals. A threshold value is set to determine the delay memory size, and whether to transfer data is determined depending on whether it is a slave or a master.

  The diversity processing unit 120 performs real-time transfer of the diversity transfer signal in symbol units without additional data buffering for diversity transfer according to the data output period of the deinterleaver unit 118. The diversity processing unit 120 determines a synchronization memory size used for diversity combining based on a delay threshold between the symbol start signal and the data valid (Valid) period. Diversity processing unit 120 plays back so that the reset generation point avoids the effective period of diversity processing when an exception operation occurs in any one of a plurality of slaves or masters and initialization by reset occurs Thus, no additional control logic is required due to the loss of data or control signals in symbol units that are processed in symbol units.

  According to another aspect of the present invention, the diversity processing unit 120 may be positioned on the demapper 122 and the channel decoding unit 124. When the diversity processing unit 120 is located between the demapper 122 and the channel decoding unit 124, the diversity processing unit 120 outputs the demodulated data output bit received from the demapper 122, the deinterleaving data output clock frequency, and the diversity transfer clock frequency. The number of diversity data transfer pins minimized is calculated based on the above, and communication is performed with different diversity processing units using the number of diversity data transfer pins. At this time, the diversity processing unit 120 calculates the number of diversity data transfer pins by rounding up the value obtained by dividing the product of the output bit of the demodulated data and the output clock frequency of the deinterleaving data by the diversity transfer clock frequency.

  When the diversity processing unit 120 is located between the demapper 122 and the channel decoding unit 124, the same function as when the diversity processing unit 120 is located between the deinterleaver unit 118 and the demapper 122 may be performed. it can.

  The demapper 122 outputs demodulated data that is a result of demodulating the deinterleaving data received from the deinterleaver unit 118. At this time, the demapper 122 applies a demodulation method such as BPSK (Binary Phase Shift Keying), QPSK (Quadrature Phase Shift Keying), or QAM (Quadrature Amplitude Modulation) to the deinterleaving data received from the deinterleaver unit 118. Generated demodulated data. In other words, the demapper 122 processes (demodulates) the deinterleaving data received through the channel so that it can be used by the block at the rear end (channel decoding unit 124). When data is transmitted, the demapper 122 outputs demodulated data demodulated by any one of QPSK (Quadrature Phase Shift Keying), 16QAM (Quadrature Amplitude Modulation), and 64QAM. The channel decoding unit 124 generates decoded data obtained by decoding the data sequence of the demodulated data received from the demapper 122.

  Hereinafter, an operation of the diversity receiving apparatus 100 will be described with two or more ISDB-T single receiving chips to which the diversity processing unit 120 is applied based on FIG.

  Diversity combining is performed in the order of slave-0 110, slave-1 130 to master 150, and the final combined performance can be obtained at the master 150. If only two paths are used, slave-0 110 performs only transmission, and master 150 performs only reception to perform diversity combining. When two or more paths are used, slave-0 110 performs transmission, master 150 receives, and the remaining slaves perform transmission and reception simultaneously.

  As data used for diversity combining of the mobile broadcast receiving chip, input data of the demapper 122 or output data of the demapper 122 is used. Input data of the demapper 122 refers to channel-compensated I, Q (In-phase Quadrature) data and channel power information, and output data of the demapper 122 refers to a soft decision result value. In FIG. 1, the diversity processing unit 120 is positioned between the deinterleaver unit 118 and the demapper 122, and diversity combining is performed using the input of the demapper 122. However, the demapper 122 is described as an embodiment. Even if the output data is used, the range of this embodiment is not exceeded.

  The output of the channel compensation unit 116 includes channel compensated I and Q data and channel power information. The number of bits of the channel compensated I and Q data and channel power information is the FFT output bits used in the OFDM signal processing unit 114. And the number of bits in the channel estimate. Since the number of output bits of the channel compensation unit 116 affects the frequency and the memory size of the time deinterleaver, it is generally minimized by a criterion that satisfies the performance of the diversity receiver 100.

  The I and Q data channel-compensated by the channel compensator 116 of the diversity receiver 100 according to the present embodiment is each composed of 23 bits (Signed) and the channel power information is 22 bits (Unsigned). Floating transformation (expressed as mantissa and exponent) is performed within a range that minimizes the decrease in performance. The channel compensated I and Q data and the channel power information are each floating-converted to 8 bits by the channel compensation unit 116, and the sum of the input bits of the deinterleaver unit 118 becomes 24 bits (8 bits × 3).

  If the frequency (Frequency) of the memory output clock (Clock) of the deinterleaver unit 118 is determined to be ADC (Analog-Digital Converter) sampling clock frequency (Sampling Clock Frequency) / 2, the diversity depends on the transfer clock frequency of diversity. The number of lines to send data is determined by <Equation 1>.

  ROUND_UP is a decimal point round-up function.

In the diversity receiver 100 of ISDB-T, is determined to 16.25396MH _Z than twice the ADC sampling clock frequency is generally transmitter IFFT (Inverse Fast Fourier Transform) sampling frequency (8.12698MH _Z) . Diversity receiver 100 according to the present embodiment determines the ADC clock to 16.67MH _Z, determines the maximum available clock frequency to 100 MHz _Z is a 6-fold 16.67MH _Z within the receiving chip. When the diversity receiver 100 determines the diversity transfer clock frequency to be three times the ADC clock frequency, the data transfer can be performed by four lines (4 lines), and when the diversity transfer clock frequency is determined to be six times the ADC clock frequency, Data necessary for diversity combining can be transmitted using a line. The diversity receiving apparatus 100 has an advantage that the number of pins can be reduced as a high-speed clock is used. However, the clock is within a range that satisfies the criteria considering the operation due to insufficient timing margin and SSN (Simultaneous Switching Noise) in each line. Comes to determine the frequency.

  When the diversity processing unit 120 in the diversity receiving apparatus 100 is positioned after the demapper 122, the number of diversity data transfer pins is determined as shown in Equation 2 by determining the number of bits of the soft decision data.

  ROUND_UP is a decimal point round-up function.

  In the case of ISDB-T, 64QAM (Quadrature Amplitude Modulation) must be supported. Therefore, when the diversity receiving apparatus 100 determines the soft decision bits to be 4 bits, the output bits are 24 bits (= 4 bits × 6). . As described above, when the diversity receiver 100 determines the diversity transfer clock frequency to be three times the ADC clock frequency, the data transfer is four lines, and when it is determined to be six times the ADC clock frequency, the two lines are changed. Can be used to communicate.

  In the diversity receiver 100 for mobile broadcasting, when implementing the diversity function, fins used other than data pins generally include a diversity transfer clock, a symbol start signal, a data valid signal, and the like. . In the present embodiment, a symbol start signal is generated during a data valid interval using the feature that the frequency of the output clock of the deinterleaver unit 118 in the diversity receiver 100 is operated at the ADC sampling clock frequency / 2 of the receiver. One pin can be reduced.

  When the structure of the diversity receiver 100 according to the present embodiment is applied, the number of lines finally required for the diversity interface is as described below, and the number of pins for diversity of the slave-0 110 and the master 150 is as follows. Is the same as the number of lines, and the number of pins of the remaining slaves is the number of lines × 2.

  When diversity receiver 100 determines the diversity transfer clock frequency to be three times the ADC clock frequency, the total number of lines is “6”. Here, the total number of lines (6) can be diversity transfer clock (1) + diversity control signal (1) + diversity data line (4). When the diversity receiver 100 determines the diversity transfer clock frequency to be six times the ADC clock frequency, the total number of lines is “4”. Here, the total number of lines (4) can be diversity transfer clock (1) + diversity control signal (1) + diversity data line (2).

  The diversity receiver 100 generates a symbol start signal in one clock, and thereafter puts system-related information and reception status information necessary for data combination on the data line before the data interval for several to several tens of clock cycles. Will tell you in advance. Diversity receiving apparatus 100 performs a determination necessary for data combination using data carried on the data line. At this time, the diversity receiving apparatus 100 uses only one of the I- and Q-data compensated for the channel according to the reception state of each receiving chip or the restored data, or assigns a weight to each data, thereby combining the diversity. Will come to carry out.

  Since the process up to diversity combining is performed in real time in units of OFDM symbols from the output of the deinterleaver unit 118 in the diversity receiver 100, only a number of cycles of latency exists, and a delay for symbol synchronization (Delay) No additional memory is required other than memory. Diversity receiving apparatus 100 limits the memory size of the delay memory required for matching the symbol synchronization of both-side paths for diversity combining by operating with a threshold between the symbol start signal and the data valid interval. can do.

  The diversity processing unit of the master 150 in the diversity receiver 100 finally transmits the channel-compensated I and Q data and the channel power information, which are diversity-coupled, to the demapper 122 and has high reliability compared with a single receiving chip. Since soft decision data is obtained and transmitted to the channel decoding unit 124, better reception performance can be obtained.

  FIG. 2 is a diagram illustrating timing of a diversity interface according to an embodiment of the present invention.

  FIG. 2 shows the timing for the diversity interface. The OFDM symbol 202 shown in FIG. 2 is an ISDB-T time domain OFDM symbol, and when the mode 3 and the guard interval are 1/8, the symbol length is 1,008 us. The valid section 204 is a valid section of the output data of the deinterleaver unit 118, and the number of samples per symbol is 4,992 on the basis of mode 3 (Mode 3), and the length of the valid section 204 is 1,000. / (ADC clock (16.67) / 2) × 4,992 = 599 us. The output data 206 of the deinterleaver unit 118 is composed of 24 bits (I: 8 bits, Q: 8 bits, channel power: 8 bits) × 4,992 samples. The interval between the valid sections 204 of the output data of the deinterleaver unit 118 is 409 us (= 1008-599), and a newly generated symbol start signal 208 can be inserted at an intermediate point of such an interval. Diversity receiving apparatus 100 serializes and transmits system information after symbol start signal 208. The related system information 216 is used for the operation of the diversity combining and channel decoding unit 124.

  The output data 212 of the deinterleaver unit 118 is serialized and transmitted so as to match the number of lines determined by <Equation 1> as data for diversity coupling.

  For example, the number of diversity data transfer lines = ROUND_UP (output bit of deinterleaver unit 118 × output clock frequency of deinterleaver unit 118 / diversity transfer clock frequency). Diversity receiving apparatus 100 serializes 24-bit data (212) of 24 × (16.67 / 2) / (16.67 × 3) = 24 × 1/6 = 4 lines into 1/6, and 4 Transfer data to the line.

  FIG. 3 is a block diagram schematically showing a diversity processing unit according to the embodiment of the present invention.

  The diversity processing unit 120 according to the present embodiment includes a reception signal decoder unit 304, a combining unit 310, and a transfer signal encoder unit 324. The components included in the diversity processing unit 120 are not necessarily limited to this.

  FIG. 3 shows the basic structure of the diversity processing unit 120. The input data 302 is data in which system information and data necessary for diversity combination are serialized and transmitted according to the number of lines calculated by the diversity interface lines. Input data 302 includes a diversity transfer clock and a diversity control signal.

  The reception signal decoder unit 304 decodes the serialized data according to the number of diversity data transfer lines. The reception signal decoder unit 304 restores the serialized data to the original. The received signal decoder 304 restores (306) the channel power information and the channel compensated I and Q data for diversity combining as they were, and restores (308) the system information as they were before. To communicate.

  The combining unit 310 performs synchronization to match the start positions of the symbols of the input data, and sets a threshold value for a delay between data valid intervals to determine a delay memory size. The combining unit 310 performs a synchronization process for matching the start positions of symbols input in real time from both side paths (306, 308), and sets a delay threshold between the symbol start signal and the data valid period. To determine the delay memory size. The combining unit 310 sets the delay memory depth (Depth) to 5000 (= 150,000 / (1) when the time from the generation time of the symbol start signal 208 to the data valid start time is set to 150 us at the timing described in FIG. , 000 / 16.67 / 2)), and the memory width (Width) is 24 bits. When the symbol delay deviation of both side paths (306, 308) falls within 150 us, the combining unit 310 first stores the data of the input path in the memory in advance, and then combines the data with the data of the path to be input later in synchronization. Is transmitted to the channel decoding unit 124, and when the delay deviation exceeds 150 us, the previously entered path is bypassed and transmitted to the channel decoding unit 124.

  The transfer signal encoder unit 324 determines whether to transfer data depending on whether the slave 110 or 130 or the master 150 is used. If the receiving chip is currently operating as slaves 110 and 130, the transfer signal encoder unit 322 serializes the data to match the diversity transfer line, and then transmits the data to the next receiving chip via the diversity interface 324. . The transfer signal encoder unit 324 does not perform diversity combining when the current receiving chip state is the first slave (slave-0 110).

  In the case of the first slave (slave-0 110), the transfer signal encoder unit 324 transmits its data information to the next slave (eg, slave-1 130). If it is not the first slave (slave-0 110), the transfer signal encoder unit 324 transmits the data subjected to diversity combining to the next slave. The input max 318 selects data to be input to the transfer signal encoder unit 322 depending on whether it is a slave-0 110 or not. The input max 320 also selects system information to be input to the transfer signal encoder unit 322 depending on whether or not it is a slave-0 110.

  FIG. 4 is a diagram showing timing for regenerating a reset signal for initializing the receiving chip according to the embodiment of the present invention.

  FIG. 4 shows the timing for regenerating a reset signal for initializing the receiving chip. When the receiving state of one receiving chip is bad or an abnormal phenomenon occurs during operation, the receiving chip is generally automatically initialized and starts again from tuning. During the diversity operation, when an exception operation occurs in one receiving chip and the receiving chip is initialized, data and control signals are processed during the processing of data on both sides in the diversity processing unit in the diversity receiving apparatus 100. A complicated control logic that takes into account the scenario where the data breaks is required. Diversity receiving apparatus 100 according to the present embodiment is processed on a symbol-by-symbol basis using a function that generates a reset signal again so as to avoid a diversity processing effective section when a reset signal for initializing a receiving chip is generated. The control logic of the coupling unit 310 is simplified.

  The above description is merely illustrative of the technical idea of the present invention. If the person has ordinary knowledge in the technical field to which the present invention belongs, the essential characteristics of the present invention are described. Various modifications and variations are possible without departing from the scope. Therefore, the present invention is not intended to limit the technical idea of the present invention, but to explain it, and the scope of the technical idea of the present invention is not limited by such embodiments. The protection scope of the present invention should be construed in accordance with the claims, and all technical ideas within the equivalent scope should be construed as being included in the scope of the right of the present invention.

100 Diversity receiver 110 Slave-0
112 RF processing unit 114 OFDM signal processing unit 116 channel estimation and compensation unit 118 deinterleaver unit 120 diversity processing unit 122 demapper 124 channel decoding unit 130 slave-1
150 Master 304 Reception Signal Decoder 310 Connection Unit 322 Transfer Signal Encoder Unit

Claims (13)

A data receiving unit for receiving a bitstream from a transmitting device;
A deinterleaver unit for generating deinterleaving data obtained by deinterleaving the bitstream;
Calculates the number of diversity data transfer lines minimized based on the output bit of the deinterleaving data, output clock frequency, and diversity transfer clock frequency, and communicates with different diversity processing units using the number of diversity data transfer lines And a diversity processing unit for transferring the diversity-coupled diversity transfer signal to another diversity processing unit,
A diversity receiving apparatus comprising: Diversity processing department
2. The diversity data transfer line according to claim 1, wherein the diversity data transfer line number is calculated based on a value obtained by dividing a product of an output bit of the deinterleaving data and the output clock frequency by the diversity transfer clock frequency. Receiver device.   At least two different diversity processing units are connected to each other, and a plurality of slaves that transfer a diversity transfer signal between them, and a diversity transfer signal that is finally combined from the last slave among the plurality of slaves is acquired 1 3. The diversity reception according to claim 1, wherein a diversity transfer signal having a structure of one master and diversity-coupled in the order of the masters is transmitted from the first slave among the plurality of slaves. apparatus. The diversity processing unit
4. The diversity control transfer period is set to one line by inserting a symbol start signal between valid periods of the deinterleaving data that is output data of the deinterleaver unit. The diversity receiver according to any one of the above. The diversity processing unit
5. The diversity receiver according to claim 4, wherein system information including symbol index information is transferred to a data line of a next cycle of the symbol start signal. The diversity processing unit
A reception signal decoder for decoding serialized data according to the number of diversity data transfer lines;
A coupling unit that performs synchronization to match the start positions of symbols of input data, sets a threshold value for a delay between data valid sections, and determines a delay memory size;
A transfer signal encoder that determines whether to transfer data depending on whether it is a slave or a master, and
The diversity receiving apparatus according to claim 1, wherein the diversity receiving apparatus includes: The diversity processing unit
The diversity reception according to any one of claims 1 to 6, wherein a diversity transfer signal is transferred in real time in symbol units without additional data buffering for diversity transfer according to a data output section of the deinterleaver unit. apparatus. The diversity processing unit
8. The diversity receiver according to claim 1, wherein a synchronization memory size used for diversity combining is determined based on a delay threshold between the symbol start signal and the data valid period. The diversity processing unit
When an exception operation occurs in any one of the plurality of slaves or the master and initialization by reset occurs, the symbol is generated by regenerating so that the reset generation time avoids the effective period of diversity processing. 4. The diversity receiving apparatus according to claim 3, wherein additional control logic is not required due to data of a symbol unit processed in units or a cut of a control signal. A demapper that outputs demodulated data obtained by demodulating the deinterleaving data;
A decoding unit that generates decoded data obtained by decoding the demodulated data;
The diversity receiver according to claim 1, further comprising: A data receiving unit for receiving a bitstream from a transmitting device;
A deinterleaver unit for generating deinterleaving data obtained by deinterleaving the bitstream;
A demapper that outputs demodulated data obtained by demodulating the deinterleaving data;
Diversity processing units that calculate the number of diversity data transfer pins minimized based on the output bit of the demodulated data, the output clock frequency of the deinterleaving data, and the diversity transfer clock frequency, and that differ from each other using the number of diversity data transfer pins A diversity processing unit that performs communication with the diversity transfer unit and transfers the diversity-coupled diversity transfer signal to another diversity processing unit;
A diversity receiving apparatus comprising: The diversity processing unit
12. The diversity data transfer pin number is calculated based on a value obtained by dividing a product of an output bit of the demodulated data and an output clock frequency of the deinterleaving data by the diversity transfer clock frequency. The diversity receiver described.   The diversity receiver according to claim 11, further comprising a decoding unit that generates decoded data obtained by decoding the demodulated data.