JP2015216240A - MOSFET type semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a MOSFET type semiconductor device in which the film thickness of a field insulation film 22 can be reduced while suppressing insulation breakdown of the field insulation film.SOLUTION: A MOSFET type semiconductor device has a field insulation film 22 formed on a first principal face 10a of a semiconductor substrate 10, a resistance film 23 formed on the field insulation film 22, an insulation film 24 which has two opening portions OP1, OP2 and is formed on the resistance film 23, a first resistance electrode R1 which is formed on the insulation film 24 and contacts the resistance film 23 through one opening portion OP1 of the insulation film 24, and a second resistance electrode R2 which is formed on the insulation film 24 to be separate from the first resistance electrode R1, contacts the resistance film 23 through the other opening portion OP2 of the insulation film 24 and is electrically connected to a gate electrode G. The sheet resistance value in an area of the resistance film 23 between the outer peripheral end of the resistance film 23 and the periphery of the lower layer of the opening portions OP1, OP2 of the insulation film 24 is larger than the sheet resistance value in the other area of the resistance film 23.

Description

  The present invention relates to a MOSFET type semiconductor device having a gate resistance.

  In a MOSFET type semiconductor device, when a sudden large voltage (surge voltage) is applied to the gate electrode, there is a risk that dielectric breakdown of the gate insulating film may occur. Therefore, a mode is known in which a resistor is provided between the gate terminal and the gate electrode, and this resistor lowers the voltage applied to the gate electrode, thereby protecting the MOSFET from the breakdown of the gate insulating film due to the surge voltage. Yes. Such a resistance provided between the gate terminal and the gate electrode is referred to as a gate resistance.

  For example, in Patent Document 1, as shown in FIG. 6, a field insulating film 22 is formed on a first main surface 10 a of a semiconductor substrate 10, and a resistance film 23 is formed on the field insulating film 22. Embodiments are described. The resistance film 23 is provided between a gate terminal and a gate electrode (not shown) and functions as a gate resistance.

Japanese Patent Laid-Open No. 5-90523

  However, in the semiconductor device described in Patent Document 1, although the breakdown of the gate insulating film can be prevented by using a resistance film that functions as a gate resistance, the field insulating film must be sufficiently thick. Insulation breakdown of the field insulating film may occur. That is, if the thickness of the field insulating film is reduced, the breakdown voltage, which is a voltage that causes dielectric breakdown of the field insulating film, is reduced.

  In addition, in a MOSFET having a trench structure, as a method for reducing the resistance between the source and the drain (on-resistance) when the MOSFET is in an on state, the trench width is reduced and the trenches are arranged at a high density, whereby the source and drain are arranged. It is conceivable to increase the current density. In order to reduce the trench width, it is required to reduce the thickness of the field insulating film in order to improve the dimensional accuracy of the trench width.

  An object of the MOSFET type semiconductor device of the present invention is to reduce the film thickness while suppressing the breakdown of the field insulating film.

  The MOSFET type semiconductor device of the present invention is a MOSFET type semiconductor device having a plurality of semiconductor layers formed in a semiconductor substrate, a source electrode, a gate electrode, a drain electrode, and a gate insulating film, A field insulating film formed on the first main surface of the substrate; a resistance film formed on the field insulating film; an insulating film having two openings and formed on the resistance film; A first resistive electrode formed on the insulating film and in contact with the resistive film through one opening of the insulating film; and formed on the insulating film and separated from the first resistive electrode; A second resistance electrode that is in contact with the resistance film through the other opening of the insulating film and electrically connected to the gate electrode; and an outer peripheral end of the resistance film and an opening of the insulating film Area of the resistive film between the lower layer and the surrounding The sheet resistance value in may be greater than the sheet resistance value in the other regions of the resistive film.

  According to the MOSFET type semiconductor device of the present invention, the sheet resistance value in the region of the resistance film between the outer peripheral edge of the resistance film and the periphery of the lower layer of the opening of the insulating film is the sheet resistance value in the other region of the resistance film. Therefore, even if a surge voltage is applied to the first resistance electrode, the voltage drops due to the high resistance in the region of the resistance film between the outer periphery of the resistance film and the periphery of the lower layer of the opening of the insulating film. To do. Therefore, the concentration of electrolysis occurring at the end of the joint surface between the field insulating film and the resistance film is alleviated, and the dielectric breakdown of the field insulating film can be suppressed. Therefore, since the dielectric breakdown of the field insulating film can be suppressed, the thickness of the field insulating film can be reduced.

1 is a cross-sectional view of a MOSFET type semiconductor device according to a first embodiment of the present invention. It is a figure which shows the manufacturing method of the MOSFET type semiconductor device. It is sectional drawing of the MOSFET type semiconductor device which concerns on Embodiment 2 of this invention. It is sectional drawing of the conventional MOSFET type semiconductor device. (A) is a principal part top view of the MOSFET type semiconductor device which concerns on Embodiment 1 of this invention, (b) is a principal part top view of the MOSFET type semiconductor device which concerns on Embodiment 2 of this invention, (C) is a principal part top view of the conventional MOSFET type semiconductor device. It is principal part sectional drawing of the conventional MOSFET type semiconductor device.

(Embodiment 1)
The MOSFET type semiconductor device according to the first embodiment will be described below with reference to FIGS. The MOSFET type semiconductor device 1 according to the present embodiment includes a MOSFET and a gate resistor adjacent to the MOSFET. The MOSFET includes a semiconductor substrate 10, a source electrode S, a gate electrode G, a drain electrode D, and a gate insulating film 21, and the gate resistance is the first resistance electrode R1 and the second resistance. The electrode R 2, the field insulating film 22, the resistance film 23, and the insulating film 24 are configured. 5A and 5B are plan views of the periphery of the gate resistance of the MOSFET type semiconductor device. FIG. 5A is the first embodiment, FIG. 5B is the second embodiment, and FIG. 5C is the configuration of the conventional MOSFET type semiconductor device. Show.

  The semiconductor substrate 10 includes an N-type semiconductor layer 11, a P-type diffusion layer 12, an N-type diffusion layer 13, and a trench 14. A source electrode S is formed in the MOSFET formation region on the first main surface 10a of the semiconductor substrate 10, and a field insulating film 22 is formed in the gate resistance formation region on the first main surface 10a. On the second main surface 10b opposite to the main surface 10a, a drain electrode D is formed on the entire surface. In the MOSFET formation region of the semiconductor substrate 10, the N-type semiconductor layer 11, the P-type diffusion layer 12, and the N-type diffusion layer 13 are sequentially arranged from the second main surface 10 b side to the first main surface 10 a side. The N-type diffusion layer 13 is not formed in the gate resistance formation region, and the N-type semiconductor layer 11 and the P-type are formed in the direction from the second main surface 10b side to the first main surface 10a side. The diffusion layers 12 are formed in order.

  The trench 14 of the semiconductor substrate 10 is formed from the first main surface 10 a to the N-type diffusion layer 13, the P-type diffusion layer 12, and the N-type semiconductor layer 11. A gate insulating film 21 is formed on the inner surface of the trench 14. The gate electrode G is formed further inside the gate insulating film 21. As a result, the gate electrode G faces the P-type diffusion layer 12 with the gate insulating film 21 interposed therebetween.

  As described above, when a voltage is applied to the gate electrode G, an inversion layer is formed in the P-type diffusion layer 12 around the trench 14, and electrons flowing to the source electrode S are transferred to the N-type diffusion layer 13, the P-type semiconductor layer. It flows to the drain electrode D through 12 inversion layers and the N-type semiconductor layer 11. Here, in this embodiment, the semiconductor substrate 10, the source electrode S, the gate electrode G, the drain electrode D, and the gate insulating film 21 constitute a vertical MOSFET having a trench structure.

  The field insulating film 22 is located immediately above the P-type diffusion layer 12 of the semiconductor substrate 10, and a resistance film 23 is formed on the field insulating film 22. Therefore, the resistance film 23 is electrically insulated from the P-type diffusion layer 12 by the field insulating film 22. On the resistance film 23, an insulating film 24 having a first opening OP1 and a second opening OP2 is formed.

  On the insulating film 24, the first resistance electrode R1 that is in contact with the resistance film 23 via the first opening OP1 and the second resistance electrode that is in contact with the resistance film 23 via the second opening OP2. R2 is formed. The first and second resistance electrodes R1 and R2 are separated from each other, the first resistance electrode R1 is electrically connected to the gate terminal, and the second resistance electrode R2 is electrically connected to the gate electrode G. It is connected.

  As described above, the current flowing from the gate terminal to the first resistance electrode R1 flows to the gate electrode G through the first opening OP1, the resistance film 23, the second opening OP2, and the second resistance electrode R2. It becomes. Here, the resistance film 23 is provided between the gate terminal and the gate electrode G, and protects the MOSFET from the dielectric breakdown of the gate insulating film 21 due to the surge voltage by dropping the voltage applied to the gate electrode G. It works as follows.

  Further, in the conventional configuration, the gate insulating film can be prevented from breakdown by using a resistance film functioning as a gate resistance. However, if the field insulating film is not sufficiently thick, Dielectric breakdown may occur. Specifically, the film thickness of the conventional field insulating film 22 is 320 nm. At this time, the breakdown withstand voltage, which is a voltage causing the field insulating film 22 to cause dielectric breakdown, is 1500V. When the film thickness of the field insulating film 22 is reduced to 200 nm, 150 nm, and 100 nm, the breakdown voltage is reduced to 1300 V, 1200 V, and 900 V.

  Here, the dielectric breakdown of the field insulating film 22 occurs at the end of the junction surface between the field insulating film 22 and the resistance film 23 (hereinafter referred to as a junction end). This is because when a surge voltage is applied to the first resistance electrode R1, the current flows through the first opening OP1 to the outer peripheral end side of the resistance film 23, and electrolytic concentration occurs at the junction end. Here, the outer peripheral edge is a side surface of the resistance film 23 and indicates the surface of the resistance film 23 parallel to the thickness direction of the resistance film 23.

  In the MOSFET type semiconductor device 1 according to the present embodiment, a region of the resistance film 23 (hereinafter referred to as an outer edge region 23a) between the outer peripheral edge of the resistance film 23 and the periphery of the openings OP1 and OP2 of the insulating film 24. ) Is larger than the sheet resistance value in the other region 23b of the resistance film. Here, as shown in FIG. 5A, the outer edge region 23a includes the region of the resistance film 23 below the first and second openings OP1 and OP2, and the first opening OP1 and the second opening. The region of the resistive film 23 in the lower layer between the parts OP2 is not included. That is, the outer edge region 23a is an outer edge region in a direction perpendicular to the thickness direction of the resistance film 23, one end includes the outer peripheral end, and the other end is the periphery of the lower layer of the first and second openings OP1 and OP2. Or may be between the lower layer and the outer peripheral edge.

  The other region 23b is a region of the resistance film 23 inside the outer edge region 23a, and the region of the resistance film 23 below the first and second openings OP1 and OP2, and the first opening OP1 And the region of the resistance film 23 in the lower layer between the second openings OP2.

  Thereby, even if a surge voltage is applied to the first resistance electrode R1, the voltage drops due to the high resistance of the outer edge region 23a. As a result, the concentration of electrolysis occurring at the junction end is alleviated, and the dielectric breakdown of the field insulating film can be suppressed. Since the dielectric breakdown of the field insulating film 22 can be suppressed, the thickness of the field insulating film can be reduced.

In addition, the sheet resistance value in the outer edge region 23a is preferably set to 10 times or more the sheet resistance value in the other region 23b. Details will be described below.
Table 1 below shows experimental results showing the relationship between the electrical resistance value in the outer edge region 23a, the film thickness of the field insulating film 22, and the breakdown voltage. This experimental method is based on IEC61000-4-2.

According to Table 1, when the film thickness is constant, it can be seen that the higher the electric resistance value in the outer edge region 23a, the higher the breakdown voltage can be maintained. In the conventional configuration, the field insulating film 22 has a thickness of 320 nm and a breakdown voltage of 1500 V. At this time, the electric resistance value in the outer edge region 23a was 60Ω.

  If the electric resistance value in the outer edge region 23a is 600Ω, the breakdown voltage of 1500 V can be maintained even if the field insulating film 22 is thinned to 150 nm. Further, when the thickness of the field insulating film 22 is reduced to 100 nm, a breakdown voltage of 1100 V can be obtained and the breakdown voltage is lowered as compared with the conventional case, but it can exceed the standard value of the breakdown voltage of 1000 V.

Further, if the electric resistance value in the outer edge region 23a is 1500Ω, the breakdown voltage 1500V can be maintained even if the thickness of the field insulating film 22 is reduced to 150 nm. Further, when the thickness of the field insulating film 22 is reduced to 100 nm, a breakdown voltage of 1300 V can be obtained. Therefore, the electrical resistance value in the outer edge region 23a is preferably 600Ω or more. Here, the electrical resistance value R is proportional to the sheet resistance value _RS as shown in the following Expression 1.

Specifically, the sheet resistance value of the conventional resistance film 23 is uniform at 1000Ω / □, and at this time, the electrical resistance value of the outer edge region 23a is 60Ω. Therefore, when the other end of the outer edge region 23a reaches the periphery of the lower layer of the first and second openings OP1 and OP2, only the sheet resistance value in the outer edge region 23a is 10000Ω / □ or more, and the sheet resistance in the other region 23b. If the value is 10 times or more, the sheet resistance value of the outer edge region 23a is 10 times or more of the conventional value, so that the electric resistance value in the outer edge region 23a can be 600Ω or more, which is 10 times or more of the conventional value. Therefore, it is preferable that the sheet resistance value in the outer edge region 23a is 10 times or more the sheet resistance value in the other region 23b.

  Next, a method for manufacturing a MOSFET type semiconductor device according to an embodiment of the present invention will be described with reference to FIG. First, as shown in FIG. 2A, an N-type semiconductor layer 11a is formed in a semiconductor substrate 10, and one surface of the N-type semiconductor layer 11a is epitaxially grown to form an N-type epitaxial growth layer 11b. At this time, the semiconductor substrate 10 has a configuration in which an N-type semiconductor layer 11 having an N + type silicon layer 11a and an N− type epitaxial growth layer 11b is formed. Here, the surface of the semiconductor substrate 10 on the N − -type epitaxial growth layer 11b side is defined as a first main surface 10a, and the surface opposite to the first main surface 10a is defined as a second main surface 10b.

  Next, as shown in FIG. 2B, the P-type diffusion layer 12 is formed on the entire first main surface 10 a of the semiconductor substrate 10. Specifically, the upper layer of the N − type epitaxial growth layer 11 b is inverted by implanting boron ions over the entire first main surface 10 a of the semiconductor substrate 10 to obtain the P type diffusion layer 12.

  Thereafter, as shown in FIG. 2C, a field insulating film 22 is formed on the entire surface of the first main surface 10a of the semiconductor substrate. Specifically, the first main surface 10a of the semiconductor substrate is formed by thermal oxidation.

  Then, as shown in FIG. 2D, a trench 14 is formed at a location where a gate electrode is to be formed. Specifically, first, a resist pattern is formed through a lithography process, and the field insulating film 22 immediately above the trench 14 is dry-etched using the resist pattern as a mask. Then, using the field insulating film 22 as a mask, the trench 14 is formed by dry-etching the first main surface 10a of the semiconductor substrate. Thereafter, the surface of the trench 14 is thermally oxidized to form an oxide film as the gate insulating film 21. Here, in order to improve the dimensional accuracy of the width of the trench 14, the field insulating film 22 is formed thin. Details will be described below.

  When the field insulating film 22 is dry-etched using the resist pattern as a mask, the field insulating film 22 is tapered. Therefore, the width of the trench 14 is narrower than the interval between the resist patterns. Here, when the film thickness of the field insulating film 22 is large, a large shift occurs between the width of the trench 14 and the interval between the resist patterns, and the dimensional accuracy of the trench width is lowered. On the other hand, when the film thickness of the field insulating film 22 is thin, the deviation between the width of the trench 14 and the interval between the resist patterns can be minimized, and the dimensional accuracy of the trench width can be improved.

  Next, as shown in FIG. 2E, a resistance film 23 is formed on the field insulating film 22, and the gate electrode G is formed inside the gate insulating film 21. The material of the resistance film 23 and the gate electrode G is, for example, polycrystalline silicon, and can be formed by CVD. With respect to the resistance film 23, it is preferable that the outer edge region 23a is not doped with impurities but only the other regions 23b are doped with impurities. Details will be described below.

  When the material of the resistance film 23 is a semiconductor such as silicon, the sheet resistance value depends on the impurity doping amount. That is, the greater the impurity doping amount, the lower the sheet resistance value of the resistance film 23. Therefore, if the outer edge region 23a of the resistance film 23 is not doped with impurities, a state in which the sheet resistance value in the outer edge region 23a of the resistance film 23 is high can be easily configured.

  Then, as shown in FIG. 2F, an insulating film 24 is formed on the resistance film 23, and openings OP1 and OP2 that expose the resistance film 23 are formed in the insulating film 24, and the first main substrate of the semiconductor substrate is formed. The field insulating film 22 on the surface 10a where the source electrode is to be formed is removed. Specifically, the insulating film 24 is formed by CVD, and thereafter, the openings OP1 and OP2 are formed by dry etching, and the field insulating film 22 is removed at a place where the source electrode is to be formed. At this time, it is necessary to form the openings OP1 and OP2 on the other region 23b inside the outer edge region 23a.

  Next, as shown in FIG. 2G, the N-type diffusion layer 13 is formed in the upper layer of the semiconductor substrate at the location where the field insulating film 22 is removed. By performing phosphorus ion implantation at the location where the field insulating film 22 is removed, the upper layer of the P-type diffusion layer 12 is inverted to form the N-type diffusion layer 13. The amount and concentration of phosphorus ions are adjusted so that the P-type diffusion layer 12 can be inverted. Further, the N-type diffusion layer 13 is set so as not to reach the region of the N-type semiconductor layer 11.

  Finally, as shown in FIG. 2H, the source electrode S is formed on the N-type diffusion layer 13, the drain electrode D is formed on the entire surface of the second main surface 10b, and the first and second resistances are formed. The electrodes R1 and R2 are formed on the insulating film 24 so as to be separated from each other. At this time, the first and second resistance electrodes R1 and R2 are formed so as to be in contact with the resistance film 23 through the openings OP1 and OP2 of the insulating film 24. The material of each electrode is aluminum, for example, and can be formed by sputtering.

According to MOSFET type semiconductor device 1 according to the present embodiment, since the sheet resistance value in outer edge region 23a is larger than the sheet resistance value in other region 23b, a surge voltage is applied to first resistance electrode R1. However, the voltage drops due to the high resistance of the outer edge region 23a. Therefore, the concentration of electrolysis occurring at the end of the joint surface between the field insulating film 22 and the resistance film 23 is alleviated, and the dielectric breakdown of the field insulating film 22 can be suppressed. Therefore, since the dielectric breakdown of the field insulating film 22 can be suppressed, the thickness of the field insulating film 22 can be reduced.
(Embodiment 2)
Next, a MOSFET type semiconductor device according to the second embodiment will be described with reference to FIGS.

  In MOSFET type semiconductor device 1 according to the first embodiment, the case where the sheet resistance value in outer edge region 23a of resistance film 23 is larger than the sheet resistance value in other region 23b of resistance film 23 has been described. In the MOSFET type semiconductor device 2 according to No. 2, the sheet resistance value of the resistance film 23 is the same as the conventional one and is uniform.

  In the MOSFET type semiconductor device 2 according to the second embodiment, the shortest distances (hereinafter referred to as outer edge distances) L1 ′ and L2 ′ from the outer peripheral end of the resistance film 23 to the lower layers of the openings OP1 and OP2 are the conventional ones. The outer edge region 23a in the first embodiment is larger than the outer edge distances L1 and L2, and one end of the outer edge region 23a includes the outer peripheral end and the other end reaches the periphery of the lower layer of the first and second openings OP1 and OP2. Although it has been described that it may be between the lower layer and the outer peripheral end, the outer edge region in the second embodiment has one end being the outer peripheral end of the resistance film 23 and the other end being the first and second ends. The area | region to the circumference | surroundings of the lower layer of opening part OP1, OP2 of this is shown.

  The electrical resistance value R is also proportional to the distance L, as shown in Equation 1 above. Therefore, the electrical resistance value in the outer edge region can be increased by increasing the outer edge distance. Thereby, even if a surge voltage is applied to the first resistance electrode R1, the voltage drops due to the high resistance of the outer edge region. Therefore, the concentration of electrolysis that occurs at the junction end is alleviated, and the dielectric breakdown of the field insulating film 22 can be suppressed. Thereby, since the dielectric breakdown of the field insulating film 22 can be suppressed, the film thickness of the field insulating film 22 can be reduced.

  As described above, the breakdown voltage, which is a voltage that causes breakdown of the field insulating film 22, increases as the film thickness of the field insulating film 22 increases, and also increases as the outer edge distances L1 ′ and L2 ′ increase. Become. Here, the breakdown voltage depends on the product of the field insulating film 22 and the outer edge distance L1 ′ or L2 ′ within a practical range. For this reason, if the product of the film thickness of the field insulating film 22 and the outer edge region L1 or L2 of the MOSFET type semiconductor device is maintained, by increasing the outer edge distance while suppressing the dielectric breakdown of the field insulating film 22, The field insulating film 22 can be thinned.

For example, the outer edge distances L1 and L2 of the conventional resistance film 23 are 4 μm, the film thickness of the field insulating film 22 is 0.4 μm, and the product of the outer edge region L1 or L2 and the film thickness of the field insulating film 22 is 1.6 μm. ² . On the other hand, in the MOSFET according to the present embodiment, the outer edge distances L1 ′ and L2 ′ are distances in which the product of the outer edge distance L1 ′ or L2 ′ and the field insulating film 22 is larger than 1.6 μm ^2. . That is, the outer edge distances L1 ′ and L2 ′ satisfy the condition shown in the following formula 2. If Expression 2 is satisfied, the dielectric breakdown of the field insulating film 22 can be more effectively suppressed than in the past, so that the field insulating film 22 can be made thinner.

Further, the conventional outer edge distances L1 and L2 were 4 μm, and the electric resistance value in the outer edge region of the resistance film 23 was 60Ω. As described in the first embodiment, the electric resistance value in the outer edge region of the resistance film 23 is preferably 600Ω or more. For this purpose, the outer edge distances L1 ′ and L2 ′ according to the present embodiment are 40 μm or more. I just need it.

  In the first and second embodiments, the case where the electrical resistance value in the outer edge region is controlled by operating one of the outer edge distance and the sheet resistance value in the outer edge region has been described. Thus, the electrical resistance value in the outer edge region may be controlled.

  In the first and second embodiments, the case where the semiconductor substrate 10 includes the N-type semiconductor layer 11, the P-type diffusion layer 12, and the N-type diffusion layer 13 is described. However, all of these channels may be inverted. That is, instead of the N-type semiconductor layer 11, the P-type diffusion layer 12, and the N-type diffusion layer 13 of the present embodiment, a P-type semiconductor layer, an N-type diffusion layer, and a P-type diffusion layer may be used.

  In the first and second embodiments, the case where the trench type vertical MOSFET is used has been described. However, the present invention is not limited to this, and a planar structure or a horizontal type may be used. For example, in the MOSFET type semiconductor device shown in FIG. 4, the source electrode S, the gate insulating film 21, the drain electrode D, and the field insulating film 22 are formed on the first main surface 10 a of the semiconductor substrate 10. A gate electrode G is formed, and a resistance film 23 is formed on the field insulating film 22. Then, in the lower layer region of the source electrode S and the drain electrode D in the semiconductor substrate 10, the P-type diffusion layer 12 and the N-type semiconductor layer 11 are formed in this order from the first main surface 10a side, and the gate insulating film 21 and the field In the lower layer region of the insulating film 22, the N-type semiconductor layer 11 is formed. However, the channels of the N-type semiconductor layer 11 and the P-type diffusion layer 12 may be inverted. N-type diffusion layer 13 and trench 14 are not formed.

  Even in this configuration, the configuration of the field insulating film 22, the resistance film 23, the insulating film 24, the openings OP1 and OP2, and the first and second resistance electrodes R1 and R2 are the same as those in the first and second embodiments. With the configuration, the same effects as those of the first and second embodiments can be obtained. For example, as in the first embodiment, if the sheet resistance value in the outer edge region 23a is larger than the sheet resistance value in the other region 23b, even if a surge voltage is applied to the first resistance electrode R1, Since the electrolytic concentration occurring at the junction end is alleviated, the dielectric breakdown of the field insulating film 22 can be suppressed. Therefore, the dielectric breakdown of the field insulating film 22 can be suppressed, and the film thickness of the field insulating film 22 can be reduced.

  The present invention is a MOSFET type semiconductor device capable of reducing the film thickness of the field insulating film while suppressing dielectric breakdown of the field insulating film, and is useful for a MOSFET type semiconductor device having a gate resistance.

1, 2 MOSFET type semiconductor device 10 Semiconductor substrate 10a First main surface 10b Second main surface 11 N type semiconductor layer 11a N + type silicon layer 11b N− type epitaxial growth layer 12 P type diffusion layer 13 N type diffusion layer 14 Trench 21 Gate Insulating film 22 Field insulating film 23 Resistance film 23a Outer edge area 23b Other area 24 Insulating film S Source electrode G Gate electrode D Drain electrode R1 First resistance electrode R2 Second resistance electrodes L1, L2, L1 ′, L2 ′ Outer edge distance

Claims (5)

A MOSFET type semiconductor device having a plurality of semiconductor layers formed in a semiconductor substrate, a source electrode, a gate electrode, a drain electrode, and a gate insulating film,
A field insulating film formed on the first main surface of the semiconductor substrate;
A resistance film formed on the field insulating film;
An insulating film having two openings and formed on the resistive film;
A first resistance electrode formed on the insulating film and in contact with the resistive film through one opening of the insulating film;
A second electrode formed on the insulating film and spaced apart from the first resistive electrode, in contact with the resistive film through the other opening of the insulating film, and electrically connected to the gate electrode; A resistance electrode,
The sheet resistance value in the region of the resistance film between the outer peripheral edge of the resistance film and the periphery of the lower layer of the opening of the insulating film is larger than the sheet resistance value in other regions of the resistance film. MOSFET type semiconductor device. The sheet resistance value in the region of the resistance film between the outer peripheral edge of the resistance film and the periphery of the lower layer of the opening is 10 times or more the sheet resistance value in the other region. 2. The MOSFET type semiconductor device according to 1. The resistance film is a semiconductor material,
3. The MOSFET type semiconductor device according to claim 1, wherein impurities are doped only in the other region. A MOSFET type semiconductor device having a plurality of semiconductor layers formed in a semiconductor substrate, a source electrode, a gate electrode, a drain electrode, and a gate insulating film,
A field insulating film formed on the first main surface of the semiconductor substrate;
A resistance film formed on the field insulating film;
An insulating film having two openings and formed on the resistive film;
A first resistance electrode formed on the insulating film and in contact with the resistive film through one opening of the insulating film;
A second electrode formed on the insulating film and spaced apart from the first resistive electrode, in contact with the resistive film through the other opening of the insulating film, and electrically connected to the gate electrode; A resistance electrode,
The shortest distance from the outer peripheral edge of the resistive film to the lower layer of the opening of the insulating film is a distance in which the product of the shortest distance and the thickness of the resistive film is greater than 1.6 μm ^2. A MOSFET type semiconductor device characterized. 5. The MOSFET type semiconductor device according to claim 1, wherein an electric resistance value in a region of the resistance film from an outer peripheral end of the resistance film to a lower layer of the opening is 600Ω or more.