JP2015215641A - Information processor, emulation program and emulation method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information processor capable of reproducing an object device which includes an object storage and plural object processing parts sharing a storage area of the object storage by using a virtual model while preventing performance degradation of the virtual model.SOLUTION: The information processor includes: a storage section 41 that stores requests to write on a virtual storage part 30 in a processing order corresponding to object storage which is issued from each of plural virtual processing parts 10 and 20 corresponding to plural object processing parts; and read-out control units 42 and 43 that determine, relevant to the read-out request to the virtual storage part 30 issued from the virtual processing parts 10 and 20, whether or not an access range relevant to the read-out request overlaps with an access range relevant to one or more write requests stored in the storage section 41, and if not overlap, executes the read-out processing relevant to the read-out request.

Description

  The present invention relates to an information processing apparatus, an emulation program, and an emulation method.

  In recent years, the life cycle of various devices including DVD (Digital Versatile Disc) / HDD (Hard Disk Drive) recorders and NAS (Network Area Storage) devices has been shortened, and vendors manufacture all parts of the devices by themselves. That is decreasing. Instead, vendors often procure parts from various companies, assemble them, and incorporate software (Firmware, FW, etc.) to manufacture a single device.

  Large-scale devices often incorporate many small pieces of software (modules, etc.). Since most of these softwares are debugged after the apparatus is completed, debugging takes time as the number of softwares increases.

  For this reason, a method of shortening the debugging period by creating a large number of prototype devices (prototype devices) and performing debugging simultaneously (in parallel) can be considered. However, this method is costly because many prototype devices are created. In addition, when the device is corrected (revised) or the like, a plurality of prototype devices are created again, which may increase the number of man-hours and may not be able to meet the life cycle or increase the cost of the device.

  As a technique for avoiding the above inconvenience, it is conceivable to emulate (reproduce) the whole or a part of the apparatus on a computer (information processing apparatus) such as a server or a PC (Personal Computer).

  In the above-described emulation, the device is virtually configured by software (emulator) that emulates the device (hardware) on the computer without actually manufacturing the device, and on the virtual device (virtual device). Run the actual software. Thereby, the problem at the time of actually manufacturing an apparatus can be identified.

JP 2001-175632 A JP 2001-318825 A

  However, in the emulator, unlike the target device (hardware) to be reproduced, the processor (CPU, etc.) of the information processing device accesses the virtual memory from the virtual CPU (Central Processing Unit) and virtual device reproduced by software. Do. For this reason, unlike the target device, the virtual device may have a decrease in performance (operation speed) that is unique to the emulator.

  In one aspect, an object of the present invention is to suppress degradation in performance of a virtual model in an information processing apparatus that reproduces a target device using a virtual model.

  In addition, the present invention is not limited to the above-described object, and other effects of the present invention can be achieved by the functions and effects derived from the respective configurations shown in the embodiments for carrying out the invention which will be described later. It can be positioned as one of

  The information processing apparatus according to the present embodiment is an information processing apparatus that reproduces a target device including a target storage unit and a plurality of target processing units that share the storage area of the target storage unit, and includes a storage unit and a read control unit. The storage unit stores a write request to the virtual storage unit corresponding to the target storage unit issued from each of the plurality of virtual processing units corresponding to the plurality of target processing units in the order of processing. For the read request to the virtual storage unit issued from the virtual processing unit, whether the access range related to the read request overlaps the access range related to one or more write requests stored in the storage unit Determine whether or not. If they do not overlap, the read control unit executes a read process related to the read request.

  According to one embodiment, it is possible to suppress the performance degradation of the virtual model in the information processing apparatus that reproduces the target device using the virtual model.

It is a figure which shows the structural example of the virtual apparatus which reproduced the apparatus (target apparatus) of reproduction object by the emulator. It is a figure which shows the structural example of the virtual apparatus which reproduced the apparatus (target apparatus) of reproduction object by the emulator. It is a figure which shows the structural example of the emulation server which concerns on one Embodiment. It is a figure which shows the hardware structural example of the emulation server shown in FIG. It is a figure which shows the structural example of the emulator which concerns on one Embodiment. It is a figure explaining the operation example of the queue process part shown in FIG. It is a figure explaining the operation example of the queuing (addition) by the queue process part shown in FIG. It is a figure explaining the operation example of the queuing (deletion) by the queue process part shown in FIG. It is a figure explaining the operation example of insertion of the queue in the queue storage part by the queue process part shown in FIG. It is a figure explaining the operation example of insertion of the queue in the queue storage part by the queue process part shown in FIG. It is a sequence diagram showing an operation example of an emulator (virtual device) according to an embodiment. It is a sequence diagram showing an operation example of an emulator (virtual device) according to an embodiment. It is a flowchart explaining an example of the processing procedure of the Write function in the emulator which concerns on one Embodiment. It is a flowchart explaining an example of the process sequence of the Queue registration function in the emulator which concerns on one Embodiment. It is a flowchart explaining an example of the processing procedure of the Read function in the emulator which concerns on one Embodiment. It is a flowchart explaining an example of the processing procedure of the Read function in the emulator which concerns on one Embodiment. It is a flowchart explaining an example of the process sequence of the access process (thread) in the emulator which concerns on one Embodiment. It is a figure explaining an example of the process of a Read function and the access process (thread) in the emulator which concerns on one Embodiment. It is a flowchart explaining an example of the processing procedure of the setting of the EXEC flag in the emulator which concerns on one Embodiment. It is a figure which shows the structural example of the virtual apparatus which reproduced the apparatus (target apparatus) of reproduction object by the emulator. It is a figure which shows the structural example of the virtual apparatus to which the emulator which concerns on one Embodiment is applied. It is a figure which shows the structural example of the target apparatus which concerns on one Embodiment.

  Embodiments of the present invention will be described below with reference to the drawings. However, the embodiment described below is merely an example, and there is no intention to exclude various modifications and technical applications that are not explicitly described below. That is, the present embodiment can be implemented with various modifications without departing from the spirit of the present embodiment. Note that, in the drawings used in the following embodiments, portions denoted by the same reference numerals represent the same or similar portions unless otherwise specified.

[1] One Embodiment [1-1] Comparison The comparison shown in FIGS. 1 and 2 will be described first. FIG. 1 and FIG. 2 are diagrams showing configuration examples of virtual devices 100 and 200 in which a reproduction target device (target device) 1000 (see FIG. 22) is reproduced by an emulator, respectively. A configuration example of the target device 1000 is shown in FIG. As illustrated in FIG. 22, the target device 1000 allows the CPU 1100 and the plurality of devices 1200-1 to 1200-3 to access the memory 1300 via the internal bus 1400.

  The emulator is software for emulating the device (target device) 1000, and is executed on a computer (information processing device) such as a server or a PC having a memory such as a CPU and a RAM (Random Access Memory) (not shown). The emulator is realized by executing an emulation program developed on a memory by a CPU in a computer. The emulator can configure the virtual device 100 in software as shown in FIG.

  The virtual device 100 is a reproduction of the emulation target device 1000, and as shown in FIG. 1, a virtual (pseudo) CPU (Pseudo CPU) 110 and a plurality of (for example, three) virtual (pseudo) devices (Pseudo Device). 120-1 to 120-3 and a virtual memory 130 are provided.

  The virtual CPU 110 is a virtual CPU that executes an actual program (FW). Virtual devices 120-1 to 120-3 (in the following description, when virtual devices 120-1 to 120-3 are not distinguished from each other, they are simply referred to as virtual devices 120) It is a virtual device that simulates the operation. Hereinafter, the virtual CPU 110 and the plurality of virtual devices 120 may be collectively referred to as a virtual processing unit.

  The virtual memory 130 is a virtual memory that is realized using the memory resources of the computer. The virtual CPU 110 and the virtual device 120 can access the virtual memory 130, that is, read and write data.

  By the way, in the emulator shown in FIG. 1, each virtual processing unit generates access to the virtual memory 130 in the virtual device 100 independently of each other. That is, the emulator shown in FIG. 1 does not have a function of performing exclusive processing between virtual processing units.

  In the virtual device 100, a program may be executed in which the virtual CPU 110 monitors a value written from the virtual device 120 to the virtual memory 130 and shifts to the next process when the state changes. At this time, the virtual CPU 110 may shift to the next operation even when the writing from the virtual device 120 to the virtual memory 130 is halfway.

  As an example, consider a process in which the virtual CPU 110 and the virtual device 120 access the same space (storage area) of the virtual memory 130. Such processing includes processing in which the virtual device 120 writes a plurality of data in the virtual memory 130 using an interrupt or the like, and the virtual CPU 110 reads the data. In this case, before the virtual device 120 completes the writing of data to the virtual memory 130, the virtual CPU 110 executes reading from the same storage area, and the data from the virtual device 120 is only partially written. Can occur.

  Further, in an emulator operating on a computer that executes Linux (registered trademark), when the virtual CPU 110 accesses the virtual memory 130, there is a possibility that threads are switched in units of 4K bytes depending on the page concept. For this reason, similarly to the state where data is written only halfway, the next process may be executed during the transfer and the process may be overtaken, and an unexpected malfunction may occur.

  As described above, when the virtual device 100 operates different from the specification of the target device 1000, the emulator user or the like examines and corrects the countermeasure whenever such inconvenience occurs.

  As a technique for solving the above-described inconvenience, an emulator shown in FIG. 2 may be used. The emulator can configure (reproduce) the virtual device 200 in software as shown in FIG.

  The virtual device 200 basically has the same configuration as that of the virtual device 100 shown in FIG. 1, except that it includes an arbiter 140 and a selector 150 in addition to the configuration of the virtual device 100 as shown in FIG.

  Similar to the arbiter used in the hardware device, the arbiter 140 adjusts memory access by arbitrating (exclusive processing) memory access to the virtual memory 130 between the virtual processing units. For example, the arbiter 140 performs arbitration for the virtual processing unit that is the source of a plurality of input request signals, and causes the virtual processing unit to perform memory access until a completion signal is input from the selected virtual processing unit.

  The selector 150 selects a virtual processing unit corresponding to the selection signal input from the arbiter 140 and performs switching on the input side to permit access to the virtual memory 130. At this time, the selector 150 outputs a signal (selected signal) indicating that it is selected to the virtual processing unit corresponding to the selection signal, so that the virtual processing unit detects that it is selected. .

  As described above, in the virtual device 200, arbitration (exclusive processing) is performed on all reads and writes to the virtual memory 130 by all virtual processing units (the virtual CPU 110 and the virtual device 120).

  However, in the virtual device 200 shown in FIG. 2, the arbitration processing portion including the arbiter 140 and the selector 150 becomes more complicated and the scale increases as the virtual device 120 increases, and the processing speed of the virtual device 200 decreases. obtain. For example, the program area viewed from the CPU is read-only, and no arbitration is actually required. However, since the virtual device 200 mediates up to the area, unnecessary arbitration occurs and processing is performed. The speed will be reduced.

  As described above, when the target device 1000 is reproduced by the emulator and the virtual device 200 including the arbitration processing portion is configured, the operation speed of the virtual device 200 (emulator, and thus the computer) may be lowered, which is peculiar to the emulator.

[1-2] Emulation Server In view of the above points, according to the emulation server 1 (see FIG. 3) according to the present embodiment, the virtual device 3 (see FIG. 5) performs queue processing as will be described in detail below. A part 40 is provided. The queue processing unit 40 stores a write request to the virtual storage unit issued from each of the plurality of virtual processing units in the order of processing. Further, the queue processing unit 40 determines whether the access range related to the read request overlaps the access range related to one or more write requests to be stored for the read request issued from the virtual processing unit to the virtual storage unit. judge. Then, when there is no overlap, the queue processing unit 40 executes a read process related to the read request.

  As described above, in the virtual device 200 shown in FIG. 2, even when the access ranges of the write request and the read request do not overlap, arbitration by the arbiter 140 is performed uniformly, and the processing speed may decrease.

  On the other hand, according to the emulation server 1, since the memory arbitration (exclusive processing) of each virtual processing unit can be minimized and simplified, the speed reduction can be suppressed and the emulation can be performed at high speed. it can. Accordingly, it is possible to suppress the performance degradation of the virtual model in the information processing apparatus that reproduces the target device 1000 using the virtual model.

[1-3] Configuration of Emulation Server The configuration of the emulation server 1 according to this embodiment will be described below with reference to FIGS. 3 and 4. FIG. 3 is a diagram illustrating a configuration example of the emulation server 1 according to an embodiment, and FIG. 4 is a diagram illustrating a hardware configuration example of the emulation server 1 illustrated in FIG. 3.

  The emulation server 1 includes a target device 1000 to be emulated that includes a memory (target storage unit), a plurality of devices that share the storage area of the memory, and one or more CPUs (a plurality of target processing units). (Model) to emulate (reproduce). Examples of the emulation server 1 include information processing apparatuses such as servers and PCs.

  As shown in FIGS. 3 and 4, the emulation server 1 can include a CPU 1a, a memory 1b, a storage unit 1c, an interface unit 1d, an input / output unit 1e, a recording medium 1f, and a reading unit 1g.

  The CPU 1a is an example of an arithmetic processing device (processor) that performs various controls and arithmetic operations. The CPU 1a is connected to the corresponding blocks 1b to 1g, and executes various programs stored in a memory 1b, a storage unit 1c, a recording medium 1f or 1h, a ROM (Read Only Memory) (not shown), and the like. Function can be realized. For example, the CPU 1a can realize the function as the emulator 2 that emulates the virtual device 3 by executing the emulation program 5 (see FIG. 3) stored in the memory 1b.

  The memory 1b is a storage device that stores various data and programs. When executing the program, the CPU 1a stores and develops data and programs in the memory 1b. The memory 1b stores the emulation program 5 and secures an emulation area 4 used for emulation by the emulator 2. As the memory 1b, for example, a volatile memory such as a RAM can be cited. The storage unit 1c is hardware that stores various data, programs, and the like. Examples of the storage unit 1c include various devices such as a magnetic disk device such as an HDD, a semiconductor drive device such as an SSD (Solid State Drive), and a nonvolatile memory such as a flash memory.

  The interface unit 1d performs connection and communication control with a network (not shown) or another information processing apparatus by wire or wireless. Examples of the interface unit 1d include an adapter compliant with LAN (Local Area Network), Fiber Channel (FC), InfiniBand, and the like. The input / output unit 1e can include at least one of an input device such as a mouse and a keyboard and an output device such as a display and a printer. For example, the input device is used for operations such as conditions of the emulation server 1 (virtual device 3) and data input by a user or the like, and the output device outputs an operation state, processing result, etc. by the emulation server 1 (virtual device 3). Used for.

  The recording medium 1f is a storage device such as a flash memory or a ROM, and can record various data and programs. The reading unit 1g is a device that reads data and programs recorded on a computer-readable recording medium 1h. At least one of the recording media 1f and 1h may store an emulation program 5 that realizes all or some of the various functions of the emulation server 1 according to the present embodiment. For example, the CPU 1a may develop and execute the program read from the recording medium 1f or the program read from the recording medium 1h via the reading unit 1g in a storage device such as the memory 1b.

  Examples of the recording medium 1h include optical disks such as a flexible disk, CD (Compact Disc), DVD (Digital Versatile Disc), and Blu-ray disc, and flash memories such as a USB (Universal Serial Bus) memory and an SD card. Examples of the CD include CD-ROM, CD-R (CD-Recordable), and CD-RW (CD-Rewritable). Examples of DVD include DVD-ROM, DVD-RAM, DVD-R, DVD-RW, DVD + R, DVD + RW, and the like.

  The blocks 1a to 1g described above are connected to be communicable with each other via a bus. The above-described hardware configuration of the emulation server 1 is an example. Therefore, hardware increase / decrease in the emulation server 1 (for example, addition or omission of arbitrary blocks), division, integration in an arbitrary combination, addition or omission of buses, etc. may be appropriately performed.

[1-4] Configuration of Emulator Next, the configuration of the emulation server 1 according to the present embodiment will be described with reference to FIGS. FIG. 5 is a diagram illustrating a configuration example of the virtual device 3 reproduced by the emulator 2 according to the embodiment, and FIG. 6 is a diagram illustrating an operation example of the queue processing unit 40 illustrated in FIG.

  The virtual device 3 is a reproduction of the target device 1000 for emulation. As shown in FIG. 5, the virtual device 3 includes one or more (for example, one) virtual (pseudo) CPUs 10, a plurality (for example, three) of virtual (pseudo) devices 20-1 to 20-3, a virtual memory 30, And a queue processing unit 40.

  The virtual CPU 10 is a virtual CPU that executes an actual program (FW). Virtual devices 20-1 to 20-3 (in the following description, when virtual devices 20-1 to 20-3 are not distinguished, they are simply referred to as virtual devices 20) are the devices in the target device 1000 (virtual device 3). It is a virtual device that simulates the operation. The virtual CPU 10 and the virtual device 20 are set so as to have the same functions and performance as the CPU and device mounted on the target apparatus 1000, and are realized using the resources of the CPU 1a of the emulation server 1.

  The virtual memory 30 is a virtual memory that is realized by using resources of the memory 1b of the emulation server 1 (for example, the emulation area 4 (see FIG. 3)). The virtual CPU 10 and the virtual device 20 can access the virtual memory 30, that is, read and write data. Thus, the virtual CPU 10 and the virtual device 20 are an example of a plurality of virtual processing units that share the storage area of the virtual memory 30. Note that the plurality of virtual processing units correspond to the plurality of target processing units provided in the target device 1000.

  The queue processing unit 40 controls read / write access from each virtual CPU 10 and virtual device 20 to the virtual memory 30, and the read / write access is processed via the queue processing unit 40.

  The queue processing unit 40 includes, for example, a queue storage unit 41, a queue control unit 42, a read determination unit 43, and an access control unit 44.

  The queue storage unit 41 stores (queues) write requests and read requests issued from each of the virtual CPU 10 and the plurality of virtual devices 20 in the processing order (for example, issue order) to be processed. The queue storage unit 41 is realized by a storage area such as a part of a cache memory (not shown) of the CPU 1a or a part of the memory 1b (for example, the emulation area 4).

  The queue storage unit 41 can store a plurality of queues 41a and message queues 41b as shown in FIG. 6, for example. The queue 41a is management (control) information including an R / W flag (R_FLG) indicating any of an address (start address) (addr), a data size (size), and a read / write for accessing the virtual memory 30. Hold. Further, as shown in FIG. 7, the queue 41a further includes Before_wp and Next_wp indicating write pointers of the preceding and succeeding queues 41a. The message queue 41b holds write data (W_data) for a write request.

  The queue control unit 42 manages (queuing) registration, deletion, update, and the like of access requests to the queue storage unit 41 (queue 41a and message queue 41b), and registers access requests in the queue storage unit 41. It is an example of a queue registration function.

Here, the virtual CPU 10 and the plurality of virtual devices 20 can issue a write request and a read request using a common format. As an example, the write request has the following format (message) for calling the call function of the queue processing unit 40 (call), and the read request has the following format (message) for calling the read function of the queue processing unit 40. be able to.
Write: address (W_addr), data size (W_size), write data (W_data)
Read: Address (R_addr), data size (R_size), data storage pointer

  For example, when a write request is input from each of the virtual CPU 10 and the plurality of virtual devices 20, the queue control unit 42 stores the write address (W_addr) and the write data size (Byte) (W_size) in the management queue 41a. sign up. At this time, the queue control unit 42 sets a write flag (for example, R_FLG (read flag) = 0) in the queue 41a. Further, the queue control unit 42 stores the write data (W_data) in the message queue 41b for write data.

  Here, an operation example of queuing (addition and deletion) by the queue control unit 42 will be described with reference to FIGS.

  First, referring to FIG. 7, an example of queuing (addition) when only the first request (Que_REQ0) is registered in the queue storage unit 41 (Que_WP (read pointer from the queue 41a) = Que_REQ0) will be described. In this case, when the next access request is input, the queue control unit 42 registers the pointer of Que_REQ1, which is the pointer (address (addr) of the queue 41a) acquired by the next access, in Next_wp of Que_REQ0. Further, the queue control unit 42 registers the pointer of Que_REQ0 that is the pointer of the previous access in Before_wp of Que_REQ1. When the next access request is further input, the queue control unit 42 registers the pointer of Que_REQ2, which is the pointer acquired by the next access, in Next_wp of Que_REQ1, and uses the pointer of the previous access in Before_wp of Que_REQ2. Register a Que_REQ1 pointer.

  Next, an example of queuing (deleting Que_REQ0) when Que_REQ0 to Que_REQ2 are registered in the queue storage unit 41 and the read pointer is Que_REQ1 will be described with reference to FIG. In this case, the queue control unit 42 deletes the access request (information) relating to Que_REQ0 (free), and sets “0” to Before_wp because the previous information is deleted for Que_REQ1 in which the Que_REQ0 pointer is set in Before_wp. Set (Que_WP-> Before_wp = 0). If there is no next entry (Next_wp) in the access request indicated by the read pointer, the access request in the state of Que_WP-> Before_wp = 0 and Que_WP-> Next_wp = 0 is the first.

  Note that the registration process of the read request to the queue storage unit 41 by the queue control unit 42 will be described later because the read determination unit 43 makes a storage determination in the queue storage unit 41.

  When a read request is input from each of the virtual CPU 10 and the plurality of virtual devices 20, the read determination unit 43 determines whether to store the read request in the queue storage unit 41, and read processing according to the determination result To do. The read determination unit 43 is an example of a Read function that performs read processing.

For example, the read determining unit 43 writes the area obtained from the address (R_addr) and read data size (R_size) of the virtual memory 30 instructed by the input read request, and the write data stored in the management queue 41a. It is determined whether or not the area overlaps. As an example, the read determination unit 43 performs the following determination, and when one of the conditions is satisfied, the access range of the read request overlaps with the access range of the write data in the queue storage unit 41 (it hits). judge.
・ (W_addr> = R_addr) && (W_addr <= R_addr + R_size)
(Whether or not the start address of the write request is included within the access range of the read request)
・ (R_addr> = W_addr) && (R_addr <= W_addr + W_size)
(Whether or not the read request start address is included in the access range of the write request)

  At this time, the read determination unit 43 obtains the address (addr) and the size (size) of the entry (request) for which the write request entry, that is, R_FLG is “0”, from the queue 41a in the queue storage unit 41, respectively. Get as W_size.

  Note that the read determination unit 43 has the one or more access requests (write requests) stored in the queue storage unit 41 in the reverse order of the storage order (processing order), that is, the order in which Before_wp is traced from the last access request. It is preferable to determine whether or not it overlaps the access range of the read request. Thus, even when there are a plurality of write requests in the queue storage unit 41 that overlap with the access range of the read request, the write request that affects the read process (the write process is performed last) can be reliably identified. . Therefore, even when a read / write access conflict occurs, the data consistency of the virtual memory 30 can be maintained.

  Next, if the result of the determination is that there is no overlap (no hit), the read determination unit 43 reads the data requested by the read request from the address (R_addr) of the virtual memory 30 by the read data size (R_size), This is the return value of the Read function. This return value is stored (transmitted) as a response to the read request in the data storage pointer designated by the read request of the requesting virtual CPU 10 or virtual device 20. The read determination unit 43 reads data from the virtual memory 30 by performing a direct copy from the virtual memory 30 space to the requesting virtual CPU 10 or virtual device 20 using, for example, a memcpy command. Also good.

  Note that the read processing from the virtual memory 30 when the access ranges do not overlap does not cause access contention, and therefore can be performed in parallel with the write processing to the virtual memory 30 by the access control unit 44 described later.

  On the other hand, the read determination unit 43 registers the read request in the management queue 41a in the queue storage unit 41 when the determination results in overlapping (hit). For example, the read determination unit 43 passes the read address (R_addr) and read data size (Byte) (R_size) relating to the input read request to the queue control unit 42 so as to register them in the management queue 41a.

  At this time, the read determination unit 43 notifies the queue control unit 42 of the pointer of the write request determined that the access range overlaps so that the processing order of the read request is immediately after the write request that overlaps the read request and the access range. be able to.

  Next, the read determination unit 43 receives the registration pointer (address, QueueBuff pointer) of the entry of the read request registered in the queue storage unit 41 as a return value from the queue control unit 42, and waits for a read process related to the read request. The read determination unit 43 checks the pointer of the queue 41 a when data (addr, size) is read from the queue storage unit 41 by the access control unit 44. Then, the read determination unit 43 releases the standby and executes the read process when the read process waiting is hit with the pointer of the read queue 41a. In the read process, as described above, the read determination unit 43 reads the read data from the virtual memory 30 and returns it to the request source as a return value of the Read function.

  If the access ranges overlap, there may be an access conflict in the read process from the virtual memory 30, and therefore the write process to the virtual memory 30 by the access control unit 44 is suppressed during the read process. For example, the read determination unit 43 enables the flag (R_EXEC) indicating that the read process is being executed for the registration pointer of the return value from the queue control unit 42, and waits for the write process by the access control unit 44 while R_EXEC is valid. be able to.

  Details of processing performed by the read determination unit 43 and an operation example will be described later with reference to FIGS. 15, 16, 18, and 19.

  Here, the description returns to the queue control unit 42. When the read determination unit 43 determines that the access range of the read request overlaps the access range of the write request in the queue storage unit 41 as described above, the queue control unit 42 stores the read request in the queue storage unit 41. . As a result, the read process is executed after the write process to the overlapping area of the virtual memory 30 is completed, so that the consistency of the read data can be maintained.

  For example, the queue control unit 42 uses the read address (R_addr) and the read data size (Byte) (R_size) passed from the read determination unit 43 and the read flag (for example, R_FLG (read flag) = 1) as a management queue. 41a is registered. At this time, when the queue control unit 42 is notified of the pointer of the queue 41a together with the data related to the read request from the read determination unit 43, the read request is issued between the notified pointer access request and the next access request. An entry (request) related to can be inserted.

  Hereinafter, an example of an operation of inserting a read request into the queue storage unit 41 (queue 41a) by the queue control unit 42 will be described with reference to FIGS.

  9, an example of inserting an access request for Que_REQ3 when the access request for the read request (Que_REQ3) is hit in the access range of Que_REQ1 in the queue 41a in the queue storage unit 41 will be described. It is assumed that the queue control unit 42 has been notified of the Que_REQ1 pointer from the read determination unit 43. In this case, for example, as illustrated in FIG. 10, the queue control unit 42 inserts Que_REQ3 related to the read request between Que_REQ1 and the next Que_REQ2.

  Specifically, the queue control unit 42 registers the pointer of Que_REQ3 related to the read request in Next_wp of the hit Que_REQ1. Further, the queue control unit 42 registers the pointer of Que_REQ1 hit in Before_wp of Que_REQ3, and registers the pointer of Que_REQ2 immediately after Que_REQ1 (registered in Next_wp of Que_REQ1) in Next_wp of Que_REQ3. Further, the queue control unit 42 registers the pointer of Que_REQ3 related to the read request in Before_wp of Que_REQ2.

  As described above, the queue control unit 42 can store (insert) the read request immediately after the write request determined to have overlapping access ranges, thereby minimizing the waiting time for the read process. Can be speeded up.

  Details of processing performed by the queue control unit 42 and an operation example will be described later with reference to FIGS. 13 and 14.

  As described above, for the read request, the queue control unit 42 and the read determination unit 43 determine whether or not the access range related to the read request overlaps the access range related to one or more write requests stored in the queue storage unit 41. It can be said that this is an example of a read control unit for determination. Specifically, this read control unit executes a read process related to a read request when the determination results in no overlap.

  As described above, according to the emulation server 1 according to the embodiment, when there is no write request to hit in the read request area in the queue storage unit 41, the read process is performed without storing the read request in the queue storage unit 41. be able to. Accordingly, it is possible to increase the speed of the read process and suppress the performance degradation of the virtual device 3.

  Note that the determination of the insertion position of the read request to the queue storage unit 41 may be performed by the read determination unit 43 or the queue control unit 42.

  The access control unit 44 reads information from the queue 41a and the message queue 41b (W_addr, W_size, W_data) in the processing order (for example, the order in which the access requests are issued) for the queue stored in the queue storage unit 41, and executes the write process. . For example, the access control unit 44 reads the head entry (access request) from the queue storage unit 41, and reads the head message queue 41b when the write flag is valid (for example, R_FLG (read flag) = 0). Then, the access control unit 44 transfers write data for the write data size (W_size) in the message queue 41b to the address (W_addr) of the virtual memory 30.

  In this way, the access control unit 44 reads out the write requests in the order in which they are stored in the queue storage unit 41 and performs the write process so that another thread (Thread) accesses the virtual memory 30 unless one write process is completed. Exclusive control is possible so that it cannot be done. Note that the Write function called by sending a write request from the virtual CPU 10 or the virtual device 20 is a push-out type that only writes to the queue storage unit 41. Therefore, unlike a Read function that waits for a read completion (return), even if a write request is queued in the queue storage unit 41, the performance (operation speed) of the virtual device 3 is not affected.

  Information read from the queue storage unit 41 is deleted from the queue 41a and the message queue 41b by the queue storage unit 41 or the access control unit 44, for example. Alternatively, for the write address in the message queue 41b, the data read from the queue storage unit 41 may be automatically deleted from the message queue 41b.

  Further, when there is no access request stored in the queue 41a of the queue storage unit 41 and there is a read request during execution of read processing, if a write request that overlaps the read processing access range is input, the queue control unit 42 Thus, the write request is stored in the queue 41a. Even in this case, the write request is read by the access control unit 44 and the write process is executed. However, when executing the write process, if the access range related to the write request hits the access range during the read process, the access control unit 44 executes the write process after the read process is completed.

  Further, when the request read from the queue 41 a is a read request, the access control unit 44 passes the pointer of the queue 41 a to the read determination unit 43 in order to execute a read process related to the read request.

  As described above, the queue control unit 42 and the access control unit 44 are an example of an execution unit that reads one or more requests (write request / read request) stored in the queue storage unit 41 in the processing order and executes a predetermined process. It can be said. Specifically, when the execution unit determines that the access range related to the write request read from the queue storage unit 41 overlaps the access range related to the read request during the execution of the read process, the execution unit completes the read process. It waits for execution of a predetermined process in response to the write request.

  As described above, according to the queue control unit 42 and the access control unit 44, the write process read from the queue storage unit 41 is executed after the completion of the read process. Therefore, the read / write exclusive process can be appropriately performed. . Therefore, the consistency of read / write data in the virtual memory 30 can be maintained.

  Details of processing performed by the access control unit 44 and an operation example will be described later with reference to FIGS. 17 and 18.

[1-5] Operation Example of Emulation Server Next, an operation example of the emulation server 1 configured as described above will be described with reference to FIGS.

  First, an overall operation example of the emulator 2 (virtual device 3) by the emulation server 1 will be described with reference to sequence diagrams shown in FIGS. As a premise, it is assumed that there is no access request in the queue storage unit 41 (no access request waiting for execution).

  First, as shown in FIG. 11, a case where the virtual CPU 10 performs a read access to the same range as the write access by the virtual device 20 will be described.

  As shown in FIG. 11, the queue control unit 42 loads (registers) a write request in the queue storage unit 41 (queue 41a and message queue 41b) by the Write function CALL by the virtual device 20 (process T1). Next, the access control unit 44 (thread) reads an access request (write request in this case) from the queue 41a of the queue storage unit 41 (process T2), and checks R_EXEC and the like. Then, the access control unit 44 determines whether or not a read process for the same range as the read write request has been performed. If the check of R_EXEC or the like is OK (there is no conflicting read process), the access control unit 44 executes the write process of the virtual device 20 (process T3). In addition, the queue control unit 42 notifies the virtual device 20 that the registration of the write request to the queue 41a is completed (process T4).

  On the other hand, when the Read function CALL is generated by the virtual CPU 10, the read determination unit 43 confirms the queue storage unit 41 (Process T5). As a result of the confirmation, when the access range of the write request during the write process in the queue 41a overlaps with the read access, the read determination unit 43 sends the read request to the entry related to the write process of the queue storage unit 41 via the queue control unit 42. Is inserted immediately after (processing T6).

  In the access control unit 44, when the write process is completed (process T7), the entry related to the write process in the queue 41a is deleted and updated via the queue control unit 42 (process T8), and the next entry (access request) ) Is read (process T9). When the next access request is a read request (R_FLG is set), the access control unit 44 notifies the read determination unit 43 that the read entry is a read request (process T10). Note that since the access request is a read request (R_FLG is set), the access control unit 44 does not wait for the completion of the read process, and does not wait for the completion of the read process, and enters an entry related to the read process in the queue 41a. Delete and update (process T11), and read the next entry.

  The read determination unit 43 sets an EXEC flag for the read request notified from the access control unit 44 (process T12) and executes a read process (process T13). When the read process is completed (process T14), the read determination unit 43 clears the EXEC flag (process T15), and the process ends.

  Next, as shown in FIG. 12, a case where the virtual CPU 10 performs a write access to the same range as the read access by the virtual device 20 will be described.

  As shown in FIG. 12, when the Read function CALL is generated by the virtual device 20, the read determination unit 43 checks the queue storage unit 41 (Process T21). As a result of the confirmation, there is no access request in the queue 41a (there is no write access overlapping the read access access range), so the read determination unit 43 sets the EXEC flag (process T22) and executes the read process ( Process T23).

  On the other hand, by the write function CALL by the virtual CPU 10, the queue control unit 42 loads (registers) a queue of write requests in the queue storage unit 41 (process T24). Next, the access control unit 44 (thread) reads the queue from the queue storage unit 41 (process T25), checks R_EXEC, etc., and determines whether read processing for the same range as the read queue is not executed. To do. However, since the R_EXEC flag is set for read access to the same range as the write access in process T22, the check of R_EXEC or the like becomes NG (there is a conflicting read process) (process T26). The queue control unit 42 notifies the virtual CPU 10 that the registration of the write request to the queue 41a has been completed (process T27).

  When the read process is completed (process T28), the read determination unit 43 clears the EXEC flag (process T29). Since the R_EXEC flag is cleared, the access control unit 44 (thread) checks R_EXEC and the like, and if the check is OK (if there is no conflicting read process), the write process of the virtual CPU 10 is executed (process T30). ). In the access control unit 44, when the write process is completed (process T31), the entry related to the write process in the queue storage unit 41 is deleted and updated via the queue control unit 42 (process T32), and the process ends. .

[1-5-1] Example of Write Function Operation Next, an example of the Write function operation will be described with reference to the flowchart shown in FIG.

  The virtual CPU 10 or the virtual device 20 generates a write request (message) in a format for calling the above-described Write function as data to be written in the virtual memory 30, and transmits it to the queue processing unit 40. The queue processing unit 40 executes the following Write function based on the received write request (step S1), and calls the queue registration function for write access to the queue storage unit 41 by the queue control unit 42.

Write_p = Que registration (W_addr, W_size, * W_data, 0, 0)
However, Que registration arguments are a write address, a write data size, write data, a pointer, and a read flag (R_FLG) in order from the left.

[1-5-2] Operation Example of Queue Registration Function Next, an operation example of the Queue registration function will be described with reference to the flowchart shown in FIG.

  The queue registration function is executed by the queue control unit 42 when a write request or a read request is added to or inserted into the queue storage unit 41 by executing the Write function or the Read function. When the queue registration function is activated, the queue control unit 42 receives a value from the caller (step S11). For example, the queue control unit 42 acquires the head address, data size, write data, pointer for inserting a read request, and the value of the R / W flag set in the queue 41a and the message queue 41b.

  Next, the queue control unit 42 determines whether or not R_FLG == 0 in order to determine whether the access request to be registered is read / write (step S12). If R_FLG == 0, that is, if it is a write request (Yes route in step S12), the queue control unit 42 sets the write request information in the area indicated by wp (write pointer) which is a Global variable. Register in the queue 41a (step S13). Specifically, the queue control unit 42 sets an address, a size, and an R / W flag relating to a write request in addr, size, and R_FLG of the entry indicated by wp, respectively.

  Further, the queue control unit 42 stores the write data (W_data) for the write data size in the message queue 41b (step S14), and secures the Next_wp area, that is, the next area of the queue 41a (step S15). . The queue control unit 42 repeats the process of step S15 until Next_wp! = 0 is not satisfied (No route of step S16 and step S16). When the Next_wp area is secured (Yes route of step S16), the process proceeds to step S17. .

  In step S17, the queue control unit 42 sets Next_wp reserved in Next_wp of the entry indicated by wp, sets the current wp in Before_wp of the entry indicated by the Next_wp, and updates the current wp value to the value of Next_wp. (Switch to the next queue 41a). Then, the queue control unit 42 returns wp as a return, and the processing of the Queue registration function ends.

  On the other hand, if R_FLG == 0 in step S12, that is, if it is a read request (No route in step S12), the queue control unit 42 secures an area for Read_p (read pointer), that is, information related to the read request. An area for storing (inserting) is secured (step S18). The queue control unit 42 repeats the process of step S18 until Read_p! = 0 is not satisfied (No route of step S19 and step S19). When the Read_p area is secured (Yes route of step S19), the queue control unit 42 proceeds to step S20. .

  In step S20, the queue control unit 42 sets the read request information in the area indicated by Read_p and registers (inserts) the information in the queue 41a, and changes Next_wp and Before_wp of the access requests before and after registering in the queue 41a. To do. Specifically, the queue control unit 42 sets the address, size, and R / W flag related to the read request in the addr, size, and R_FLG of the entry indicated by Read_p, respectively. Further, the queue control unit 42 changes the Next_wp and Before_wp of the entry indicated by Read_p and the entries Next_wp and Before_wp before and after the inserted access request (see FIGS. 9 and 10). Then, the queue control unit 42 returns Read_p as a return value, and the processing of the Queue registration function ends.

[1-5-3] Operation Example of Read Function Next, an operation example of the Read function will be described with reference to the flowcharts illustrated in FIGS. 15 and 16 and the diagram illustrated in FIG.

  When the virtual CPU 10 or the virtual device 20 reads data from the virtual memory 30, the virtual CPU 10 or the virtual device 20 generates a format read request (message) for calling the above-described Read function, and transmits the request to the queue processing unit 40. The queue processing unit 40 executes the following Read function processing mainly by the read determination unit 43.

  First, the read determination unit 43 acquires the read start address and data size from the read request (step S21). Then, the read determination unit 43 registers the read process of the virtual CPU 10 or the virtual device 20 (Device (Read_Req_DEV)) that requested the read process in ReadExec of the corresponding device (Step S22, reference numerals 43a and A1 in FIG. 18). Refer to “1”).

  Next, the read determination unit 43 sets the value of the global variable wp (write pointer) (in this case, a pointer indicating the last entry of the queue 41a) to rp (read pointer) (step S23). It is determined whether or not 0 (step S24). If rp! = 0 (Yes route in step S24), the read determination unit 43 determines whether or not R_FLG == 1 for the entry indicated by rp (step S25). When R_FLG == 1 (read process) (Yes route in step S25), the read determination unit 43 changes rp to the pointer of the previous entry (goes back to the queue 41a) (step S27), and the process proceeds to step S24. Migrate to

  On the other hand, when R_FLG == 1 is not satisfied (write process) (No route in step S25), the read determination unit 43 determines whether the access range of the read process overlaps with the access range of the write process (step S26, (Refer to reference numeral “2” in FIG. 18). If the access ranges do not overlap (No route in step S26), the process proceeds to step S27. On the other hand, when the access ranges overlap (Yes route of step S26), the read determination unit 43 calls the queue registration function of the read access to the queue storage unit 41 by the queue control unit 42 for the read process (step S28, FIG. 18 reference A2).

  Next, the read determination unit 43 registers the pointer of the read process to be executed in R_EXEC of the corresponding device (see step S29, “rp” in reference numeral 43b in FIG. 18 and “2.1” in A1). Thus, by registering the pointer of the read process to be executed, the read determination unit 43 can detect, via the access control unit 44, that the read process is read from the queue storage unit 41 and the process is completed. it can. Note that ReadExec 43a and R_EXEC 43b exist for each device of the virtual CPU 10 and the virtual device 20, respectively. The read determination unit 43 can store ReadExec 43a and R_EXEC 43b in a part of a storage area such as the cache memory or the virtual memory 30 of the CPU 1a.

  Then, the read determination unit 43 waits for reading from the queue 41a by the access control unit 44 (Yes route of step S30 and step S30). When the access request for the read process is read (No route in step S30), the process proceeds to step S31 in FIG.

  In step S31 of FIG. 16, the read determination unit 43 sets an EXEC flag indicating that the read process is being executed for the R_EXEC 43b corresponding to the device that has issued the read request (“EXEC of reference numeral 43b in FIG. 18). ", See A2.1," 2.1 ", and A3). Then, the read determination unit 43 clears the pointer of the read process in R_EXEC (for example, sets “0”) (step S32) and executes the read process (see step S33, symbol A4 in FIG. 18). The read process can be executed by, for example, a memcpy command, and read data can be returned to the device as a return value.

  Finally, the read determination unit 43 resets ReadExec 43a and R_EXEC 43b (for example, “0” is set) (see steps S34 and S35, “3” and A5 of reference symbol A1 in FIG. 18), and ends the process. In step S24 in FIG. 15, when rp! = 0 is not satisfied, that is, when the search is performed up to the first entry in the queue storage unit 41 (No route in step S24), the read determination unit 43 performs read processing and access. It is determined that there is no write process with overlapping ranges. Then, the process proceeds to step S31 in FIG. 16 (see “2.2” in reference numeral A1 in FIG. 18).

[1-5-4] Operation Example of Access Process (Thread) Next, an operation example of the access process (thread) will be described with reference to the flowchart shown in FIG. 17 and the diagram shown in FIG.

  The access control unit 44 reads access requests from the queue storage unit 41 (queue 41a) in the order of storage, and executes predetermined processing on the read access requests.

  First, the access control unit 44 registers the address, size, and R / W flag of the access request indicated by the global variable querp (read pointer from the queue 41a) in the variable (see step S41, symbol B1 in FIG. 18). . Then, the access control unit 44 determines whether or not the content of the access request is empty (step S42). If it is empty (Yes route of step S42), the process proceeds to step S41. On the other hand, when it is not empty (No route in step S42), the access control unit 44 determines whether or not the content of the access request is a read process with reference to R_FLG (step S43).

  On the other hand, when it is not a read process (a write process) (No route of step S43), the process proceeds to step S44. In steps S44 to S48, the access control unit 44 causes the read determination unit 43 to determine whether or not a read process overlapping with the access range of the write process is being performed before performing the write process (FIG. 18). Reference B2).

  As an example, the read determination unit 43 can determine whether or not the read process registered (ReadExec) is being executed (R_EXEC == 1). Then, the read determination unit 43 compares the registration information being executed (for example, the corresponding ReadExec 43a) with information related to the write process acquired from the access control unit 44, and determines whether to wait for the write process.

  For example, in step S44, the read determination unit 43 determines whether or not the EXEC flag of the virtual CPU 10 is valid (for example, “1”) with the device that checks the R_EXEC 43b as the virtual CPU 10 (step S45).

  When the EXEC flag is valid (Yes route in step S45), the read determination unit 43 determines whether the access range of the write process overlaps with the access range of the read process by the same method as the process of the Read function. (See step S46, "2" of reference A1 in FIG. 18). If the access ranges do not overlap (No route in step S46), or if the EXEC flag is invalid in step S45 (No route in step S45), the read determination unit 43 changes the virtual CPU 10 to another virtual device 20. (Step 47). Then, the read determination unit 43 repeats the process until determination is made for all devices (No route in step S48 and step S48).

  If the access ranges overlap in step S46 (Yes route in step S46), the processing while the EXEC flag is valid (during the read process) enters the loop from the Yes route in step S45 to the Yes route in step S46. Thereby, the read determination unit 43 can wait for the write process.

  If all the devices have been determined (Yes route in step S48), the process is returned from the read determination unit 43 to the access control unit 44, and the access control unit 44 executes the write process (step S49, code in FIG. 18). (See B3). For example, the access control unit 44 can read write data for the write size from the message queue 41 b (buffer) using the memcpy command and copy it to the virtual memory 30.

  Next, the access control unit 44 instructs the queue control unit 42 to delete the access request for which the write process has been completed, and the queue control unit 42 deletes the access request from the queue storage unit 41 (Step S50, (See symbol B4 in FIGS. 8 and 18). In step S43, when the content of the access request is a read process (Yes route in step S43), the process proceeds to step S50. In this case, the access control unit 44 notifies the read determination unit 43 of the pointer of the queue 41a related to the read process, and instructs the queue control unit 42 to delete the access request related to the read process.

  Next, the access control unit 44 acquires a new access request because Querp is updated to Next_wp and Que_WP is also updated in step S50. At this time, since the thread switching may be slow, if the read access request data is a read, the access control unit 44 sets an EXEC flag indicating that the read is being executed (Yes in steps S51 and S51). Route and S52). When the process of step S52 is completed, or when the read access request data is a write (No route of step S51), the process proceeds to step S41.

[1-5-5] Example of EXEC Flag Setting Process Next, an example of the EXEC flag setting process will be described with reference to the flowchart shown in FIG.

  In step S52 of FIG. 17, when the EXEC flag setting process is executed by the access control unit 44, the read determination unit 43 is activated. The read determination unit 43 sets the device that confirms the R_EXEC 43b as the virtual CPU 10 (step S61), and determines whether or not the rp of the virtual CPU 10 matches Que_WP and is not “0” (step S62). When the condition is not satisfied (No route in step S62), the read determination unit 43 changes the virtual CPU 10 to another virtual device 20 (step 63), and repeats the process until all the devices are determined (step S64 and step S64). No route in step S64). When the determination is made for all devices, the process ends.

  On the other hand, if the condition is satisfied in step S62 (Yes route in step S62), the read determination unit 43 determines whether or not the EXEC flag is valid (step S65), and if valid (Yes route in step S65). , The process ends. If the EXEC flag is invalid (No route in step S65), the read determination unit 43 validates the EXEC flag (step S66), and the process ends.

  The above-described EXEC flag setting process may be performed by the access control unit 44.

[1-6] Effects of this Embodiment According to the emulation server 1 according to this embodiment, the performance of the virtual device 3 is higher than that of the virtual device 200 shown in FIG. 2 provided with an arbitration function (arbiter) equivalent to hardware. Deterioration of (processing speed) can be suppressed.

  Here, since the arbiter is a circuit that performs bus arbitration, while either the virtual CPU or the virtual device accesses the virtual memory, the other device cannot access the virtual memory, and the process is waited for (response) Speed decreases). In the arbitration by hardware, when one device (including the CPU) uses the bus, arbitration is performed so that other devices cannot use the bus.

  However, in software, a plurality of processes (threads) can access the virtual memory. For this reason, it is preferable from the viewpoint of reproducibility of the target device 1000 by the emulator that the emulator that implements (reproduces) the hardware by software performs exclusive processing like hardware. In this case, as described with reference to FIG. 2, the speed reduction of the virtual device is significant.

  On the other hand, according to the emulation server 1 according to the present embodiment, memory arbitration (exclusive processing) of each virtual processing unit can be minimized and simplified, so that the speed reduction can be suppressed and the emulation can be performed at high speed. Rate can be done. Accordingly, it is possible to suppress the performance degradation of the virtual model in the information processing apparatus that reproduces the target device 1000 using the virtual model. In addition, since the exclusiveness of access to the virtual memory 30 is maintained, the virtual CPU 10 and the virtual device 20 can be easily multi-threaded.

  Furthermore, since the emulation server 1 includes the queue storage unit 41 that stores the write requests in the processing order in the virtual device 3, the order of access to the virtual memory 30 is guaranteed. Therefore, a memory barrier can also be mounted on the virtual CPU 10 portion.

  Furthermore, since the order of access to the virtual memory 30 by the virtual CPU 10 and the virtual device 20 is constant, it is easy to find bugs such as memory data destruction caused by DMA (Direct Memory Access) or the like. it can.

[1-7] Application Example As described above, the emulation server 1 can realize exclusive control when one or more virtual CPUs 10 and a plurality of virtual devices 20 access the same memory space of the virtual memory 30. . Such exclusive control is suitable, for example, for interrupt processing in which the virtual device 20 uses the virtual memory 30 to cause the virtual CPU 10 to generate an interrupt.

  Hereinafter, application examples of the emulation server 1 according to the present embodiment will be described with reference to the virtual device 300 illustrated in FIG. 20 and the virtual device 6 illustrated in FIG. 21. Note that the virtual device 300 has basically the same configuration as the virtual device 100 shown in FIG. 1, and the virtual device 6 has basically the same configuration as the virtual device 3 shown in FIGS. And

In FIG. 20, reference numerals (1) to (6) are the following processes.
(1) Write process from virtual device 120-1 to virtual memory 130 (2) Virtual device 120-1 read process from virtual memory 130 (3) Write process from virtual device 120-2 to virtual memory 130 (4 ) The virtual device 120-2 reads from the virtual memory 130 (5) The virtual CPU 110 writes to the virtual memory 130 (6) The virtual CPU 110 reads from the virtual memory 130

In the following description, it is assumed that the virtual device 300 performs the processes (* 1) to (* 4).
(* 1) The virtual device 120-1 performs a write process of writing “0x100 Byte” data to “0x0F80” of the virtual memory 130.
(* 2) The virtual device 120-2 performs a read process of reading data “0x200 Byte” from “0x2000” of the virtual memory 130.
(* 3) The virtual device 120-1 performs a write process of writing “0x100 Byte” data to “0x1080” of the virtual memory 130.
(* 4) The virtual CPU 110 confirms and processes the completion of data writing by the virtual device 120-1.

  When the virtual CPU 110 waits for the completion of writing by the virtual device 120-1 as in the process of (* 4), the virtual CPU 110 waits for a writing completion interrupt from the virtual device 120-1. Then, it can be considered that the virtual CPU 110 moves to the interrupt handler due to the interrupt and recognizes the completion of the writing.

  However, since the virtual device 120-1 performs the processes (* 1) and (* 3), for example, the process (* 3) may be completed during the interrupt handler process related to the process (* 1). . In this case, since the interrupt according to (* 3) may occur immediately after the completion of the interrupt process according to (* 1) of the virtual CPU 110 and the process may be transferred again to the interrupt handler, the efficiency is low.

  In recent systems, a technique is known in which interrupt information is written into a memory space before a virtual device generates an interrupt to a virtual CPU, and MSI (Message Signaled Interrupt) or MSI-X (MSI-eXtended) is used as an interrupt notification. It has been. The interrupt information includes an error status, a data transfer address (because transfer using a table such as Scatchather is possible), and the like.

  In this method, since the interrupt information is written in the memory space, the virtual CPU determines that the processing is completed if data is written in a certain area at the time of one interrupt handler process. The overhead due to interrupt processing is reduced. In actual hardware, while the interrupt information is being written into the memory space, the CPU does not allow the data to be read by the exclusive control, but as described above, it is possible in the software emulator.

  As an example, assume that the virtual device 120-1 writes “8 Byte” data in the memory space A as interrupt information for each interrupt (see FIG. 20). The memory space A is registered as a writable memory in the virtual device 120-1, and A is increased by “8 Bytes” after data is written to the memory space A every time an interrupt occurs. The write data to the memory space A is the information indicating what interrupt the first “2 Byte” is, the next “2 Byte” is the status information such as an error, and the last “4 Byte” is the data storage destination Assume that it is an address.

  In normal processing, the virtual device 300 operates in the following procedure, for example.

  In the path (1), the virtual device 120-1 performs a write process of “0x100 Byte” to “0x0F80” of the virtual memory 130. Then, the virtual device 120-1 writes “8 Byte” data in the memory space A when writing is completed, generates an interrupt to the virtual CPU 110, and then sets “A = A + 8” as the next write address. ”.

  The virtual CPU 110 performs an interrupt process on the route (6). The virtual CPU 110 reads the data in the space (A + 0) before the update, and confirms the data at the address indicated by the space (A + 4) before the update. Then, the virtual CPU 110 confirms that there is no problem and continues (returns) the process.

  In the path (4), the virtual device 120-2 performs a read process from “0x2000” to “0x200 Byte” of the virtual memory 130.

  In the path (1), the virtual device 120-1 performs a write process of “0x100 Byte” to “0x1080” of the virtual memory 130. Then, the virtual device 120-1 writes “8 Byte” data in the memory space A when writing is completed, generates an interrupt to the virtual CPU 110, and then sets “A = A + 8” as the next write address. ”.

  The virtual CPU 110 performs an interrupt process on the route (6). The virtual CPU 110 reads the data in the space (A + 0) before the update, and confirms the data at the address indicated by the space (A + 4) before the update. Then, the virtual CPU 110 confirms that there is no problem and continues (returns) the process.

  The above-described procedure is described as the operation of an interrupt handler that executes a plurality of interrupt processes with a single interrupt as follows.

  In the path (1), the virtual device 120-1 performs a write process of “0x100 Byte” to “0x0F80” of the virtual memory 130. Then, the virtual device 120-1 writes “8 Byte” data in the memory space A when writing is completed, generates an interrupt to the virtual CPU 110, and then sets “A = A + 8” as the next write address. ”.

  The virtual CPU 110 performs an interrupt process on the route (6). The virtual CPU 110 reads the data in the space (A + 0) before the update, and confirms the data at the address indicated by the space (A + 4) before the update.

  In addition, the virtual CPU 110 reads the data in the space (A + 8) before the update, checks whether the data is written, and if not written, continues the processing (return) while the data is written. For example, the data of the address indicated by the space before update (A + 12) is confirmed. Then, the virtual CPU 110 reads the data in the space (A + 16) before the update and checks whether the data is written. If not, the process continues (returns). Check the data at the address indicated by the space (A + 20). Thereafter, the virtual CPU 110 proceeds in the same manner when data is written in a space (A + x (x is a multiple of 4)).

  In the path (4), the virtual device 120-2 performs a read process from “0x2000” to “0x200 Byte” of the virtual memory 130.

  In the path (1), the virtual device 120-1 performs a write process of “0x100 Byte” to “0x1080” of the virtual memory 130. Then, the virtual device 120-1 writes “8 Byte” data in the memory space A when writing is completed, generates an interrupt to the virtual CPU 110, and then sets “A = A + 8” as the next write address. ”.

  The virtual CPU 110 performs an interrupt process on the route (6). The virtual CPU 110 reads the data in the space (A + 0) before the update, and confirms the data at the address indicated by the space (A + 4) before the update.

  In addition, the virtual CPU 110 reads the data in the space (A + 8) before the update, checks whether the data is written, and if not written, continues the processing (return) while the data is written. For example, the data of the address indicated by the space before update (A + 12) is confirmed. Then, the virtual CPU 110 reads the data in the space (A + 16) before the update and checks whether the data is written. If not, the process continues (returns). Check the data at the address indicated by the space (A + 20). Thereafter, the virtual CPU 110 proceeds in the same manner when data is written in a space (A + x (x is a multiple of 4)).

  In this way, if the processing of (* 2) and (* 3) is executed after the processing of (* 1) is completed and before the processing moves to the interrupt handler, The interrupt process 3) is also performed.

  In the software emulator, each virtual device 120 operates in a separate thread (process). Therefore, when proceeding with (* 1), (* 2), (* 3), it is not possible to write A + 0 to A + 7 in (* 3), but around A + 0, A + 1 It is possible that the virtual device 120-1 is switched to another thread (for example, the virtual device 120-2) when the above is written.

  In this case, in the order of the threads of the virtual CPU 110, the address of the area (* 3) processed by the interrupt handler indicates an address of a different area, and a malfunction occurs.

  On the other hand, the virtual device 6 according to the application example of the present embodiment operates in the following procedure, for example.

  In the path (1), the virtual device 20-1 performs write processing of “0x100 Byte” on “0x0F80” of the virtual memory 30, so the write data for the write address, size, and size is written to the queue processing unit 40. Is written (stored in the queue storage unit 41).

  When the writing is completed, the virtual device 20 writes “8 Byte” data in the memory space A, so the address (A), size (8 Byte), and data (8) of the memory space A are stored in the queue processing unit 40. Byte) is written (stored in the queue storage unit 41). Then, the virtual device 20 generates an interrupt to the virtual CPU 10 and implements “A = A + 8” as the next write address.

  The virtual CPU 110 performs an interrupt process on the route (6). The virtual CPU 110 instructs the queue processing unit 40 to read the read address (A + 0), the size (1 byte), and the pointer for storing the read data of the virtual CPU 10 in order to read the data in the space (A + 0) before the update. And access.

  At this time, the queue processing unit 40 checks whether the access range overlaps from the address (read address) for accessing the virtual memory 30 and the address (write address) stored in the queue storage unit 41. If they overlap, in the queue processing unit 40, the read processing is accumulated in the queue storage unit 41, the virtual CPU 10 waits for a read response, and cannot proceed to the next processing. In this case, the writing and reading of the memory space A overlap.

  When the read process is read from the queue processing unit 40, the virtual CPU 10 reads from the memory space A of the virtual memory 30. Then, the virtual CPU 10 checks the queue processing unit 40 with the address (A + 4), size (4 bytes), virtual, in order to confirm the data of the address indicated in the space (A + 4) before update as the next processing. A pointer for storing read data of the CPU 10 is designated and accessed. At that time, the virtual CPU 10 confirms whether or not it is loaded in the queue storage unit 41 and proceeds with the processing. With such a processing method, the virtual device 6 can prevent halfway data from being read from the virtual memory 30 by the virtual CPU 10 or the like, and can prevent malfunction.

  In the path (4), the virtual device 120-2 performs read processing from “0x2000” to “0x200 Byte” of the virtual memory 130, so that the queue processing unit 40 is addressed (0x2000), size (0x200), Then, the virtual device 20-2 designates and accesses a pointer for storing data. The queue processing unit 40 checks whether the access ranges overlap from the address (read address) for accessing the virtual memory 30 and the address (write address) stored in the queue storage unit 41. If they overlap, the queue storage unit 41 is loaded with the read process of the virtual device 20-2, waits for a read response, and cannot proceed to the next process. In this case, the process proceeds because there is no overlap.

  At this time, the processing in the queue processing unit 40 may overtake the processing of the virtual CPU 10, but there is no particular problem because the situation is in a non-overlapping area. Rather, the queue processing unit 40 can prevent the overall speed reduction of the virtual device 6 by causing such overtaking. Since the subsequent processing proceeds in the same manner, it is omitted.

  As described above, in the application example of this embodiment, the same effect as that of the embodiment can be obtained, and in the case where each of the virtual CPU 10 and the virtual device 20 operates in different threads, the virtual device 6 Overall performance degradation can be suppressed.

[2] Others While the preferred embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes can be made without departing from the spirit of the present invention. It can be changed and implemented.

  For example, in the virtual devices 3 and 6, the functions of the queue control unit 42, the read determination unit 43, and the access control unit 44 may be combined in any combination or divided.

[3] Supplementary Notes Regarding the above embodiment, the following supplementary notes are further disclosed.

(Appendix 1)
An information processing apparatus that reproduces a target device having a target storage unit and a plurality of target processing units that share a storage area of the target storage unit,
A storage unit for storing a write request to the virtual storage unit corresponding to the target storage unit issued from each of the plurality of virtual processing units corresponding to the plurality of target processing units in the processing order;
For a read request issued from the virtual processing unit to the virtual storage unit, determine whether the access range related to the read request overlaps the access range related to one or more write requests stored in the storage unit, An information processing apparatus comprising: a read control unit that executes a read process related to the read request when they do not overlap.

(Appendix 2)
The read control unit stores the read request in the storage unit when it is determined that an access range related to the read request overlaps an access range related to one or more write requests stored in the storage unit. The information processing apparatus according to attachment 1.

(Appendix 3)
When the read control unit determines that the access range related to the read request overlaps with the access range related to one or more write requests stored in the storage unit, the processing order of the read requests overlaps the read request and the access range The information processing apparatus according to appendix 2, wherein the read request is stored in the storage unit immediately after a write request.

(Appendix 4)
It further includes an execution unit that reads one or more requests stored in the storage unit in a processing order and executes a predetermined process,
If the execution unit determines that the access range related to the write request read from the storage unit overlaps the access range related to the read request during the read process, the execution unit reads from the storage unit until the read process is completed 4. The information processing apparatus according to any one of appendices 1 to 3, wherein the information processing apparatus waits for execution of a predetermined process in response to a write request.

(Appendix 5)
The read control unit searches for one or more write requests stored in the storage unit in an order reverse to the processing order, and determines whether or not the access range of the read request overlaps. The information processing apparatus according to any one of appendices 1 to 4.

(Appendix 6)
A computer that reproduces a target device that includes a target storage unit and a plurality of target processing units that share a storage area of the target storage unit,
Write requests to the virtual storage unit corresponding to the target storage unit, issued from each of the plurality of virtual processing units corresponding to the plurality of target processing units, are stored in the storage unit in the order of processing,
For a read request issued from the virtual processing unit to the virtual storage unit, determine whether the access range related to the read request overlaps the access range related to one or more write requests stored in the storage unit,
An emulation program characterized by causing a process of executing a read process related to the read request to be executed when there is no overlap as a result of the determination.

(Appendix 7)
In the computer,
Note that when it is determined that an access range related to a read request overlaps an access range related to one or more write requests stored in the storage unit, a process of storing the read request in the storage unit is executed. 6. The emulation program according to 6.

(Appendix 8)
In the process of storing the read request, when it is determined that the access range related to the read request overlaps with the access range related to one or more write requests stored in the storage unit, the processing order of the read request is the read request and the access The emulation program according to appendix 7, wherein the read request is stored in the storage unit immediately after a write request with overlapping ranges.

(Appendix 9)
In the computer,
One or more requests stored in the storage unit are read in the order of processing, and predetermined processing is executed.
Determining whether the access range related to the write request read from the storage unit overlaps the access range related to the read request during the execution of the read process;
If the result of the determination is that there is an overlap, any one of appendices 6 to 8, wherein a process of waiting for execution of a predetermined process for the write request read from the storage unit until the read process is completed is further executed The emulation program described in the section.

(Appendix 10)
In the determination process, the one or more write requests stored in the storage unit are searched in an order reverse to the processing order, and it is determined whether or not the access range of the read request overlaps. The emulation program according to any one of appendices 6 to 9.

(Appendix 11)
An emulation method in an information processing apparatus for reproducing a target device having a target storage unit and a plurality of target processing units sharing a storage area of the target storage unit,
Write requests to the virtual storage unit corresponding to the target storage unit, issued from each of the plurality of virtual processing units corresponding to the plurality of target processing units, are stored in the storage unit in the order of processing,
For a read request issued from the virtual processing unit to the virtual storage unit, determine whether the access range related to the read request overlaps the access range related to one or more write requests stored in the storage unit,
An emulation method, wherein if the result of determination is that there is no overlap, a read process related to the read request is executed.

(Appendix 12)
The emulation according to appendix 11, wherein the read request is stored in the storage unit when it is determined that the access range related to the read request overlaps with an access range related to one or more write requests stored in the storage unit Method.

(Appendix 13)
In the process of storing the read request, when it is determined that the access range related to the read request overlaps with the access range related to one or more write requests stored in the storage unit, the processing order of the read request is the read request and the access 13. The emulation method according to appendix 12, wherein the read request is stored in the storage unit immediately after a write request having overlapping ranges.

(Appendix 14)
One or more requests stored in the storage unit are read in the order of processing, and predetermined processing is executed.
Determining whether the access range related to the write request read from the storage unit overlaps the access range related to the read request during the execution of the read process;
14. The emulation method according to any one of appendices 11 to 13, wherein when the determination results in overlapping, the execution of a predetermined process for the write request read from the storage unit is waited until the read process is completed. .

(Appendix 15)
In the determination process, the one or more write requests stored in the storage unit are searched in an order reverse to the processing order, and it is determined whether or not the access range of the read request overlaps. The emulation method according to any one of appendices 11 to 14.

1 Emulation server (information processing device)
1a, 1100 CPU
1b, 1300 Memory 1c Storage unit 1d Interface unit 1e Input / output unit 1f, 1h Recording medium 1g Reading unit 2 Emulator 3, 6, 100, 200, 300 Virtual device 4 Emulation area 5 Emulation program 10, 110 Virtual CPU
20, 20-1 to 20-3, 120, 120-1 to 120-3 Virtual device 30, 130 Virtual memory 40 Queue processing unit 41 Queue storage unit (storage unit)
41a Queue 41b Message Queue 42 Queue Control Unit 43 Read Determination Unit 44 Access Control Unit 140 Arbiter 150 Selector 1000 Target Device (Device)
1200-1 to 1200-3 device 1400 internal bus

Claims (7)

An information processing apparatus that reproduces a target device having a target storage unit and a plurality of target processing units that share a storage area of the target storage unit,
A storage unit for storing a write request to the virtual storage unit corresponding to the target storage unit issued from each of the plurality of virtual processing units corresponding to the plurality of target processing units in the processing order;
For a read request issued from the virtual processing unit to the virtual storage unit, determine whether the access range related to the read request overlaps the access range related to one or more write requests stored in the storage unit, An information processing apparatus comprising: a read control unit that executes a read process related to the read request when they do not overlap. The read control unit stores the read request in the storage unit when it is determined that an access range related to the read request overlaps an access range related to one or more write requests stored in the storage unit. The information processing apparatus according to claim 1. When the read control unit determines that the access range related to the read request overlaps with the access range related to one or more write requests stored in the storage unit, the processing order of the read requests overlaps the read request and the access range The information processing apparatus according to claim 2, wherein the read request is stored in the storage unit immediately after the write request. It further includes an execution unit that reads one or more requests stored in the storage unit in a processing order and executes a predetermined process,
If the execution unit determines that the access range related to the write request read from the storage unit overlaps the access range related to the read request during the read process, the execution unit reads from the storage unit until the read process is completed The information processing apparatus according to claim 1, wherein the information processing apparatus waits for execution of a predetermined process for a write request. The read control unit searches for one or more write requests stored in the storage unit in an order reverse to the processing order, and determines whether or not the access range of the read request overlaps. The information processing apparatus according to any one of claims 1 to 4. A computer that reproduces a target device that includes a target storage unit and a plurality of target processing units that share a storage area of the target storage unit,
Write requests to the virtual storage unit corresponding to the target storage unit, issued from each of the plurality of virtual processing units corresponding to the plurality of target processing units, are stored in the storage unit in the order of processing,
For a read request issued from the virtual processing unit to the virtual storage unit, determine whether the access range related to the read request overlaps the access range related to one or more write requests stored in the storage unit,
An emulation program characterized by causing a process of executing a read process related to the read request to be executed when there is no overlap as a result of the determination. An emulation method in an information processing apparatus for reproducing a target device having a target storage unit and a plurality of target processing units sharing a storage area of the target storage unit,
Write requests to the virtual storage unit corresponding to the target storage unit, issued from each of the plurality of virtual processing units corresponding to the plurality of target processing units, are stored in the storage unit in the order of processing,
For a read request issued from the virtual processing unit to the virtual storage unit, determine whether the access range related to the read request overlaps the access range related to one or more write requests stored in the storage unit,
An emulation method, wherein if the result of determination is that there is no overlap, a read process related to the read request is executed.

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