JP2015210659A - Arithmetic processing unit and control method of arithmetic processing unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an arithmetic processing unit with improved throughput and a control method of arithmetic processing unit.SOLUTION: A cache RAM 133 has RAMs #0-#15, and each of the RAMs #0-#15 is assigned with an address the way of which is continuous. An instruction control section 11 acquires an arithmetic processing instruction which includes plural cache access requests 200 each of which instructs to process on the data with predetermined address intervals on the same way, and transmits the acquired cache access requests 200. A cache control section 13 receives cache access requests 200 transmitted from the instruction control section 11 and controls to execute the access processing on the data at predetermined address intervals on the way specified by the cache access requests 200. An arithmetic control section 12 controls to execute the arithmetic processing based on the access processing result made by the cache control section 13.

Description

  The present invention relates to an arithmetic processing device and a control method for the arithmetic processing device.

  In recent years, in order to improve calculation performance, an arithmetic processing apparatus sometimes performs processing called SIMD (Single Instruction Multiple Data). SIMD is a method for processing operations on a plurality of pieces of data in a single instruction. Also, in order to improve the performance of arithmetic processing using SIMD, it is preferable that the load / store processing is also expanded according to SIMD.

  Also, in load / store processing using SIMD, high throughput between the arithmetic unit and the cache is a key to performance improvement. In load / store processing using SIMD, it is preferable that data corresponding to the SIMD data width is transferred between the arithmetic unit and the cache in one cycle for one load / store instruction.

  For example, in order to realize a load / store process with a SIMD data width of 32 bytes in a 4-way set associative cache configuration, the following configuration may be used.

  In this case, the cache is composed of four ways, and each way has four RAMs (Random Access Memory). Each RAM is, for example, a 1 read or 1 weight RAM with a read width of 8 bytes. As a result, the read width per one way is 8 bytes × 4 = 32 bytes. Therefore, if this cache RAM is used, the SIMD data width of 8 bytes × 4 = 32 bytes can be read in one cycle. In other words, this cache RAM can realize load / store processing with a SIMD data width of 32 bytes.

  In addition, when executing a matrix product operation or the like, it is conceivable that data is arranged on the memory at specific address intervals. Such an interval between data arranged on a memory at a specific address interval may be called a stride, and access to data arranged in a stride pattern may be called a stride access.

  In consideration of such stride access, there is a technique for performing SIMD calculation with a single instruction for a plurality of data in a stride pattern as a technique for further improving the calculation performance. It may be called a load stride store process.

  Even when this stride load / stride store process is executed, high throughput between the arithmetic unit and the cache is important for improving performance, and it is preferable to transfer stride pattern data in one cycle.

  For example, as a stride access technique, there is a conventional technique in which a plurality of data is accessed simultaneously by adjusting the memory interleave configuration to the stride interval. Further, there is a conventional technique for improving the throughput by changing the memory access unit in accordance with the stride interval.

JP 2000-163316 A JP 2008-250926 A

  However, if stride access is performed in a configuration in which a RAM is independently assigned to each way as in the conventional cache configuration, it is difficult to access data of all elements in one cycle.

  For example, as described above, 4 ways of 1 read or 1 weight RAM with a read width of 8 bytes are allocated to 1 way, and 8 bytes of data from 0x0, which is the top address, are loaded with a SIMD data width of 32 bytes and a stride interval of 2. The case will be described. Here, four cache access requests of SIMD are set as elements 0 to 3.

  In this configuration, the data is returned to the same RAM every 32 bytes, so the data of element 2 is stored at a location starting from the address after 0 bytes from 0x0, so the data of element 0 and the data of element 2 are stored in the same RAM. Exists. For the same reason, the data of element 1 and the data of element 3 exist on the same RAM.

  As described above, in the conventional way arrangement, it is difficult to access data of all elements in one cycle, and the throughput may be reduced.

  Further, even when the conventional technique of adjusting the memory interleaved configuration to the stride interval is used, the same RAM is accessed in the stride access, and it is difficult to access the data of all elements in one cycle. In addition, even when the conventional technology that changes the memory access unit according to the stride interval is used, the RAM configuration for one way does not change, and the same RAM is accessed in the stride access. It is difficult to access the data. That is, there is a possibility that the throughput may be reduced by using any of the conventional techniques.

  The disclosed technology has been made in view of the above, and an object thereof is to provide an arithmetic processing device and a control method for the arithmetic processing device that improve the throughput.

  In one aspect, the arithmetic processing device and the control method of the arithmetic processing device disclosed in the present application are such that the cache memory has a plurality of storage elements for each way, and is continuous with respect to the plurality of storage elements belonging to each way. Address to be assigned. The instruction control unit acquires an operation processing instruction including a plurality of cache access requests that respectively instruct processing on data at a predetermined address interval included in the same way, and transmits the acquired plurality of cache access requests. The cache control unit receives each of the plurality of cache access requests transmitted from the instruction control unit, and performs a plurality of access processes on the data at the predetermined address interval included in the way specified by each cache access request Execute. The arithmetic control unit performs arithmetic processing based on the processing result of the access processing by the cache control unit.

  According to one aspect of the arithmetic processing device and the control method of the arithmetic processing device disclosed in the present application, there is an effect that the throughput can be maintained even when data is read from data at a predetermined address interval.

FIG. 1 is a block diagram of an arithmetic processing unit. FIG. 2 is a schematic configuration diagram of the cache control unit. FIG. 3 is a diagram illustrating allocation of addresses to the cache RAM in the embodiment. FIG. 4 is a diagram for explaining that no address interference occurs. FIG. 5 is a block diagram of the read function of the RAM address generation circuit. FIG. 6 is a diagram showing the addition amount by the adder for each element. FIG. 7 is a circuit diagram showing details of the selector corresponding to reading. FIG. 8 is a circuit diagram of the RAM # 0 read selection condition circuit. FIG. 9 is a diagram showing a RAM selection truth table at the time of reading by way and address. FIG. 10 is a diagram illustrating conditions under which RAM # 0 is selected during reading. FIG. 11 is a block diagram of the write function of the RAM address generation circuit. FIG. 12 is a diagram showing a RAM selection truth table at the time of writing by way and address. FIG. 13 is a circuit diagram showing details of a selector corresponding to writing. FIG. 14 is a circuit diagram of the RAM # 0 write selection condition circuit. FIG. 15 is a diagram showing conditions for selecting RAM # 0 during writing. FIG. 16 is a flowchart of the load / store process performed by the arithmetic processing apparatus according to the embodiment.

  Embodiments of an arithmetic processing device and a control method for the arithmetic processing device disclosed in the present application will be described below in detail with reference to the drawings. The following embodiments do not limit the arithmetic processing device and the control method of the arithmetic processing device disclosed in the present application.

  FIG. 1 is a block diagram of an arithmetic processing unit. In this embodiment, a CPU (Central Processing Unit) will be described as an example of the arithmetic processing device.

  The CPU 1 includes an instruction control unit 11, an operation control unit 12, a cache control unit 13, a secondary cache control unit 14, and a memory control unit 15. The memory control unit 15 is connected to the memory 2.

  The instruction control unit 11 acquires an instruction from an application or the like. Then, the instruction control unit 11 determines whether or not a cache access request is included in the acquired instruction. The cache access request is, for example, a load / store request for requesting data reading from the memory to the computing unit via the cache or data writing from the computing unit to the memory via the cache.

  The cache access request according to the present embodiment is a request for performing stride access to access a plurality of non-contiguous data on the memory.

  The instruction control unit 11 transmits a cache access request included in the instruction to the cache control unit 13. Hereinafter, the cache access request is simply referred to as “request”.

  In addition, the instruction control unit 11 sends an execution request for the arithmetic processing included in the instruction to the arithmetic control unit 12.

  The cache control unit 13 has a primary cache. Then, the cache control unit 13 receives a request indicating stride access from the instruction control unit 11.

  When each received request is a request for load processing, the cache control unit 13 determines whether or not a cache hit occurs in the primary cache. If there is no cache hit, the cache control unit 13 notifies the secondary cache control unit 14 of a data transfer request. Thereafter, the cache control unit 13 receives response data for the data transfer request from the secondary cache control unit 14. Then, the cache control unit 13 writes the response data to the primary cache. Thereafter, the cache control unit 13 determines whether or not a cache hit occurs in the primary cache. When a cache hit occurs, the cache control unit 13 acquires the hit data from the primary cache and transmits it to the arithmetic control unit 12.

  If each received request is a request for store processing, the cache control unit 13 updates the data stored in the primary cache.

  Here, the cache control unit 13 will be described in detail with reference to FIG. FIG. 2 is a schematic configuration diagram of the cache control unit. The cache control unit 11 includes a tag determination unit 131, a RAM address generation circuit 132, a cache RAM 133, a hit determination unit 134, and a memory access control unit 135. In this embodiment, the stride width is assumed to be 1 to 7, and the case where the stride width is 4 will be described as an example. In this embodiment, a case where four elements E1 to E4 are included in one instruction will be described. Hereinafter, the number of requests included in one instruction is referred to as “number of elements”. That is, in this embodiment, the number of elements is four. In this embodiment, the cache RAM 133 is described as having four ways.

  Here, in the present embodiment, 16 1 read or 1 weight RAMs of RAMs # 0 to # 15 are mounted on the cache RAM 133 which is a primary cache. Here, it is assumed that the read width of data from one RAM constituting the RAMs # 0 to # 15 is 8 bytes. That is, since the stride width is 4, the amount of data that can be read at one time by one command, that is, the read width per one way is 32 bytes. Hereinafter, when the RAMs # 0 to # 15 are not distinguished, they are simply referred to as “RAM”. This RAM is an example of a “memory element”.

  Here, the number of RAMs included in the cache RAM 133 is set so as to satisfy one of the following two conditions with respect to the stride width used. The first condition is that the stride width and the number of RAMs are prime. The second condition is that the value obtained by multiplying the stride width by the number of elements does not exceed the least common multiple of the number of RAMs and the stride width. In this embodiment, the stride width used is from 1 to 7. In this case, when the stride width is 1 to 4 and 6, the second condition is satisfied. When the stride width is 5 or 7, the first condition is satisfied.

  An address is assigned to the cache RAM 133 as shown in FIG. FIG. 3 is a diagram illustrating allocation of addresses to the cache RAM in the embodiment. Specifically, in the present embodiment, addresses are allocated so that addresses of continuous 128 bytes in one way do not correspond to the same RAM among the RAMs # 0 to # 15. In FIG. 3, w0, w1, w2, and w3 each represent a way.

  Further, the memories having the number of stride widths are assigned as one memory group, and the addresses of the respective ways w0 to w3 are assigned consecutively in each RAM of the memory group.

  Here, FIG. 3 describes how to assign 128 bytes of addresses for each way. Actually, however, the address assignment is repeated for all the storage areas of the RAMs # 0 to # 15 according to the assignment shown in FIG. It will be.

  For example, an 8-bit address from 00 to 07 in the way w0 is assigned to the RAM # 0. An 8-bit address from 08 to 0F in the way w0 is assigned to the RAM # 1. Also, 8-bit addresses from 10 to 17 in the way w0 are assigned to the RAM # 2. An 8-bit address from 18 to 1F in way w0 is assigned to RAM # 3. An 8-bit address from 20 to 27 in the way w0 is assigned to the RAM # 4. Also, 8-bit addresses 28 to 2F in the way w0 are assigned to the RAM # 5. Further, 8-bit addresses 30 to 37 in the way w0 are assigned to the RAM # 6. An 8-bit address from 38 to 3F in way w0 is assigned to RAM # 7. Such address assignment is repeated up to RAM # 15.

  Further, for example, an 8-bit address from 00 to 07 in the way w0 and an 8-bit address from 20 to 27 in the way w1 are allocated to the RAM # 0. Further, an 8-bit address from 40 to 47 in the way w2 and an 8-bit address from 60 to 67 in the way w3 are allocated to the RAM # 0.

  Returning to FIG. 2, the description will be continued. The request 200 output from the instruction control unit 11 includes an address, SIMD, and stride. Here, the address is information indicating an address to be subjected to load / store processing. The element number is information indicating the number of the request. The stride is information indicating a stride interval. Furthermore, the address represents the way with the upper 2 bits.

  The tag determination unit 131 acquires information on the address of the request 200. Then, the tag determination unit 131 determines whether or not the cache tag is hit in the cache set in the cache RAM 133 corresponding to the acquired address. If the cache tag does not hit, the tag determination unit 131 determines that there is a cache miss. On the other hand, when the cache tag is hit, the tag determination unit 131 outputs information on the hit way to the RAM address generation circuit 132.

  The RAM address generation circuit 132 acquires an address, an element number, and a stride from the request 200. Further, the RAM address generation circuit 132 receives input of way information from the tag determination unit 131.

  The RAM address generation circuit 132 acquires each address for stride access from the address, element number, stride and way information. In this case, the RAM address generation circuit 132 sets the address targeted for processing of the element E1 as the address stored in the request 200. Further, the RAM address generation circuit 132 sets the address targeted for the processing of the element E2 as the address obtained by adding the value obtained by multiplying the stride by 8 bytes to the address stored in the request 200. Further, the RAM address generation circuit 132 sets the address targeted for the processing of the element E3 as an address obtained by adding a value obtained by multiplying the value obtained by multiplying the stride by 8 bytes to 2 to the address stored in the request 200.

  Here, the cache RAM 133 has 16 RAMs, RAM # 0 to # 15. When the stride width and the number of RAMs are prime, the same RAM is not accessed multiple times in one process. Further, when the value obtained by multiplying the stride width by the number of elements does not exceed the number of RAMs and the least common multiple of the stride widths, the same RAM is not accessed multiple times in one process. Hereinafter, the occurrence of multiple accesses to the same RAM in one process is referred to as “address interference”.

  FIG. 4 is a diagram for explaining that no address interference occurs. Graphs 201 to 204 in FIG. 4 indicate the positions of addresses used for processing when the stride width is changed. The RAMs # 0 to # 15 are represented at respective positions obtained by dividing the circle into 16 parts. Further, the numbers written in the positions indicating the RAMs # 0 to 15 indicate that the addresses used in the elements E1 to E4 respectively exist on the corresponding RAM. Here, the address of the element E1 is shown when it exists on the RAM # 0.

  As shown in FIG. 4, as shown in graphs 201 to 207, it can be seen that the addresses corresponding to the elements E <b> 1 to E <b> 4 do not interfere even when the stride width is 1 to 7. That is, it can be seen that the addresses corresponding to the elements E1 to E4 generated by the cache RAM 133 according to the present embodiment do not interfere with each other.

  Further, returning to FIG. The RAM address generation circuit 132 acquires the values of the fifth bit and the sixth bit from the top of the request. Then, the RAM address generation circuit 132 specifies the RAM having the address from the RAMs # 0 to # 15 from the acquired value and the way number.

  For example, the following addresses are assigned to RAM # 0. In the following, the range from x bits to y bits counted from the top of the request is indicated by [y: x]. In addition, the value of each bit in a certain range is expressed as “001” as a numerical sequence in brackets. In RAM # 0, the address [6: 3] of the element n (n = E1, E2, E3, E4) is “0000” and the address of the way w0 is assigned. Further, the address of the element n is [0: 3] “0100” and the address of the way w1 is assigned to the RAM # 0. In addition, the address [6: 3] of the element n is “1000” and the address of the way w2 is assigned to the RAM # 0. Further, the address of the element n is [1: 3] “1100” and the address of the way w3 is assigned to the RAM # 0. The value of [6: 3] of the address of the element n has 16 combinations, and the value of [6: 3] of the address of the element n for each way corresponds to each of the RAMs # 0 to # 15. Assigned so that they do not overlap.

  Therefore, the RAM address generation circuit 132 can specify the RAM to be used from the [6: 3] value of the address of the element n and the way number.

  Here, with reference to FIG. 5, the address generation at the time of reading by the RAM address generation circuit 132 will be described in detail. FIG. 5 is a block diagram of the read function of the RAM address generation circuit.

  The RAM address generation circuit 132 includes adders 301 to 303 and selectors 311 to 314. However, in FIG. 5, only four selectors are shown, but actually, the RAM address generation circuit 132 has as many selectors as RAMs # 0 to # 15.

  The adders 301 to 303 receive an input of an address corresponding to [13: 3] of the request of the element E1. Further, the adders 301 to 303 receive an input of a stride width corresponding to [2: 0] of the request of the element E1. Here, the stride width is indicated to be any one of 1 to 7 using 3 bits [2: 0] of the request of the element w1.

  The adder 301 adds a value obtained by multiplying the input stride width by 8 to [13: 3] of the request of the element E1. This addition result corresponds to the address represented by [13: 3] of the element E2. Then, the adder 301 outputs the addition result to the selectors 311 to 314.

  The adder 302 adds the value obtained by multiplying the input stride width by 16 to [13: 3] of the request of the element E1. This addition result corresponds to the address represented by [13: 3] of the element E3. Adder 302 then outputs the addition result to selectors 311 to 314.

  The adder 303 adds a value obtained by multiplying the input stride width by 32 to [13: 3] of the request of the element E1. This addition result corresponds to the address represented by [13: 3] of the element E4. Then, the adder 303 outputs the addition result to the selectors 311 to 314.

  Specifically, the adders 301 to 303 add the values shown in FIG. 6 to each element in accordance with the stride width. FIG. 6 is a diagram showing the addition amount by the adder for each element.

  The selector 311 is a selector that determines selection of the RAM # 0. The selector 312 is a selector that determines selection of the RAM # 1. The selector 313 is a selector that determines selection of the RAM # 2. The selector 314 is a selector that determines selection of the RAM # 15.

  The selectors 311 to 314 receive an input of an address corresponding to [13: 3] of the request of the element E1. Further, the selectors 311 to 314 receive the addresses of the elements E2 to E4 from the adders 301 to 303.

  Here, the operation of the selector will be described using the selector 311 as an example. FIG. 7 is a circuit diagram showing details of the selector corresponding to reading. The selector 311 includes RAM # 0 read selection condition circuits 321 to 324, AND circuits 331 to 334, and an OR circuit 340.

  The RAM # 0 read selection condition circuits 321 to 324 receive input of addresses corresponding to [13: 3] of the elements E1 to E4, respectively. The RAM # 0 read selection condition circuits 321 to 324 receive the way ID input.

  The RAM # 0 read selection condition circuits 321 to 324 have the circuit configuration shown in FIG. That is, the RAM # 0 read selection condition circuits 321 to 324 include AND circuits 351 to 354 and an OR circuit 355. FIG. 8 is a circuit diagram of the RAM # 0 read selection condition circuit.

  The AND circuit 351 receives a value obtained by inverting the value of each bit of [6: 3] in the input address. Further, the AND circuit 351 receives an input of a value obtained by inverting each bit of [1: 0] representing the way ID. The AND circuit 351 calculates a logical product of the input values and outputs the result to the OR circuit 355.

  The AND circuit 352 receives an input of a value obtained by inverting the third and fourth bits of the [6: 3] bits in the input address. Further, the AND circuit 352 receives an input of a value obtained by inverting the first bit of each bit of [1: 0] representing the way ID. Then, the AND circuit 352 calculates the logical product of the input values and outputs the result to the OR circuit 355.

  The AND circuit 353 receives an input of a value obtained by inverting the third, fourth, and fifth bits of the [6: 3] bits in the input address. Further, the AND circuit 353 receives an input of a value obtained by inverting the 0th bit of [1: 0] representing the way ID. Then, the AND circuit 353 calculates the logical product of the input values and outputs the result to the OR circuit 355.

  The AND circuit 354 receives an input of a value obtained by inverting the third, fourth, and sixth bits of the [6: 3] bits in the input address. Further, the AND circuit 354 receives an input of each bit value [1: 0] representing the way ID. Then, the AND circuit 354 calculates the logical product of the input values and outputs the result to the OR circuit 355.

  The OR circuit 355 calculates the logical sum of the values input from the AND circuits 351 to 354 and outputs the result.

  Here, RAM # 0 to # 15 correspond to the combination of [1: 0] representing the way ID and [6: 3] in the address as in the RAM used in FIG. FIG. 9 is a diagram showing a RAM selection truth table at the time of reading by way and address. That is, the RAM # 0 read selection condition circuits 321 to 324 output 1 when a combination of way ID and address corresponding to RAM # 0 is input in the RAM selection truth table at the time of reading. . The same applies to the other RAMs # 1 to # 15.

  For example, selection of RAM # 0 will be described. When the case where RAM # 0 is selected at the time of reading is extracted from FIG. 9, FIG. 10 is completed. FIG. 10 is a diagram illustrating conditions under which RAM # 0 is selected during reading. Here, the operation of the AND circuits 353 to 354 is confirmed in each case shown in FIG. When [1: 0] representing the way ID is “00” and [6: 3] in the address is “0000”, the AND circuit 351 outputs “1”. When [1: 0] representing the way ID is “01” and [6: 3] in the address is “1100”, 1 is output from the AND circuit 352. When [1: 0] representing the way ID is “10” and [6: 3] in the address is “1000”, 1 is output from the AND circuit 353. When [1: 0] representing the way ID is “11” and [6: 3] in the address is “0100”, 1 is output from the AND circuit 354. That is, if any combination of the inputs in FIG. 10 is input to the RAM # 0 read selection condition circuits 321 to 324, the RAM # 0 read selection condition circuits 321 to 324 that have received the inputs output 1. That is, when the selection condition for RAM # 0 is satisfied, the selection condition circuits 321 to 324 for reading RAM # 0 output 1, and when the selection condition for RAM # 0 is not satisfied, the selection condition circuit 321 for reading RAM # 0. 324 outputs 0.

  Returning to FIG. 7, the description will be continued. AND circuits 331 to 334 receive outputs from RAM # 0 read selection condition circuits 321 to 324. Each of the AND circuits 331 to 334 receives an input of an address represented by [13: 5] of the elements E1 to E4. Then, each of the AND circuits 331 to 344 calculates a logical product of the input values and outputs the logical product to the OR circuit 340. More specifically, among the AND circuits 331 to 344, the address received by the circuit receiving 1 input from the RAM # 0 read selection condition circuits 321 to 324 is output, and all the circuits receiving 0 input are 0. The value of is output.

  The OR circuit 340 calculates the logical sum of the values input from the AND circuits 331 to 334 and outputs the result. That is, when 1 is output from any of RAM # 0 read selection condition circuits 321 to 324, OR circuit 340 outputs any of elements E1 to E4 corresponding thereto as a read address of RAM # 0. To do.

  Returning to FIG. The selector 311 outputs an address that is an output from the OR circuit 340 to the hit determination unit 134. Similarly, the selector 312 outputs the address to the hit determination unit 134 when the combination of each bit of [1: 0] representing the way ID and [6: 3] in the address matches the selection condition of the RAM # 1. To do. The selector 313 outputs the address to the hit determination unit 134 when the combination of each bit of [1: 0] representing the way ID and [6: 3] in the address matches the selection condition of the RAM # 2. The selector 314 outputs the address to the hit determination unit 134 when the combination of each bit of [1: 0] representing the way ID and [6: 3] in the address matches the selection condition of the RAM # 15.

  The hit determination unit 134 uses the addresses input from the selectors 311 to 314 to determine cache hits in the corresponding RAMs # 0 to # 15.

  Next, referring to FIG. 11, address generation at the time of writing by the RAM address generation circuit 132 will be described in detail. FIG. 11 is a block diagram of the write function of the RAM address generation circuit.

  The RAM address generation circuit 132 includes selectors 361 to 364 for writing. The selectors 361 to 364 correspond to the RAMs # 0 to # 15, respectively.

  The selectors 361 to 364 receive an input of an address corresponding to [13: 5] of the request. Further, the selectors 361 to 364 receive the input of the way ID corresponding to [1: 0] of the request.

  The combination of [1: 0] representing the way ID and [6: 5] in the address corresponds to the RAMs # 0 to # 15 represented as the used RAMs in FIG. FIG. 12 is a diagram showing a RAM selection truth table at the time of writing by way and address.

  The selectors 361 to 364 select the corresponding RAM to be used in FIG. 12 as the RAM to be used for writing according to the combination of [1: 0] representing the way ID and [6: 5] in the address. Then, the selectors 361 to 364 output the selected RAM address to the hit determination unit 134.

  Here, with reference to FIG. 13, the selectors 361 to 364 will be described in detail by taking the selector 361 as an example. FIG. 13 is a circuit diagram showing details of a selector corresponding to writing. The selector 361 includes a RAM # 0 write selection condition circuit 371 and an AND circuit 372.

  For example, when the element E1 is processed, the RAM # 0 write selection condition circuit 371 receives a bit input corresponding to [6: 5] in the address represented by [13: 5] of the element E1. Further, the RAM # 0 write selection condition circuit 371 receives [1: 0] representing the way ID.

  Then, the RAM # 0 write selection condition circuit 371, when the RAM used in FIG. 12 corresponding to the combination of [1: 0] representing the way ID and [6: 5] in the address matches the RAM # 0. 1 representing the selection of the RAM # 0 is output to the AND circuit 372. On the other hand, if the RAM used in FIG. 12 corresponding to the combination of [1: 0] representing the way ID and [6: 5] in the address does not match RAM # 0, the selection condition for writing RAM # 0 The circuit 371 outputs 0 to the AND circuit 372.

  Further, the configuration of the RAM # 0 write selection condition circuit 371 will be specifically described. FIG. 14 is a circuit diagram of the RAM # 0 write selection condition circuit. The RAM # 0 write selection condition circuit 371 includes AND circuits 381 to 384 and an OR circuit 385.

  The AND circuit 381 receives a value obtained by inverting each bit of [6: 5] in the address. The AND circuit 381 receives an input of a value obtained by inverting each bit of [1: 0] representing the way ID. Then, the AND circuit 381 obtains a logical product of the input values and outputs the result to the OR circuit 385.

  The AND circuit 382 receives the value of each [6: 5] bit in the input address. Further, the AND circuit 382 receives an input of a value obtained by inverting the first bit of each bit of [1: 0] representing the way ID. Then, the AND circuit 382 calculates the logical product of the input values and outputs the result to the OR circuit 385.

  The AND circuit 383 receives an input of a value obtained by inverting the fifth bit among the [6: 5] bits in the input address. Further, the AND circuit 383 receives an input of a value obtained by inverting the 0th bit of [1: 0] representing the way ID. Then, the AND circuit 383 obtains a logical product of the input values and outputs the result to the OR circuit 385.

  The AND circuit 384 receives an input of a value obtained by inverting the sixth bit among the [6: 5] bits in the input address. Furthermore, the AND circuit 384 receives the value of each bit of [1: 0] representing the way ID. Then, the AND circuit 384 calculates a logical product of the input values and outputs the result to the OR circuit 385.

  The OR circuit 385 calculates the logical sum of the values input from the AND circuits 381 to 384 and outputs the result.

  For example, selection of RAM # 0 will be described. FIG. 15 shows a case where RAM # 0 is selected at the time of writing from FIG. FIG. 15 is a diagram showing conditions for selecting RAM # 0 during writing. Here, the operation of the AND circuits 383 to 384 is confirmed in each case shown in FIG. When [1: 0] representing the way ID is “00” and [6: 5] in the address is “00”, the AND circuit 381 outputs 1. When [1: 0] representing the way ID is “01” and [6: 5] in the address is “11”, 1 is output from the AND circuit 382. When [1: 0] representing the way ID is “10” and [6: 5] in the address is “10”, 1 is output from the AND circuit 383. When [1: 0] representing the way ID is “11” and [6: 5] in the address is “01”, 1 is output from the AND circuit 384. That is, if any combination of the inputs in FIG. 15 is input to the RAM # 0 write selection condition circuit 371, the RAM # 0 write selection condition circuit 371 that receives the input outputs 1. That is, when the selection condition of RAM # 0 is satisfied, the selection condition circuit 371 for writing the RAM # 0 outputs 1, and when the selection condition of the RAM # 0 is not satisfied, the selection condition circuit 371 for writing the RAM # 0 is 0 is output.

  Returning to FIG. AND circuit 372 receives an input of a value representing the selection result of RAM # 0 from RAM # 0 write selection condition circuit 371. The AND circuit 372 receives an input of an address represented by [13: 5] of the element E1.

  When the input value from the RAM # 0 write selection condition circuit 371 is 1, the AND circuit 372 outputs the address represented by [13: 5] of the element E1. On the other hand, when the input value from the RAM # 0 write selection condition circuit 371 is 0, the AND circuit 372 outputs 0.

  Returning to FIG. 11, the description will be continued. The selector 361 outputs the output from the AND circuit 372 to the hit determination unit 134. Similarly, the selectors 362 to 364 output addresses to the hit determination unit 134 when the corresponding RAMs # 1 to # 15 are selected as the write destination RAMs.

  The hit determination unit 134 uses the addresses input from the selectors 361 to 364 to determine cache hits in the corresponding RAMs # 0 to # 15.

  Further, returning to FIG. The hit determination unit 134 receives input of information and an address of a RAM to be subjected to load / store processing from the RAM address generation circuit 132. The hit determination unit 134 determines a cache hit for the designated RAM using the input address. When a cache hit occurs, the hit determination unit 134 acquires the data hit by the cache and outputs it to the arithmetic control unit 12. When a cache miss occurs, the hit determination unit 134 transmits a data transfer request to the memory access control unit 135.

  When a cache miss occurs, the memory access control unit 135 receives a data transfer request from the hit determination circuit 134. Then, the memory access control unit 135 transmits to the secondary cache control unit 14 a data transfer request for a request for which a hit determination has been made at the transmission source of the data transfer request.

  Thereafter, the memory access control unit 135 receives response data for the data transfer request from the secondary cache control unit 14. Then, the memory access control unit 135 stores the received response data in the cache RAM 133. Thereafter, the memory access control unit 135 notifies the transmission source of the data transfer request in the hit determination unit 134 to store the response data.

  Returning to FIG. 1, the description will be continued. The secondary cache control unit 14 has a secondary cache. The secondary cache control unit 14 receives a data transfer request from the memory access control unit 138. Then, the secondary cache control unit 14 determines whether the data designated by the data transfer request is stored in the secondary cache that the secondary cache control unit 14 has. If stored, the secondary cache control unit 14 acquires the data specified by the data transfer request from the secondary cache, and transmits the acquired data to the memory access control unit 135 as response data.

  On the other hand, when the data specified by the data transfer request is not stored in the secondary cache, the secondary cache control unit 14 transmits the data transfer request to the memory control unit 15. Thereafter, the secondary cache control unit 14 receives the response data from the memory control unit 15. Then, the secondary cache control unit 14 transmits the received response data to the memory access control unit 135.

  The arithmetic control unit 12 receives an execution request for arithmetic processing from the instruction control unit 11. The arithmetic processing 12 receives data from the cache control unit 13. Then, the arithmetic control unit 12 executes arithmetic processing using the data received from the cache control unit 13. However, when the cache data is not used for the process to be executed, the arithmetic control unit 12 may execute the process without receiving data from the cache control unit 13.

  Next, with reference to FIG. 16, the flow of load / store processing by the arithmetic processing unit according to the present embodiment will be described. FIG. 16 is a flowchart of the load / store process performed by the arithmetic processing apparatus according to the embodiment.

  The instruction control unit 11 acquires a request from the instruction and issues the acquired request to the cache control unit 13 (step S1).

  The tag determination unit 131 of the cache control unit 13 acquires a tag from the acquired request, and determines whether or not the acquired tag is hit in the cache RAM 133 (step S2). If the tag does not hit (No at Step S2), the cache control unit 13 proceeds to Step S8.

  On the other hand, when the tag hits (step S2: affirmative), the RAM address generation circuit 132 determines whether or not it is a read process (step S3).

  In the case of the reading process (step S3: Yes), the RAM address generation circuit 132 generates the addresses of the elements E2 to E4 from the address of the element E1 (step S4).

  Then, the RAM address generation circuit 132 selects a RAM as a read source in accordance with the stride width from each of the RAMs # 0 to 15 of the cache RAM 133 in which consecutive addresses of the respective ways w0 to w3 are allocated over all memories. Select (step S5).

  On the other hand, when the write process is not the read process (No at Step S3), the RAM address generation circuit 132 performs the following process. That is, the RAM address generation circuit 132 selects a RAM to be written to in accordance with the stride width from the RAMs # 0 to 15 of the cache RAM 133 in which consecutive addresses of the ways w0 to w3 are allocated over all memories. Select (step S6).

  Next, the RAM address generation circuit 132 outputs the selected RAM and the address on the RAM to the hit determination unit 134. The hit determination unit 134 determines whether or not a cache hit occurs at a specified address on the RAM selected by the RAM address generation circuit 132 (step S7). In the case of a cache miss (No at Step S7), the memory access control unit 135 transmits a data transfer request to the secondary cache control unit 14. Thereafter, the secondary cache control unit 14 transfers the response data to the data transfer request to the cache RAM 133 (step S8). Thereafter, the cache control unit 13 returns to step S2.

  On the other hand, in the case of a cache hit (step S7: affirmative), the hit determination unit 134 executes a load / store process for the cache hit address (step S9).

  As described above, in the cache RAM in the arithmetic processing unit according to the present embodiment, the stride width and the number of RAMs are relatively prime or the multiplication result of the stride width and the number of elements is the minimum of the number of RAMs and the stride width. It becomes smaller than the common multiple. Further, consecutive addresses for each way are assigned so as to be arranged over all the RAMs. As a result, even when stride access is performed with one instruction, multiple accesses to the same memory can be avoided and throughput can be improved.

1 CPU
2 memory 11 instruction control unit 12 arithmetic control unit 13 cache control unit 14 secondary cache control unit 15 memory control unit 131 tag determination unit 132 RAM address generation circuit 133 cache RAM
134 Hit Determination Unit 135 Memory Access Control Unit 301 to 302 Adder 311 to 314 Selector 321 to 324 RAM # 0 Read Selection Condition Circuit 331 to 334 AND Circuit 340 OR Circuit 351 to 354 AND Circuit 355 OR Circuit 361 to 364 Selector 371 RAM # 0 write selection condition circuit 372 AND circuit 381-384 AND circuit 385 OR circuit

Claims (5)

A cache memory having a plurality of storage elements for each way, and assigned consecutive addresses to the plurality of storage elements belonging to each way;
An instruction control unit that acquires an arithmetic processing instruction including a plurality of cache access requests that respectively instruct processing on data at a predetermined address interval included in the same way, and transmits the acquired plurality of cache access requests;
Cache control that receives each of the plurality of cache access requests transmitted from the command control unit and executes a plurality of access processes for the data of the predetermined address interval included in the way specified by each cache access request And
An arithmetic processing unit comprising: an arithmetic control unit that performs arithmetic processing based on a processing result of the access processing by the cache control unit.   The predetermined address interval is relatively prime to the number of storage elements, or the multiplication result of the predetermined address interval and the cache access request included in the arithmetic processing instruction is the number of storage elements and the predetermined number The arithmetic processing unit according to claim 1, wherein the arithmetic processing unit is smaller than a least common multiple of the address interval.   In the cache memory, the storage elements of the number of all cache access requests included in the arithmetic processing instruction are grouped, and the addresses assigned to the ways on each group are assigned so as to be serial numbers. The arithmetic processing apparatus according to claim 1 or 2, characterized in that   4. The arithmetic processing apparatus according to claim 3, wherein in the cache memory, addresses of the ways are serial numbers for each group. A method for controlling an arithmetic processing unit having a plurality of storage elements for each way and having a cache memory in which consecutive addresses are assigned to the plurality of storage elements belonging to each way,
Obtaining an arithmetic processing instruction including a plurality of cache access requests each instructing processing for data of a predetermined address interval included in the same way;
Executing a plurality of access processes on the data of the predetermined address interval included in the way designated by each acquired cache access request;
An arithmetic processing unit that performs arithmetic processing based on the processing result of the access processing.

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