JP2015210655A - Arithmetic processing unit and control method of arithmetic processing unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an arithmetic processing unit and a control method of the arithmetic processing unit with an improved arithmetic processing capability.SOLUTION: An instruction control section 11 acquires an arithmetic processing instruction including plural cache access requests and sequentially transmits the cache access requests included in the arithmetic processing instruction. A cache control section 13 receives the cache access requests transmitted from the instruction control section 11 and sequentially executes access processing to the caches instructed by the cache access requests. An arithmetic control section 12 controls to execute the arithmetic processing based on the result of access processing by the cache control section 13.

Description

  The present invention relates to an arithmetic processing device and a control method for the arithmetic processing device.

  In recent years, in order to improve calculation performance, an arithmetic processing apparatus sometimes performs processing called SIMD (Single Instruction Multiple Data). SIMD is a method for processing operations on a plurality of pieces of data in a single instruction. Also, in order to improve the performance of arithmetic processing using SIMD, it is preferable that the load / store processing is also expanded according to SIMD.

  For a cache access request by a general load / store instruction, one address is designated per request. The cache control unit provided in the arithmetic processing unit performs load / store processing on the data at the address specified by the cache access request.

  On the other hand, in a cache access request by a load / store instruction expanded by SIMD, one address and the number of elements indicating the number of data to be operated are designated for each request. Then, the cache control unit collectively performs load / store processing on the continuous data for the number of elements from the designated address.

  Whether a general load / store instruction or a SIMD-extended load / store instruction, one request is assigned to one control port provided in the cache control unit, its instruction type, address, and number of SIMD elements. For example, processing was performed while holding various control signals.

  The cache access request is accompanied by IID (Instruction Identification) that is information indicating the order of instructions on the program. The cache control unit may have a plurality of cache control pipelines that are paths for determining a cache hit. In an arithmetic processing unit having a plurality of cache control pipelines, a plurality of cache access requests may simultaneously flow through different cache control pipelines. In this case, the cache control unit determines the order relation of these requests by determining the size of the IID attached to each cache access request. For example, when acquiring a single resource shared between different cache control pipelines, the cache control unit performs processing such as giving an acquisition priority to an older request using the determination result of the request order.

  Furthermore, in order to improve the performance of arithmetic processing by SIMD, correspondence to indirect load / indirect store processing can be mentioned. In load / store processing using conventional SIMD, data to be processed is continuously arranged on a memory. On the other hand, indirect load / indirect store processing is a technique that enables load / store processing to be performed collectively even when data is discontinuously arranged.

  For example, there is a conventional technique for issuing a load / store instruction for each element by the number of elements. Further, for example, there is a conventional technique in which a new indirect load / indirect store instruction is newly defined and a plurality of cache access requests are simultaneously transmitted in parallel with a plurality of element addresses by one instruction.

JP 2009-163442 A Japanese Patent Publication No. 04-79026

  However, in the conventional technology that issues the load / store instructions for the number of elements, the load / store instructions to be used increase as the number of elements increases, which occupies each resource of the arithmetic processing unit, which may hinder performance improvement. There is.

  In addition, in the conventional technology that simultaneously transmits a plurality of cache access requests in parallel, it is necessary to provide the width of the address bus and data bus for transmitting requests to the control port by the number of elements. Will increase. For this reason, the number of elements that can be processed simultaneously is limited by the amount of circuit that can be used by the arithmetic processing unit, which may hinder performance improvement.

  The disclosed technology has been made in view of the above, and an object thereof is to provide an arithmetic processing device and an arithmetic processing device control method with improved arithmetic processing capability.

  An arithmetic processing device and a control method for the arithmetic processing device disclosed in the present application include: an instruction control unit that acquires an arithmetic processing instruction including a plurality of cache access requests and sequentially transmits the cache access requests included in the arithmetic processing instruction; A cache control unit that receives the cache access request transmitted from the instruction control unit and sequentially executes an access process to the cache instructed by each cache access request; and a processing result of the access process by the cache control unit And an arithmetic control unit that performs arithmetic processing based on the above.

  According to one aspect of the arithmetic processing device and the control method for the arithmetic processing device disclosed in the present application, there is an effect that the arithmetic processing capability can be improved.

FIG. 1 is a block diagram of an arithmetic processing unit. FIG. 2 is a block diagram showing details of the cache control unit. FIG. 3 is a diagram illustrating an example of a format of a request sent from the instruction control unit. FIG. 4 is a diagram illustrating an example of entries included in the control port. FIG. 5 is a diagram for explaining arbitration processing between requests. FIG. 6 is a time chart of arbitration of a data transfer request between pipelines. FIG. 7 is a flowchart of command processing performed by the arithmetic processing apparatus according to the first embodiment. FIG. 8 is a flowchart of the comparison process by the magnitude comparator. FIG. 9 is a flowchart of a data transfer arbitration process between pipelines. FIG. 10 is a flowchart of command processing performed by the arithmetic processing apparatus according to the second embodiment.

  Embodiments of an arithmetic processing device and a control method for the arithmetic processing device disclosed in the present application will be described below in detail with reference to the drawings. The following embodiments do not limit the arithmetic processing device and the control method of the arithmetic processing device disclosed in the present application.

  FIG. 1 is a block diagram of an arithmetic processing unit. FIG. 2 is a block diagram showing details of the cache control unit. In this embodiment, a CPU (Central Processing Unit) will be described as an example of the arithmetic processing device.

  The CPU 1 includes an instruction control unit 11, an operation control unit 12, a cache control unit 13, a secondary cache control unit 14, and a memory control unit 15. The memory control unit 15 is connected to the memory 2.

  The instruction control unit 11 acquires an instruction from a program. Then, the instruction control unit 11 determines whether or not the acquired instruction is a cache access request. The cache access request is, for example, a load / store request for requesting reading of data from the memory to the arithmetic control unit 12 via the cache or an update of data from the arithmetic control unit 12 via the cache. Here, the instruction according to the present embodiment is defined so as to include a plurality of cache access requests.

  If it is a cache access request, the instruction control unit 11 transmits the cache access request to the cache control unit 13. Hereinafter, the cache access request is simply referred to as “request”.

  Here, the instruction control unit 11 can issue requests to two pipelines 132 and 133 included in the cache control unit 13 described later. For example, when four requests are included in one instruction, the instruction control unit 11 sends each of the two requests to the pipelines 132 and 133, and then transmits each of the remaining two requests. It sends out toward each pipeline 132 and 133.

  As described above, the instruction control unit 11 according to the present embodiment sequentially sends requests based on one indirect instruction to the cache control unit 13. That is, since the instruction control unit 11 in this embodiment can process a plurality of requests with one indirect instruction, an increase in the number of instructions due to indirect load / indirect store processing can be suppressed, and performance degradation can be avoided. it can. In addition, the bus between the instruction control unit 11 and the cache control unit 13 in this embodiment has the same number of buses and the same width as those used in conventional SIMD processing, and can suppress an increase in circuit amount.

  Thereafter, the instruction control unit 11 receives a request completion response notification from the cache control unit 13. Then, upon receiving the request completion response notification, the instruction control unit 11 determines completion of the cache access request.

  In addition, the instruction control unit 11 sends an execution request for an operation instruction to the operation control unit 12.

  Next, the cache control unit 13 will be described with reference to FIG. The cache control unit 13 includes a control port management unit 131, pipelines 132 and 133, a cache RAM (Random Access Memory) 134, hit determination circuits 135 and 136, a size comparator 137, and a memory access control unit 138.

  The control port management unit 131 has a plurality of control ports 30. Each control port 30 is connected to the cache RAM 134 via a pipeline 132 and a path 133, respectively. Hereinafter, when the pipelines 132 and 133 are not distinguished from each other, they are referred to as “pipeline 130”. Here, in this embodiment, there are two pipelines 130, but this may be one. Further, if possible, the CPU 1 may include three or more pipelines 130.

  The control port 30 receives a request sent from the instruction control unit 11. Then, the control port 30 inputs a request to the pipeline 130 designated by the instruction control unit 11. Here, when another request has already been input to the input pipeline 130 and the processing has not been completed, the control port 30 is in a state where the input pipeline 130 has completed processing and the request can be input. Keep the request until For example, the control port 30 accumulates requests using a queue or the like.

  Here, the format of the request received by the control port 30 will be described with reference to FIG. FIG. 3 is a diagram illustrating an example of a format of a request sent from the instruction control unit. As shown in FIG. 3, the request 200 includes items of request, address, IID, SIMD, indirect, and element. request represents the type of access such as load or store. address represents the address of the access destination. The IID is an identifier of an instruction including the request. In this embodiment, the IID is assigned to the instructions in ascending order by serial number, and indicates the order of the instructions. SIMD represents the number of elements of SIMD. Indirect is a flag indicating whether or not indirect access is performed. In the present embodiment, when indirect is “0”, it indicates that the indirect load process or the indirect store process is not performed. Further, when “indirect” is “1”, this indicates that the request is a target of indirect load processing or indirect store processing. element represents the SIMD element number of the request. In this embodiment, the element numbers are assigned sequentially in ascending order.

  Further, as shown in FIG. 4, the control port 30 stores an entry including a status flag indicating a current state of cache access such as load or store indicated by the request in association with each request. FIG. 4 is a diagram illustrating an example of entries included in the control port. In the request column of FIG. 4, a request having the format shown in FIG. 3 is stored. A status flag is set in the status column. If the status flag is “1”, this indicates that the request has been received and has not been processed. If the status flag is “2”, it indicates that the processing of the request has been completed. If the status flag is “0”, it indicates that a request completion response notification regarding the request has already been sent to the command control unit 11 and the entry of the request has been released.

  That is, when processing a request with DIRECT = 0, when the request is received from the instruction control unit 131, the control port 30 sets an entry with a status flag having a value of “1” corresponding to the received request to 1 Create one.

  Next, when the control port 30 inputs a request to the pipeline 130 and receives a notification of processing completion from the hit determination circuit 135 or 136, the control port 30 changes the status flag of the entry corresponding to the request to “2”. On the other hand, when a request for re-input is received from the hit determination circuit 135 or 136 after the request is input to the pipeline 130, the control port 30 re-inputs the request to the pipeline 130 and the status flag is “1”. ”.

  Thereafter, when a request completion response is transmitted from the control port management unit 131 to the command control unit 11, the control port 30 releases the entry of the request corresponding to the request completion response and changes the status to “0”.

  When processing a request with DIRECT = 1, the instruction control unit 131 issues requests for the number of SIMD values to the cache control unit 13 with the same IID, and the control port 30 corresponds to the received request. As many entries as the number of SIMD values are created with the status flag set to "1". The control port management unit 131 monitors each request entry in each control port 30. When the status flag of any entry becomes 2, the control port management unit 131 acquires the IID of the request stored in the entry. Next, the control port management unit 131 acquires the number of elements of the instruction having the acquired IID. Thereafter, the control port management unit 131 extracts a request having the same IID from an entry included in each control port 30. Then, the control port management unit 131 checks the status flag of each extracted entry.

  When all the status flags of the extracted entries are “2”, the control port management unit 131 transmits a request completion response to the instruction control unit 11. On the other hand, when an entry with a status flag “1” is included in each extracted entry, the control port management unit 131 waits until the status flag is changed to “2” next time.

  Here, in this embodiment, the control port management unit 131 transmits a request completion response if the status flags of the entries with the same IID are all “2”, but the number of requests included in each command, that is, the number of elements You may confirm using. For example, it can be realized by the following processing. When the request is indirect access, the control port management unit 131 receives the request and receives the number of elements of the instruction including the request from the instruction control unit 11. The control port 131 stores the number of elements corresponding to the IID. Thereafter, when the control port 131 extracts the entries having the same IID, the control port 131 acquires the number of elements corresponding to the IID, and determines whether or not the number of extracted entries matches the acquired number of elements. Good.

  Then, after transmitting the request completion response, the control port management unit 131 instructs each control port 30 to change the status flag of each entry extracted for determination of the status flag to “0”.

  Pipelines 132 and 133 receive requests from the control port 30. Then, the pipelines 132 and 133 send a request to the cache RAM 134. The pipeline 132 also sends the request to the hit determination circuit 135. In addition, the pipeline 133 sends the request to the hit determination circuit 136. Further, the pipelines 132 and 133 send the request to the magnitude comparator 137.

  When there is data at the address specified by the request received from the pipeline 132, the cache RAM 134 extracts the data from the specified address and outputs the data to the hit determination circuit 135. Further, the cache RAM 134 extracts data from the address specified by the request received from the pipeline 133 and outputs the data to the hit determination circuit 136.

  The hit determination circuit 135 receives a request input from the control port 30 from the pipeline 132. The hit determination circuit 135 acquires data from the cache RAM 134 when there is data at the address specified by the request. Furthermore, the hit determination circuit 135 receives the comparison result of the requests input to the pipelines 132 and 133 from the magnitude comparator 137.

  Next, the hit determination circuit 135 determines whether there is hit data in the data acquired from the cache RAM 134 using the tag of the request received from the pipeline 132.

  If there is hit data, the hit determination circuit 135 transmits the hit data to the arithmetic control unit 12. Hereinafter, the case where the hit determination circuit 135 or 136 determines that the data has hit is referred to as “cache hit”. In addition, the hit determination circuit 135 transmits a processing completion notification to the control port 30 that is the request source.

  On the other hand, when there is no data that hits the cache, that is, when data is not transmitted from the cache RAM 134 or when data is not hit by the determination using the tag, the hit determination circuit 135 performs the following processing.

  The hit determination circuit 135 refers to the comparison result input from the magnitude comparator 137. When the comparison result is a result representing execution of processing of the request input to the pipeline 132, the hit determination circuit 135 requests the memory access control unit 138 to transfer data corresponding to the request. Thereafter, the hit determination circuit 135 receives a notification of storing the response data in the cache RAM 134 from the memory access control unit 138. Then, the hit determination circuit 135 notifies the control port 30 of request re-input.

  On the other hand, when the comparison result is a result indicating execution of processing of a request input to the pipeline 133, the hit determination circuit 135 transmits a request re-input notification to the control port 30 that is a request transmission source.

  Since the hit determination circuit 136 performs the same operation as the hit determination circuit 135, the description thereof is omitted. However, in the hit determination circuit 136, the relationship between the pipeline 132 and the pipeline 133 is reversed.

  The large / small comparator 137 receives a request input from each of the pipelines 132 and 133. Then, the large / small comparator 137 acquires the element number of each received request. Next, the magnitude comparator 137 compares the obtained element numbers in magnitude. Then, the magnitude comparator 137 transmits a comparison result indicating execution of processing of the request having the larger element number to the hit determination circuits 135 and 136. For example, when the element number of the request input from the pipeline 132 is larger than the element number of the request input from the pipeline 133, the magnitude comparator 137 executes the processing of the request input from the pipeline 132. Output the comparison result.

  When a cache miss occurs, the memory access control unit 138 receives a data transfer request from the hit determination circuit 135 or 136. Then, the memory access control unit 138 transmits a data transfer request for the request for which the hit determination is performed at the transmission source of the data transfer request to the secondary cache control unit 14.

  Thereafter, the memory access control unit 138 receives response data for the data transfer request from the secondary cache control unit 14. Then, the memory access control unit 138 stores the received response data in the cache RAM 134. Thereafter, the memory access control unit 138 notifies the transmission source of the data transfer request in the hit determination circuits 135 and 136 to store the response data.

  Here, with reference to FIG. 5, arbitration processing between requests by the hit determination circuits 135 and 136 and the magnitude comparator 137 when none of the requests input from the pipelines 132 and 133 is hit. This will be specifically described. FIG. 5 is a diagram for explaining arbitration processing between requests. The hit determination circuits 135 and 136 shown in FIG. 5 are an example of details of the hit determination circuits 135 and 136. In this case, the hit determination circuit 135 includes a hit determination unit 351 and AND circuits 352 and 353. The hit determination circuit 136 includes a hit determination unit 361 and AND circuits 362 and 363. Further, the circle on the input side in the AND circuits 352 and 362 indicates inversion of the input. In the following description, description of processing that is not directly related to arbitration processing between requests such as transmission of a request to the cache RAM 134 is omitted.

  The instruction control unit 11 extracts the request A and the request B from the instruction XXX whose IID is “0”. Then, the instruction control unit 11 assigns “0” as the element number to the request A and assigns “1” as the element number to the request B. In FIG. 5, the number following “element #” represents an element number.

  The instruction control unit 11 sends the request A with the element number “0” to the control port 31. Further, the instruction control unit 11 sends the request B having the element number “1” to the control port 32. Here, the control ports 31 and 32 are any of the control ports 30 of FIG.

  The control port 31 transmits the request A to the hit determination unit 351 and the size comparator 137. In addition, the control port 32 transmits the request B to the hit determination unit 361 and the magnitude comparator 137.

  The hit determination unit 351 performs a hit determination for the request A. When the request is hit, the hit determination unit 351 outputs “0” to the AND circuits 352 and 353. If the request does not hit, the hit determination unit 351 outputs “1” to the AND circuits 352 and 353. Here, since the request A does not hit, the hit determination unit 351 outputs “1” to the AND circuits 352 and 353.

  The hit determination unit 361 performs hit determination for the request B. When the request is hit, the hit determination unit 361 outputs “0” to the AND circuits 362 and 363. If the request does not hit, the hit determination unit 361 outputs “1” to the AND circuits 362 and 363. Here, since the request B does not hit, the hit determination unit 361 outputs “0” to the AND circuits 362 and 363.

  The large / small comparator 137 receives requests A and B from the control ports 31 and 32. Then, the large / small comparator 137 acquires the element number “0” from the request A. The large / small comparator 137 acquires the element number “1” from the request B. Next, the size comparator 137 compares the element number “0” of the request A with the element number “1” of the request B. In this case, the size comparator 137 determines that the element number of the request A is smaller than the element number of the request B.

  The large / small comparator 137 sets the request with the smaller element number as the request for executing the data transfer request. Further, the magnitude comparator 137 outputs “0” to the hit determination circuits 135 and 136 that perform the hit determination of the request that does not execute the data transfer request, and outputs “1” to the other. Here, the magnitude comparator 137 outputs “1” to the AND circuits 352 and 353 as a determination result indicating execution of the data transfer request for the request A. Further, the magnitude comparator 137 outputs “0” to the AND circuits 362 and 363 as a determination result indicating execution of the data transfer request for the request A, that is, a determination result indicating that the request B does not execute the data transfer request. To do.

  The AND circuit 352 outputs a logical product of the input from the hit determination unit 351 and the value obtained by inverting the input from the magnitude comparator 137 to the control port 31. Here, the AND circuit 352 generates “0”, which is the logical product of “1” input from the hit determination unit 351 and “0”, which is a value obtained by inverting the input from the magnitude comparator 137. Output to. Here, the output of “0” to the control port 31 or 32 represents the continuation of request processing.

  The AND circuit 353 outputs the logical product of the input from the hit determination unit 351 and the input from the magnitude comparator 137 to the memory access control unit 138. Here, since “1” is input from both the hit determination unit 351 and the magnitude comparator 137, the AND circuit 352 outputs “1” to the memory access control unit 138.

  The AND circuit 362 outputs a logical product of the input from the hit determination unit 351 and the value obtained by inverting the input from the magnitude comparator 137 to the control port 32. Here, the AND circuit 362 generates “1” which is a logical product of “1” input from the hit determination unit 361 and “1” which is an inverted value of the input from the magnitude comparator 137, as the control port 31. Output to. An output of “1” to the control port 31 or 32 represents a request re-injection.

  The AND circuit 363 outputs the logical product of the input from the hit determination unit 361 and the input from the magnitude comparator 137 to the memory access control unit 138. Here, since “1” is input from the hit determination unit 351 and “0” is input from the magnitude comparator 137, the AND circuit 352 outputs “0” to the memory access control unit 138.

  When receiving “0” input from the AND circuit 352, the control port 31 confirms that the processing of the request A is continued. Further, upon receiving “1” input from the AND circuit 362, the control port 32 re-injects the request B into the pipeline 133.

  Here, the description is about the arbitration process when both of them make a cache miss, and it is the explanation until the control port 30 is notified of the arbitration results by the hit determination circuits 135 and 136. However, finally, the hit determination circuits 135 and 136 perform the following processing. That is, when the data designated by the request is registered in the cache while the request processing is continued, the hit determination circuits 135 and 136 instruct the control port 30 of the request transmission source to reinject the request. When the request has a cache hit, the hit determination circuits 135 and 136 notify the request transmission source control port 30 of the completion of the request processing.

  The memory access control unit 138 receives logical product inputs from the AND circuits 353 and 363. Then, the memory access control unit 138 outputs a data transfer request for the request on the side where the value “1” is input to the secondary cache control unit 14. Here, since the input of “1” is received from the AND circuit 353 and the input of “0” is received from the AND circuit 363, the memory access control unit 138 sends the data transfer request for the request A to the secondary cache control unit 14. Output.

  Next, with reference to FIG. 6, the timing of each process in the arbitration of the data transfer request between the pipelines 132 and 133 will be described. FIG. 6 is a time chart of arbitration of a data transfer request between pipelines.

  FIG. 6 describes the processing target at the left end. The bottom column represents a size comparison using both requests A and B. FIG. 6 shows that the time elapses from time T1 to time T9 as it moves to the left. Here, a case will be described in which hit determination processing is performed in three cycles P1 to P3 for the requests input to the pipelines 132 and 133.

  At time T1, request A is input to the pipeline 132, and request B is input to the pipeline 133.

  Then, the cache hit of request A and request B is determined in cycle P2 corresponding to time T3.

  Thereafter, the request A and the request B are determined to be large and small at time T5. Here, a case where it is determined that request A is smaller than request B will be described. Therefore, for request A, a memory request for data acquisition from the secondary cache or the memory 2 is performed by a data transfer request. Request B is re-entered into pipeline 133.

  Thereafter, the cache miss of the request B occurs again in the cycle P2 of the next timing at the time T7. Here, since there is no request other than the requests A and B, at time T9, a memory request for data acquisition from the secondary cache or the memory 2 is performed for the request B by a data transfer request.

  As described above, even when a cache miss conflicts between the pipelines 132 and 133, the data transfer request is sequentially executed from the request given the young number, so that the data transfer of all the requests is finally executed. The

  Returning to FIG. 1, the description will be continued. The secondary cache control unit 14 has a secondary cache. The secondary cache control unit 14 receives a data transfer request from the memory access control unit 138. Then, the secondary cache control unit 14 determines whether the data designated by the data transfer request is stored in the secondary cache that the secondary cache control unit 14 has. If stored, the secondary cache control unit 14 acquires the data specified by the data transfer request from the secondary cache, and transmits the acquired data to the memory access control unit 138 as response data.

  On the other hand, when the data specified by the data transfer request is not stored in the secondary cache, the secondary cache control unit 14 transmits the data transfer request to the memory control unit 15. Thereafter, the secondary cache control unit 14 receives the response data from the memory control unit 15. Then, the secondary cache control unit 14 transmits the received response data to the memory access control unit 138.

  The memory control unit 15 receives a data transfer request from the secondary cache control unit 14. Then, the memory control unit 15 acquires the data designated by the data transfer request from the memory 2. Then, the memory control unit 15 transmits the acquired data to the secondary cache control unit 14.

  The arithmetic control unit 12 receives an execution request for arithmetic processing from the instruction control unit 11. The arithmetic processing 12 receives data from the cache control unit 13. Then, the arithmetic control unit 12 executes arithmetic processing using the data received from the cache control unit 13. However, when the cache data is not used for the process to be executed, the arithmetic control unit 12 may execute the process without receiving data from the cache control unit 13.

  Next, with reference to FIG. 7, the flow of instruction processing by the arithmetic processing unit according to this embodiment will be described. FIG. 7 is a flowchart of command processing performed by the arithmetic processing apparatus according to the first embodiment. Hereinafter, the hit determination circuit 135 and the hit determination circuit 136 are referred to as “hit determination circuit 140” without being distinguished from each other.

  The command control unit 11 acquires a request from the command and issues the acquired request to the control port 30 (step S101).

  The control port 30 receives the request (step S102). Then, the control port 30 sets the status flag of the received request entry to “1” (status = 1) (step S103).

  Next, the control port 30 inputs the request to the pipeline 130 (step S104).

  The hit determination circuit 140 determines whether or not the request has a cache hit (step S105). If there is no cache hit (No at Step S105), the memory access control unit 138 transmits a data transfer request to the secondary cache control unit 14 (Step S106). Then, the memory access control unit 138 receives the response data from the secondary cache control unit 14, and registers the received response data in the cache RAM 134 (step S107). Thereafter, the hit determination circuit 140 notifies the control port 30 of the request re-injection. The control port 30 returns to step S104.

  On the other hand, when a cache hit occurs (step S105: Yes), the hit determination circuit 140 executes a load / store process (step S108).

  The hit determination circuit 140 notifies the control port 30 of the completion of the request processing. In response to the notification of the completion of the request processing, the control port 30 changes the status flag of the entry of the corresponding request to “2” (status = 2) (step S109).

  When the status flag is changed to “2”, the control port management unit 131 sets the flag indicating whether the request is not indirect access, that is, whether it is indirect access, to “0” (indirect = 0). Is determined (step S110). If the request is not indirect access (step S110: Yes), the control port management unit 131 proceeds to step S113.

  On the other hand, when the request is indirect access (No at Step S110), the control port management unit 131 acquires the IID of the instruction including the request. Next, the control port management unit 131 searches all entries (step S111). Then, the control port management unit 131 determines whether or not the status flags of all the entries of the requests included in the instruction having the same IID as the acquired IID are “2” (status = 2) (step S112).

  If an entry other than the status flag “2” is included (No at Step S112), the control port management unit 131 returns to Step S111. Here, since the processes of steps S101 to S109 are performed for other requests in parallel, the status flags of all entries are changed to “2” while steps S111 and S112 are repeated. On the other hand, if the status flags of all the entries are “2” (step S112: Yes), the control port management unit 131 proceeds to step S113.

  Then, the control port management unit 131 transmits a request completion response to the command control unit 11 (step S113).

  Then, the control port 30 changes the status flag of the entry of the request to which the request completion response is transmitted to “0” (status = 0) (step S114).

  Next, with reference to FIG. 8, the flow of comparison processing by the size comparator will be described. FIG. 8 is a flowchart of the comparison process by the magnitude comparator. Here, a case where request A is input to the pipeline 132 and request B is input to the pipeline 133 will be described. In FIG. 8, the request A is simply expressed as “A”, and the request B is simply expressed as “B”.

  The magnitude comparator 137 determines whether or not the IID of the instruction including the request A (hereinafter referred to as “A's IID”) is different from the IID of the instruction including the request B (hereinafter referred to as “B's IID”). Is determined (step S201).

  When the IIDs are different (step S201: Yes), the size comparator 137 determines whether the IID of the request A is smaller than the IID of the request B (step S202).

  When A's IID is smaller than B's IID (step S202: affirmative), the magnitude comparator 137 instructs the hit determination circuit 135 to make a request data transfer request (step S204). For example, in the case of the configuration as shown in FIG. 5, the magnitude comparator 137 outputs “1” to the AND circuits 352 and 353. In this case, the magnitude comparator 137 outputs “0” to the AND circuits 362 and 363.

  On the other hand, when the IID of B is smaller than the IID of A (No at Step S202), the magnitude comparator 137 instructs the hit determination circuit 136 to make a request data transfer request (Step S205). For example, in the case of the configuration shown in FIG. 5, the magnitude comparator 137 outputs “1” to the AND circuits 362 and 363. In this case, the magnitude comparator 137 outputs “0” to the AND circuits 352 and 353.

  On the other hand, when the IID is the same (No at Step S201), the magnitude comparator 137 determines whether the element number of the request A is smaller than the element number of the request B (Step S203).

  When the element number of request A is smaller than the element number of request B (step S203: Yes), the magnitude comparator 137 instructs the hit determination circuit 135 to make a request data transfer request (step S204). For example, in the case of the configuration as shown in FIG. 5, the magnitude comparator 137 outputs “1” to the AND circuits 352 and 353. In this case, the magnitude comparator 137 outputs “0” to the AND circuits 362 and 363.

  On the other hand, when the element number of the request B is smaller than the element number of the request A (No at Step S203), the magnitude comparator 137 instructs the hit determination circuit 136 to make a request data transfer request (Step S205). For example, in the case of the configuration shown in FIG. 5, the magnitude comparator 137 outputs “1” to the AND circuits 362 and 363. In this case, the magnitude comparator 137 outputs “0” to the AND circuits 352 and 353.

  Next, the flow of data transfer arbitration between pipelines will be described with reference to FIG. FIG. 9 is a flowchart of a data transfer arbitration process between pipelines. Here, there will be described a case where there are two requests A and B, and there are two control ports #a and #b as the control port 30.

  The instruction control unit 11 inputs the request A to the control port #a and inputs the request B to the control port #b (step S301).

  The control port #a sets the status flag of the entry of request A to “1” (status = 1). Further, the control port #b sets the status flag of the entry of the request B to “1” (status = 1) (step S302).

  The control port #a inputs the request A into the pipeline 132, and the control port #b inputs the request B into the pipeline 133 (step S303).

  The hit determination circuit 135 determines whether or not the request A has a cache hit (step S304). When the request A does not have a cache hit (No at Step S304), the hit determination circuit 136 determines whether or not the request B has a cache hit (Step S305). When the request B has a cache hit (step S305: Yes), the control port #b sets the status flag of the entry of the request B to “2” (status = 2) (step S306).

  The memory access control circuit 138 transmits a data transfer request for the request A to the secondary cache control unit 14 (step S307).

  Thereafter, the memory access control circuit 138 registers response data for the data transfer request for the request A in the cache RAM 134 (step S308). Thereafter, the process returns to step S303.

  On the other hand, when the request B does not hit the cache (No at Step S305), the large / small comparator 137 determines whether the element number of the request A is smaller than the element number of the request B (Step S309).

  When the element number of the request A is smaller than the element number of the request B (step S309: Yes), the memory access control circuit 138 transmits a data transfer request for the request A to the secondary cache control unit 14 (step S310).

  Thereafter, the memory access control circuit 138 registers response data for the data transfer request for the request A in the cache RAM 134 (step S311). Thereafter, the process returns to step S303.

  On the other hand, when the element number of request B is smaller than the element number of request A (step S309: No), the memory access control circuit 138 transmits a data transfer request for the request B to the secondary cache control unit 14. (Step S312).

  Thereafter, the memory access control circuit 138 registers response data for the data transfer request for the request B in the cache RAM 134 (step S313). Thereafter, the process returns to step S303.

  On the other hand, when the request A has a cache hit (Yes at Step S304), the hit determination circuit 136 determines whether or not the request B has a cache hit (Step S314). When the request B does not hit the cache (Step S314: No), the control port #a sets the status flag of the entry of the request A to “2” (status = 2) (Step S315).

  The memory access control circuit 138 transmits a data transfer request for the request B to the secondary cache control unit 14 (step S316).

  Thereafter, the memory access control circuit 138 registers response data for the data transfer request for the request B in the cache RAM 134 (step S317). Thereafter, the process returns to step S303.

  On the other hand, when the request B has a cache hit (step S314: affirmative), the control port #a sets the status flag of the entry of the request A to “2” (status = 2). Further, the control port #b sets the status flag of the entry of request B to “2” (status = 2) (step S318).

  As described above, in the indirect access process, the arithmetic processing unit according to the present embodiment extracts a plurality of cache access requests from one instruction and uses the cache instruction access requests sequentially extracted by the number of pipelines as a control port. send. Thereby, the number of instructions when performing indirect access can be suppressed, and the processing load of the instruction control unit can be reduced.

  In addition, an increase in the bus between the instruction control unit and the cache control unit can be suppressed, and the circuit scale can be reduced. Further, it is possible to avoid the limitation on the number of cache access requests processed in parallel due to the limitation on the circuit scale.

  Furthermore, since the processing order of data transfer requests is adjusted according to the size of the element number of each request number, cache access requests can be appropriately processed even if the command numbers are the same. In addition, after all processing of the cache access request included in one instruction is completed, a request completion notification is sent from the cache control unit to the instruction control unit, so that the cache access processing for one instruction is properly completed. You can be notified.

  Next, Example 2 will be described. The arithmetic processing unit according to the present embodiment is different from the first embodiment in that cache access requests are processed in ascending order of element numbers. The arithmetic processing unit and the cache control unit according to this embodiment are also shown in FIGS. In the following, description of functions of the same parts as those in the first embodiment will be omitted.

  First, the hit determination circuits 135 and 136 will be described. Since both have the same function, the hit determination circuit 135 will be described as an example here.

  The hit determination circuit 135 determines a cache hit for the request input to the pipeline 132. If there is no hit, the hit determination circuit 135 makes a data transfer request under the same data transfer request arbitration process as in the first embodiment. When the response data is registered in the cache RAM 134 by the memory access control unit 138, the hit determination circuit 135 instructs the control port 30 that is the request source to re-inject the request.

  On the other hand, when a cache hit occurs, the hit determination circuit 135 determines whether or not the request is indirect access from the entry of the control port 30 corresponding to the cache hit request. If it is not indirect access, the hit determination circuit 135 performs the load / store processing of the request having a cache hit as it is. Then, the hit determination circuit 135 notifies the completion of processing of the processed request to the control port 30 that is the request source.

  On the other hand, in the case of indirect access, the hit determination circuit 135 determines whether the element number of the request is “0” from the entry of the control port 30 corresponding to the cache hit request. When the element number is “0”, the hit determination circuit 135 refers to the status flag of the request with the number immediately before the element number of the request.

  When the status flag is “2”, since the processing of the request with the previous number has been completed, the hit determination circuit 135 performs the load / store processing of the cache hit request. Then, the hit determination circuit 135 notifies the completion of processing of the processed request to the control port 30 that is the request source.

  If the status flag is not “2”, the processing of the request with the previous number has not been completed, so the hit determination circuit 135 does not perform the load / store processing of the cache hit request and re-enters the request. An instruction is given to the control port 30 of the request source.

  Upon receiving a request processing completion notification from the hit determination circuit 135 or 136, the control port management unit 131 determines whether indirect access is made from the notified request entry. If the request is not indirect access, a request completion response is notified to the instruction control unit 11 as it is. Thereafter, the control port management unit 131 changes the status flag of the entry of the quest to “0”.

  On the other hand, when the request is indirect access, the control port management unit 131 determines whether the element number of the request is the same as the number of elements of the cache access request included in the instruction including the request. Hereinafter, an instruction including a request is simply referred to as an “instruction”. When the number of elements is the same, that is, when the element number of the request is the largest among the element numbers of the requests included in the instruction, the control port management unit 131 notifies the instruction control unit 11 of a request completion response.

  On the other hand, if the element number of the request is different from the number of elements of the command, the control port management unit 131 requests the request until the request having the same element number as the number of elements is completed in the request included in the command. Pause processing for. When the completion notification of the request processing with the element number equal to the number of elements is received from the hit determination circuit 135 or 136, the control port management unit 131 transmits a request completion notification to the instruction control unit 11. Thereafter, the control port management unit 131 changes the status flags of all the request entries included in the command to “0”.

  Next, with reference to FIG. 10, the flow of instruction processing by the arithmetic processing unit according to this embodiment will be described. FIG. 10 is a flowchart of command processing performed by the arithmetic processing apparatus according to the second embodiment. Hereinafter, the hit determination circuit 135 and the hit determination circuit 136 are referred to as “hit determination circuit 140” without being distinguished from each other.

  The command control unit 11 acquires a request from the command and issues the acquired request to the control port 30 (step S401).

  The control port 30 receives the request (step S402). Then, the control port 30 sets the status flag of the received request entry to “1” (status = 1) (step S403).

  Next, the control port 30 inputs the request to the pipeline 130 (step S404).

  The hit determination circuit 140 determines whether or not the request has a cache hit (step S405). If there is no cache hit (No at Step S405), the memory access control unit 138 transmits a data transfer request to the secondary cache control unit 14 (Step S406). Then, the memory access control unit 138 receives the response data from the secondary cache control unit 14, and registers the received response data in the cache RAM 134 (step S407). Thereafter, the hit determination circuit 140 notifies the control port 30 of the request re-injection. The control port 30 returns to step S404.

  On the other hand, when a cache hit occurs (step S405: affirmative), the hit determination circuit 140 determines whether or not the request is not indirect access (indirect = 0) (step S408). If it is not indirect access (step S408: Yes), the hit determination circuit 140 proceeds to step S412.

  On the other hand, in the case of indirect access (No at Step S408), the hit determination circuit 140 determines whether or not the element number of the request is “0” (Step S409). When the element number of the request is “0” (step S409: Yes), the hit determination circuit 140 proceeds to step S412.

  On the other hand, when the element number of the request is not “0” (step S409: No), the hit determination circuit 140 has a status of an element number having a value (element number−1) obtained by subtracting 1 from the element number of the request The flag is referenced (step S410). Then, the hit determination circuit 140 determines whether or not the status flag is “2” (status = 2) (step S411). When the status flag is “2” (step S411: Yes), the hit determination circuit 140 proceeds to step S412. On the other hand, when the status flag is “1” (No at Step S411), the hit determination circuit 140 notifies the control port 30 of request re-injection. The control port 30 returns to step S404.

  Then, the hit determination circuit 140 executes load / store processing (step S412).

  The hit determination circuit 140 notifies the control port 30 of the completion of the request processing. The control port 30 receives the notification of the request processing completion and changes the status flag of the entry of the corresponding request to “2” (status = 2) (step S413).

  When the status flag is changed to “2”, the control port management unit 131 sets the flag indicating whether the request is not indirect access, that is, whether it is indirect access, to “0” (indirect = 0). It is determined whether or not (step S414). When the request is not indirect access (step S414: Yes), the control port management unit 131 proceeds to step S417.

  On the other hand, when the request is indirect access (No at Step S414), the control port management unit 131 determines whether the element number of the request is the same as the number of elements of the cache access request of the instruction including the request. Is determined (step S415). If the element number of the request is the same as the number of elements (step S415: affirmative), the control port management unit 131 transmits a request completion response related to the request to the instruction control unit 11 (step S417).

  On the other hand, when the element number of the request is different from the element number (step S415: No), the control port management unit 131 sends a request completion response for the request whose element number matches the element number, that is, the request with the largest element number. Wait until output (step S416).

  Thereafter, the control port management unit 131 transmits to the control port 30 an instruction to set the status flag of the request entry corresponding to the request completion response to “0”. Upon receiving an instruction from the control port management unit 131, the control port 30 sets the status flag of the instructed request to “0” (status = 0) (step S418).

  As described above, the arithmetic processing apparatus according to the present embodiment processes a request with a lower element number. Thereby, when the processing of the request whose element number matches the number of elements of the command is completed, it is determined that the processing of all the requests included in the command is completed. Therefore, the arithmetic processing unit can determine whether or not to transmit a request completion response without confirming the statuses of all requests included in the instruction, and can simplify the processing and the circuit.

1 CPU
2 Memory 11 Instruction control unit 12 Operation control unit 13 Cache control unit 14 Secondary cache control unit 15 Memory control unit 30 Control port 130, 132, 133 Pipeline 131 Control port management unit 134 Cache RAM
135, 136, 140 Hit determination circuit 137 Size comparator 138 Memory access control circuit

Claims (7)

An instruction control unit that acquires an arithmetic processing instruction including a plurality of cache access requests and sequentially transmits the cache access requests included in the arithmetic processing instruction;
A cache control unit that receives the cache access request transmitted from the instruction control unit and sequentially executes a process of accessing the cache instructed by each cache access request;
An arithmetic processing unit comprising: an arithmetic control unit that performs arithmetic processing based on a processing result of the access processing by the cache control unit. When the cache control unit completes processing of all the cache access requests included in the arithmetic processing instruction transmitted from the instruction control unit, the cache control unit notifies the instruction control unit of the completion of processing,
The arithmetic processing apparatus according to claim 1, wherein the instruction control unit determines completion of a cache access request in the arithmetic processing instruction when receiving a processing completion notification from the cache control unit. The cache access requests included in the arithmetic processing instructions are numbered sequentially.
The cache control unit processes the cache access requests in ascending order of numbers, and notifies the instruction control unit of completion of processing when processing of the cache access request having the last number is completed. 2. The arithmetic processing apparatus according to 2. The cache control unit has a plurality of cache access request processing paths,
The arithmetic processing apparatus according to claim 1, wherein the instruction control unit transmits the cache access requests for the number of processing paths to the cache control unit at the same time. The instruction control unit transmits the arithmetic processing instruction identification information and the cache access request identification information added to the cache access request,
The cache control unit determines the processing order of the cache access request based on the identification information of the arithmetic processing instruction and the identification information of the cache access request. The arithmetic processing unit described in 1.   The cache control unit determines the processing order between the cache access requests based on the identification information of the arithmetic processing instructions when the identification information of the arithmetic processing instructions added to the cache access requests is different. 6. The processing order between the cache access requests is determined based on the identification information of the cache access request when the identification information of the arithmetic processing instruction added to the access request is the same. The arithmetic processing unit according to claim 1. Obtain an arithmetic processing instruction including multiple cache access requests,
Sequentially obtaining the cache access requests included in the arithmetic processing instructions;
Sequentially execute access processing to the cache instructed by the acquired cache access request,
An arithmetic processing unit that performs arithmetic processing based on the processing result of the access processing.

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