JP2015203861A - semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor element with a solder flow prevention structure, which prevents a solder material from flowing over a semiconductor chip surface and a solder ball from being deposited onto a lateral face, and therefore causes no problem even when a carrier material contacts another carrier material, or the carrier material contacts other conductors.SOLUTION: The semiconductor element of the present invention comprises: a semiconductor chip provided on a semi-insulating or insulating substrate; a first metal layer formed on an undersurface of the substrate of the semiconductor chip; and a solder flow prevention structure including a carrier material and a second metal layer formed on the carrier material. The second metal layer includes: a first region for positioning and fixing the semiconductor chip and the carrier material by fastening the first and second metal layers with a solder material interposed therebetween; and a second region for guiding a solder material leaking out of the first region.

Description

  The present invention suppresses the flow and protrusion of a solder material used for securing the position of a semiconductor chip when the semiconductor chip is mounted on a carrier material in a semiconductor element composed of a semiconductor chip and a carrier material. The present invention relates to a semiconductor device having a solder flow prevention structure.

  With the diversification of optical communication systems and the increase in communication capacity, it is necessary to develop high-performance optical modules that enable high-speed optical signal processing. As means for realizing large-capacity transmission, multi-level modulation technology with improved frequency utilization efficiency has attracted attention. In particular, an IQ (Inphase-Quadrature) modulator capable of simultaneously modulating the intensity and phase of light is an optical transmitter. It is important as a key part.

Up to now, the IQ modulator has been mainly a modulator using a dielectric material such as LiNbO ₃ (lithium niobate: LN), but in a modulator using LN, light obtained from the electro-optic effect of LN is obtained. The electrode length required for modulation is several tens of millimeters, and further, an electrode for bias adjustment is required to align the operating point for each of the I channel and the Q channel, but if including these electrodes, the module size of the LN modulator Is as long as 100 mm.

  From the viewpoint of miniaturization and low power consumption of optical modules, semiconductor materials such as InP (indium phosphide) have attracted attention as materials that can replace LN, and IQ modulators using InP have been realized (for example, non-patented). Reference 1).

  FIG. 1 shows an example of a waveguide cross section in a passive region where no voltage is applied to the waveguide. FIG. 1 shows a semi-insulating (SI) -InP substrate 101 on a lower cladding layer 102 made of n-type InP, an undoped multiple quantum well (i-MQW) core layer 103, and an upper cladding layer. A layer structure in which 104 is grown in order is shown. In the layer structure shown in FIG. 1, a polymer 106 is provided so as to cover this layer structure, and a fixing metal layer 105 is provided on the back surface (lower side) of the SI-InP substrate 101.

  These layers have a high mesa structure as shown in FIG. 1 by a fine processing technique using photolithography. This high mesa structure is protected by embedding the left and right sides of the high mesa structure using an insulating polymer or the like. At this time, the polymer is required to cover at least the left and right sides of the waveguide, but may be thinly deposited on the waveguide.

  The upper cladding layer 104 may be a non-doped InP (i-InP) layer, or a p-InP layer laminated on an i-InP layer, or an n-InP layer on an i-InP layer. Or a thin p-InP layer on an i-InP layer and a further n-InP layer.

  FIG. 2 shows a cross-sectional view of an active region waveguide structure that applies a voltage to the waveguide. FIG. 2 shows a layer structure in which a lower cladding layer 202, a core layer 203, and an upper cladding layer 204 are grown in this order on an SI-InP substrate 201. In the layer structure shown in FIG. 2, a fixing metal layer 205 is provided on the back surface (lower side) of the SI-InP substrate 201, a polymer 206 is provided on both side surfaces of the waveguide portion, and modulation is performed on the upper cladding layer 204. A configuration in which an electrode 207 is provided and ground electrodes 208 and 209 are provided on the lower cladding layer is shown. Since an insulating polymer is used as the polymer 206, the modulation electrode 207 is provided after removing the polymer immediately above the waveguide. In the configuration shown in FIG. 2, the waveguide is protected by the polymer 206.

  FIG. 3 is a top view of an IQ modulator (semiconductor chip) using InP. FIG. 3 shows an IQ modulator 300 in which four Mach-Zehnder type optical modulators are arranged in parallel. As shown in FIG. 3, the IQ modulator 300 includes an active region 301 that applies a voltage and a passive region 302 that does not apply a voltage. The waveguide cross section of the passive region 302 corresponds to the cross sectional view shown in FIG. 1, and the waveguide cross section of the active region 301 corresponds to the cross sectional view shown in FIG.

  In the IQ modulator 300, the light modulation electrode length is about 3 mm, and even if the bias adjustment electrode is included, the chip length for the IQ modulator is 10 mm or less, and the area is reduced to about 1/20 that of LN. Is possible.

However, since the semiconductor element using InP is small in size, there is a problem in that the solder used for fixing overflows. Details are described below.
Optical communication modules are required to have strict reliability under high-temperature and high-humidity environments. In order to satisfy the reliability, they are generally housed in a hermetically sealed package made of metal such as Kovar. Like other optical modules, the InP semiconductor chip is mounted on an airtight package made of metal or ceramics and loaded with optical fibers and electrode terminals.

In mounting an optical module using such an InP semiconductor, the thermal expansion coefficient of InP (= 4.5 × 10 ⁻⁶ / K) and the thermal expansion coefficient of the package material (for example, in the case of Kovar, 5.3 × 10 ^{− 6} / K) and the coefficient of thermal expansion cause stress due to thermal distortion when the environmental temperature changes, causing deterioration of optical characteristics. Therefore, the InP semiconductor chip is temporarily mounted on a carrier material having a value close to the thermal expansion coefficient of InP to produce a chip-mounted carrier, which is housed in a package as a subassembly, and distortion due to the difference in thermal expansion coefficient is carrier. It is relaxed by.

Here, AlN (aluminum nitride) ceramics having a thermal expansion coefficient (= 4.5 × 10 ⁻⁶ / K) equivalent to InP is generally used as the carrier material. Since AlN has a large thermal conductivity of over 200 W / (m · K) and excellent thermal conductivity, it also serves as a heat sink in semiconductor elements that require temperature control, such as LDs (Laser Diodes). ing.

  For fixing the InP chip and the carrier, gold-tin (AuSn) eutectic solder having excellent electrical conductivity and thermal conductivity, high shear strength, high melting point, high hardness after melting and excellent stability is used. A metal pattern for melting the solder is formed on the chip mounting surface of the carrier material, and an AuSn solder sheet or the like is laid on the carrier mounting surface. After the semiconductor chip alignment, the solder is heated and melted to near the melting point of the solder. During melting, in order to suppress the semiconductor chip mounting position deviation due to the convection of the molten solder when the solder melts, and to properly spread the semiconductor chip so that the solder spreads well between the back surface of the InP chip and the carrier mounting. It is necessary to press.

  FIG. 4 shows a conventional solder flow prevention structure in a semiconductor element. FIG. 4A shows a solder flow prevention structure of a semiconductor element during mounting, and FIG. 4B shows a solder flow prevention structure of the semiconductor element after mounting.

  FIG. 4A shows a carrier material 401 made of AlN or the like, a semiconductor chip 402 provided with a fixing metal layer 403 on the lower surface, and a solder melting metal layer provided on the semiconductor chip mounting surface of the carrier material 401. A semiconductor element having 404 and a solder material 405 made of AuSn or the like provided between the fixing metal layer 403 and the solder melting metal layer 404 is shown. The carrier material 401 and the solder melting metal layer 404 constitute a solder flow prevention structure.

  As shown in FIGS. 4A and 4B, in the solder flow preventing structure at the time of mounting, the fixing metal layer 403 and the solder melting metal layer 404 are fixed by using a solder material 405, so that the carrier The position of the semiconductor chip 402 is fixed on the material 401.

  As described above, in mounting the semiconductor chip 402, ceramics such as AlN having a thermal expansion coefficient close to that of the semiconductor chip 402 in order to relieve stress strain due to the difference in thermal expansion coefficient between the semiconductor chip 402 and the outer package material. A semiconductor chip 402 is fixed on a carrier material 401 using a material using a solder material 405 made of AuSn or the like having excellent stability for the purpose of ensuring electrical continuity and thermal conductivity.

  At this time, if the amount of solder is excessive or the pressing force is large, as shown in FIG. 4B, the molten solder material 405 protrudes from the side surface or top surface of the semiconductor chip 402, and a ball-shaped solder pool is formed. Become. When a plurality of semiconductor chips are mounted close to each other, the ball-shaped solder pool interferes with another adjacent semiconductor chip (is in electrical contact with a carrier material on which the adjacent semiconductor chip is mounted). If it occurs on the end face on the optical waveguide side, the propagation of the optical signal is hindered. Further, when the amount of the solder material 405 that protrudes is large, the solder material 405 rises to the surface of the semiconductor chip 402 and wets and spreads on the semiconductor chip 402 to crush the electrical wiring pattern formed on the surface of the semiconductor chip 402. Things can happen.

  In order to solve these problems, a method of providing a metal layer on the end face of a carrier material has been studied. For example, FIG. 5 shows an example of a structure in which a metal layer is provided on an end face of a carrier material as shown in Patent Document 1. The structure shown in FIG. 5 is an example in which the Au layer 13 is provided on the upper surface of the carrier material 11 and the position of the semiconductor chip 12 made of a semiconductor laser is fixed using the solder material 14 made of AuSn. Here, the Au layer 13 on the carrier material 11 is used as a wiring for supplying a current to the semiconductor chip 12 at the same time as fixing the position.

  In FIG. 5, an Au layer 13 is also provided on the end face of the carrier material 11 on the emission end face side of the laser light 15 output from the semiconductor chip 12. As a result, the protruding solder material 14 can be guided toward the end surface on the side surface where the Au layer 13 of the carrier material 11 is provided. Accordingly, it is possible to prevent the propagation of the laser beam from reaching the end face on the waveguide side of the semiconductor laser, or to avoid crushing the electric wiring pattern formed on the surface of the semiconductor chip 12 with the solder material 14. can do.

  FIG. 6 shows another example of a structure in which a metal layer is provided on an end surface of a carrier material as shown in Patent Document 2. In the structure shown in FIG. 6, the recess 22 is provided on the end face of the carrier material 21, and the metal layer 23 and the solder material 24 are provided on the recess 22 in the end face, and the same effect as the structure shown in FIG. 5 is obtained. Can do.

JP-A-6-350202 JP 2003-46181 A

H. Yagi et al., “Low driving voltage InP-based Mach-Zehnder modulators for compact 128 Gb / s DP-QPSK module”, 2013 Conference on Lasers and Electro-Optics Pacific Rim (CLEO-PR), 2013, WK2 -2

  However, the configuration shown in FIGS. 5 and 6 can prevent the solder ball from being generated on the end face of the optical waveguide and can prevent the electric wiring pattern formed on the surface of the semiconductor chip from being crushed. It never happened. The reason is as follows.

  First, in many cases, a lens or a waveguide (such as an optical fiber or a silica-based waveguide is not a semiconductor) is usually provided in the immediate vicinity of the input end face or the output end face of the semiconductor chip. That is, when the protruding solder is guided toward the input surface or output surface of the semiconductor chip and a solder ball is formed there, the solder ball interferes with the arrangement of the lens and the waveguide. In addition, even when the recess as shown in FIG. 6 is provided, if the solder ball becomes large, the recess may overflow.

  Therefore, it is necessary to guide the overflowing solder toward the side of the semiconductor chip that is not the input surface or the output surface. However, this causes a problem of interfering with each other when mounting a plurality of semiconductor chips close to each other. .

  On the other hand, conventionally, a metal film of a carrier material has been used as an electrode for fixing a position and supplying a current or a voltage. In other words, considering that a plurality of semiconductor elements each having a semiconductor chip and a carrier material having a metal layer on a side surface are arranged in parallel, the carrier material on the side surface is a metal, so that the carrier material and other semiconductor elements There has been a problem of conduction when in contact with the carrier material. Usually, a certain distance is provided between the carrier material and the carrier material of another semiconductor element. However, if the solder ball is present there, there is a possibility of contact. Even when the concave portion is provided on the side surface, if the solder ball is large, it overflows from the groove and still comes into contact.

  The present invention has been made in view of the above problems, and when mounting a semiconductor chip on a carrier material, it suppresses the flow and protrusion of the solder material used when securing the position fixing of the semiconductor chip, It is an object of the present invention to realize a semiconductor element having a solder flow prevention structure which does not cause a problem even when a carrier material and a carrier material or a carrier material and another conductor are in contact with each other.

  In order to solve the above problems, a semiconductor element according to claim 1 of the present invention is a semiconductor provided on a semi-insulating or insulating substrate, and an electrode for applying a current or a voltage is formed on the upper surface. A chip, a first metal layer for fixing the position of the semiconductor chip formed on a lower surface of the substrate of the semiconductor chip, a carrier material, and a second metal layer formed on the carrier material. A solder flow prevention structure, and the second metal layer is formed by fixing the first metal layer and the second metal layer via a solder material, thereby connecting the semiconductor chip and the carrier material. A first region for fixing the position and a second region for guiding the solder material leaking from the first region are included.

  A semiconductor element according to claim 2 of the present invention is the semiconductor element according to claim 1 of the present invention, wherein the first region and the second region are provided on the same upper surface of the carrier material. It is characterized by.

  A semiconductor element according to a third aspect of the present invention is the semiconductor element according to the first aspect of the present invention, wherein the first region is provided on an upper surface of the carrier material, and the second region is the It is provided on the side surface of the carrier material.

  A semiconductor element according to a fourth aspect of the present invention is the semiconductor element according to the third aspect of the present invention, wherein a concave portion is provided on a side surface of the carrier material.

  A semiconductor element according to a fifth aspect of the present invention is the semiconductor element according to the third aspect of the present invention, wherein the second metal layer is made of gold plating.

  A semiconductor element according to a sixth aspect of the present invention is the semiconductor element according to any one of the first to fifth aspects of the present invention, wherein the substrate is made of InP.

  A semiconductor element according to a seventh aspect of the present invention is the semiconductor element according to any one of the first to sixth aspects of the present invention, wherein the carrier material is made of AlN.

  According to the present invention, in a semiconductor element in which the position of a semiconductor chip and a carrier material is fixed with a solder material, the solder material is suppressed from rising onto the surface of the semiconductor chip and the solder balls are deposited on the side surface. It is possible to realize a solder flow prevention structure that does not cause a problem even when a material and another conductor are in contact with each other.

  In addition, according to the present invention, since the semi-insulating substrate is used only for position fixing in the semiconductor chip, no current / voltage is applied to the metal film on the lower surface of the semiconductor chip, and the carrier material and the carrier material, or the carrier There is no problem even if the material and the adjacent conductor are in contact with each other.

It is a figure which shows an example of the waveguide cross section of a passive region. It is a figure which shows an example of the waveguide cross section of an active region. It is a top view of an IQ modulator (semiconductor chip) using InP. It is a figure which shows the conventional solder flow prevention structure in a semiconductor element. It is a figure which shows an example of the structure which provided the metal layer in the end surface of a carrier material. It is a figure which shows the other example of the structure which provided the metal layer in the end surface of a carrier material. It is a figure which shows the solder flow prevention structure of the semiconductor element which concerns on Example 1 of this invention. It is a figure which shows the solder flow prevention structure of the semiconductor element which concerns on Example 2 of this invention. It is a figure which shows the solder flow prevention structure of the semiconductor element which concerns on Example 3 of this invention.

Hereinafter, although each Example of this invention is described in detail with reference to drawings, this invention is not limited to these Examples.
(Example 1)
FIG. 7 shows a solder flow prevention structure of a semiconductor device according to the first embodiment of the present invention, and specifically shows a part of an optical communication module in which an optical semiconductor chip is mounted on a carrier substrate. FIG. 7A shows a structure for preventing solder flow of a semiconductor element during mounting, and FIG. 7B shows a structure for preventing solder flow of a semiconductor element after mounting.

  7A shows a carrier material 701 made of AlN or the like, a semiconductor chip 702 provided with a fixing metal layer 703 on the lower surface, and a solder melting metal layer provided on the semiconductor chip mounting surface of the carrier material 701. A semiconductor element having 704 and a solder material 705 made of AuSn or the like provided between the fixing metal layer 703 and the solder melting metal layer 704 is shown. The carrier material 701 and the solder melting metal layer 704 constitute a solder flow prevention structure.

  As shown in FIGS. 7A and 7B, in the solder flow prevention structure at the time of mounting, the fixing metal layer 703 and the solder melting metal layer 704 are fixed by using the solder material 705, so that the carrier The position of the semiconductor chip 702 is fixed on the material 701.

  The optical semiconductor chip 704 has a structure in which an optical waveguide layer and an electrode layer are stacked on a semiconductor substrate such as InP. For example, in the case of a semiconductor optical modulator chip, the optical semiconductor chip 704 includes an n-type InP cladding layer, an i-type MQW optical core layer, a semi-insulating InP layer, and an n-type InP cladding layer in this order on a semi-insulating InP substrate. An optical waveguide layer is formed by laminating, and further, the optical waveguide layer is processed into a mesa shape with a width of about 2 μm, a modulation electrode is formed using Au immediately above the optical waveguide, and grounded on both sides of the mesa By forming the electrode, a configuration in which an electric field necessary for light modulation can be efficiently applied can be obtained.

The solder melting metal layer 704 has a position fixing region 704 ₁ for fixing the position of the semiconductor chip 702 via the solder material 705 and a solder guide pattern region 704 ₂ for guiding the leaked solder material 705. . In the present invention, in order to prevent the exudation of the solder material 705 to the side surface or the upper surface of the semiconductor chip 702, as shown in FIG. 7 (b), the solder guide pattern region 704 _2, the semiconductor chip 702 after mounting The carrier material 701 is provided on the semiconductor chip mounting surface so as to be disposed outside the semiconductor chip 702 to be mounted without being covered from above. Solder guided by the pattern area 704 _2, it can be derived so as to extend along the guide pattern area 704 ₂ solder the solder material 705 extra protrusion.

  With this solder flow prevention structure, it is possible to suppress the solder material from rising to the surface of the semiconductor chip and from the deposition of solder balls on the side surfaces. Further, since no metal is provided on the side surface of the carrier material, no problem occurs even when the carrier material and the carrier material or the carrier material and another conductor are in contact with each other.

For simplicity, the semiconductor chip 702 according to the first embodiment shown in FIG. 7 has a structure having a straight waveguide instead of the IQ modulator as shown in FIG. there is, unless the waveguide end face and the solder guide pattern region 704 ₂ is close, but may be a semiconductor chip having any waveguide structure.

(Example 2)
FIG. 8 shows a solder flow prevention structure for a semiconductor device according to Example 2 of the present invention. FIG. 8A shows a solder flow prevention structure of a semiconductor element during mounting, and FIG. 8B shows a solder flow prevention structure of the semiconductor element after mounting.

  FIG. 8A shows a carrier material 801 made of AlN or the like, a semiconductor chip 802 provided with a fixing metal layer 803 on the lower surface, and a solder melting metal layer provided on the semiconductor chip mounting surface of the carrier material 801. A semiconductor element having 804 and a solder material 805 made of AuSn or the like provided between a fixing metal layer 803 and a solder melting metal layer 804 is shown. The carrier material 801 and the solder melting metal layer 804 constitute a solder flow prevention structure.

  In the second embodiment, an InP optical semiconductor chip is used as the semiconductor chip 802, and an n-type InP clad layer, an i-type MQW optical core layer, and a semi-insulating InP are formed on a semi-insulating (or insulating) InP substrate. An optical waveguide layer is formed by laminating a layer and an n-type InP clad layer.

Solder melting metal layer 804, the position fixing region 804 ₁ for fixing the position of the semiconductor chip 802 via the solder material 805, side surfaces for guiding the solder material 805 leaks to the side of the carrier material 801 solder having a guide region 804 _2. In Example 2, partially cutaway side of the carrier material 801, to form a side solder guide region 804 ₂ by metal evaporation or the like to the cutout portion. Thus, since the side surface solder guide 806 of the carrier material 801 is arranged inside the semiconductor chip 802 to be mounted, the excess solder that protrudes due to melting hardly protrudes to the side surface.

  Since the semiconductor chip 802 shown in FIG. 8 is formed on a semi-insulating or insulating InP substrate, no current / voltage is applied to the fixing metal layer 803 on the lower surface of the semiconductor chip 802. That is, current or voltage is applied between the modulation electrode and the two ground electrodes, and does not reach the fixing metal layer 803. Therefore, even if the solder material 805 protrudes from the side surface and comes into contact with an adjacent carrier material (or an adjacent conductor), no problem occurs.

  For simplicity, the semiconductor chip 802 according to the second embodiment shown in FIG. 8 has a structure having a linear waveguide instead of the IQ modulator as shown in FIG. As long as there is, a semiconductor chip having any waveguide structure may be used. The same applies to the semiconductor chip according to Example 3 shown below.

(Example 3)
FIG. 9 shows a solder flow prevention structure for a semiconductor device according to Example 3 of the present invention. FIG. 9A shows a solder flow prevention structure of a semiconductor element during mounting, and FIG. 9B shows a solder flow prevention structure of the semiconductor element after mounting.

  FIG. 9A shows a carrier material 901 made of AlN or the like, a semiconductor chip 902 having a fixing metal layer 903 on the lower surface, a metal film 904 provided on the entire surface of the carrier material 901, and a fixing metal. A semiconductor element having a solder material 905 made of AuSn or the like provided between a layer 903 and a carrier material 901 is shown. The carrier material 901 and the metal film 904 constitute a solder flow prevention structure.

  A semiconductor chip 902 to be mounted is the same as that of the second embodiment, and is a semiconductor chip on a semi-insulating (or insulating) InP substrate.

  The third embodiment is characterized in that a metal film 904 made of gold plating or the like is applied to the carrier material 901 as a material with good wettability of the solder material 905, and it is possible to guide the solder that protrudes over the entire periphery of the carrier material 901. It becomes.

  With the solder flow prevention structure according to the third embodiment, it is possible to suppress the solder material 905 from rising onto the surface of the semiconductor chip and the deposition of solder balls on the side surfaces. In addition, since no current / voltage is applied to the carrier material, no problem occurs even if the solder material protrudes from the side surface and contacts the adjacent carrier material (or adjacent conductor).

Carrier material 11, 21, 401, 701, 801, 901
Semiconductor chip 12, 402, 702, 802, 902
Au layer 13
Solder material 14, 24, 405, 705, 805, 905
Recess 22
Metal layer 23
SI-InP substrate 101, 201
Lower cladding layer 102, 202
Core layer 103, 203
Upper cladding layer 104, 204
Fixing metal layer 105, 205, 403, 703, 803, 903
Polymer 106, 206
Modulation electrode 207
Ground electrode 208, 209
IQ modulator 300
Active area 301
Passive region 302
Solder melting metal layer 404, 704, 804
Position fixing area 704 ₁ , 804 ₁
Solder guide pattern area 704 ₂
Side solder guide area 804 ₂
Metal film 904

Claims (7)

A semiconductor chip provided on a semi-insulating or insulating substrate and having an electrode for applying a current or voltage applied to the upper surface;
A first metal layer for fixing the position of the semiconductor chip, formed on the lower surface of the substrate of the semiconductor chip;
A solder flow prevention structure comprising a carrier material and a second metal layer formed on the carrier material;
The second metal layer comprises:
A first region for fixing the position of the semiconductor chip and the carrier material by fixing the first metal layer and the second metal layer via a solder material;
A second region for guiding the solder material leaking from the first region;
A semiconductor device comprising:   The semiconductor element according to claim 1, wherein the first region and the second region are provided on the same upper surface of the carrier material.   The semiconductor element according to claim 1, wherein the first region is provided on an upper surface of the carrier material, and the second region is provided on a side surface of the carrier material.   The semiconductor element according to claim 3, wherein a concave portion is provided on a side surface of the carrier material.   The semiconductor element according to claim 3, wherein the second metal layer is made of gold plating.   The semiconductor device according to claim 1, wherein the substrate is made of InP.   The semiconductor element according to claim 1, wherein the carrier material is made of AlN.

Images