JP2015201664A - semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an art of enabling reduction in chip size of a semiconductor chip; and especially provide an art of enabling reduction in chip size of a semiconductor chip by shaping a layout arrangement in a short side direction in a rectangular-shaped semiconductor chip which composes an LCD driver.SOLUTION: A semiconductor chip CHP2 which composes an LCD driver comprises: input protective circuits 3a-3c arranged in a lower layer of part of a plurality of input bump electrodes IBMP; and SRAMs 2a-2c (internal circuits) arranged in the lower layer of the rest part of the plurality of input bump electrodes IBMP, where the input protective circuits 3a-3c are not arranged.

Description

  The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a semiconductor device used in a driver for an LCD (Liquid Crystal Display).

  Japanese Patent Application Laid-Open No. 2006-210607 (Patent Document 1) describes a technique that can reduce the chip size. Specifically, the buffers are collectively arranged in a region away from each of the pads. This area is an area excluding the formation area of the central processing unit, the nonvolatile memory and the volatile memory in the main area. Since a buffer requiring a large area is not provided in the peripheral portion of the pad, it is possible to shorten the distance between the pads and the distance between the pads and the internal circuit (for example, the central processing unit). As a result, the chip size can be reduced.

  Japanese Unexamined Patent Application Publication No. 2007-103848 (Patent Document 2) describes a technique capable of reducing the size of a semiconductor chip. Specifically, first, a pad and a wiring other than the pad are provided on the insulating film. A surface protective film is formed on the insulating film including the pad and the wiring, and an opening is provided in the surface protective film. The opening is formed on the pad and exposes the surface of the pad. A bump electrode is formed on the surface protective film including the opening. Here, the size of the pad is made sufficiently smaller than the size of the bump electrode. Thus, the wiring is arranged immediately below the bump electrode and in the same layer as the pad. That is, the wiring is arranged in a space under the bump electrode formed by reducing the pad.

JP 2006-210607 A JP 2007-103848 A

  In recent years, LCDs using liquid crystals as display elements are rapidly spreading. This LCD is controlled by a driver for driving the LCD. The LCD driver is composed of a semiconductor chip and is mounted on, for example, a glass substrate. A semiconductor chip constituting an LCD driver has a structure in which a plurality of transistors and multilayer wiring are formed on a semiconductor substrate, and bump electrodes are formed on the surface. And it is mounted in the glass substrate through the bump electrode formed in the surface.

  The semiconductor chip constituting the LCD driver has a rectangular shape having a short side and a long side, and a plurality of bump electrodes are arranged along the long side direction of the semiconductor chip. For example, an input bump electrode is arranged on a straight line along the first long side of the pair of long sides, and the second long side facing the first long side has the second long side. Output bump electrodes are arranged in a staggered pattern along the side. That is, the semiconductor chip constituting the LCD driver has a feature that the number of output bump electrodes is larger than the number of input bump electrodes. This is because the input bump electrode mainly inputs serial data, whereas the output bump electrode outputs parallel data converted by the LCD driver.

  Here, with the miniaturization of semiconductor elements, miniaturization of semiconductor chips constituting LCD drivers is also being promoted. However, in a semiconductor chip constituting an LCD driver, the number of bump electrodes greatly affects the length in the long side direction. That is, in the liquid crystal display device, the number of output bump electrodes of the LCD driver is almost determined, so the number of output bump electrodes cannot be reduced, and the long side of the semiconductor chip constituting the LCD driver can be reduced. Is becoming difficult. In other words, it is necessary to form a predetermined number of output bump electrodes on the long side of the semiconductor chip constituting the LCD driver, and the distance between the bump electrodes is reduced to the minimum. It is difficult to reduce the long side direction.

  An object of the present invention is to reduce the chip size of a semiconductor chip.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A semiconductor device in a typical embodiment includes a rectangular semiconductor chip having a pair of short sides and a pair of long sides. Here, the semiconductor chip is (a) disposed along the first long side of the semiconductor chip, and closer to the first long side than the second long side facing the first long side. A plurality of first bump electrodes disposed on the semiconductor chip; (b) an internal circuit formed on the semiconductor chip; and (c) protecting the internal circuit from static electricity, and the plurality of first bump electrodes; A plurality of first electrostatic protection circuits electrically connected. At this time, some of the first electrostatic protection circuits among the plurality of first electrostatic protection circuits electrically connected to some of the first bump electrodes among the plurality of first bump electrodes are Of the plurality of first electrostatic protection circuits which are arranged in a position overlapping with the first bump electrode of the plurality of first bump electrodes and electrically connected to the other first bump electrodes among the plurality of first bump electrodes. The other first electrostatic protection circuit is arranged at a position different from a position overlapping the other first bump electrode in plan view.

  In addition, a semiconductor device in a typical embodiment includes a rectangular semiconductor chip having a pair of short sides and a pair of long sides. Here, the semiconductor chip is (a) disposed along the first long side of the semiconductor chip, and closer to the first long side than the second long side facing the first long side. A plurality of first bump electrodes disposed on the semiconductor chip; (b) an internal circuit formed on the semiconductor chip; and (c) protecting the internal circuit from static electricity, and the plurality of first bump electrodes; A plurality of first electrostatic protection circuits electrically connected. At this time, the plurality of first electrostatic protection circuits are arranged at a position different from a position overlapping the plurality of first bump electrodes in plan view.

  The semiconductor device according to a representative embodiment has a first short side, a second short side facing the first short side, a first long side, and a second long side facing the first long side. A rectangular semiconductor chip is provided. Here, the semiconductor chip is (a) arranged along the first long side of the semiconductor chip and arranged closer to the first long side than the second long side. One bump electrode and a second bump electrode; and (b) an uppermost layer wiring disposed via an insulating film at a position overlapping the first bump electrode and the second bump electrode in plan view. Further, (c) a first opening formed in the insulating film for connection to the first bump electrode, and (d) formed in the insulating film for connection to the second bump electrode. A second opening. At this time, in the direction along the first short side or the second short side, the formation position of the first opening with respect to the first bump electrode and the formation position of the second opening with respect to the second bump electrode are It is characterized by being different.

  In addition, a semiconductor device in a typical embodiment includes a rectangular semiconductor chip having a pair of short sides and a pair of long sides. Here, the semiconductor chip is (a) disposed along the first long side of the semiconductor chip, and closer to the first long side than the second long side facing the first long side. A first bump electrode and a second bump electrode disposed on the first bump electrode; and (b) an uppermost layer wiring disposed via an insulating film at a position overlapping the first bump electrode and the second bump electrode in a plane. Have Further, (c) a first opening formed in the insulating film for connection to the first bump electrode, and (d) formed in the insulating film for connection to the first bump electrode. A second opening. At this time, the uppermost layer wiring is connected to the first uppermost layer wiring connected to the first bump electrode via the first opening, and to the first bump electrode connected to the second opening, In addition, the second uppermost layer wiring is different from the first uppermost layer wiring, and the first opening and the second opening are formed to be connected at different positions of the first bump electrode. It is characterized by this.

  The semiconductor device according to a representative embodiment has a first short side, a second short side facing the first short side, a first long side, and a second long side facing the first long side. A rectangular semiconductor chip is provided. Here, the semiconductor chip is (a) arranged along the first long side of the semiconductor chip, and closer to the first long side than the second long side facing the first long side. A first bump electrode disposed at a close position; (b) an internal circuit formed on the semiconductor chip; and (c) protecting the internal circuit from static electricity and being electrically connected to the first bump electrode. A first electrostatic protection circuit connected to the first electrostatic protection circuit. At this time, the internal circuit is arranged at a position overlapping the first bump electrode in a plane, and the first electrostatic protection circuit is located at a position different from the position overlapping the first bump electrode. It is characterized by being arranged.

  The semiconductor device according to a representative embodiment has a first short side, a second short side facing the first short side, a first long side, and a second long side facing the first long side. A rectangular semiconductor chip is provided. Here, the semiconductor chip is (a) arranged along the first long side of the semiconductor chip, and closer to the first long side than the second long side facing the first long side. A first bump electrode disposed at a close position; (b) an internal circuit formed on the semiconductor chip; and (c) protecting the internal circuit from static electricity and being electrically connected to the first bump electrode. A first electrostatic protection circuit connected to the first electrostatic protection circuit. At this time, the first electrostatic protection circuit is disposed at a position different from the position overlapping the first bump electrode in a plane, and a plurality of wirings are provided at the position overlapping the first bump electrode in a plane. Is characterized by passing.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  The chip size of the semiconductor chip can be reduced.

It is a figure which shows the structure of the semiconductor chip which comprises a general LCD driver. It is a circuit block diagram which shows an example of an input protection circuit. It is a circuit block diagram which shows another example of an input protection circuit. In Embodiment 1 of this invention, it is a figure which shows the structure of the semiconductor chip which comprises an LCD driver. It is a figure which expands and shows the vicinity area | region of the long side of the semiconductor chip which comprises a general LCD driver. FIG. 5 is an enlarged view showing a region in the vicinity of a long side on the input bump electrode side of a semiconductor chip that is an LCD driver according to the first embodiment. In Embodiment 2, it is a figure which shows the structure of the semiconductor chip which comprises an LCD driver. It is a figure explaining the 1st device point in Embodiment 3. FIG. It is a figure explaining the 2nd device point in Embodiment 3. FIG. It is a figure explaining the 3rd device point in Embodiment 3. FIG. FIG. 11 is a diagram showing an example of a wiring layout that incorporates first to third contrivance points in the third embodiment. In Embodiment 4, it is an enlarged view which shows the semiconductor chip which comprises an LCD driver. In Embodiment 5, it is a figure which shows one bump electrode for input. It is sectional drawing cut | disconnected by the AA line of FIG. In Embodiment 5, it is a figure which shows one bump electrode for input. It is sectional drawing cut | disconnected by the AA line of FIG. 27 is a cross-sectional view showing a manufacturing step of the semiconductor device in the sixth embodiment. FIG. 18 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 17; FIG. 19 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 18; FIG. 20 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 19; It is the figure which showed the whole structure of LCD (liquid crystal display device). It is a figure which expands and shows the area | region of the long side at the side of the output bump electrode of the semiconductor chip which is an LCD driver in this Embodiment 7. FIG. It is sectional drawing in Embodiment 8, and is sectional drawing cut | disconnected by the AA line of FIG.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.

  Similarly, in the following embodiments, when referring to the shape, positional relationship, etc., of components, etc., unless otherwise specified, and in principle, it is considered that this is not clearly the case, it is substantially the same. Including those that are approximate or similar to the shape. The same applies to the above numerical values and ranges.

  In all the drawings for explaining the embodiments, the same members are denoted by the same reference symbols in principle, and the repeated explanation thereof is omitted. In order to make the drawings easy to understand, even a plan view may be hatched.

(Embodiment 1)
In the LCD driver, miniaturization of the semiconductor chip has been promoted as described above, and in particular, reduction of the short side direction of the semiconductor chip is being studied.

  First, the external configuration of a general LCD driver will be described. FIG. 1 is a plan view showing the surface of a semiconductor chip CHP1 constituting the LCD driver. In FIG. 1, a semiconductor chip CHP1 has a semiconductor substrate formed in, for example, an elongated rectangular shape (rectangular shape), and an LCD driver for driving a display device such as a liquid crystal display device is provided on the main surface thereof. Is formed.

  The semiconductor chip CHP1 has a rectangular shape having a pair of short sides (short side SS1 and short side SS2) and a pair of long sides (long side LS1 and long side LS2), and one long side of the pair of long sides. A plurality of input bump electrodes IBMP are arranged along the side LS1 (the lower side in FIG. 1). These input bump electrodes IBMP are arranged on a straight line. The input bump electrode IBMP functions as an external connection terminal connected to an integrated circuit (LSI (Large Scale Integration)) formed of semiconductor elements and wirings formed inside the semiconductor chip CHP. Bump electrodes for digital input signals or analog input signals.

  Next, a plurality of output bump electrodes OBMP are arranged along another long side LS2 (the upper side in FIG. 1) of the pair of long sides. These output bump electrodes OBMP are arranged in two rows along the long side LS2, and the two rows along the long side LS2 are arranged in a staggered manner. Thereby, the output bump electrodes OBMP can be arranged with high density. These output bump electrodes OBMP also function as external connection terminals for connecting the integrated circuit formed inside the semiconductor substrate and the outside. In particular, the output bump electrode OBMP is a bump electrode for an output signal from the integrated circuit.

  As described above, the input bump electrode IBMP and the output bump electrode OBMP are formed on the pair of long side LS1 and long side LS2 constituting the outer periphery of the semiconductor chip CHP1. At this time, since the number of output bump electrodes OBMP is larger than the number of input bump electrodes IBMP, the input bump electrodes IBMP are formed in a straight line along the long side LS1. The output bump electrodes OBMP are arranged in a staggered pattern along the long side LS2. This is because the input bump electrode IBMP is a bump electrode for input signals input to the LCD driver, whereas the output bump electrode OBMP is a bump electrode for output signals output from the LCD driver. . That is, since the input signal input to the LCD driver is serial data, the number of input bump electrodes IBMP which are external connection terminals does not increase so much. On the other hand, since the output signal output from the LCD driver is parallel data, the number of output bump electrodes OBMP which are external connection terminals increases. That is, since the output bump electrodes OBMP are provided for individual cells (pixels) constituting the liquid crystal display element, the output bump electrodes OBMP are equivalent to the matrix lines (for example, gate lines and source lines) for driving the cells. This is because the output bump electrode OBMP is required. Therefore, the number of output bump electrodes OBMP is larger than that of the input bump electrodes IBMP. Therefore, the input bump electrodes IBMP can be arranged in a straight line along the long side LS1, but the output bump electrodes OBMP are arranged in a staggered manner along the long side LS2 to increase the number. .

  In FIG. 1, the input bump electrode IBMP and the output bump electrode OBMP are arranged along the pair of long sides LS1 and long side LS2 constituting the semiconductor chip CHP1, respectively. In addition to the side LS1 and the long side LS2, the bump electrodes can be arranged along the pair of short side SS1 and short side SS2.

  The external configuration of the semiconductor chip CHP1 is as described above, and the function of the LCD driver realized by the integrated circuit formed in the semiconductor chip CHP1 will be described below. FIG. 1 also shows functional blocks showing functions of the LCD driver. In FIG. 1, a semiconductor chip CHP1 includes a control unit 1, SRAM (Static Random Access Memory) 2a, SRAM 2b, an input protection circuit (electrostatic protection circuit) 3, and an output protection circuit (electrostatic protection circuit) 4 as memory circuits. Have. The control unit 1 is configured to include, for example, an LCD control unit and an analog unit. The SRAM 2a and the SRAM 2b include, for example, a memory cell array in which SRAM memory cells (storage elements) are arranged in a matrix, and a memory cell array. The SRAM control unit and the word driver for driving are included. Furthermore, the input protection circuit 3 and the output protection circuit 4 are configured as a part of an I / O circuit that is an input circuit, an output circuit, or an input / output circuit, for example.

  The I / O circuit has a function of exchanging data input / output to / from the semiconductor chip CHP1, and the SRAMs 2a and 2b are examples of storage circuits (memory circuits) that store data. The SRAMs 2a and 2b have a configuration in which storage elements for storing data are arranged in an array, and store image data to be displayed on a liquid crystal display device. The word driver has a function of selecting the rows of the SRAMs 2a and 2b arranged in an array (matrix), and the SRAM control unit has a function of controlling writing and reading of data to and from the SRAMs 2a and 2b. doing. That is, the SRAM control unit includes an address decoder and a read / write control circuit for controlling reading and writing of the SRAMs 2a and 2b.

  The LCD control unit has a function of generating an access signal with a microcomputer mounted outside the LCD driver (semiconductor chip CHP1), a timing signal for operating internal circuits necessary for display such as the SRAMs 2a, 2b, and the counter. And a reset circuit for resetting the display, a clock circuit for generating a clock signal, and the like. Furthermore, the analog unit has a function (level shift function) for increasing the voltage level of the image data stored in the SRAMs 2a and 2b and converting it to a voltage suitable for the liquid crystal display cell, for example. In other words, the analog circuit is configured to include a booster circuit that increases the voltage, and is configured to generate various voltages to be applied to the liquid crystal display cell.

  The input protection circuit 3 is a circuit having a function of protecting internal circuits (SRAM, word driver, SRAM control unit, LCD control unit, analog unit, etc.) from a surge voltage accidentally applied to the input bump electrode IBMP. . Here, the surge voltage is an abnormal voltage instantaneously induced by static electricity or the like. Similarly, the output protection circuit 4 is a circuit that protects an internal circuit from a surge voltage that is accidentally applied to the output bump electrode OBMP. By providing the input protection circuit 3 and the output protection circuit 4 as described above, the internal circuit that realizes the function of the LCD driver can be protected from static electricity.

  Hereinafter, configuration examples of the input protection circuit 3 and the output protection circuit 4 will be described. FIG. 2 is a diagram illustrating a configuration example of the input protection circuit 3 provided between the input bump electrode IBMP and the internal circuit IU. In FIG. 2, the input protection circuit 3 is connected between the input bump electrode IBMP and the internal circuit IU. That is, the input bump electrode IBMP and the internal circuit IU are electrically connected via the input protection circuit 3. The internal circuit IU indicates, for example, a circuit including the control unit 1 and the SRAMs 2a and 2b. As shown in FIG. 2, the input protection circuit 3 includes a diode D1 and a diode D2. The anode of the diode D1 is connected to the ground potential Vss, and the cathode of the diode D1 is connected to the point A connecting the input bump electrode IBMP and the internal circuit IU. On the other hand, the anode of the diode D2 is connected to the point A, and the cathode of the diode D2 is connected to the power supply potential Vdd. The input protection circuit 3 is configured as described above, and the operation thereof will be described below.

  First, the normal operation will be described. When an input voltage is applied to the input bump electrode IBMP, the potential of the terminal A becomes a predetermined potential. At this time, the potential of the terminal A is larger than the ground potential Vss and smaller than the power supply potential Vdd. Therefore, considering the diode D1, since the cathode of the diode D1 (potential of the terminal A) is higher than the anode of the diode D1 (ground potential Vss), no current flows through the diode D1. Similarly, considering the diode D2, since the cathode (power supply potential Vdd) of the diode D2 is higher than the anode of the diode D2 (potential of the terminal A), no current flows through the diode D2. In this way, during normal operation, no current flows through the diode D1 and the diode D2, and therefore the input voltage (input signal) input to the input bump electrode IBMP is output to the internal circuit IU.

  Next, the operation at the time of abnormality will be described. For example, consider a case where a surge voltage is applied to the input bump electrode IBMP due to the influence of static electricity or the like. Specifically, when a positive voltage larger than the power supply potential Vdd is applied as the surge voltage, a positive potential larger than the power supply potential Vdd is applied to the terminal A to which the cathode of the diode D1 is connected. For this reason, a large reverse voltage is applied to the diode D1, causing breakdown, and a reverse current flows from the terminal A toward the ground potential Vss. On the other hand, since a positive potential larger than the power supply potential Vdd is applied to the anode of the diode D2, a forward current flows from the terminal A toward the power supply potential Vdd through the diode D2. Thus, when a positive voltage larger than the power supply potential Vdd is applied as the surge voltage, the diode D1 breaks down in the reverse direction and the diode D2 is turned on in the forward direction. Can be pulled out to the power line or ground line. As a result, it is possible to prevent a high voltage from being applied to the internal circuit IU and being destroyed.

  Similarly, when a negative voltage whose absolute value is larger than the ground potential Vss is applied as the surge voltage, a negative potential smaller than the ground potential Vss is applied to the terminal A to which the cathode of the diode D1 is connected. Therefore, a forward voltage is applied to the diode D1, and a forward current flows from the ground potential Vss toward the terminal A. On the other hand, since a large negative potential is applied to the anode of the diode D2, a large reverse voltage is applied to the diode D2, causing breakdown, and a reverse current flows from the power supply potential Vdd toward the terminal A. Thus, when a large negative voltage is applied as the surge voltage, the diode D2 breaks down in the reverse direction and the diode D1 is turned on in the forward direction. Can be pulled out. As a result, it is possible to prevent a high voltage from being applied to the internal circuit IU and being destroyed.

  FIG. 3 is a diagram showing another configuration example of the input protection circuit 3 provided between the input bump electrode IBMP and the internal circuit IU. In FIG. 3, the input protection circuit 3 is connected between the input bump electrode IBMP and the internal circuit IU. That is, the input bump electrode IBMP and the internal circuit IU are electrically connected via the input protection circuit 3. The internal circuit IU indicates, for example, a circuit including the control unit 1 and the SRAMs 2a and 2b. As shown in FIG. 3, the input protection circuit 3 has an n-channel MISFET Tr1 and a p-channel MISFET Tr2. In the n-channel type MISFET Tr1, the drain region is connected to the terminal A, and the source region and the gate electrode are connected to the ground potential Vss. On the other hand, in the p-channel type MISFET Tr2, the drain region is connected to the terminal A, and the source region and the gate electrode are connected to the power supply potential Vdd.

  Even in the input protection circuit 3 configured as described above, when a surge voltage is applied to the terminal A from the outside, one of the n-channel type MISFET Tr1 and the p-channel type MISFET Tr2 is turned on according to the polarity of the surge voltage. The other causes breakdown between the source region and the drain region. Thereby, the electric charge accompanying a surge voltage can be extracted to a power supply line or a ground line. As a result, it is possible to prevent a high voltage from being applied to the internal circuit IU and being destroyed. As described above, the configuration example of the input protection circuit 3 has been described, but the output protection circuit 4 has the same configuration as the input protection circuit 3.

  The main functions of the LCD driver are realized by the above-described functional blocks, and these functional blocks are arranged so as to be aligned in the long side direction of the rectangular semiconductor chip CHP, for example, as shown in FIG. . Each functional block constituting the LCD driver is composed of a MISFET formed on a semiconductor substrate and a multilayer wiring formed on the MISFET. At this time, for example, the SRAM control unit and the LCD control unit are formed from a digital circuit, and the analog unit is formed from an analog circuit. The SRAM control unit and the LCD control unit are formed of a digital circuit. The MISFET constituting the digital circuit is formed of a low withstand voltage MISFET having a low operating voltage absolute value. That is, the SRAM control unit and the LCD control unit are composed of logic circuits (logic circuits), and the degree of integration is improved. For this reason, the miniaturization of the MISFET has progressed, and the absolute value of the operating voltage of the MISFET has become lower with the miniaturization of the MISFET. Therefore, the SRAM control unit and the LCD control unit use a low withstand voltage MISFET having the lowest absolute value of the operating voltage among the LCD drivers. For example, the absolute value of the operating voltage of the low withstand voltage MISFET used in the LCD control unit is about 1.5V.

  On the other hand, the analog portion is composed of an analog circuit, and the MISFET constituting the analog circuit is composed of a high voltage MISFET whose absolute value of the operating voltage is relatively higher than that of the low voltage MISFET. This is because the analog circuit has a function of converting the voltage level of the image data and applying a medium-high voltage (several tens of volts) to the liquid crystal display cell. As described above, a plurality of types of MISFETs having different operating voltage absolute values are formed in the semiconductor chip CHP constituting the LCD driver. In particular, in the SRAM control unit and the LCD control unit, the absolute value of the operating voltage is the highest. A low low voltage MISFET is used. On the other hand, in the analog portion, a high voltage MISFET having a relatively high absolute value of the operating voltage is used. The MISFET used in the input protection circuit 3 or the output protection circuit 4 is also a high voltage MISFET. The absolute value of the operating voltage of these high voltage MISFETs is, for example, about 20-30V.

  Next, a simple operation of the LCD driver will be described. First, serial data for displaying an image is input from a microcomputer or the like mounted outside the LCD driver (semiconductor chip CHP1). This serial data is input to the LCD controller via the I / O circuit. The LCD control unit that receives the serial data converts the serial data into parallel data based on the clock signal generated by the clock circuit. Then, in order to store the converted parallel data in the SRAMs 2a and 2b, a control signal is output to the SRAM control unit. In the SRAM control unit, when a control signal is input from the LCD control unit, the word driver is operated to store image data as parallel data in the SRAMs 2a and 2b. At a predetermined timing, the image data stored in the SRAMs 2a and 2b is read and output to the analog unit. The analog unit converts the voltage level of the image data (parallel data) and outputs it from the LCD driver. Image data (parallel data) output from the LCD driver is applied to each liquid crystal display cell to display an image. Thus, an image can be displayed on the liquid crystal display device by the LCD driver.

  In the semiconductor chip CHP1 constituting the general LCD driver shown in FIG. 1, the input bump electrode IBMP is formed along the long side LS1, and the output bump electrode OBMP is formed along the long side LS2. At this time, the number of output bump electrodes OBMP arranged along the long side LS2 is the same as the number of matrix lines (for example, gate lines and source lines) for driving the cells, and the long side LS1. Is larger than the number of input bump electrodes IBMP arranged along. Therefore, the length in the long side direction of the semiconductor chip CHP constituting the LCD driver is substantially defined by the number of output bump electrodes OBMP having a large number. Therefore, it is difficult to reduce the length in the long side direction of the semiconductor chip CHP constituting the LCD driver when the number of output bump electrodes OBMP is defined. Furthermore, if the arrangement of the output bump electrodes OBMP arranged in the long side direction of the LCD driver is changed, it is necessary to change the layout of the wiring connecting the LCD driver and the display unit of the liquid crystal display device on which the LCD driver is mounted. There is. Usually, an LCD driver is delivered to a manufacturer that manufactures a display unit of a liquid crystal display device, and the LCD driver is mounted on the liquid crystal display device. At this time, since the manufacturer that manufactures the liquid crystal display device does not want to change the configuration of the display unit, the arrangement of the output bump electrodes OBMP arranged in the long side direction of the LCD driver is defined in advance. For this reason, it is difficult to change the arrangement and number of output bump electrodes OBMP formed in the LCD driver. For this reason as well, it is difficult to reduce the long side of the semiconductor chip CHP constituting the LCD driver. Nevertheless, with the miniaturization of semiconductor elements, it is desired to reduce the chip size of the semiconductor chip CHP constituting the LCD driver. Therefore, in order to reduce the size of the semiconductor chip CHP1 constituting the LCD driver, reduction in the short side direction of the semiconductor chip CHP1 has been studied. Hereinafter, a technical idea capable of reducing the length in the short side direction of the semiconductor chip CHP1 constituting the LCD driver by devising the layout configuration of the semiconductor chip CHP1 will be described.

  FIG. 4 is a diagram showing a layout configuration of the semiconductor chip CHP2 in the first embodiment. 4, the semiconductor chip CHP2 in the first embodiment includes a pair of short sides SS1 and short sides SS2, and a pair of long sides LS1 and long sides LS2, similarly to the general semiconductor chip CHP1 shown in FIG. Has a rectangular shape. An input bump electrode IBMP is disposed along the long side LS1, and the input bump electrode IBMP is disposed at a position closer to the long side LS1 than the long side LS2 facing the long side LS1. On the other hand, the output bump electrode OBMP is disposed along the long side LS2, and the output bump electrode OBMP is disposed at a position closer to the long side LS2 than the long side LS1 facing the long side LS2. Further, the semiconductor chip CHP2 in the first embodiment includes a control unit 1, SRAMs 2a to 2c, input protection circuits 3a to 3c, and an output protection circuit 4 like the general semiconductor chip CHP1 shown in FIG. Yes. The input protection circuits 3a to 3c are configured to protect the internal circuit from static electricity and to be electrically connected to the plurality of input bump electrodes IBMP. The output protection circuit 4 also protects the internal circuit from static electricity, In addition, it is configured to be electrically connected to a plurality of output bump electrodes OBMP.

  Here, the difference between the semiconductor chip CHP2 in the first embodiment shown in FIG. 4 and the general semiconductor chip CHP1 shown in FIG. 1 will be described. First, in the general semiconductor chip CHP1 shown in FIG. 1, the output bump electrode OBMP is formed along the long side LS2, and the output protection circuit 4 is formed in a lower layer overlapping the output bump electrode OBMP in a plane. Has been. In other words, the output protection circuit 4 is arranged along the long side LS2, similarly to the output bump electrode OBMP. SRAMs 2 a and 2 b and a control unit 1 are formed in the central portion of the semiconductor chip CHP 1 adjacent to the output protection circuit 4. Specifically, the SRAMs 2a and 2b and the control unit 1 are arranged so as to be aligned in the long side direction. Subsequently, the input bump electrode IBMP is formed along the long side LS1 facing the long side LS2 of the semiconductor chip CHP1, and the input protection circuit 3 is formed in a lower layer overlapping the input bump electrode IBMP in a plane. Has been. Therefore, the functional block functioning as the LCD driver includes an output protection circuit 4 formed along the long side LS2, an input protection circuit 3 formed along the long side LS1, an output protection circuit 4, and an input protection circuit 3 SRAM 2a, 2b and a control unit 1 formed in the central part between the two. In other words, in the semiconductor chip CHP1, a region along the long side LS2 is defined as an upper block, a region along the long side LS1 is defined as a lower block, and a region sandwiched between the upper block and the lower block is defined as a central block. In the semiconductor chip CHP1, the output protection circuit 4 is formed in the upper block, and the SRAMs 2a and 2b and the control unit 1 are formed in the central block. An input protection circuit 3 is formed in the lower block. Therefore, in a general LCD driver, the length in the short side direction is formed in the output protection circuit 4 formed in the upper block, the SRAMs 2a and 2b formed in the central block, the control unit 1, and the lower block. The input protection circuit 3 is defined.

  On the other hand, in the semiconductor chip CHP2 in the first embodiment shown in FIG. 4, the output bump electrode OBMP is formed along the long side LS2, and the output is output to the lower layer overlapping the output bump electrode OBMP in a plane. A protection circuit 4 is formed. In other words, the output protection circuit 4 is arranged along the long side LS2, similarly to the output bump electrode OBMP. The SRAMs 2a to 2c, the control unit 1, and the input protection circuits 3a to 3c are formed in the central portion of the semiconductor chip CHP2 adjacent to the output protection circuit 4. That is, in the semiconductor chip CHP2 in the first embodiment, the output protection circuit 4 is formed in the upper block along the long side LS2, and the SRAMs 2a to 2c, the control unit 1, and the input protection circuit are arranged in the central block adjacent to the upper block. 3a to 3c are formed. That is, in the semiconductor chip CHP1 constituting the general LCD driver shown in FIG. 1, the output protection circuit 4, the SRAMs 2a and 2b, the control unit 1 and the input protection circuit 3 are arranged in three stages: an upper block, a central block and a lower block. In contrast to the separate arrangement, in the semiconductor chip CHP2 constituting the LCD driver in the first embodiment, the output protection circuit 4, the SRAMs 2a to 2c, the control unit 1, and the input protection circuits 3a to 3c are the upper block. The difference is that it includes a region arranged separately in two stages of the central block. Here, focusing on the arrangement area of the control unit 1 and the input protection circuit 3c, the output protection circuit 4, the control unit 1, and the input protection circuit 3c seem to be configured in three stages, but the SRAM 2a When the length in the short side direction of ˜2c is considered as the length in the short side direction of the central block, the length in the short side direction of the control unit 1 and the input protection circuit 3c is the length in the short side direction of the SRAMs 2a to 2c. Therefore, it can be considered that the control unit 1 and the input protection circuit 3c are substantially formed within the range of the central block defined by the length in the short side direction of the SRAMs 2a to 2c. Therefore, in the first embodiment, even in the layout configuration shown in FIG. 4, the output protection circuit 4, the SRAMs 2a to 2c, the control unit 1, and the input protection circuits 3a to 3c are divided into two stages of an upper block and a central block. It is expressed as being arranged. Alternatively, in consideration of the arrangement area of the control unit 1 and the input protection circuit 3c that can be regarded as being divided into three stages, in the first embodiment, the output protection circuit 4, the SRAMs 2a to 2c, the control unit 1 and It can also be said that a part of the input protection circuits 3a to 3c is arranged separately in two stages of the upper block and the central block.

  As described above, the semiconductor chip CHP2 constituting the LCD driver according to the first embodiment is characterized in that the output protection circuit 4, the SRAMs 2a to 2c, the control unit 1 and the input protection circuits 3a to 3c are the upper block, the central block, and the lower block. Rather than being arranged in three stages, it is arranged in two stages of an upper block and a central block. In other words, in the first embodiment, the input protection circuits 3a to 3c are not arranged in the lower block along the long side LS1, but are arranged in a part of the central block in which the SRAMs 2a to 2c and the control unit 1 are arranged. It is characterized in that the input protection circuits 3a to 3c are arranged. Thereby, according to the semiconductor chip CHP2 in the first embodiment, the length in the short side direction can be reduced. That is, in the semiconductor chip CHP1 constituting the general LCD driver shown in FIG. 1, the upper block, the central block, and the lower block are arranged along the short side direction, and the upper block, the central block, and the lower block 3 are arranged. The length in the short side direction is determined by the area occupied by the step. On the other hand, according to the semiconductor chip CHP2 in the first embodiment shown in FIG. 4, the upper block and the central block are arranged along the short side direction, and the area occupied by the upper block and the central block is two steps. Thus, the length in the short side direction is determined. That is, in the semiconductor chip CHP2 shown in FIG. 4, there is no lower block present in the semiconductor chip CHP1 shown in FIG. Therefore, in the semiconductor chip CHP2 shown in FIG. 4, the length in the short side direction can be shortened by the amount where the lower block is not arranged. As a result, the semiconductor chip CHP2 in the first embodiment has a remarkable effect that the length in the short side direction can be reduced.

  In the first embodiment, the length of the semiconductor chip CHP2 in the short side direction is reduced by devising the arrangement positions of the input protection circuits 3a to 3c. Specifically, as shown in FIG. 4, the input protection circuits 3 a to 3 c are not arranged along the long side LS <b> 1 where the input bump electrodes IBMP are arranged side by side. For example, the input protection circuit 3a is formed between the SRAM 2a and the SRAM 2b, and the input protection circuit 3b is formed between the SRAM 2b and the SRAM 2c. The input protection circuit 3c is formed between the control unit 1 and the long side LS1. As a result, all of the input protection circuits 3a to 3c are not formed in the lower layer overlapping the input bump electrode IBMP in a plane. That is, in the first embodiment, as shown in FIG. 4, the input protection circuits 3a to 3c and the SRAMs 2a to 2c are formed below the input bump electrode IBMP disposed along the long side LS1. become. For this reason, in the first embodiment, the input protection circuits 3a to 3c are arranged below a part of the input bump electrodes IBMP among the plurality of input bump electrodes IBMP, while the plurality of input bump electrodes The SRAMs 2a to 2c (internal circuits) are arranged without the input protection circuits 3a to 3c being arranged below the other input bump electrodes IBMP of the IBMP. In particular, in the first embodiment, the number of some input bump electrodes IBMP in which the input protection circuits 3a to 3c are arranged in the lower layer is the same as that of the other one in which the input protection circuits 3a to 3c are not arranged in the lower layer. This is smaller than the number of input bump electrodes IBMP.

  In other words, the feature in the first embodiment is an internal region sandwiched between a region where a plurality of input bump electrodes IBMP are formed and a region where a plurality of output bump electrodes OBMP are formed. It can also be said that a part of the input protection circuits 3a and 3b is arranged. Furthermore, it can be said that a part of the input protection circuits 3a to 3c is formed in a region that does not overlap with the plurality of input bump electrodes IBMP, and is adjacent to the SRAMs 2a to 2c in the long side direction. It can also be said that part of the input protection circuits 3a and 3b is formed in the region. Further, some of the input protection circuits 3a and 3b that are electrically connected to some of the plurality of input bump electrodes IBMP are planar with some of the input bump electrodes. The other input protection circuits of the plurality of input protection circuits 3a and 3b that are electrically connected to the other input bump electrodes among the plurality of input bump electrodes IBMP are It can also be said that it is arranged at a position different from the position overlapping the input bump electrode in plan view.

  In the first embodiment, the input protection circuit 3a and the input protection circuit 3b are arranged between the SRAMs 2a to 2c. In this way, the input protection circuit 3a and the input protection circuit 3b are arranged between the SRAMs 2a to 2c. The problem is whether there is just enough space. This is because, normally, in order to reduce the size of the semiconductor chip CHP2, it is considered that the length of the semiconductor chip CHP2 in the long side direction does not leave an extra space. However, in practice, a space enough to insert the input protection circuit 3a and the input protection circuit 3b can be secured between the SRAMs 2a to 2c. The reason for this will be described.

  The length in the long side direction of the semiconductor chip CHP2 is also reduced as much as possible, but the length in the long side direction is defined by the output bump electrode OBMP arranged along the long side LS2. That is, the length in the long side direction of the semiconductor chip CHP2 is not defined by the SRAMs 2a to 2c and the control unit 1 arranged along the long side direction, but is defined by the number of output bump electrodes OBMP. . For example, from the viewpoint of reducing the length of the semiconductor chip CHP2 in the long side direction, it is conceivable to reduce the formation regions of the SRAMs 2a to 2c and the control unit 1 arranged along the long side direction as much as possible. Specifically, it is conceivable to make the space between the SRAMs 2a to 2c and the control unit 1 as small as possible. However, even if the formation regions of the SRAMs 2a to 2c and the control unit 1 are densely arranged in this way to reduce the length in the long side direction of the semiconductor chip CHP2, they are arranged along the long side LS2 of the semiconductor chip CHP2. If all the bump electrodes OBMP for output cannot be arranged, it is meaningless. Therefore, the length of the semiconductor chip CHP2 in the long side direction needs to be at least long enough to arrange all the output bump electrodes OBMP. That is, the length in the long side direction of the semiconductor chip CHP2 is determined from the viewpoint that all the output bump electrodes OBMP can be arranged.

  At this time, for example, the size relationship between the SRAMs 2a to 2c arranged in the long side direction and the length in the long side direction of the control unit 1 and the total length of the output bump electrode OBMP arranged along the long side LS2 is a problem. Actually, however, the total length of the output bump electrodes OBMP is longer than the length in which the SRAMs 2a to 2c and the control unit 1 are arranged. For this reason, if the length in the long side direction of the semiconductor chip CHP2 is determined so that all the output bump electrodes OBMP are arranged, there is an extra space in the region where the SRAMs 2a to 2c and the control unit 1 are arranged. From this, for example, a space for inserting the input protection circuit 3a and the input protection circuit 3b can be secured between the SRAMs 2a to 2c. Therefore, in the first embodiment, for example, the length of the semiconductor chip CHP2 in the short side direction can be shortened by inserting the input protection circuit 3a or the input protection circuit 3b between the SRAMs 2a to 2c. is there.

  Next, the semiconductor chip CHP2 includes an output protection circuit 4 in addition to the input protection circuits 3a to 3c. The input protection circuits 3a to 3c and the output protection circuit 4 function as an electrostatic protection circuit that protects internal circuits from static electricity. And since it functions as the same electrostatic protection circuit, it is thought that the input protection circuits 3a-3c and the output protection circuit 4 have the same structure. Therefore, it is conceivable to insert the output protection circuit 4 instead of the input protection circuits 3a and 3b in the space generated when the SRAMs 2a to 2c and the control unit 1 are arranged in the long side direction. Also in this case, if all of the output protection circuit 4 can be inserted into the extra space generated between the SRAMs 2a to 2c and the control unit 1, the length of the semiconductor chip CHP2 in the short side direction can be reduced. However, in the first embodiment, the arrangement of the input protection circuits 3a to 3c is changed without changing the arrangement of the output protection circuit 4. The reason for this will be described below.

  As shown in FIG. 4, the number of output bump electrodes OBMP is very large compared to the number of input bump electrodes IBMP. Since an output signal is output from each of the output bump electrodes OBMP, the output protection circuit 4 needs to be provided for each of the output bump electrodes OBMP. For this reason, the number of output protection circuits 4 is enormous. On the other hand, the number of input bump electrodes IBMP is smaller than the number of output bump electrodes OBMP, and it is not necessary to connect the input protection circuits 3a to 3c to all of the input bump electrodes IBMP. Among the input bump electrodes IBMP, the bump electrodes to which the input protection circuits 3a to 3c are connected are only bump electrodes for inputting an input signal (input data). For this reason, the number of input protection circuits 3 a to 3 c is smaller than the number of output protection circuits 4. This means that the entire occupied area of the input protection circuits 3a to 3c is smaller than the occupied area of the entire output protection circuit 4. That is, the space for inserting the input protection circuits 3a to 3c is smaller than the space for inserting the output protection circuit 4.

  Here, the space generated when the SRAMs 2a to 2c and the control unit 1 are arranged in the long side direction is not so large. That is, the space generated when the SRAMs 2a to 2c and the control unit 1 are arranged in the long side direction is not sufficiently formed to insert the entire output protection circuit 4. In other words, since the space generated when the SRAMs 2a to 2c and the control unit 1 are arranged in the long side direction cannot be made so large, the input protection circuits 3a to 3c, not the output protection circuit 4, are changed to the above-described space. It is decided to insert.

  Next, the second feature point in the first embodiment will be described. As shown in FIG. 4, the second feature point in the first embodiment is that the input protection circuits 3a to 3c are dispersed in the long side direction of the semiconductor chip CHP2 without being concentrated in one place. For example, it is also conceivable that the spaces generated when the SRAMs 2a to 2c and the control unit 1 are arranged in the long side direction are gathered in one place, and the input protection circuits 3a to 3c are arranged in one place. In this case, the semiconductor chip size can be reduced. However, the reason why it is more effective to dispose the input protection circuits 3a to 3c as shown in FIG. 4 will be described below.

  For example, it is necessary to electrically connect the input protection circuits 3a to 3c between the input bump electrode IBMP and the internal circuit. At this time, for example, in the semiconductor chip CHP1 constituting the general LCD driver shown in FIG. 1, since the input protection circuit 3 is formed in the lower layer overlapping the input bump electrode IBMP, the input bump electrode IBMP Can be electrically connected to the input protection circuit 3 by multilayer wiring from the input bump electrode IBMP to the lower layer. This means that it is not necessary to use a lead wiring extending in the plane direction of the semiconductor chip CHP1 in order to connect the input bump electrode IBMP to the input protection circuit 3.

  However, in the first embodiment, the input protection circuits 3a to 3c are formed in regions that do not overlap the input bump electrode IBMP in a planar manner. Therefore, in the first embodiment, in order to connect the input bump electrode IBMP and the input protection circuits 3a to 3c, it is necessary to use a lead wiring extending in the planar direction of the semiconductor chip CHP2. On the premise of this, when the input protection circuits 3a to 3c are collectively arranged at one place, the input protection circuits 3a to 3c arranged together and the bump electrode for input arranged in the long side direction of the semiconductor chip CHP2 It is necessary to connect IBMP with a lead wiring extending in the plane direction of the semiconductor chip CHP2. In this case, if the input protection circuits 3a to 3c are concentrated in one place, the layout configuration of the routing wiring becomes complicated.

  Therefore, in the first embodiment, the input protection circuits 3a to 3c are distributed and arranged on the premise that the input protection circuits 3a to 3c are formed in a region that does not overlap with the input bump electrode IBMP. . Thereby, the bump electrode IBMP for input arranged in the long side direction of the semiconductor chip CHP2 can be connected to the input protection circuits 3a to 3c arranged in a dispersed manner with the shortest distance. This can reduce the number of routing wirings connecting the input bump electrodes IBMP and the input protection circuits 3a to 3c, and the layout configuration of the routing wirings compared to the case where the input protection circuits 3a to 3c are concentrated in one place. Means that it can be simplified. Therefore, according to the first embodiment, the LCD driver is configured by the first feature point that the input protection circuits 3a to 3c are arranged in a space generated when the SRAMs 2a to 2c and the control unit 1 are arranged in the long side direction. The length in the short side direction of the semiconductor chip CHP2 to be reduced can be reduced. Then, due to the first feature point, the input protection circuits 3a to 3c are formed in regions that do not overlap with the input bump electrode IBMP, but the input protection circuits 3a to 3c are not concentrated in one place. By the second feature point that the semiconductor chip CHP2 is distributed in the long side direction, the layout configuration of the routing wiring for electrically connecting the input bump electrode IBMP and the input protection circuits 3a to 3c is simplified. Can do.

  Although it is desirable to provide the first feature point and the second feature point as in the first embodiment, the length of the semiconductor chip CHP2 in the short side direction is set even in the configuration including only the first feature point. The object of the present invention to reduce the size can be sufficiently achieved.

  Next, according to the semiconductor chip CHP2 in the first embodiment, the fact that the length of the semiconductor chip CHP2 in the short side direction can be reduced will be described using an enlarged view. FIG. 5 is an enlarged view showing a region near the long side LS1 of the semiconductor chip CHP1 constituting a general LCD driver. In FIG. 5, the X direction indicates the long side direction in which the long side LS1 of the semiconductor chip CHP1 extends, and the Y direction indicates the short side direction of the semiconductor chip CHP1. As shown in FIG. 5, two input bump electrodes IBMP1 and IBMP2 are arranged side by side along the long side LS1 of the semiconductor chip CHP1. The uppermost layer wirings TM1, TM3, and TM4 are formed below the input bump electrode IBMP1. Similarly, the uppermost layer wirings TM2, TM3, and TM4 are formed below the input bump electrode IBMP2. At this time, the uppermost layer wiring TM1 is formed only under the input bump electrode IBMP1, and the uppermost layer wiring TM2 is formed only under the input bump electrode IBMP2. On the other hand, the uppermost layer wiring TM3 and the uppermost layer wiring TM4 are formed over the lower layers of the input bump electrode IBMP1 and the input bump electrode IBMP2, and extend in the long side direction (x direction).

  The input bump electrode IBMP1 and the uppermost layer wiring TM1 are electrically connected by embedding a conductive material in the opening CNT1. The uppermost layer wiring TM1 is connected to the input protection circuit 3A through a multilayer wiring formed in the lower layer. Similarly, the input bump electrode IBMP2 and the uppermost layer wiring TM2 are electrically connected by embedding a conductive material in the opening CNT2. The uppermost layer wiring TM2 is connected to the input protection circuit 3B via a multilayer wiring formed in the lower layer. As described above, in the semiconductor chip CHP1 constituting the general LCD driver, the input protection circuits 3A and 3B are formed below the input bump electrodes IBMP1 and IBMP2. Therefore, the internal circuit IU is formed inside the input bump electrodes IBMP1 and IBMP2 (region farther from the long side LS1) so as not to overlap the input bump electrodes IBMP1 and IBMP2. Therefore, the distance between the internal circuit IU and the long side LS1 of the semiconductor chip CHP1 is the distance Y1.

  On the other hand, FIG. 6 is an enlarged view showing a region in the vicinity of the long side LS1 of the semiconductor chip CHP2 which is the LCD driver in the first embodiment. In FIG. 6, the X direction indicates the long side direction in which the long side LS1 of the semiconductor chip CHP2 extends, and the Y direction indicates the short side direction of the semiconductor chip CHP2. As shown in FIG. 6, two input bump electrodes IBMP1 and IBMP2 are arranged side by side along the long side LS1 of the semiconductor chip CHP2. The uppermost layer wirings TM1, TM3, and TM4 are formed below the input bump electrode IBMP1. Similarly, the uppermost layer wirings TM2, TM3, and TM4 are formed below the input bump electrode IBMP2. At this time, the uppermost layer wiring TM1 is formed only under the input bump electrode IBMP1, and the uppermost layer wiring TM2 is formed only under the input bump electrode IBMP2. On the other hand, the uppermost layer wiring TM3 and the uppermost layer wiring TM4 are formed over the lower layers of the input bump electrode IBMP1 and the input bump electrode IBMP2, and extend in the long side direction (x direction).

  The input bump electrode IBMP1 and the uppermost layer wiring TM1 are electrically connected by embedding a conductive material in the opening CNT1, but in the first embodiment, the input protection circuit is provided below the uppermost layer wiring TM1. Not formed. Similarly, the input bump electrode IBMP2 and the uppermost layer wiring TM2 are electrically connected by embedding a conductive material in the opening CNT2, but in the first embodiment, the input is input to the lower layer of the uppermost layer wiring TM2. A protection circuit is not formed. In the first embodiment, the input protection circuit (not shown in FIG. 6) is formed in a region that does not overlap the input bump electrodes IBMP1 and IBMP2. As described above, in the semiconductor chip CHP2 in the first embodiment, since the input protection circuit is not formed below the input bump electrodes IBMP1 and IBMP2, the internal circuit is formed below the input bump electrodes IBMP1 and IBMP2 in a plane. A part of the IU is formed. As a result, the distance between the internal circuit IU and the long side LS1 of the semiconductor chip CHP2 is the distance Y2.

  Here, comparing the distance Y1 shown in FIG. 5 with the distance Y2 shown in FIG. 6, it can be seen that the distance Y2 shown in FIG. 6 is smaller than the distance Y1 shown in FIG. This means that the semiconductor chip CHP2 shown in FIG. 6 can be made shorter in the short side direction than the semiconductor chip CHP1 shown in FIG. That is, according to the semiconductor chip CHP2 in the first embodiment, it can be seen that the length in the short side direction can be reduced as compared with the general semiconductor chip CHP1.

  Note that the input bump electrode IBMP1 in FIG. 6 corresponds to FIG. 13 in the fifth embodiment described later, and a cross-sectional view taken along the line AA in FIG. This corresponds to FIG. The device structure in the first embodiment will be described in more detail using a cross-sectional view in a fifth embodiment to be described later.

  In the first embodiment, an example in which the plurality of uppermost layer wirings TM3 and TM4 pass below the input bump electrodes IBMP1 and IBMP2 is shown, but the present invention is not limited to this, and at least one uppermost layer wiring is present. Even when passing, the same effect can be obtained. The same applies to the following embodiments.

(Embodiment 2)
In the first embodiment, for example, as shown in FIG. 4, the input protection circuits 3 a to 3 c are arranged below a part of the input bump electrodes IBMP among the plurality of input bump electrodes IBMP, The configuration in which the SRAMs 2a to 2c (internal circuits) are disposed without the input protection circuits 3a to 3c being disposed below the other input bump electrodes IBMP among the plurality of input bump electrodes IBMP has been described. .

  In the second embodiment, an example in which no input protection circuit is formed below all the input bump electrodes IBMP will be described.

  FIG. 7 is a diagram showing a layout configuration of the semiconductor chip CHP2 in the second embodiment. In FIG. 7, the semiconductor chip CHP2 in the second embodiment is similar to the semiconductor chip CHP2 in the first embodiment shown in FIG. 4 in that a pair of short sides SS1 and short sides SS2 and a pair of long sides LS1 and long sides. It has a rectangular shape with LS2. An input bump electrode IBMP is disposed along the long side LS1, and an output bump electrode OBMP is disposed along the long side LS2. Furthermore, the semiconductor chip CHP2 in the second embodiment includes a control unit 1, SRAMs 2a and 2b, input protection circuits 3a and 3b, and an output protection circuit 4.

  At this time, also in the second embodiment, the input protection circuits 3a and 3b are formed in a space generated when the SRAMs 2a and 2b and the control unit 1 are arranged in the long side direction. However, the input protection circuits 3a and 3b formed in this space are formed so as not to planarly overlap with the input bump electrodes IBMP disposed along the long side LS1. That is, in the second embodiment, unlike the first embodiment, the input protection circuit is not formed below all the input bump electrodes IBMP.

  It is also possible to configure the semiconductor chip CHP2 that constitutes the LCD driver as in the second embodiment. Also in the case of the configuration as in the second embodiment, the LCD driver is provided by the first feature that the input protection circuits 3a and 3b are arranged in a space generated when the SRAMs 2a and 2b and the control unit 1 are arranged in the long side direction. It is possible to reduce the length of the semiconductor chip CHP2 constituting the short side direction. The first feature points cause the input protection circuits 3a and 3b to be formed in a region that does not overlap the input bump electrode IBMP. However, the input protection circuits 3a and 3b are not concentrated in one place. The layout configuration of the routing wiring for electrically connecting the input bump electrode IBMP and the input protection circuits 3a and 3b is simplified by the second feature that the semiconductor chip CHP2 is distributed in the long side direction. Can do. That is, the same effects as those of the first embodiment can be obtained by the layout configuration according to the second embodiment.

(Embodiment 3)
In the first embodiment, as shown in FIG. 4, the LCD has the first feature that the input protection circuits 3a to 3c are arranged in a space generated when the SRAMs 2a to 2c and the control unit 1 are arranged in the long side direction. The length in the short side direction of the semiconductor chip CHP2 constituting the driver is reduced. Therefore, in the first embodiment, the input protection circuits 3a to 3c are formed in regions that do not overlap the input bump electrode IBMP in a plan view. For this reason, in the first embodiment, in order to connect the input bump electrode IBMP and the input protection circuits 3a to 3c, it is necessary to use the lead wiring extending in the planar direction of the semiconductor chip CHP2. In this case, the wiring layout of the semiconductor chip CHP2 becomes complicated unless the layout configuration of the routing wiring is devised.

  Therefore, in the third embodiment, a technical idea that can efficiently use the lead wiring extending in the planar direction of the semiconductor chip CHP2 will be described. In other words, in the third embodiment, when the input protection circuits 3a to 3c are formed in regions that do not overlap with the input bump electrode IBMP, the input bump electrodes IBMP and the input protection circuits 3a to 3c are electrically connected. The wiring layout connected to is devised. Below, the some device in this Embodiment 3 is demonstrated.

  First, the first device point in the third embodiment will be described. FIG. 8 is a diagram for explaining the first device point in the third embodiment. In FIG. 8, the X direction indicates the long side direction in which the long side LS1 of the semiconductor chip CHP2 extends, and the Y direction indicates the short side direction of the semiconductor chip CHP2. As shown in FIG. 8, along the long side LS1 of the semiconductor chip CHP2, three input bump electrodes IBMP1, input bump electrodes IBMP2, and input bump electrodes IBMP3 are arranged side by side.

  Here, the first device point in the third embodiment is, for example, the uppermost layer wiring TM1 that is electrically connected to the input bump electrodes IBMP1 to IBMP3 and connected to the input protection circuit 3, and the input bump electrode IBMP1. This is a connection method with IBMP3. Specifically, as shown in FIG. 8, the input bump electrode IBMP1 and the uppermost layer wiring TM1 are connected by a conductive material embedded in the opening CNT1, and the input bump electrode IBMP2 and the uppermost layer wiring TM1 are opened. They are connected by a conductive material embedded in the part CNT2. The input bump electrode IBMP3 and the uppermost layer wiring TM1 are connected by a conductive material embedded in the opening CNT3. At this time, the first device point is that the formation positions of the openings CNT1 to CNT3 are different.

  In other words, in addition to the uppermost layer wiring TM1, another uppermost layer wiring may be disposed below the input bump electrodes IBMP1 to IBMP3. In this case, if the formation positions of the openings CNT1 to CNT3 with respect to the input bump electrodes IBMP1 to IBMP3 are made the same, the arrangement of other uppermost layer wirings may be disturbed. Therefore, according to the first device point in the third embodiment shown in FIG. 8, the formation position of the opening CNT1 with respect to the input bump electrode IBMP1, the formation position of the opening CNT2 with respect to the input bump electrode IBMP2, and the input bump electrode The formation position of the opening CNT3 with respect to the IBMP3 is made different. As a result, the lower layer of the input bump electrodes IBMP1 to IBMP3 is extended and connected to the input protection circuit 3 without interfering with another uppermost layer wiring disposed under the input bump electrodes IBMP1 to IBMP3. The upper layer wiring TM1 can be formed.

  For example, as shown in FIG. 8, the opening CNT1 connected to the input bump electrode IBMP1 is formed at a position closest to the long side LS1 of the semiconductor chip CHP2, and the opening CNT3 connected to the input bump electrode IBMP3 is formed. Is formed at a position farthest from the long side LS1 of the semiconductor chip CHP2.

  In FIG. 8, since the bump electrodes IBMP1 to IBMP3 for input are connected by the uppermost layer wiring TM1, the bump electrodes have the same function. As such a bump electrode, for example, a bump electrode for a power source (Vcc, Vdd) can be exemplified. The present invention can also be applied to the case where the input bump electrodes IBMP2 and IBMP3 are used as dummy bump electrodes. That is, when bump electrodes of the same application are adjacent to each other, they can be shared by the uppermost layer wiring TM1 as shown in FIG.

  Next, the second device point in the third embodiment will be described. FIG. 9 is a diagram for explaining the second device point in the third embodiment. In FIG. 9, the X direction indicates the long side direction in which the long side LS1 of the semiconductor chip CHP2 extends, and the Y direction indicates the short side direction of the semiconductor chip CHP2. As shown in FIG. 9, along the long side LS1 of the semiconductor chip CHP2, three input bump electrodes IBMP1, input bump electrodes IBMP2, and input bump electrodes IBMP3 are arranged side by side. The uppermost layer wirings TM1 to TM3 are arranged below the input bump electrodes IBMP1 to IBMP3, and these uppermost layer wirings TM1 to TM3 are connected to the input protection circuit 3.

  Here, the input bump electrode IBMP1 and the uppermost layer wiring TM1 are connected by a conductive material embedded in the opening CNT1, and the input bump electrode IBMP2 and the uppermost layer wiring TM2 are connected by a conductive material embedded in the opening CNT2. Connected. Further, the input bump electrode IBMP3 and the uppermost layer wiring TM3 are connected by a conductive material embedded in the opening CNT3. This is the second device point in the third embodiment.

  That is, the second contrivance point in the third embodiment is that different uppermost layer wirings TM1 to TM3 are connected to the different input bump electrodes IBMP1 to IBMP3, and the openings CNT1 to CNT3 with respect to the input bump electrodes IBMP1 to IBMP3. This is in the point of changing the formation position. Thus, by forming the openings CNT1 to CNT3 connected to the different input bump electrodes IBMP1 to IBMP3 at different positions, the uppermost layer wirings without changing the wiring layout of the uppermost layer wirings TM1 to TM3. TM1 to TM3 and the respective input bump electrodes IBMP1 to IBMP3 can be efficiently connected.

  Specifically, due to the second contrivance in the third embodiment, the uppermost wiring is connected to the input bump electrode IBMP1 through the opening CNT1, passes under the input bump electrode IBMP2, and The uppermost wiring TM1 that is not connected to the input bump electrode IBMP2, the input bump electrode IBMP2, and the input bump electrode IBMP1 that pass through the input bump electrode IBMP1 are connected to the input bump electrode IBMP2. The uppermost layer wiring TM2 that is not connected is included. Further, the uppermost layer wiring includes the uppermost layer wiring TM3 that passes under the input bump electrode IBMP1 and the input bump electrode IBMP2 and is not connected to the input bump electrode IBMP1 and the input bump electrode IBMP2. .

  Next, the 3rd device point in this Embodiment 3 is demonstrated. FIG. 10 is a diagram for explaining a third device point in the third embodiment. In FIG. 10, the X direction indicates the long side direction in which the long side LS1 of the semiconductor chip CHP2 extends, and the Y direction indicates the short side direction of the semiconductor chip CHP2. As shown in FIG. 10, along the long side LS1 of the semiconductor chip CHP2, three input bump electrodes IBMP1, input bump electrodes IBMP2, and input bump electrodes IBMP3 are arranged side by side. The uppermost layer wirings TM1 to TM3 are arranged below the input bump electrodes IBMP1 to IBMP3. Of these uppermost layer wirings TM1 to TM3, the uppermost layer wiring TM3 is connected to the input protection circuit 3. Yes.

  Here, the input bump electrode IBMP1 and the uppermost layer wiring TM1 are connected by a conductive material embedded in the opening CNT1, and the input bump electrode IBMP2 and the uppermost layer wiring TM2 are connected by a conductive material embedded in the opening CNT2. Connected. The input bump electrode IBMP3 and the uppermost layer wiring TM3 are connected by a conductive material embedded in the opening CNT3b. Further, the input bump electrode IBMP3 is also connected to the uppermost layer wiring TM1 through a conductive material embedded in the opening CNT3a. That is, the third device in the third embodiment is that it is connected to a plurality of different uppermost layer wirings TM1 and TM3, for example, like the input bump electrode IBMP3. Specifically, two openings CNT3a and CNT3b are connected to the input bump electrode IBMP3. The input bump electrode IBMP3 and the uppermost layer wiring TM1 are connected via a conductive material embedded in the opening CNT3a, and the input bump electrode IBMP3 and the uppermost layer are connected via a conductive material embedded in the opening CNT3b. The wiring TM3 is connected.

  That is, the third device of the third embodiment is that the input bump electrode IBMP3 has a function of connecting the uppermost layer wiring TM1 and the uppermost layer wiring TM3. That is, in the third device, the input bump electrode IBMP3 functions as a wiring for connecting the uppermost layer wiring TM1 and the uppermost layer wiring TM3. Accordingly, it is not necessary to form another wiring for connecting the uppermost layer wiring TM1 and the uppermost layer wiring TM3, and the wiring layout can be simplified.

  As shown in FIG. 10, it is not necessary to provide a plurality of openings in all of the input bump electrodes IBMP1 to IBMP3, and input bump electrodes (input input) connected to one opening according to the wiring layout. The bump electrodes IBMP1, IBMP2) and the input bump electrodes (input bump electrodes IBMP3) connected to the plurality of openings can be mixed. Further, in FIG. 10, for example, the input bump electrode IBMP3 is configured to be connected to the two openings CNT3a and 3b, but is not limited thereto, and is connected to three or more openings. You may comprise.

  As described above, in the third embodiment, the first contrivance point to the third contrivance point are applied to the wiring layout that electrically connects the input bump electrode IBMP and the input protection circuits 3a to 3c. Below, the example of a wiring layout which took in the 1st device point-the 3rd device point is explained. FIG. 11 is a diagram showing a wiring layout example in the third embodiment. In FIG. 11, the X direction indicates the long side direction in which the long side LS1 of the semiconductor chip CHP2 extends, and the Y direction indicates the short side direction of the semiconductor chip CHP2. As shown in FIG. 11, five input bump electrodes IBMP1 to IBMP5 are arranged side by side along the long side LS1 of the semiconductor chip CHP2. The uppermost layer wirings TM1a to TM3b are arranged below the input bump electrodes IBMP1 to IBMP5. Among these uppermost layer wirings TM1a to TM3b, the uppermost layer wiring TM2a is connected to the input protection circuit 3. Yes.

  First, the uppermost layer wirings TM1a, TM2a, and TM3a are arranged below the input bump electrode IBMP1, and the input bump electrode IBMP1 is connected to the uppermost layer wiring TM1a via a conductive material embedded in the opening CNT1. Electrically connected.

  Next, the uppermost layer wirings TM1b, TM2a, TM3a are arranged below the input bump electrode IBMP2. The input bump electrode IBMP2 is connected to the opening CNT2a and the opening CNT2b, and the input bump electrode IBMP2 is electrically connected to the uppermost layer wiring TM1b by a conductive material embedded in the opening CNT2a. In addition, the input bump electrode IBMP2 is electrically connected to the uppermost layer wiring TM3a by a conductive material embedded in the opening CNT2b. In other words, the input bump electrode IBMP2 is connected to two different uppermost layer wirings TM1b and TM3a, and the third device is used for the configuration of the input bump electrode IBMP2.

  Subsequently, the uppermost layer wirings TM1b and TM2a are disposed below the input bump electrode IBMP3, and the input bump electrode IBMP3 is connected to the uppermost layer wiring TM2a via a conductive material embedded in the opening CNT3. Electrically connected. Here, paying attention to the input bump electrode IBMP1 and the input bump electrode IBMP3, the positions of the opening CNT1 connected to the input bump electrode IBMP1 and the opening CNT3 connected to the input bump electrode IBMP3 are different. The uppermost layer wiring TM1a connected to the input bump electrode IBMP1 is different from the uppermost layer wiring TM2a connected to the input bump electrode IBMP3. That is, in the configuration of the input bump electrode IBMP1 and the input bump electrode IBMP3, the second device point in the third embodiment is used.

  Next, the uppermost layer wirings TM1b, TM2b, and TM2a are arranged below the input bump electrode IBMP4, and the input bump electrode IBMP4 passes through the conductive material embedded in the opening CNT4a. The wiring TM2b is connected to the uppermost layer wiring TM2a by a conductive material embedded in the opening CNT4b. Therefore, the third device point in the third embodiment is also used in the configuration of the input bump electrode IBMP4. Further, paying attention to the input bump electrode IBMP3 and the input bump electrode IBMP4, the input bump electrode IBMP3 and the input bump electrode IBMP4 are connected to the same uppermost layer wiring TM2a and have an opening CNT3 with respect to the input bump electrode IBMP3. Is different from the formation position of the opening CNT4b with respect to the input bump electrode IBMP4. Therefore, the first device point in the third embodiment is used for this configuration.

  Subsequently, the uppermost layer wirings TM1b, TM2b, and TM3b are disposed below the input bump electrode IBMP5. The input bump electrode IBMP5 is connected to the uppermost layer wiring through the conductive material embedded in the opening CNT5. It is electrically connected to TM3b. The wiring layout example shown in FIG. 11 is configured as described above, and it can be seen that the wiring layout is made by using the first to third device points in the third embodiment. By configuring the wiring layout in this way, the uppermost layer wirings TM1a to TM3b can be efficiently arranged for the input bump electrodes IBMP1 to IBMP5, so that the wiring layout can be simplified.

  Note that the technique disclosed in the third embodiment is also effective when the input protection circuits 3a to 3c are formed in a region overlapping the input bump electrode IBMP in a planar manner as in the prior art. Of course, similar effects can be obtained when used in combination with the first and second embodiments.

(Embodiment 4)
In the fourth embodiment, an example will be described in which the shape of the input bump electrode and the shape of the output bump electrode are not the same shape but different shapes.

  The technical idea described in the third embodiment relates to the connection configuration between the input bump electrode and the uppermost layer wiring, but the first device point to the third device point described in the third embodiment are effective. In order to utilize this, it is assumed that a plurality of uppermost layer wirings are arranged below the input bump electrodes. Based on this premise, in the fourth embodiment, the first device point to the third device point in the third embodiment are more useful as the number of the uppermost layer wirings arranged under the input bump electrode is increased. Focuses on technology. Therefore, in the fourth embodiment, the configuration of the input bump electrode is devised in order to make more effective use of the first to third contrivance points in the third embodiment. The technical idea in the fourth embodiment will be described below.

  FIG. 12 is an enlarged view showing the configuration of the semiconductor chip CHP2 constituting the LCD driver. In FIG. 12, the X direction indicates the long side direction in which the long sides LS1 and LS2 extend, and the Y direction indicates the short side direction. As shown in FIG. 12, a plurality of input bump electrodes IBMP are arranged along the long side LS1, and are arranged at positions facing the long side LS1 where the input bump electrodes IBMP are arranged. A plurality of output bump electrodes OBMP are arranged along the other long side LS2. The input bump electrodes IBMP are arranged in a straight line along the long side LS1, while the output bump electrodes OBMP are arranged in a zigzag pattern in two rows along the long side LS2. Therefore, the number of output bump electrodes OBMP is larger than the number of input bump electrodes IBMP.

  The feature of the fourth embodiment is that the size of the input bump electrode IBMP is not the same as the size of the output bump electrode OBMP, but is larger than the size of the output bump electrode OBMP. . More specifically, when the length in the short side direction of the input bump electrode IBMP is a and the length in the short side direction of the output bump electrode OBMP is b, the length a of the input bump electrode IBMP is It is longer than the length b of the output bump electrode OBMP. The reason why the size of the input bump electrode IBMP is increased is as follows.

  That is, increasing the length in the short side direction of the input bump electrode IBMP means that the number of uppermost wiring lines arranged in the lower layer overlapping the input bump electrode IBMP can be increased. . That is, by increasing the length of the input bump electrode IBMP in the short side direction, the number of uppermost layer wirings extending in the direction of the long side LS1 through the lower layer of the input bump electrode IBMP increases. This means that the number of uppermost layer wirings passing through the lower layer of the plurality of input bump electrodes IBMP arranged along the long side LS1 increases, and as a result, the maximum distance between the plurality of input bump electrodes IBMP is obtained. The degree of freedom of connection with the upper layer wiring increases. Further, the fact that the uppermost layer wiring passing through the lower layers of the plurality of input bump electrodes IBMP increases the potential for effectively utilizing the first to third device points described in the third embodiment. is there. Therefore, according to the fourth embodiment, by adopting a characteristic configuration in which the length a of the input bump electrode IBMP is made larger than the length b of the output bump electrode OBMP, the degree of freedom in wiring layout is achieved. There is a remarkable effect that increases.

  As described above, in the fourth embodiment, the length of the input bump electrode IBMP is increased from the viewpoint of increasing the degree of freedom of the wiring layout and effectively utilizing the first to third contrivance points in the third embodiment. The characteristic configuration is that a is larger than the length b of the output bump electrode OBMP. That is, the plane area of the input bump electrode IBMP is made larger than the plane area of the output bump electrode OBMP. By taking the characteristic configuration of the fourth embodiment, the following secondary effects are also achieved. This secondary effect will be described.

  For example, consider a case where the size of the input bump electrode IBMP is the same as the size of the output bump electrode OBMP. In this case, since the number of the input bump electrodes IBMP is smaller than the number of the output bump electrodes OBMP, the total area of the input bump electrodes IBMP is smaller than the total area of the output bump electrodes OBMP.

  The input bump electrode IBMP and the output bump electrode OBMP formed on the semiconductor chip CHP2 function as connection terminals when the semiconductor chip CHP2 as an LCD driver is mounted on the glass substrate of the liquid crystal display device. At this time, the total area of the input bump electrode IBMP is smaller than the total area of the output bump electrode OBMP. This means that the bonding area on the input bump electrode IBMP side is equal to the output bump electrode OBMP side. It means that it becomes smaller than the bonding area. For this reason, the bonding area along the long side LS1 of the semiconductor chip CHP2 (total area of the input bump electrode IBMP) and the bonding area along the long side LS2 of the semiconductor chip CHP2 (total area of the output bump electrode OBMP) ) Will be different. As a result, when the semiconductor chip CHP2 is mounted on the glass substrate, an imbalance occurs between the bonding strength at the long side LS1 of the semiconductor chip CHP2 and the bonding strength at the long side LS2 of the semiconductor chip CHP2, and the semiconductor chip CHP2 and the glass substrate There is a risk that the bonding strength of the steel will be reduced.

  On the other hand, as in the fourth embodiment, consider a case where a characteristic configuration is adopted in which the length a of the input bump electrode IBMP is made larger than the length b of the output bump electrode OBMP. In this case, the number of input bump electrodes IBMP is smaller than the number of output bump electrodes OBMP, but the size of one input bump electrode IBMP is larger than the size of one output bump electrode OBMP. Therefore, the difference between the total area of the input bump electrode IBMP and the total area of the output bump electrode OBMP is that the size of the input bump electrode IBMP is the same as the size of the output bump electrode OBMP. Compared to That is, according to the characteristic configuration of the fourth embodiment, the difference between the bonding area on the input bump electrode IBMP side and the bonding area on the output bump electrode OBMP side can be reduced. As a result, when the semiconductor chip CHP2 is mounted on the glass substrate, the imbalance between the bonding strength at the long side LS1 of the semiconductor chip CHP2 and the bonding strength at the long side LS2 of the semiconductor chip CHP2 is alleviated, so that the semiconductor chip CHP2 and the glass The bonding strength with the substrate is improved.

  In the fourth embodiment, the length in the Y direction (the short side direction of the semiconductor chip CHP) is exemplified. However, the length in the X direction (the long side direction of the semiconductor chip CHP) is used as the input bump electrode IBMP. The length of the output bump electrode OBMP is preferably the same, or the length of the input bump electrode IBMP is preferably longer than the length of the output bump electrode OBMP.

  As described above, according to the characteristic configuration of the fourth embodiment, it is possible to obtain the effect of improving the bonding strength between the semiconductor chip CHP2 and the glass substrate as well as the effect of increasing the degree of freedom of the wiring layout. is there.

  Further, the technique disclosed in the fourth embodiment is not limited to the case of the above-described third embodiment, and can be applied to the above-described first and second embodiments.

(Embodiment 5)
In the fifth embodiment, a device structure formed below the input bump electrode will be described. FIG. 13 is a diagram showing one input bump electrode IBMP1. In FIG. 13, the extending direction of the long side LS1 of the semiconductor chip CHP2 is defined as the X direction, and the short side direction of the semiconductor chip CHP2 is defined as the Y direction. As shown in FIG. 13, the input bump electrode IBMP1 has a rectangular shape, and three uppermost layer wirings TM1 to TM3 are arranged below the input bump electrode IBMP1. The input bump electrode IBMP1 is electrically connected to the uppermost layer wiring TM1 through a conductive material embedded in the opening CNT1. A device structure formed in the lower layer of the input bump electrode IBMP1 configured as described above will be described with reference to FIG.

  FIG. 14 is a cross-sectional view taken along the line AA in FIG. 13 and is a cross-sectional view showing the configuration of the semiconductor device according to the fifth embodiment. In the fifth embodiment, for example, as shown in FIG. 4 of the first embodiment, internal circuits (for example, SARMs 2a to 2c) are formed below the input bump electrodes IBMP. Therefore, n-channel MISFETs and p-channel MISFETs constituting the SRAMs 2a to 2c are formed on the semiconductor substrate below the input bump electrode IBMP. Hereinafter, the device structure will be described on the assumption that, for example, an n-channel MISFET and a p-channel MISFET constituting the SRAMs 2a to 2c are formed below the input bump electrode IBMP. That is, the semiconductor device according to the fifth embodiment includes an n-channel type MISFET Q1 and a p-channel type MISFET Q2, and the configuration of each will be described.

  An element isolation region STI for isolating elements is formed in the semiconductor substrate 1S. Of the active regions divided by the element isolation region STI, the region (inside the semiconductor substrate 1S) where the n-channel type MISFET Q1 is formed is p. A type well PWL is formed, and an n-type well NWL is formed in a region (in the semiconductor substrate 1S) where the p-channel type MISFET Q2 is to be formed.

  The n-channel MISFET Q1 has a gate insulating film GOX on the p-type well PWL formed in the semiconductor substrate 1S, and the gate electrode G1 is formed on the gate insulating film GOX. The gate insulating film GOX is formed of, for example, a silicon oxide film, and the gate electrode G1 is formed of, for example, a stacked film of a polysilicon film PF and a cobalt silicide film CS in order to reduce resistance.

However, the gate insulating film GOX is not limited to the silicon oxide film and can be variously changed. For example, the gate insulating film GOX may be a silicon oxynitride film (SiON). That is, a structure in which nitrogen is segregated at the interface between the gate insulating film GOX and the semiconductor substrate 1S may be employed. The silicon oxynitride film has a higher effect of suppressing generation of interface states in the film and reducing electron traps than the silicon oxide film. Therefore, the hot carrier resistance of the gate insulating film GOX can be improved, and the insulation resistance can be improved. In addition, the silicon oxynitride film is less likely to penetrate impurities than the silicon oxide film. For this reason, by using a silicon oxynitride film as the gate insulating film GOX, it is possible to suppress a variation in threshold voltage due to diffusion of impurities in the gate electrode toward the semiconductor substrate 1S. For example, the silicon oxynitride film may be formed by heat-treating the semiconductor substrate 1S in an atmosphere containing nitrogen such as NO, NO _2, or NH ₃ . Further, after forming a gate insulating film GOX made of a silicon oxide film on the surface of the semiconductor substrate 1S, the semiconductor substrate 1S is heat-treated in an atmosphere containing nitrogen, and nitrogen is segregated at the interface between the gate insulating film GOX and the semiconductor substrate 1S. The same effect can be obtained also by making it.

  Further, the gate insulating film GOX may be formed of a high dielectric constant film having a dielectric constant higher than that of a silicon oxide film, for example. Conventionally, a silicon oxide film has been used as the gate insulating film GOX from the viewpoint of high insulation resistance and excellent electrical and physical stability at the silicon-silicon oxide interface. However, with the miniaturization of elements, the thickness of the gate insulating film GOX is required to be extremely thin. When such a thin silicon oxide film is used as the gate insulating film GOX, a so-called tunnel current is generated in which electrons flowing through the channel of the MISFET tunnel through the barrier formed by the silicon oxide film and flow to the gate electrode.

  Therefore, by using a material having a dielectric constant higher than that of the silicon oxide film, a high dielectric constant film capable of increasing the physical film thickness even when the capacitance is the same has been used. According to the high dielectric constant film, since the physical film thickness can be increased even if the capacitance is the same, the leakage current can be reduced. In particular, the silicon nitride film is also a film having a dielectric constant higher than that of the silicon oxide film. In the fifth embodiment, it is desirable to use a high dielectric constant film having a dielectric constant higher than that of the silicon nitride film.

For example, a hafnium oxide film (HfO ₂ film), which is one of hafnium oxides, is used as a high dielectric constant film having a dielectric constant higher than that of a silicon nitride film, but instead of the hafnium oxide film, an HfAlO film (hafnium film) is used. Other hafnium-based insulating films such as aluminate film), HfON film (hafnium oxynitride film), HfSiO film (hafnium silicate film), and HfSiON film (hafnium silicon oxynitride film) can also be used. Further, a hafnium-based insulating film in which an oxide such as tantalum oxide, niobium oxide, titanium oxide, zirconium oxide, lanthanum oxide, or yttrium oxide is introduced into these hafnium-based insulating films can also be used. Since the hafnium-based insulating film has a dielectric constant higher than that of the silicon oxide film or the silicon oxynitride film, like the hafnium oxide film, the same effect as that obtained when the hafnium oxide film is used can be obtained.

  Sidewalls SW are formed on the sidewalls on both sides of the gate electrode G1, and a shallow n-type impurity diffusion region EX1 is formed as a semiconductor region in the semiconductor substrate 1S under the sidewalls SW. The sidewall SW is formed from an insulating film such as a silicon oxide film, for example. A deep n-type impurity diffusion region NR is formed outside the shallow n-type impurity diffusion region EX1, and a cobalt silicide film CS is formed on the surface of the deep n-type impurity diffusion region NR.

  The sidewall SW is formed so that the source region and the drain region, which are semiconductor regions of the n-channel type MISFET Q1, have an LDD structure. That is, the source region and the drain region of the n-channel type MISFET Q1 are formed by the shallow n-type impurity diffusion region EX1 and the deep n-type impurity diffusion region NR. At this time, the impurity concentration of the shallow n-type impurity diffusion region EX1 is lower than the impurity concentration of the deep n-type impurity diffusion region NR. Therefore, by making the source region and the drain region under the sidewall SW a low-concentration shallow n-type impurity diffusion region EX1, electric field concentration under the end of the gate electrode G1 can be suppressed.

  Next, the p-channel type MISFET Q2 has a gate insulating film GOX on the n-type well NWL formed in the semiconductor substrate 1S, and the gate electrode G2 is formed on the gate insulating film GOX. The gate insulating film GOX is formed of, for example, a silicon oxide film, and the gate electrode G2 is formed of, for example, a stacked film of a polysilicon film PF and a cobalt silicide film CS in order to reduce resistance. At this time, also in the p-channel type MISFET Q2, the gate insulating film GOX is not limited to the silicon oxide film, and similarly to the n-channel type MISFET Q1, a silicon oxynitride film or a high dielectric constant film having a higher dielectric constant than the silicon oxide film May be used.

  Sidewalls SW are formed on the sidewalls on both sides of the gate electrode G2, and a shallow p-type impurity diffusion region EX2 is formed as a semiconductor region in the semiconductor substrate 1S under the sidewalls SW. The sidewall SW is formed from an insulating film such as a silicon oxide film, for example. A deep p-type impurity diffusion region PR is formed outside the shallow p-type impurity diffusion region EX2, and a cobalt silicide film CS is formed on the surface of the deep p-type impurity diffusion region PR.

  The sidewall SW is formed so that the source region and the drain region, which are semiconductor regions of the p-channel type MISFET Q2, have an LDD structure. That is, the source region and the drain region of the p-channel type MISFET Q2 are formed by the shallow p-type impurity diffusion region EX2 and the deep p-type impurity diffusion region PR. At this time, the impurity concentration of the shallow p-type impurity diffusion region EX2 is lower than the impurity concentration of the deep p-type impurity diffusion region PR. Therefore, by making the source region and the drain region under the sidewall SW a low-concentration shallow p-type impurity diffusion region EX2, electric field concentration under the end portion of the gate electrode G2 can be suppressed.

  As described above, the n-channel MISFET Q1 and the p-channel MISFET Q2 are formed on the semiconductor substrate 1S. A contact interlayer insulating film CIL made of, for example, a silicon oxide film is formed so as to cover the n channel MISFET Q1 and the p channel MISFET Q2, and a contact hole is formed so as to penetrate the contact interlayer insulating film CIL. Yes. The contact hole is formed so as to reach the source region and drain region of the n-channel type MISFET Q1, and the source region and drain region of the p-channel type MISFET Q2, and a plug PLG1 is formed in the contact hole. The plug PLG1 is formed by embedding a barrier conductor film made of, for example, a titanium / titanium nitride film (a titanium film and a titanium nitride film formed on the titanium film) and a tungsten film in the contact hole.

  Specifically, the contact interlayer insulating film CIL includes, for example, an ozone TEOS film formed by a thermal CVD method using ozone and TEOS as raw materials, and a plasma TEOS film formed by a plasma CVD method using TEOS as raw materials. And a laminated film. Note that an etching stopper film made of, for example, a silicon nitride film may be formed under the ozone TEOS film.

  The reason for forming the contact interlayer insulating film CIL from the TEOS film is that the TEOS film is a film having a good coverage with respect to the base step. The underlayer for forming the contact interlayer insulating film CIL is an uneven state in which a MISFET is formed on the semiconductor substrate 1S. That is, since the MISFET is formed on the semiconductor substrate 1S, the gate electrode is formed on the surface of the semiconductor substrate 1S to form an uneven base. Therefore, unless the film has a good coverage with respect to uneven steps, fine unevenness cannot be embedded, which causes generation of voids and the like. Therefore, a TEOS film is used as the contact interlayer insulating film CIL. This is because in the TEOS film using TEOS as a raw material, an intermediate is formed before TEOS as a raw material becomes a silicon oxide film, and it is easy to move on the film formation surface, so that the coverage with respect to the base step is improved.

The titanium / titanium nitride film constituting the barrier conductor film is a film provided for preventing tungsten constituting the tungsten film from diffusing into silicon, and the WF when the tungsten film is constituted. _{6 In} the CVD method in which tungsten (tungsten fluoride) is reduced, the fluorine attack is prevented from being applied to the contact interlayer insulating film CIL and the semiconductor substrate 1S to cause damage.

  Next, a multilayer wiring is formed on the contact interlayer insulating film CIL in which the plug PLG1 is formed. The structure of this multilayer wiring will be described below. As shown in FIG. 14, the first layer wiring L1 is formed on the plug PLG1 formed in the contact interlayer insulating film CIL. The first layer wiring L1 is formed of, for example, a laminated film including a titanium nitride film, an aluminum film, and a titanium nitride film. An interlayer insulating film IL1 that covers the first layer wiring L1 is formed on the contact interlayer insulating film CIL on which the first layer wiring L1 is formed. The interlayer insulating film IL1 is made of, for example, a silicon oxide film. In the interlayer insulating film IL1, a plug PLG2 reaching the first layer wiring L1 is formed. The plug PLG2 is also formed by embedding a barrier conductor film made of a titanium / titanium nitride film and a tungsten film.

  Subsequently, a second layer wiring L2 is formed on the plug PLG2 formed in the interlayer insulating film IL1. The second layer wiring L2 is formed from, for example, a laminated film made of a titanium nitride film, an aluminum film, and a titanium nitride film. An interlayer insulating film IL2 that covers the second layer wiring L2 is formed on the interlayer insulating film IL1 on which the second layer wiring L2 is formed. This interlayer insulating film IL2 is formed of, for example, a silicon oxide film. A plug PLG3 reaching the second layer wiring L2 is formed in the interlayer insulating film IL2. The plug PLG3 is also formed by embedding a barrier conductor film made of a titanium / titanium nitride film and a tungsten film.

  Next, a third layer wiring L3 is formed over the plug PLG3 formed in the interlayer insulating film IL2. The third layer wiring L3 is formed of, for example, a laminated film made of a titanium nitride film, an aluminum film, and a titanium nitride film. Then, an interlayer insulating film IL3 covering the third layer wiring L3 is formed on the interlayer insulating film IL2 on which the third layer wiring L3 is formed. This interlayer insulating film IL3 is formed of, for example, a silicon oxide film. A plug PLG4 reaching the third layer wiring L3 is formed in the interlayer insulating film IL3. The plug PLG4 is also formed by embedding a barrier conductor film made of a titanium / titanium nitride film and a tungsten film.

  Subsequently, a fourth layer wiring L4 is formed on the plug PLG4 formed in the interlayer insulating film IL3. The fourth layer wiring L4 is formed of, for example, a laminated film including a titanium nitride film, an aluminum film, and a titanium nitride film. Then, an interlayer insulating film IL4 covering the fourth layer wiring L4 is formed on the interlayer insulating film IL3 on which the fourth layer wiring L4 is formed. The interlayer insulating film IL4 is made of, for example, a silicon oxide film. In the interlayer insulating film IL4, a plug PLG5 reaching the fourth layer wiring L4 is formed. The plug PLG5 is also formed by embedding a barrier conductor film made of a titanium / titanium nitride film and a tungsten film.

  As described above, multilayer wiring is formed. In the fifth embodiment, the multilayer wiring is formed from an aluminum film, but the multilayer wiring may be formed from a copper film. That is, the first layer wiring L1 to the fourth layer wiring L4 may be formed of a conductive film mainly composed of copper such as damascene wiring. That is, after forming a groove in each of the interlayer insulating films IL1 to IL4, a conductive film mainly composed of copper is formed inside and outside the groove. Thereafter, the conductive film outside the groove is polished by a CMP method (chemical mechanical polishing method) or the like, so that the conductive film can be embedded in the groove. Specifically, copper (Cu) or a copper alloy (copper (Cu) and aluminum (Al), magnesium (Mg), titanium (Ti), manganese (Mn), iron (Fe), zinc (Zn), zirconium ( Zr), niobium (Nb), molybdenum (Mo), ruthenium (Ru), palladium (Pd), silver (Ag), gold (Au), In (indium), alloys of lanthanoid metals, actinoid metals, etc.) It may be formed.

  Further, the interlayer insulating films IL1 to IL4 may be formed of a low dielectric constant film having a dielectric constant lower than that of the SiOF film. Specifically, the interlayer insulating films IL1 to IL4 are a SiOC film having holes, an MSQ film having holes (methylsilsesquioxane, a silicon oxide film having a Si—C bond formed by a coating process, or Carbon-containing silsesquioxane), HSQ film having holes (hydrogen silsesquioxane, silicon oxide film having Si—H bond formed by coating process, or hydrogen-containing silsesquioxane) You may form from the film | membrane of. The size (diameter) of the holes is, for example, about 1 nm.

  Next, the uppermost layer wirings TM1, TM2, and TM3 are formed on the plug PLG5 formed in the interlayer insulating film IL4. The uppermost layer wirings TM1, TM2, and TM3 are formed, for example, from a laminated film including a titanium nitride film, an aluminum film, and a titanium nitride film. An interlayer insulating film (surface protection film) IL5 is formed on the interlayer insulating film IL4 on which the uppermost layer wirings TM1, TM2, and TM3 are formed so as to cover the uppermost layer wirings TM1, TM2, and TM3. The interlayer insulating film IL5 is formed of, for example, a stacked film including a silicon oxide film and a silicon nitride film formed on the silicon oxide film.

  Further, an opening CNT1 reaching the uppermost layer wiring TM1 is formed in the interlayer insulating film IL5, and a conductive material is embedded in the opening CNT1. An input bump electrode IBMP1 is formed on the interlayer insulating film IL5 in which the opening CNT1 is formed. The input bump electrode IBMP1 is formed of a UBM (Under Bump Metal) film that is a base film and a gold film formed on the UBM film. The UBM film can be formed by using, for example, a sputtering method. For example, the UBM film is formed by a single layer film or a laminated film such as a titanium film, a nickel film, a palladium film, a titanium / tungsten alloy film, a titanium nitride film, or a gold film. Yes. Here, the UBM film has a function of improving the adhesiveness between the input bump electrode IBMP1 and the surface protective film (interlayer insulating film IL5), and the metal element of the gold film moves to the multilayer wiring side. It is a film having a barrier function for suppressing or preventing the metal element of the multilayer wiring from moving to the gold film side.

  As described above, the semiconductor device according to the fifth embodiment is formed. At this time, the three uppermost layer wirings TM1, TM2, and TM3 are formed in the lower layer that overlaps the input bump electrode IBMP1 in a plan view.

  Subsequently, for example, a structure in which two openings are connected to one input bump electrode IBMP will be described. FIG. 15 is a diagram showing one input bump electrode IBMP1. In FIG. 15, the extending direction of the long side LS1 of the semiconductor chip CHP2 is defined as the X direction, and the short side direction of the semiconductor chip CHP2 is defined as the Y direction. As shown in FIG. 15, the input bump electrode IBMP1 has a rectangular shape, and three uppermost layer wirings TM1 to TM3 are arranged below the input bump electrode IBMP1. The input bump electrode IBMP1 is electrically connected to the uppermost layer wiring TM1 via a conductive material embedded in the opening CNT1a, and is connected to the uppermost layer wiring TM3 via a conductive material embedded in the opening CNT1b. Both are electrically connected. A device structure formed in the lower layer of the input bump electrode IBMP1 configured as described above will be described with reference to FIG.

  FIG. 16 is a cross-sectional view taken along the line AA in FIG. 15, and is a cross-sectional view showing the configuration of the semiconductor device according to the fifth embodiment. Since the device structure shown in FIG. 16 is almost the same as the device structure shown in FIG. 14, a different structure will be described. The device structure shown in FIG. 16 is different from the device structure shown in FIG. 14 in the connection relationship between the input bump electrode IBMP1 and the uppermost layer wirings TM1, TM2, and TM3. The input bump electrode IBMP1 shown in FIG. 16 is connected to the two openings CNT1a and CNT1b. The input bump electrode IBMP1 and the uppermost layer wiring TM1 are electrically connected via the opening CNT1a, and the input bump electrode IBMP1 and the uppermost layer wiring TM3 are electrically connected via the opening CNT1b. Yes. Other device structures are the same as the device structure shown in FIG. Thus, a device structure is formed in which two openings CNT1a and CNT1b are connected to one input bump electrode IBMP.

(Embodiment 6)
In the sixth embodiment, a process of mounting the semiconductor chip CHP2 constituting the LCD driver on a mounting substrate (glass substrate) will be described. First, by using a normal semiconductor manufacturing technique, a semiconductor element such as a MISFET is formed on a semiconductor substrate, and then a multilayer wiring is formed on the semiconductor substrate on which the semiconductor element is formed. And after forming the uppermost layer wiring formed in the uppermost layer of a multilayer wiring, the surface protection film which covers this uppermost layer wiring is formed. Thereafter, an opening reaching the uppermost layer wiring is formed in the surface protective film, and the opening is embedded and a bump electrode (input bump electrode and output bump electrode) is formed on the surface protective film. Thereafter, by dicing the semiconductor substrate, it is possible to obtain a semiconductor chip CHP2 separated into pieces as shown in FIG.

  Next, a process of bonding the semiconductor chip CHP2 formed as described above to a mounting substrate (glass substrate) and mounting it will be described. FIG. 17 shows a case where the semiconductor chip CHP2 is mounted on the glass substrate 10 (COG: Chip On Glass). As shown in FIG. 17, a glass substrate 11 is mounted on the glass substrate 10, thereby forming a display portion of the LCD. And on the glass substrate 10 in the vicinity of the display part of LCD, it is an area | region where semiconductor chip CHP2 which is an LCD driver is mounted. The semiconductor chip CHP2 is formed with an input bump electrode IBMP and an output bump electrode OBMP. The input bump electrode IBMP and the output bump electrode OBMP, and an electrode 10a (ITO electrode) formed on the glass substrate 10; Are connected via an anisotropic conductive film ACF. The anisotropic conductive film ACF is configured to have an insulating layer 12 and metal particles 13.

  In this step, the camera C is used to align the semiconductor chip CHP2 with the electrode 10a formed on the glass substrate 10. In this alignment, the alignment mark formed on the semiconductor chip CHP2 is recognized by the camera C, whereby the accurate position of the semiconductor chip CHP2 is grasped.

  FIG. 18 is a cross-sectional view showing a state in which the semiconductor chip CHP2 is mounted on the anisotropic conductive film ACF after alignment by the camera C. At this time, since the semiconductor chip CHP2 and the glass substrate 10 are accurately aligned, the input bump electrode IBMP and the output bump electrode OBMP are positioned on the electrode 10a.

  Subsequently, as shown in FIG. 19, the input bump electrode IBMP, the output bump electrode OBMP, and the electrode 10a are connected via the anisotropic conductive film ACF. The anisotropic conductive film ACF is a film formed by mixing a fine metal particle having conductivity with a thermosetting resin into a film shape. The metal particles are mainly composed of spheres having a diameter of 3 μm to 5 μm in which a nickel layer and a gold plating layer are formed from the inside, and an insulating layer is stacked on the outermost side. In this state, when the semiconductor chip CHP2 is mounted on the glass substrate 10, the anisotropic conductive film ACF is sandwiched between the electrode 10a of the glass substrate 10 and the input bump electrode IBMP and output bump electrode OBMP of the semiconductor chip CHP2. I'm stuck. When the semiconductor chip CHP2 is pressurized while applying heat with a heater or the like, pressure is applied only to the portions corresponding to the input bump electrode IBMP and the output bump electrode OBMP. Then, the metal particles dispersed in the anisotropic conductive film ACF are overlapped in contact with each other, and the metal particles are pressed against each other. As a result, a conductive path is formed in the anisotropic conductive film ACF via the metal particles. Since the metal particles in the portion of the anisotropic conductive film ACF where no pressure is applied hold the insulating layer formed on the surface of the metal particles, between the side-by-side input bump electrodes IBMP and sideways The insulation between the arranged output bump electrodes OBMP is maintained. Therefore, there is an advantage that the semiconductor chip CHP2 can be mounted on the glass substrate 10 without causing a short circuit even if the interval between the input bump electrodes IBMP or the output bump electrodes OBMP is narrow.

  Subsequently, as shown in FIG. 20, the glass substrate 10 and the flexible printed circuit FPC are also connected by the anisotropic conductive film ACF. Thus, in the semiconductor chip CHP2 mounted on the glass substrate 10, the output bump electrode OBMP is electrically connected to the display unit of the LCD, and the input bump electrode IBMP is connected to the flexible printed circuit board FPC.

  FIG. 21 is a diagram showing an overall configuration of the LCD (liquid crystal display device 15). As shown in FIG. 21, an LCD display unit 14 is formed on a glass substrate, and an image is displayed on the display unit 14. On the glass substrate in the vicinity of the display unit 14, a semiconductor chip CHP2 as an LCD driver is mounted. A flexible printed circuit board FPC is mounted in the vicinity of the semiconductor chip CHP2, and a semiconductor chip CHP2 as a driver is mounted between the flexible printed circuit board FPC and the display unit 14 of the LCD. In this way, the semiconductor chip CHP2 can be mounted on the glass substrate. As described above, the semiconductor chip CHP2 which is an LCD driver can be mounted on the liquid crystal display device 15.

(Embodiment 7)
In the seventh embodiment, a planar layout of the output bump electrode, the uppermost layer wiring, and the output protection circuit will be described. FIG. 22 is an enlarged view showing a region near the long side LS2 of the semiconductor chip CHP2 constituting the LCD driver shown in FIG.

  As shown in FIG. 22, output bump electrodes OBMP1 close to the internal circuit of the semiconductor chip CHP2 and output bump electrodes OBMP2 close to the long side LS2 are arranged in a staggered manner. A plurality of output bump electrodes OBMP1 and output bump electrodes OBMP2 are arranged in the direction along the long side LS2 (X direction). An output protection circuit 4 is arranged on the semiconductor substrate below the output bump electrode OBMP1 and the output bump electrode OBMP2. In the region of the output protection circuit 4, a plurality of semiconductor elements for the protection circuit as shown in FIG. 2 or FIG. 3 are formed and are electrically connected to the output bump electrode OBMP1 and the output bump electrode OBMP2, respectively. ing. The output protection circuit 4 is electrically connected to the output bump electrode OBMP1 and the output bump electrode OBMP2 via the uppermost layer wiring TM5 or the uppermost layer wiring TM6. The uppermost layer wiring TM5 and the uppermost layer wiring TM6 are connected to the output bump electrode OBMP1 and the output bump electrode OBMP2 through the opening CNT6 and the opening CNT7.

  Here, the opening CNT7 of the output bump electrode OBMP2 is provided not at the long side LS2 side but at a position close to the internal circuit. Thereby, the uppermost layer wiring TM7 (power supply wiring) (reference potential Vss) and the uppermost layer wiring TM8 (power supply wiring) (external power supply potential Vcc) can be routed to the outer periphery of the semiconductor chip CHP2. That is, the region above the output protection circuit 4 and the region below the output bump electrode OBMP2 can be used effectively. As described above, in the semiconductor chip CHP2 in the seventh embodiment, the output bump electrode OBMP1 and the output bump electrode OBMP2 are also devised for reducing the chip size.

  That is, the feature of the seventh embodiment is that the plurality of output bump electrodes arranged in a staggered manner are longer than the output bump electrode OBMP2 disposed at a position close to the long side LS2 and the output bump electrode OBMP2. The output bump electrode OBMP1 is disposed at a position far from the side LS2. The uppermost layer wiring TM5 is formed under the output bump electrode OBMP1, and the uppermost layer wiring TM6 is formed under the output bump electrode OBMP2. At this time, the output bump electrode OBMP1 is connected to the uppermost layer wiring TM5 via the opening CNT6 formed in the insulating film, and the output bump electrode OBMP2 includes the opening CNT7 formed in the insulating film. And is connected to the uppermost layer wiring TM6. The position where the opening CNT6 is formed is closer to the long side LS2 than the center of the output bump electrode OBMP1, and the position where the opening CNT7 is formed is longer than the center of the output bump electrode OBMP2. The position is far from the side LS2.

  Note that the output bump electrode OBMP1 and the output bump electrode OBMP2 in the seventh embodiment are different from the input bump electrode IBMP shown in the above-described third embodiment in the openings CNT7 of the plurality of output bump electrodes OBMP2. All positions are the same. The positions of the openings CNT6 of the plurality of output bump electrodes OBMP1 are all the same. In other words, a plurality of input bump electrodes IBMP are formed on a straight line, and there are cases where the positions of openings (for example, the openings CNT1 to CNT3 in FIGS. 8 and 9) are different. However, a plurality of output bump electrodes OBMP1 are formed on a straight line, and the positions of the openings CNT6 are the same. A plurality of output bump electrodes OBMP2 are formed on a straight line different from the output bump electrode OBMP1, and the positions of the openings CNT7 are the same.

  As described above, the size of the semiconductor chip CHP2 in the short side direction can be reduced by the technique disclosed in the seventh embodiment.

  In addition, the technique disclosed in the seventh embodiment can be applied to the other embodiments described above.

(Embodiment 8)
The eighth embodiment exemplifies a case where a dummy region in which no semiconductor element is formed is arranged in a region overlapping with the input bump electrodes IBMP1 and IBMP2 in a plane. FIG. 23 is a cross-sectional view taken along the line AA in FIG. 13 and is a cross-sectional view illustrating the eighth embodiment.

  For example, in the above-described fifth embodiment, the example in which the internal circuit IU is arranged in a region overlapping the input bump electrodes IBMP1 and IBMP2 is shown. However, the present invention is not limited thereto, and the input bump electrodes IBMP1 and IBMP2 The region overlapping in plan view may be a dummy region where no semiconductor element is formed. The dummy region is a region of the semiconductor substrate partitioned by the element isolation region STI and is a region that does not contribute to the circuit operation of the semiconductor device.

  In FIG. 23, a dummy pattern DP provided for preventing dishing is illustrated as an example of the dummy area. In the dummy pattern DP, a plurality of patterns are provided in the same shape, are formed at the same pitch, and are regularly arranged.

  As described above, in the eighth embodiment, as in the fifth embodiment, a plurality of wiring layers can be passed under the input bump electrodes IBMP1 and IBMP2. The degree can be improved.

  Further, since the dummy pattern DP is provided in a region overlapping the input bump electrodes IBMP1 and IBMP2, the flatness of each wiring layer can be improved.

  It should be noted that the technique disclosed in the eighth embodiment can be applied to the other embodiments described above.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  In the present embodiment, the driving device (LCD driver) for liquid crystal display is exemplified, but the present invention is not limited to this, and the present invention can also be used as another driving device for display such as organic EL. Further, the present invention is not limited to the display driving device, and can be applied to other semiconductor devices. In particular, it is preferable to apply when the semiconductor chip is rectangular.

  The present invention can be widely used in the manufacturing industry for manufacturing semiconductor devices.

DESCRIPTION OF SYMBOLS 1 Control part 1S Semiconductor substrate 2a SRAM
2b SRAM
2c SRAM
DESCRIPTION OF SYMBOLS 3 Input protection circuit 3a Input protection circuit 3b Input protection circuit 3c Input protection circuit 3A Input protection circuit 3B Input protection circuit 4 Output protection circuit 10 Glass substrate 10a Electrode 11 Glass substrate 12 Insulating layer 13 Metal particle 14 Display part 15 Liquid crystal display device A Terminal ACF Anisotropic conductive film a Length b Length C Camera CHP1 Semiconductor chip CHP2 Semiconductor chip CIL Contact interlayer insulating film CNT1 Opening CNT1a Opening CNT1b Opening CNT2 Opening CNT2a Opening CNT2b Opening CNT3 Opening CNT3a Opening CNT3b opening CNT4a opening CNT4b opening CNT5 opening CNT6 opening CNT7 opening CS cobalt silicide film D1 diode D2 diode DP dummy pattern EX1 shallow n-type impurity Diffusion region EX2 Shallow p-type impurity diffusion region FPC Flexible printed circuit board G1 Gate electrode G2 Gate electrode GOX Gate insulating film IBMP input bump electrode IBMP1 input bump electrode IBMP2 input bump electrode IBMP3 input bump electrode IBMP4 input bump electrode IBMP5 input Bump electrode IL1 Interlayer insulating film IL2 Interlayer insulating film IL3 Interlayer insulating film IL4 Interlayer insulating film IL5 Interlayer insulating film IU Internal circuit L1 First layer wiring L2 Second layer wiring L3 Third layer wiring L4 Fourth layer wiring LS1 Long side LS2 Long side NR Deep n-type impurity diffusion region NWL n-type well OBMP Output bump electrode OBMP1 Output bump electrode OBMP2 Output bump electrode PF Polysilicon film PLG1 Plug PLG2 Plug PLG3 Plug PLG4 Plug Grayed PLG5 plug PR deep p-type impurity diffusion region PWL p-type well Q1 n-channel type MISFET
Q2 p-channel MISFET
SS1 short side SS2 short side STI element isolation region SW sidewall TM1 top layer wiring TM1a top layer wiring TM1b top layer wiring TM2 top layer wiring TM2a top layer wiring TM2b top layer wiring TM3 top layer wiring TM3a top layer wiring TM3b top layer wiring TM4 Top layer wiring TM5 Top layer wiring TM6 Top layer wiring TM7 Top layer wiring (Vss)
TM8 Top layer wiring (Vcc)
Tr1 n-channel MISFET
Tr2 p-channel MISFET
Vdd Power supply potential Vss Ground potential Y1 distance Y2 distance

Claims (9)

(A) a rectangular semiconductor substrate having a pair of short sides and a pair of long sides;
(B) an internal circuit including a plurality of MISFETs formed on the semiconductor substrate;
(C) a plurality of protective elements formed on the semiconductor substrate so as to protect the internal circuit from static electricity;
(D) a first insulating film formed on the semiconductor substrate so as to cover the plurality of MISFETs and the plurality of protection elements;
(E) a plurality of bump electrodes formed on the first insulating film and arranged along a first long side of the pair of long sides;
With
The plurality of bump electrodes are bump electrodes to which an input signal from an external device is input,
The plurality of protection elements are electrically connected between each of the plurality of bump electrodes and the internal circuit,
The plurality of bump electrodes include a first bump electrode and a second bump electrode,
The plurality of protection elements include a first protection element and a second protection element,
The first protection element electrically connected to the first bump electrode is disposed at a position overlapping the first bump electrode in plan view,
The semiconductor device, wherein the second protection element electrically connected to the second bump electrode is disposed at a position different from a position overlapping the second bump electrode in plan view. The semiconductor device according to claim 1,
The semiconductor device, wherein the second bump electrode is disposed so as to overlap a part of the plurality of MISFETs in plan view. The semiconductor device according to claim 1,
The semiconductor device, wherein the second protection element is disposed more inside the semiconductor substrate than the plurality of bump electrodes in a first direction along the pair of short sides of the semiconductor substrate in a plan view. The semiconductor device according to claim 1,
further,
(F) a plurality of other protective elements formed on the semiconductor substrate so as to protect the internal circuit from static electricity;
(G) a plurality of other bump electrodes formed on the first insulating film and arranged along a second long side of the pair of long sides;
Have
The other plurality of bump electrodes are bump electrodes that output output signals to other external devices,
The other plurality of protection elements are electrically connected between each of the other plurality of bump electrodes and the internal circuit. The semiconductor device according to claim 4,
The other plurality of protection elements are arranged in positions overlapping with the other plurality of bump electrodes in plan view. The semiconductor device according to claim 4,
While the other plurality of bump electrodes are arranged in a staggered manner,
The semiconductor device, wherein the plurality of bump electrodes are arranged in a straight line. The semiconductor device according to claim 1,
Each of the plurality of protection elements is a semiconductor device including two diodes. The semiconductor device according to claim 1,
Each of the plurality of protection elements includes a semiconductor device. The semiconductor device according to claim 1,
The semiconductor device is a semiconductor device which is an LCD driver for driving a liquid crystal display device.

Images