JP2015179205A - semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a highly reliable semiconductor device which can prevent wiring delay inside a semiconductor chip and reduce power consumption by minimizing a problematic clock skew caused by wiring delay and avoiding the insertion of a number of buffer cells for clock skew control.SOLUTION: A semiconductor device comprises: a semiconductor layer 11 having a light receiving element 22 and a functional element 23; an electric wiring layer 12 formed on a principal surface of the semiconductor layer 11 and having an electrical wiring 12A connecting between the light receiving element 22 and the functional element 23; a first optical wiring layer 13a formed on a principal surface of the electric wiring layer 12; and a second optical wiring layer 13b which is connected to the first optical wiring layer 13a and extends in a perpendicular direction relative to the principal surface of the electric wiring layer 12 and is connected to the receiving element 22.

Description

  The present invention relates to a semiconductor device.

  In recent years, the miniaturization of semiconductor elements has progressed, and the performance of LSIs has been dramatically improved. For example, the gate length of the transistor is 0.1 μm or less, and the clock frequency supplied to drive the LSI is on the order of gigahertz. However, while miniaturization of semiconductor elements has progressed, the problem of wiring delay in LSI signal wiring has not been solved, and this problem has become apparent. Under such circumstances, the use of optical wiring for LSI signal transmission has been studied.

  By using the optical wiring, it is possible to suppress an increase in wiring delay in the LSI. For example, Patent Document 1 discloses a method of using light for signal transmission between semiconductor chips. This technique enables transmission of an optical signal between a plurality of semiconductor chips, and performs signal transmission between different semiconductor chips using an optical waveguide made of a material capable of transmitting light.

Japanese Patent No. 3413839

  As described above, a technique for transmitting an optical signal between a plurality of semiconductor chips has been proposed, but a technique for transmitting an optical signal within each semiconductor chip has not yet been established. In practice, it is difficult to transmit all signals using optical wiring in a semiconductor chip, and signal transmission between transistors formed in the semiconductor chip is performed using electrical signals. Therefore, when an optical wiring is used in a semiconductor chip, a photoelectric conversion circuit that converts an optical signal into an electric signal in the semiconductor chip is essential. It is necessary to construct the optical wiring that will be the path of the optical signal in the semiconductor chip, and in addition to the transistor, photoelectric conversion circuit, and optical wiring described above, LSI design that considers the layout of the electrical wiring that will be the path of the electrical signal There must be. Therefore, it is necessary to devise a configuration of the entire semiconductor chip with respect to the light refraction position and the arrangement relationship of each element in order to make the best use of the effect of the optical wiring.

  The present invention has been made in view of the above-described problems, and suppresses a wiring delay in a semiconductor chip, reduces a clock skew that becomes a problem due to the wiring delay, and a large number of buffers for adjusting the clock skew. An object of the present invention is to provide a highly reliable semiconductor device capable of suppressing power consumption by suppressing insertion of cells.

  The semiconductor device of the present invention includes a semiconductor layer having a light receiving element, an electric wiring layer formed on a main surface of the semiconductor layer, and having an electric wiring connected to the light receiving element, and a main surface of the electric wiring layer. A first optical wiring layer formed on the first optical wiring layer and connected to the first optical wiring layer, extending in a direction perpendicular to a main surface of the electric wiring layer and connected to the light receiving element. And a second optical wiring layer.

  According to the present invention, wiring delay in a semiconductor chip can be suppressed. Realizing a highly reliable semiconductor device that reduces power consumption by reducing clock skew, which is a problem due to wiring delay, and suppressing the insertion of a large amount of buffer cells to adjust the clock skew To do.

1 is a schematic perspective view showing a semiconductor device according to a first embodiment. 1 is a schematic diagram illustrating a partially enlarged semiconductor device according to a first embodiment. It is a schematic perspective view which shows the other example of the semiconductor device by 1st Embodiment. It is the schematic which shows the manufacturing method of the semiconductor device by 1st Embodiment. FIG. 5 is a schematic view illustrating the method for manufacturing the semiconductor device according to the first embodiment, continued from FIG. 4. FIG. 6 is a schematic view illustrating the method for manufacturing the semiconductor device according to the first embodiment, continued from FIG. 5. FIG. 7 is a schematic view illustrating the method for manufacturing the semiconductor device according to the first embodiment following FIG. 6. FIG. 8 is a schematic view illustrating the method for manufacturing the semiconductor device according to the first embodiment following FIG. 7. It is a schematic sectional drawing which expands and shows a part of semiconductor device by 2nd Embodiment. It is a schematic sectional drawing which expands and shows a part of semiconductor device by 3rd Embodiment.

  Hereinafter, embodiments of a semiconductor device according to the present invention will be described in detail with reference to the drawings.

(First embodiment)
First, the first embodiment will be described.
FIG. 1 is a schematic perspective view showing the semiconductor device according to the first embodiment. FIG. 2 is a schematic diagram showing a partially enlarged view of the semiconductor device according to the first embodiment, in which the semiconductor layer and the electric wiring layer represent a cross section, and the optical wiring layer represents a side surface.

  The semiconductor device 10 includes an LSI chip 1 which is a semiconductor chip, an LSI package substrate 2 on which the LSI chip 1 is mounted, an LSI package 3 which is formed on the LSI package substrate 2 and covers and protects the LSI chip 1. It is configured with. The LSI package 3 covers the LSI chip 1 with ceramic, metal, or the like and protects the LSI chip 1 from external impacts, dust, or the like. In FIG. 1, the LSI chip 1 is shown so as to be seen through the LSI package 3 in consideration of easy understanding.

  The LSI chip 1 includes a semiconductor layer 11, an electric wiring layer 12 formed on the main surface of the semiconductor layer 11, and an optical wiring layer 13 formed on the main surface of the electric wiring layer 12.

  The semiconductor layer 11 includes a light emitting element 21, a light receiving element 22, and a transistor 23, and an insulating film 24 that covers these is formed. The light emitting element 21 functions as a clock generation unit and is a light source that emits an optical signal of a clock. The light receiving element 22 is a photodiode or the like, and receives the optical signal emitted from the light emitting element 21 and photoelectrically converts it into an electrical signal. The transistor 23 is a functional element to which an electrical signal of a clock converted from an optical signal by the light receiving element 22 is supplied. For the transistor 23, only the gate electrode is shown, and the source / drain on both sides of the gate electrode is not shown.

  The electrical wiring layer 12 is a multilayer wiring layer in which a plurality of wiring layers having wiring and vias such as Al (aluminum) or Cu (copper) and an interlayer insulating film covering the wirings and vias are stacked. In FIG. 2, only the wiring structure 12 </ b> A that connects the light receiving element 22 and the transistor 23 is illustrated as an example. The wiring structure 12A is formed of the first and second wiring layers. In the first wiring layer, vias 12a1 and 12a2 connected to the light receiving element 22 and the transistor 23, and wirings 12a3 and 12a4 respectively connected to the vias 12a1 and 12a2 are formed. In the second wiring layer, vias 12b1 and 12b2 respectively connected to the wirings 12a3 and 12a4 and wirings 12b3 connected to the vias 12b1 and 12b2 are formed.

The optical wiring layer 13 includes a first optical wiring layer 13a, a second optical wiring layer 13b, and a third optical wiring layer 13c, which are formed of silicon oxide or silicon nitride that is a material that transmits light. It is configured with.
The first optical wiring layer 13 a is formed on the main surface of the electric wiring layer 12. The second optical wiring layer 13b is connected to the first optical wiring layer 13a, and extends in a direction perpendicular to the main surface of the electric wiring layer 12, in this case, on the side surface of the electric wiring layer 12, thereby receiving the light receiving element. 22 is connected. A plurality of second optical wiring layers 13 b are arranged on two side surfaces of the electric wiring layer 12 that face each other. The third optical wiring layer 13c is connected to the first optical wiring layer 13a, and extends in a direction perpendicular to the main surface of the electric wiring layer 12, in this case, the side surface of the electric wiring layer 12. 21 is connected. The third optical wiring layer 13c is disposed on the two side surfaces of the electrical wiring layer 12 that face each other.
The joint surface between the first optical wiring layer 13a and the second optical wiring layer 13b is substantially orthogonal to the optical signal transmission direction (optical waveguide direction, indicated by arrow C) of the second optical wiring layer 13b. It is arranged at the position to do.

A reflective film 14 is disposed in the vicinity of the joint surface between the first optical wiring layer 13a and the second optical wiring layer 13b. The reflection film 14 is a metal film such as Al or Au (gold), and is formed on an inclined surface of about 45 °. The reflective film 14 functions as a half mirror. That is, the horizontal optical signal that has passed through the first optical wiring layer 13a is reflected by the reflecting film 14 and travels in the vertical direction, and passes through the second optical wiring layer 13b and is received by the light receiving element 22. At the same time, the optical signal passes through the reflection film 14 and travels in the horizontal direction in the first optical wiring layer 13a and is received by the other light receiving elements 22 in the same manner.
In this way, instead of providing the reflection film 14 that guides the optical signal to the light receiving element 22 by one reflection, the optical signal is refracted in a stepwise manner from the horizontal direction to the vertical direction by a plurality of reflections. A plurality of reflective films having an inclination may be formed.

A reflective film 15 is disposed in the vicinity of the joint surface between the first optical wiring layer 13a and the third optical wiring layer 13c. The reflection film 15 is a pair of metal films made of Al, Au, or the like, each formed on an inclined surface of about 45 °, and arranged so as to be substantially orthogonal to each other. The reflective film 15 reflects the optical signal in the vertical direction that is emitted from the light emitting element 21 and passes through the third optical wiring layer 13c, and passes through the first optical wiring layer 13a in the horizontal direction.
In this way, instead of providing the reflection film 15 that guides the optical signal to the first optical wiring layer 13a by a single reflection, the optical signal is refracted so as to gradually change from the vertical direction to the horizontal direction by a plurality of reflections. A plurality of reflective films having different inclinations may be formed.

  In the present embodiment, a case where the second optical wiring layer 13b and the third optical wiring layer 13c are arranged on two opposing side surfaces of the four side surfaces of the LSI chip 1 is illustrated. Here, a plurality of second optical wiring layers 13b (three in the illustrated example) and one third optical wiring layer 13c are provided on each side surface. As shown in FIG. 3, the second optical wiring layer 13 b may be disposed on all four side surfaces of the LSI chip 1.

  Further, instead of disposing the second optical wiring layer 13b and the third optical wiring layer 13c on the side surface of the LSI chip 1, the second optical wiring layer 13b and the third optical wiring layer 13c are connected to the first optical wiring layer 13a in a via shape penetrating the electric wiring layer 12. The second optical wiring layer and the third optical wiring layer may be formed. Alternatively, one of the second optical wiring layer and the third optical wiring layer may be formed on the side surface of the electric wiring layer 12 and the other may be formed in a via shape penetrating the electric wiring layer 12. Further, some of the second optical wiring layer and the third optical wiring layer may be formed on the side surface of the electric wiring layer 12, and the rest may be formed in via shapes penetrating the electric wiring layer 12. good.

The LSI chip 1 is flip-chip mounted with the main surface of the optical wiring layer 13 on the upper surface facing the main surface of the LSI package substrate 2 face down.
An electrode 16 is formed on the bonding surface between the first optical wiring layer 13 a and the LSI package substrate 2. The electrode 16 is connected to the wiring of the electric wiring layer 12 through a via (not shown) penetrating the first optical wiring layer 13a, and between the LSI chip 1 and the LSI package substrate 2 using an electric signal. Signal transmission is performed.

Hereinafter, signal transmission in the LSI chip 1 in the semiconductor device 10 configured as described above will be described with reference to FIG.
First, an optical signal of the clock is emitted from the light emitting element 21. The optical signal is transmitted in the vertical direction indicated by arrow A in the third optical wiring layer 13c, reflected by the reflective film 15, and transmitted in the horizontal direction indicated by arrow B in the first optical wiring layer 13a. The light reflected by the film 14 is transmitted in the second optical wiring layer 13 b in the vertical direction indicated by the arrow C, and supplied to the light receiving element 22. This optical signal is photoelectrically converted by the light receiving element 22 to become an electrical signal of a clock. This electric signal is input to the transistor 23 through the wiring and vias of the electric wiring layer 12 and various signal transmissions are performed. Further, the optical signal emitted from the light emitting element 21 and transmitted through the third optical wiring layer 13c is reflected by the reflective film 15 and is transmitted through the first optical wiring layer 13a in a horizontal direction (for example, an arrow) different from the arrow B. In the direction indicated by D) and supplied to other light receiving elements.

Hereinafter, a method for manufacturing the semiconductor device 10 will be described.
4 to 8 are schematic views showing the manufacturing method of the semiconductor device according to the present embodiment in the order of steps, in which the semiconductor layer and the electric wiring layer represent a cross section, and the optical wiring layer represents a side surface.

First, as shown in FIG. 4, the semiconductor layer 11 and the electric wiring layer 12 are sequentially formed.
Specifically, the light emitting element 21, the light receiving element 22, and the transistor 23 are appropriately formed on a silicon layer (or silicon substrate). In order to form the transistor 23, a gate electrode is formed through a gate insulating film, and source / drain regions are formed by ion implantation or the like in silicon layers (or silicon substrates) on both sides of the gate electrode. An insulating film 24 that covers the light emitting element 21, the light receiving element 22, and the transistor 23 is formed. Thus, the semiconductor layer 11 is formed.
Next, an electrical wiring layer 12 is formed by forming a multilayer wiring structure in which a plurality of wiring layers each having a wiring such as Al or Cu and an interlayer insulating film covering the wiring are stacked. Here, when forming Cu wiring and vias, a so-called damascene method is used.

Subsequently, as shown in FIG. 5, a first optical wiring layer 13a is formed on the electric wiring layer 12 and an electrode 16 is formed on the first optical wiring layer 13a in this order.
Specifically, a light transmitting material, for example, silicon oxide is deposited on the electric wiring layer 12 by a CVD method or the like. Thereby, the first optical wiring layer 13a is formed. Reflective films 14 and 15 are formed in the first optical wiring layer 13a.
A via (not shown) that penetrates the first optical wiring layer 13a and is connected to the wiring of the electric wiring layer 12 is formed, and an electrode 16 that is connected to the via is appropriately formed on the first optical wiring layer 13a. .

Subsequently, as shown in FIG. 6, a second optical wiring layer 13b and a third optical wiring layer 13c connected to the first optical wiring layer 13a are formed.
Specifically, first, a plurality of grooves 12a and 12b are formed on the side surface of the electric wiring layer 12 by photolithography and dry etching so that a part of the surface of the light receiving element 22 and the light emitting element 21 is exposed. .
Next, a second optical wiring layer 13b that fills the groove 12a with silicon oxide or the like is formed. At the same time, a third optical wiring layer 13c is formed to fill the groove 12b with silicon oxide or the like.
Thus, the LSI chip 1 including the semiconductor layer 11, the electric wiring layer 12, and the optical wiring layer 13 is formed.

Subsequently, as shown in FIG. 7, the LSI chip 1 is flip-chip mounted with the main surface of the optical wiring layer 13 facing down to face the main surface of the LSI package substrate 2. At this time, the electrode 16 of the LSI chip 1 and the electrode (not shown) of the LSI package substrate 2 are bump-connected.
Thereafter, as shown in FIG. 8, an LSI package 3 for protecting the LSI chip 1 by covering it with a ceramic, metal, or the like is formed.
As described above, the semiconductor device according to the present embodiment is formed.

  According to the present embodiment, by performing signal transmission with a long transmission distance in the LSI chip 1 using an optical signal using the optical wiring layer 13, it is possible to suppress wiring delay more than signal transmission using electrical wiring. Become. With this configuration, it is possible to reduce the number of semiconductor elements required for delay adjustment due to the influence of wiring delay. Specifically, the clock skew, which is a problem due to wiring delay, is reduced, and insertion of a large amount of buffer cells for adjusting the clock skew is suppressed. Thus, a highly reliable semiconductor device that can reduce power consumption is realized.

(Second Embodiment)
Next, a second embodiment will be described. In the present embodiment, a semiconductor device in which a semiconductor chip is packaged is disclosed as in the first embodiment, but differs from the first embodiment in that the light source of the clock optical signal is different.

FIG. 9 is a schematic cross-sectional view showing a partially enlarged semiconductor device according to the second embodiment, and is a schematic view corresponding to FIG. 2 in the first embodiment. In addition, about the same structural member as 1st Embodiment, the same code | symbol is attached | subjected and detailed description is abbreviate | omitted. The illustration of the electrode 16 is omitted.
Unlike the first embodiment, this semiconductor device includes an LSI chip external light source 32 separately from an LSI chip 31 which is a semiconductor chip. The LSI chip 31 and the LSI chip external light source 32 are mounted on the LSI package substrate 2 and covered with an LSI package (not shown).

The LSI chip 31 includes a semiconductor layer 33, an electric wiring layer 12 formed on the surface of the semiconductor layer 33, and an optical wiring layer 34 formed on the surface of the electric wiring layer 12.
The semiconductor layer 33 includes the light receiving element 22 and the transistor 23 as in the first embodiment, and the insulating film 24 is formed to cover them. Unlike the first embodiment, the semiconductor layer 33 does not have the light emitting element 21. .

The light source 32 outside the LSI chip is a module having a light emitting element such as a laser diode, and is arranged on the LSI package substrate 2 so as to be separated from the LSI chip 31. The LSI chip external light source 32 functions as a clock generation unit and is a light source that emits an optical signal of a clock.
Similar to the first embodiment, the optical wiring layer 34 includes a first optical wiring layer 13a and a second optical wiring layer 13b, and a fourth optical wiring is used instead of the third optical wiring layer 13c. The layer 34a is provided.
The fourth optical wiring layer 34a is an optical waveguide that connects the LSI chip external light source 32 and the first optical wiring layer 13a, and is parallel to the first optical wiring layer 13a on the same plane of the LSI package substrate 2. Is formed.

Hereinafter, signal transmission in the LSI chip 31 in the semiconductor device will be described.
First, an optical signal of the clock is emitted from the light source 32 outside the LSI chip. This optical signal is transmitted in the horizontal direction indicated by arrow A in the fourth optical wiring layer 34a, reflected by the reflective film 14, and transmitted in the vertical direction indicated by arrow B in the second optical wiring layer 13b. To the light receiving element 22. This electric signal is input to the transistor 23 through the wiring and vias of the electric wiring layer 12 and various signal transmissions are performed. The optical signal emitted from the light source 32 outside the LSI chip and transmitted through the fourth optical wiring layer 34a passes through the reflective film 14 and passes through the first optical wiring layer 13a in the horizontal direction indicated by the arrow C. In the same manner, other light receiving elements receive light and various signal transmissions are performed.

  In the present embodiment, the fourth optical wiring layer 34a for connecting the LSI chip external light source 32 and the second optical wiring layer 13b is flush with the first optical wiring layer 13a and the second optical wiring layer 13b. Is formed. Therefore, the light emitted from the light source 32 outside the LSI chip can enter the first optical wiring layer 13a (the reflective film 14) without a steep step.

  As described above, according to the present embodiment, signal transmission with a long transmission distance in the LSI chip 31 is performed by an optical signal using the optical wiring layer 34, so that the wiring delay is longer than the signal transmission by electric wiring. It can be suppressed. With this configuration, it is possible to reduce the number of semiconductor elements required for delay adjustment due to the influence of wiring delay. Specifically, the clock skew, which is a problem due to wiring delay, is reduced, and insertion of a large amount of buffer cells for adjusting the clock skew is suppressed. Thus, a highly reliable semiconductor device that can reduce power consumption is realized.

(Third embodiment)
Next, a third embodiment will be described. In the present embodiment, a semiconductor device in which a semiconductor chip is packaged is disclosed as in the first and second embodiments, but differs from the first and second embodiments in that the light source of the optical signal of the clock is different. To do.

FIG. 10 is a schematic cross-sectional view showing a partially enlarged semiconductor device according to the third embodiment, and is a schematic view corresponding to FIG. 2 in the first embodiment. In addition, about the same structural member as 1st Embodiment, the same code | symbol is attached | subjected and detailed description is abbreviate | omitted. The illustration of the electrode 16 is omitted.
Unlike the first embodiment, this semiconductor device includes an LSI chip external light source 42 separately from an LSI chip 41 which is a semiconductor chip. The LSI chip 41 and the LSI chip external light source 42 are mounted on the LSI package substrate 2 and covered with an LSI package (not shown).

The LSI chip 41 includes a semiconductor layer 43, an electric wiring layer 12 formed on the surface of the semiconductor layer 43, and an optical wiring layer 44 formed on the surface of the electric wiring layer 12.
The semiconductor layer 43 includes the light receiving element 22 and the transistor 23 as in the first embodiment, and the insulating film 24 is formed to cover them. Unlike the first embodiment, the semiconductor layer 43 does not have the light emitting element 21. .

The LSI chip external light source 42 is a module having a light emitting element such as a laser diode, and is disposed on the back surface of the LSI package substrate 2 so as to face the first optical wiring layer 13a via the LSI package substrate 2. The LSI chip external light source 42 functions as a clock generation unit and is a light source that emits an optical signal of a clock.
Similar to the first embodiment, the optical wiring layer 44 includes a first optical wiring layer 13a and a second optical wiring layer 13b. A fifth optical wiring is used instead of the third optical wiring layer 13c. A layer 44a is provided.
The fifth optical wiring layer 44a is an optical waveguide that connects the LSI chip external light source 42 and the first optical wiring layer 13a, and the first optical wiring layer 44a is embedded in the through hole 2a formed in the LSI package substrate 2. It is formed in a direction perpendicular to the main surface of the wiring layer 13a.

Hereinafter, signal transmission in the LSI chip 41 in the semiconductor device will be described.
First, an optical signal of the clock is emitted from the light source 42 outside the LSI chip. This optical signal is transmitted in the vertical direction indicated by the arrow A in the fifth optical wiring layer 44a, reflected by the reflective film 15, and transmitted in the horizontal direction indicated by the arrow B for reflection. The light reflected by the film 14 is transmitted in the second optical wiring layer 13 b in the vertical direction indicated by the arrow C, and supplied to the light receiving element 22. This optical signal is photoelectrically converted by the light receiving element 22 to become an electrical signal of a clock. This electric signal is input to the transistor 23 through the wiring and vias of the electric wiring layer 12 and various signal transmissions are performed. An optical signal emitted from the light source 42 outside the LSI chip and transmitted through the fifth optical wiring layer 44a is reflected by the reflective film 15 and passes through the first optical wiring layer 13a in a direction different from the arrow B (for example, Transmitted in the direction indicated by arrow D) and supplied to other light receiving elements.

  In the present embodiment, even when the optical path distance from the light source 42 outside the LSI chip to each light receiving element 22 is different, the signal transmission is performed by light, so that the delay difference of the optical wiring can be ignored. Therefore, the LSI chip external light source 42 can be arranged at an arbitrary position on the back surface of the LSI package substrate 2 via the LSI chip external light source 42, and the degree of freedom in selecting the arrangement location of the LSI chip external light source 42 is high.

  As described above, according to the present embodiment, signal transmission with a long transmission distance in the LSI chip 41 is performed by an optical signal using the optical wiring layer 44, thereby reducing wiring delay compared to signal transmission by electrical wiring. It can be suppressed. With this configuration, it is possible to reduce the number of semiconductor elements required for delay adjustment due to the influence of wiring delay. Specifically, the clock skew, which is a problem due to wiring delay, is reduced, and insertion of a large amount of buffer cells for adjusting the clock skew is suppressed. Thus, a highly reliable semiconductor device that can reduce power consumption is realized.

1: LSI chip 2: LSI package substrate 2a: Through-hole 3: LSI package 10: Semiconductor device 11: Semiconductor layer 12: Electric wiring layer 12A: Wiring structure 12a1, 12a2, 12b1, 12b2: Via 12a3, 12a4, 12b3: Wiring 13: Optical wiring layer 13a: First optical wiring layer 13b: Second optical wiring layer 13c: Third optical wiring layer 14, 15: Reflective film 16: Electrode 21: Light emitting element 22: Light receiving element 23: Transistor 24 : Insulating film 31: LSI chip 32: Light source outside LSI chip 33: Semiconductor layer 34: Optical wiring layer 34 a: Fourth optical wiring layer 41: LSI chip 42: Light source outside LSI chip 43: Semiconductor layer 44: Optical wiring layer 44 a : Fifth optical wiring layer

Claims (9)

A semiconductor layer having a light receiving element;
An electrical wiring layer formed on the main surface of the semiconductor layer and having electrical wiring connected to the light receiving element;
A first optical wiring layer formed on the main surface of the electrical wiring layer;
A second optical wiring layer connected to the first optical wiring layer and extending in a direction perpendicular to a main surface of the electric wiring layer and connected to the light receiving element. A featured semiconductor device.   The semiconductor device according to claim 1, wherein the second optical wiring layer is disposed on a side surface of the electric wiring layer or through the electric wiring layer. The semiconductor layer has a light emitting element,
A third optical wiring layer connected to the first optical wiring layer, extending in a direction perpendicular to a main surface of the electric wiring layer and connected to the light emitting element; The semiconductor device according to claim 1, wherein the semiconductor device is characterized.   4. The semiconductor device according to claim 3, wherein the third optical wiring layer is disposed on a side surface of the electric wiring layer or through the electric wiring layer.   The semiconductor device according to claim 3, wherein the light emitting element emits an optical signal of a clock. A light source provided outside the semiconductor layer;
The semiconductor device according to claim 1, further comprising: a fourth optical wiring layer that connects the light source and the first optical wiring layer.   The semiconductor device according to claim 6, wherein the fourth optical wiring layer is disposed horizontally on the same plane as the first optical wiring layer.   The semiconductor device according to claim 6, wherein the fourth optical wiring layer is arranged so that an optical waveguide direction thereof is perpendicular to a main surface of the first optical wiring layer.   The semiconductor device according to claim 6, wherein the light source emits an optical signal of a clock.

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