JP2015178023A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine capable of, even when a power supply of the game machine is turned off, notifying a specific device of opening of a door body.SOLUTION: A frame opening detection circuit 270 includes a storage battery SB1, so that, even when the power supply to a Pachinko machine is cut off and no DC voltage of 12 volt is supplied from a DC power supply DC1, the frame opening detection circuit 270 can stop a high signal to be output to a hall computer 262 according to an opening period of an inner frame 12 or a front frame 14. Consequently, even when the power supply to the Pachinko machine is cut off, the Pachinko machine can detect opening of the inner frame 12 or the front frame 14 and also detect an opening period of the inner frame 12 or the front frame 14. Further, this configuration can identify the Pachinko machine, the inner frame 12 or front frame 14 of which is opened, and also detect an opening time of the inner frame 12 or an opening time of the front frame 14 of the identified Pachinko machine.

Description

  The present invention relates to a gaming machine represented by a pachinko machine, a spinning machine (for example, a slot machine), or a spinning machine using a game ball.

  In a pachinko machine, when a ball that has been driven into the game area enters the symbol operating port, a lottery is performed at the timing of the entry. Further, in a spinning-type game machine using a slot machine or a game ball, when a start lever is operated, a lottery is performed at the operation timing. As a result of the lottery, for example, when a big hit is made, a large amount of prize balls and coins can be paid out. Since the control for determining the lottery and the jackpot is performed by the main control device, the main control device is likely to be an object of fraud.

Specifically, for example, the main control device may be replaced with an unauthorized one that frequently generates jackpots, or an illegal board (for example, a “hanging board”) may be connected to the main control apparatus. There are things that illegally generate. In addition, in the case of a pachinko machine, there is also a fraudulent act that makes it easier for a ball to enter a winning port or a symbol operating port by illegally bending a nail that has been driven onto the game board surface.
In the case of a pachinko machine, the main control device is mounted on the back of the game board. On the other hand, a glass frame is provided on the front surface of the game board, and the glass frame can be individually opened and closed with respect to the inner frame body on which the game board is mounted. Therefore, when a cheating person performs cheating on the game board surface or the main control device, the inner frame or the glass frame must be opened, but when the inner frame or the glass frame is opened, Since the opening is detected by the sensor and reported to the hall computer that manages the game hall, it is possible to easily grasp which pachinko machine has been cheated.

JP 2001-198332 A

  However, if, for example, late at night after the amusement hall is closed, a fraudulent person enters, and the intruder opens the inner frame or the glass frame and conducts a fraudulent action, the pachinko machine is turned off at that time. Since the pachinko machine is stopped, the opening of the inner frame or the glass frame cannot be detected, and the opening cannot be reported to the hall computer.

  The present invention has been made in order to solve the above-described problems and the like, and allows the opening to be grasped when the door is opened while the power of the gaming machine is turned off. It aims to provide a gaming machine that can.

  In order to achieve this object, a gaming machine according to claim 1 is provided in a space formed by a main body, a door body that opens and closes the front surface of the main body, and the door body and the main body, and controls the game. Control means for performing, a door opening detection means for detecting the opening of the door body with respect to the main body, and a signal to a specific device when the door opening detection means does not detect the opening of the door body. Signal output means for outputting, and stop means for stopping signal output to the specific device by the signal output means when the door opening detection means detects opening of the door body, the signal output means Is configured so that a signal can be output to the specific device even when the power of the gaming machine is turned off and the control means is stopped, and the stopping means is configured such that the power of the gaming machine is Off said control Even when the stage is stopped, and is stopped configured to be able to signal output to the specific device according to the signal output means. In addition, the inside of the space formed by the door body and the main body indicates the back surface or the back surface side of the door body that cannot be touched when the door body is closed.

  The gaming machine according to claim 2 is the gaming machine according to claim 1, wherein the door body includes an inner frame that is opened and closed with respect to the main body, and a transparent plate support door that is opened and closed with respect to the inner frame. The door opening detecting means is provided on each of the inner frame and the transparent plate support door, and is connected in parallel to the signal output means and the stopping means, and the stopping means is configured to open the door. When the detection means detects the opening of at least one of the inner frame or the transparent plate support door, the signal output means stops the signal output to the specific device.

  The gaming machine according to claim 3 is the gaming machine according to claim 1 or 2, further comprising an off-time operation means composed of a secondary battery that is charged while the gaming machine is powered on. The output means and the stop means are operated by electric power supplied from the operating means during the off state.

  According to the gaming machine of the first aspect, when the door opening detection means does not detect the opening of the door (when the door closing is detected), the signal output means sends a signal to the specific device. Is output. On the other hand, when the door opening detection means detects the opening of the door body, the signal output means stops the signal output to the specific device by the stop means. In this way, when the door is opened, the signal output from the signal output means to the specific device is stopped, so that the gaming machine with the door opened can be determined by the specific device. it can. Here, even when the power of the gaming machine is turned off and the control means is stopped, the signal output means can output a signal to the specific device. In addition, even when the power of the gaming machine is turned off and the control means is stopped, the stop means can stop the signal output to the specific device by the signal output means. Therefore, for example, even after the store is closed with all the gaming machines turned off, even if the door is opened due to an unauthorized act by someone, the gaming machine with the opened door can be identified by the specific device. is there.

  As described above, when the door opening detection unit does not detect the opening of the door body, the signal output unit outputs a signal to the specific device. Here, when the communication medium between the signal output means and the specific device is damaged by an unauthorized person, the communication between the signal output means and the specific device is interrupted, so the door opening detection means detects the opening of the door body. Even if it is not made, that is, even if the door is in a closed state, signal output to the specific device remains stopped. Therefore, when the signal output means stops outputting the signal to the specific device when the door is in the closed state, it is possible to detect the breakage of the communication medium between the signal output means and the specific device. There is an effect.

  In addition, even if there is no abnormality in the communication medium between the signal output means and the specific device, if the signal output means fails and the signal output to the specific device is in a stopped state, the door body Even in the closed state, the signal output to the specific device remains stopped. Similarly, when a failure occurs in the stopping means and the signal output to the specific device by the signal output means is always stopped, the signal output to the specific device even if the door body is in the closed state Will remain stopped. Therefore, if there is no abnormality in the communication medium between the signal output means and the specific device, but the signal output means stops the signal output to the specific device when the door is closed, the signal output means In addition, there is an effect that it is possible to detect a failure of either one of the stop means or both of them.

According to the gaming machine of the second aspect, in addition to the effect of the gaming machine of the first aspect, the following effect can be obtained. That is, the door opening detection means is provided on each of the inner frame and the transparent plate support door and is connected in parallel to the signal output means and the stop means, so that at least the inner frame or the transparent plate support door is detected by the door opening detection means. When one of the openings is detected, signal output to the specific device by the signal output means can be stopped by the stop means. Therefore, even if one of the inner frame and the transparent plate support door constituting the door body is opened, the opening can be reported to the specific device by one set of signal output means and stop means. is there.
According to the gaming machine according to claim 3, in addition to the effect of the gaming machine according to claim 1 or 2, the off-time operation means constituted by the secondary battery is charged while the gaming machine is powered on. By simply turning on the power of the gaming machine according to the business hours of the game hall, the off-operation means can be charged. Therefore, if the door is opened while the power of the gaming machine is turned off after the game hall is closed, the signal output means and the stop means are operated by the off-operation means to identify the opening. There is an effect that it can be reported to the device.

It is a front view of a pachinko machine. It is a front view of the game board of a pachinko machine. It is a rear view of a pachinko machine. It is a perspective view of the pachinko machine in the state where an inner frame, a front frame, and a lower plate unit were opened. It is the figure which showed the structure of the switch. It is the block diagram which showed the electrical structure of the pachinko machine. It is the circuit diagram which showed the electrical structure of the frame open | release detection circuit and the external output terminal board. 6 is a timing chart showing the relationship between the state of the switch SW1, the state of the switch SW2, the voltage of the TRG terminal of the timer, the voltage of the OUT terminal of the timer, the voltage of the output terminal of the EXOR circuit, and the output of the external output terminal plate. (A) is the figure which showed typically the area division setting and effective line setting of the display screen, (b) is the figure which illustrated the actual display screen. It is a figure which shows the outline | summary of various counters. It is a flowchart which shows the starting process performed by MPU in a main controller. It is a flowchart which shows the main process performed by MPU in a main controller. It is a flowchart which shows the fluctuation | variation process performed in a main process. It is the flowchart which showed the change start process performed in a change process. It is a flowchart which shows a timer interruption process. It is a flowchart which shows the start winning process performed in a timer interruption process. It is a flowchart which shows a NMI interruption process. It is the circuit diagram which showed the electrical structure of the frame open | release detection circuit and external output terminal board of 2nd Embodiment. 7 is a timing chart showing the relationship between the state of the switch SW1, the state of the switch SW2, the voltage A of the frame opening detection circuit of the second embodiment, and the output of the external output terminal plate. It is the circuit diagram which showed the electrical structure of the frame open detection circuit and external output terminal board of 3rd Embodiment. State of switch SW1, state of switch SW2, voltage of TRG terminal of timer of third embodiment, voltage of OUT terminal of timer of third embodiment, voltage of output terminal of NOT circuit and output of external output terminal plate It is the timing chart which showed.

  Hereinafter, an embodiment of a pachinko gaming machine (hereinafter simply referred to as “pachinko machine”) will be described with reference to the drawings. 1 is a front view of the pachinko machine 10, FIG. 2 is a front view of the game board 13 of the pachinko machine 10, and FIG. 3 is a rear view of the pachinko machine 10.

  As shown in FIG. 1, the pachinko machine 10 includes an outer frame 11 having an outer shell formed of a wooden frame combined in a substantially rectangular shape, and an outer frame 11 having substantially the same outer shape as the outer frame 11. And an inner frame 12 supported to be openable and closable. In order to support the inner frame 12, metal hinges 18 are attached to the outer frame 11 at two upper and lower portions on the left side when viewed from the front (see FIG. 1), and the side on which the hinge 18 is provided is used as an opening / closing axis. The frame 12 is supported so as to be openable and closable to the front front side.

  A game board 13 (see FIG. 2) having a large number of nails, winning holes 63, 64, and the like is detachably mounted on the inner frame 12 from the back side. A ball ball game is performed when the ball flows down the front surface of the game board 13. The inner frame 12 has a ball launch unit 112a (see FIG. 5) that launches a ball to the front area of the game board 13 and a launch that guides the ball launched from the ball launch unit 112a to the front area of the game board 13. A rail (not shown) or the like is attached.

  On the front side of the inner frame 12, a front frame 14 that covers the upper side of the front surface and a lower dish unit 15 that covers the lower side of the front frame 14 are provided. In order to support the front frame 14 and the lower dish unit 15, metal hinges 19 are attached to two upper and lower portions on the left side when viewed from the front (see FIG. 1), and the side on which the hinges 19 are provided is used as an opening / closing axis. 14 and the lower pan unit 15 are supported so as to be openable and closable toward the front front side. The locking of the inner frame 12 and the locking of the front frame 14 are respectively released by inserting a dedicated key into the key hole 21 of the cylinder lock 20 and performing a predetermined operation.

  The front frame 14 is assembled with decorative resin parts, electrical parts, and the like, and a window part 14c that is formed in an approximately elliptical shape is provided at a substantially central part thereof. A glass unit 16 having two plate glasses is disposed on the back side of the front frame 14, and the front surface of the game board 13 can be seen on the front side of the pachinko machine 10 through the glass unit 16. On the front frame 14, an upper plate 17 that stores balls is formed in a substantially box shape that protrudes forward and the upper surface is opened, and prize balls and rental balls are discharged to the upper plate 17. The bottom surface of the upper plate 17 is formed to be inclined downward to the right when viewed from the front (see FIG. 1), and the sphere thrown into the upper plate 17 is guided to the ball launch unit 112a by the inclination. A frame button 22 is provided on the upper surface of the upper plate 17. This frame button 22 is operated by the player, for example, when changing the effect pattern of the variable display displayed on the third symbol display device 81 or changing the effect content at the reach effect.

  In addition, the front frame 14 is provided with light emitting means such as various lamps around the periphery (for example, a corner portion). These light-emitting means play a role of enhancing the effect of the game during the game by changing or controlling the light-emitting mode by turning on or flashing according to the change in the gaming state at the time of big hit or predetermined reach. On the peripheral edge of the window portion 14c, there are provided electric decoration portions 29 to 33 incorporating light emitting means such as LEDs. In the pachinko machine 10, these lighting parts 29 to 33 function as effect lamps such as jackpot lamps, and the lighting parts 29 to 33 are turned on by lighting or blinking of the built-in LEDs at the time of jackpot or reach effects. Alternatively, it blinks to notify that the jackpot is being hit or that the reach is one step before the jackpot.

  Further, in the upper left part of the front frame 14 as viewed from the front (see FIG. 1), there is provided a display lamp 34 which has built-in light emitting means such as LEDs and can display the payout of a prize ball and when an error occurs. In addition, a small window 35 is formed by attaching a transparent resin from the back side so that the back side of the front frame 14 can be visually recognized, on the lower side of the right illumination part 32, and a sticking space K1 on the front side of the game board 13 (FIG. 2) is visible from the front surface of the pachinko machine 10. In addition, in the pachinko machine 10, a plated member 36 made of ABS resin that is chrome-plated is attached to an area around the electric decoration parts 29 to 33 in order to bring out more gorgeousness.

  A ball rental operation unit 40 is disposed below the window 14c. The ball lending operation unit 40 is provided with a frequency display unit 41, a ball lending button 42, and a return button 43. When the ball lending operation unit 40 is operated in a state where a bill or a card is inserted into a card unit (ball lending unit) (not shown) arranged on the side of the pachinko machine 10, Loans are made. Specifically, the frequency display unit 41 is an area in which the remaining amount information such as a card is displayed, and the built-in LED is lit to display the remaining amount as the remaining amount information. The ball lending button 42 is operated to obtain a lending ball based on information recorded on a card or the like (recording medium), and the lending ball is supplied to the upper plate 17 as long as there is a remaining amount on the card or the like. Is done. The return button 43 is operated when requesting the return of a card or the like inserted into the card unit. In addition, in a pachinko machine in which a ball is lent directly to the upper plate 17 from a ball lending device or the like without using a card unit, a so-called cash machine does not require the ball lending operation unit 40. In this case, the ball lending operation unit 40 It is also possible to add a decorative seal or the like to the installation portion of the parts so that the component configuration is common. A pachinko machine using a card unit and a cash machine can be shared.

  In the lower plate unit 15 located on the lower side of the upper plate 17, a lower plate 50 for storing a ball that could not be stored in the upper plate 17 is formed in a substantially box shape having an open upper surface. Yes. On the right side of the lower plate 50, an operation handle 51 that is operated by a player to drive a ball into the front surface of the game board 13 is disposed, and the operation of the ball launching unit 112a is permitted inside the operation handle 51. Touch sensor 51a, a push button-type stop switch 51b for stopping the launch of the ball during the pressing operation, and a variable resistor for detecting the amount of rotation of the operating handle 51 by a change in electric resistance (Not shown). When the operation handle 51 is rotated clockwise by the player, the touch sensor is turned on and the resistance value of the variable resistor changes corresponding to the operation amount, and according to the rotation operation amount of the operation handle 51. A ball is fired with a strength corresponding to the resistance value of the variable resistor that changes, and the ball is driven into the front surface of the game board 13 with a jump amount corresponding to the player's operation. Further, when the operation handle 51 is not operated by the player, the touch sensor 51a and the stop switch 51b are off.

  In the lower part of the front of the lower plate 50, a ball removal lever 52 is provided for operating when the balls stored in the lower plate 50 are discharged downward. The ball removal lever 52 is always urged in the right direction. By sliding the ball release lever 52 in the left direction against the urge, the bottom opening formed in the bottom surface of the lower plate 50 is opened. A ball naturally falls from the bottom opening and is discharged. The operation of the ball removal lever 52 is normally performed in a state where a box (generally referred to as “a thousand box”) for receiving the balls discharged from the lower plate 50 is placed below the lower plate 50. As described above, the operation handle 51 is disposed on the right side of the lower plate 50, and the ashtray 53 is attached on the left side of the lower plate 50.

  As shown in FIG. 2, the game board 13 includes a wooden base plate 60 cut into a substantially square shape when viewed from the front, a large number of ball nails, windmills and rails 61 and 62, a general winning opening 63, The ball entrance 64, the variable winning device 65, the variable display device unit 80, and the like are assembled, and the peripheral edge thereof is attached to the back side of the inner frame 12. The general winning port 63, the first winning port 64, the variable winning device 65, and the variable display device unit 80 are arranged in a through hole formed in the base plate 60 by router processing, and the wood screw is provided from the front side of the game board 13. It is fixed by etc. Further, the front center portion of the game board 13 can be viewed from the front side of the inner frame 13 through the window portion 14c (see FIG. 1) of the front frame 14. Below, the structure of the game board 13 is demonstrated.

  An outer rail 62 formed by bending a strip-shaped metal plate into a substantially arc shape is planted on the front surface of the game board 13, and the strip-shaped metal plate is located on the inner side of the outer rail 62 in the same manner as the outer rail 62. The arc-shaped inner rail 61 formed by the above is planted. The inner rail 61 and the outer rail 62 surround the outer periphery of the front surface of the game board 13, and the game board 13 and the glass unit 16 (see FIG. 1) surround the front and rear. A game area in which a game is played is formed by the behavior of. The game area is a front surface of the game board 13 and is a substantially circular area formed by dividing the two rails 61 and 62 and the arc member 70 (a winning hole or the like is provided, Area).

  The two rails 61 and 62 are provided to guide the ball fired from the ball launching unit 112a to the upper part of the game board 13. A return ball preventing member 68 is attached to the front end portion of the inner rail 61 (upper left portion in FIG. 2) to prevent the ball once guided to the upper portion of the game board 13 from returning to the ball guide path again. Is done. A return rubber 69 is attached to the tip of the outer rail 62 (upper right part in FIG. 2) at a position corresponding to the maximum flying portion of the sphere, and the ball launched at a predetermined momentum or more hits the return rubber 69 and gains momentum. Is bounced back to the center while being attenuated. A resin arc member 70 formed by providing an arc connecting the rails on the inner surface side between the lower right end of the inner rail 61 and the upper right end of the outer rail 62 is a base. The plate 60 is driven and fixed.

  A first symbol display device 37 provided with a plurality of LEDs 37a, which are light emitting means, and a 7-segment display 37b is disposed in the upper right portion of the game area as viewed from the front (upper right portion in FIG. 2). The first symbol display device 37 displays information corresponding to each control performed by the main control device 110, and mainly displays the gaming state of the pachinko machine 10. The plurality of LEDs 37a indicate whether the pachinko machine 10 is in the process of being probabilistically changing, operating in a short time, or in a normal state, indicating whether the pachinko machine 10 is changing or not by a lighting state, and the symbols corresponding to the probable big hit. Whether the symbol is a symbol corresponding to a normal jackpot or an out-of-game symbol is indicated by a lighting state, or the number of reserved balls is indicated by a lighting state. The 7-segment display device 37b displays the number of rounds that are a big hit and an error display. In addition, LED37a is comprised so that the light emission color (for example, red, green, blue) of each LED may differ, The various game states of the pachinko machine 10 can be suggested with few LEDs by the combination of the light emission color. .

  In addition, the above-mentioned pachinko machine 10 being probable is a game state in which the jackpot probability is increased and it is easy to shift to the special game state. Further, during the probability change in the present embodiment, the game is in a state where the hit probability of the second symbol is increased and the ball easily enters the first entrance 64. In addition, the time when the pachinko machine 10 is short-running is a game state in which it is easy for a ball to easily enter the first entrance 64 by increasing only the hit probability of the second symbol without changing the jackpot probability. In addition, when the pachinko machine 10 is in a normal state, it is a game state in which neither the probability change nor the time is short (the state where neither the big hit probability nor the second symbol hit probability is increased). It should be noted that, depending on the gaming state of the pachinko machine 10, the time for opening the electric accessory (not shown) associated with the first entrance 64 and the number of times the electric accessory is released per hit are changed. It is good as a thing.

  The game area is provided with a plurality of general winning openings 63 through which 5 to 15 balls are paid out as winning balls when the balls win. In addition, a variable display device unit 80 is disposed in the central portion of the game area. The variable display device unit 80 includes a third symbol display device 81 configured with a liquid crystal display (hereinafter simply referred to as “display device”) that displays the third symbol in a variable manner with a winning at the first entrance 64 as a trigger. And a second symbol display device 82 composed of a light emitting diode (hereinafter abbreviated as “LED”) for variably displaying the second symbol with the passage of the ball at the second entrance 67 as a trigger. .

  The display content of the third symbol display device 81 is controlled by a display control device 114, which will be described later, and for example, three symbol sequences of left, middle and right are displayed. Each symbol row is composed of a plurality of symbols, and these symbols are vertically scrolled for each symbol row so that the third symbol is variably displayed on the display screen of the third symbol display device 81. Further, in the present embodiment, the third symbol display device 81 is constituted by a large liquid crystal display of 8 inch size, and the variable display device unit 80 surrounds the outer periphery of the third symbol display device 81 so as to surround the center frame. 86 is arranged. In the third symbol display device 81 of the present embodiment, the display of the gaming state accompanying the control of the main control device 110 is performed by the first symbol display device 37, whereas the display of the first symbol display device 37 is performed. The decorative display according to is performed. Instead of the display device, for example, the third symbol display device 81 may be configured using a reel or the like.

  In addition, when the ball enters the first entrance 64 until the stop symbol (any one of the probable jackpot symbol, the normal jackpot symbol, or the off symbol) is displayed on the first symbol display device 37. The number of entered balls is held up to 4 times, and the number of held times is indicated by the first symbol display device 37 and the number of lights of the holding lamp 85. Four hold lamps 85 are provided for the maximum number of holds, and are arranged symmetrically above the third symbol display device 81. In the present embodiment, the winning at the first entrance 64 is configured to be held up to 4 times, but the maximum holding number is not limited to 4 times, but 3 times or less. Alternatively, the number may be set to 5 times or more (for example, 8 times). In addition, the hold lamp 85 is deleted, and the number of times the variable display is held based on the winning at the first entrance 64 is numerically held in a part of the third symbol display device 81, or the area divided into four is held. You may make it display in a different aspect (for example, a color and a lighting pattern) by the frequency | count. In addition, since the number of times of holding is indicated by the first symbol display device 37, the holding lamp 85 may not perform lighting display.

  The second symbol display device 82 includes a second symbol display unit 83 and a holding lamp 84, and each time the ball passes through the second entrance 67, the display unit 83 displays a display symbol (second symbol). The “○” symbol and the “×” symbol are alternately lit and displayed in a variable manner. When the fluctuation display stops at a predetermined symbol (in this embodiment, the symbol “O”) The 1 entrance 64 is configured to be activated (opened) for a predetermined time. The number of passes through the second entrance 67 of the sphere is suspended up to a maximum of 4 times, and the number of suspensions is displayed by the above-described first symbol display device 37 and is also lit on the hold lamp 84. The second symbol variation display is performed by switching on and off of a plurality of lamps in the display unit 83 as in the present embodiment, as well as the first symbol display device 37 and the third symbol display device. A part of 81 may be used. Similarly, the hold lamp 84 may be turned on by a part of the third symbol display device 81. In addition, the passage of the second entrance 67 is not limited to 4 times as in the case of the 1st entrance 64, and is not limited to 4 times, or 3 times or less (for example, (8 times). In addition, since the number of times of holding is indicated by the first symbol display device 37, the holding lamp 84 may not perform lighting display.

  Below the variable display device unit 80, a first entrance 64 into which a sphere can enter is disposed. When a ball enters the first entrance 64, a first entrance switch (not shown) provided on the back side of the game board 13 is turned on, and the first entrance switch is turned on. The main controller 110 performs a lottery lottery, and a display corresponding to the lottery result is indicated by the LED 37 a of the first symbol display device 37. The first entrance 64 is also one of the entrances through which 5 balls are paid out as prize balls when a ball enters.

  A variable winning device 65 is disposed below the first ball opening 64, and a horizontally-long rectangular specific winning port (large opening) 65a is provided at a substantially central portion thereof. In the pachinko machine 10, when the lottery in the main controller 110 is a big hit, after a predetermined time (fluctuation time) has elapsed, the LED 37a of the first symbol display device 37 is turned on so as to become a big hit stop symbol. The stop symbol corresponding to the jackpot is displayed on the third symbol display device 81 to indicate the occurrence of the jackpot. Thereafter, the gaming state transitions to a special gaming state (big hit) where the ball is easy to win. In this special gaming state, the special winning opening 65a that is normally closed is opened for a predetermined time (for example, until 30 seconds have elapsed or ten balls have been won).

  The specific winning opening 65a is closed when a predetermined time elapses, and after the closing, the specific winning opening 65a is opened again for a predetermined time. The opening / closing operation of the specific winning opening 65a can be repeated up to 16 times (16 rounds), for example. The state in which the opening / closing operation is performed is a form of a special gaming state advantageous to the player, and the player is given out a larger amount of prize balls than usual in order to give a gaming value (game value). Is done.

  Specifically, the variable winning device 65 is a horizontally long rectangular opening / closing plate covering the specific winning opening 65a, and a large opening opening solenoid (not shown) for driving to open / close forward with the lower side of the opening / closing plate as an axis. And. The special winning opening 65a is normally closed so that the ball cannot win or is difficult to win. In the case of a big hit, the large opening opening solenoid is driven to tilt the opening / closing plate to the lower front side to temporarily form an open state in which the ball is likely to win the specific winning opening 65a. It operates to repeat the state and the state alternately.

  Note that the special gaming state is not limited to the above-described form. When the game area is provided with a large opening that is opened and closed separately from the specific winning opening 65a, and the LED 37a corresponding to the jackpot is turned on in the first symbol display device 37, the specific winning opening 65a is opened for a predetermined time, and the specific winning opening A special gaming state is defined as a game state in which a large opening provided separately from the specific winning port 65a is opened for a predetermined time and a predetermined number of times when the ball 65 is opened into the specific winning port 65a. You may make it form.

  Adhesive spaces K1, K2 for adhering certificate papers, identification labels, etc. are provided at the left and right corners on the lower side of the game board 13, and the certificate paper, etc., adhered to the adhesive space K1, is a front frame 14. It can be visually recognized through the small window 35 (see FIG. 1).

  Further, the game board 13 is provided with an out port 66. A ball that has not entered any of the winning openings 63, 64, 65a is guided through an out port 66 to a ball discharge path (not shown). A number of nails are planted on the game board 13 in order to appropriately disperse and adjust the falling direction of the ball, and various members (instruments) such as a windmill are arranged.

  As shown in FIG. 3, control board units 90 and 91 and a back pack unit 94 are mainly provided on the back side of the pachinko machine 10. The control board unit 90 is unitized by mounting a main board (main control apparatus 110), an audio lamp control board (audio lamp control apparatus 113), and a display control board (display control apparatus 114). The control board unit 91 is unitized by mounting a payout control board (payout control apparatus 111), a firing control board (launching control apparatus 112), a power supply board (power supply apparatus 115), and a card unit connection board 116.

  The back pack unit 94 includes a back pack 92 and a dispensing unit 93 that form a protective cover. In addition, each control board is used for MPU as a one-chip microcomputer that controls each control, a port for communicating with various devices, a random number generator used for various lotteries, time counting and synchronization. A clock pulse generation circuit or the like is mounted as necessary.

  The main control device 110, the sound lamp control device 113 and the display control device 114, the payout control device 111 and the firing control device 112, the power supply device 115, and the card unit connection board 116 are housed in the board boxes 100 to 104, respectively. . The board boxes 100 to 104 include a box base and a box cover that covers the opening of the box base. The box base and the box cover are connected to each other, and each control device and each board are accommodated.

  Further, the substrate box 100 (main control device 110) and the substrate box 102 (dispensing control device 111 and launch control device 112) connect the box base and the box cover so that they cannot be opened by a sealing unit (not shown) (caulking structure). Consolidated). In addition, a seal (not shown) is attached to the connecting portion between the box base and the box cover so as to cover the box base and the box cover. This seal seal is made of a brittle material. If the seal is to be peeled off in order to open the substrate boxes 100, 102, or if the substrate boxes 100, 102 are forcibly opened, the box base side and the box cover are removed. Cut to the side. Therefore, it is possible to know whether or not the substrate boxes 100 and 102 have been opened by checking the sealing unit or the sealing seal.

  The payout unit 93 includes a tank 130 that is located at the top of the back pack unit 94 and opens upward, a tank rail 131 that is connected to the lower side of the tank 130 and is gently inclined toward the downstream side, and downstream of the tank rail 131. A case rail 132 that is vertically connected to the side, and a payout device 133 that is provided at the most downstream portion of the case rail 132 and that pays out a ball by a predetermined electrical configuration of the payout motor 216 (see FIG. 5). ing. The tank 130 is successively replenished with balls supplied from the island equipment of the game hall, and a required number of balls are paid out by the payout device 133 as appropriate. A vibrator 134 for applying vibration to the tank rail 131 is attached to the tank rail 131.

  The payout control device 111 is provided with a state return switch 120, the firing control device 112 is provided with a variable resistor operation knob 121, and the power supply device 115 is provided with a RAM erase switch 122. The state return switch 120 is operated, for example, to eliminate ball clogging (return to a normal state) when a payout error occurs, such as ball clogging in the payout motor 216 (see FIG. 4). The operation knob 121 is operated to adjust the firing force of the firing solenoid. The RAM erase switch 122 is operated when the power is turned on to return the pachinko machine 10 to the initial state.

  Next, the internal configuration of the pachinko machine 10 will be described with reference to FIG. FIG. 4 is a perspective view of the pachinko machine 10 in a state where the inner frame 12, the front frame 14, and the lower dish unit 15 are opened.

  The pachinko machine 10 is provided with an outer frame 11 that forms an outer shell thereof, and an inner frame 12 is supported to the outer frame 11 so as to be opened and closed. In the game hall, the outer peripheral surface of the outer frame 11 is fixed to an installation location called an island of the game hall. Since the inner frame 12, the front frame 14, and the lower dish unit 15 are configured to be openable to the front side with respect to the outer frame 11, the inner frame 12, the front frame 14, and the lower dish unit 15 are not touched from the front side of the pachinko machine 10. Inspection and adjustment are performed with the inner frame 12 and the like open to the front side with respect to the outer frame 11.

  In order to support the inner frame 12, metal upper hinges (not shown) and lower hinges (not shown) are attached to the outer frame 11 at two upper and lower positions on the left side when viewed from the front. The inner frame 12 is supported so as to be openable and closable with the side on which the upper and lower hinges are provided as an opening / closing axis.

  The inner frame 12 is mainly composed of an ABS resin inner frame base 55 formed in a rectangular shape, and a substantially circular central window 55 a is formed at the center of the inner frame base 55. An attachment portion for the game board 13 is provided on the back side of the inner frame base 55, and the game board 13 is detachably attached.

  The lower side of the central window 55a of the inner frame base 55 is formed in a concave shape with the front side open, and a flat mounting surface 52b is formed on the back side. On the mounting surface 52b, a launch unit 140 for launching a ball to the front surface of the game board 13, a passage forming member 54 that forms a passage for discharging the ball to the upper plate 17 and the lower plate 50, and the like are attached.

  Between the outer frame 11 and the inner frame 12, switches SW1 (SW1a, SW1b) for detecting opening and closing of the inner frame 12 are provided, and between the inner frame 12 and the front frame 14, a front surface is provided. Switches SW2 (SW2a, SW2b) for detecting opening and closing of the frame 14 are provided. The switch SW1 is composed of a female switch SW1a disposed on the surface of the outer frame 11 facing the inner frame 12, and a male switch SW1b disposed on the surface of the inner frame 12 facing the outer frame 11. The The switch SW2 includes a female switch SW2a disposed on the surface of the inner frame 12 facing the front frame 14, and a male switch SW2b disposed on the surface of the front frame 14 facing the inner frame 12. Composed.

  Here, the structure of the switch SW1 and the switch SW2 will be described with reference to FIG. Since the switch SW1 and the switch SW2 have the same structure, the structure of the switch SW1 will be described, and the description of the switch SW2 will be omitted.

  FIG. 5 is a diagram showing the structure of the switch SW1. FIG. 5A is a diagram showing a state (cut-off state) of the switch SW1 in a state where the inner frame 12 is closed. FIG. 5B is a diagram showing a state (conducting state) of the switch SW1 in a state where the inner frame 12 is opened.

  As shown in FIG. 5A, the female switch SW1a disposed on the surface of the outer frame 11 facing the inner frame 12 incorporates a pair of terminal pairs SW1c made of metal as a conductive member. ing. When the inner frame 12 is closed, the female switch SW1a disposed on the surface of the outer frame 11 facing the inner frame 12 is connected to the male switch SW1a disposed on the surface of the inner frame 12 facing the outer frame 11. The mold switch SW1b is inserted, and contact between the terminal pairs SW1c is prevented. Therefore, in a state where the inner frame 12 is closed, the switch SW1 is in a state where conduction is cut off.

  On the other hand, as shown in FIG. 5B, in a state where the inner frame 12 is opened, the female switch SW1a disposed on the surface of the outer frame 11 facing the inner frame 12 is connected to the outside of the inner frame 12. The male switch SW1b disposed on the surface facing the frame 11 is pulled out. Since the terminal pair SW1c built in the female switch SW1a has a structure in which an urging force is generated in the opposite direction, the terminal pair SW1c is in contact with each other when the male switch SW1b is pulled out from the female switch SW1a. To do. Therefore, in a state where the inner frame 12 is opened, the switch SW1 is in a conductive state.

  As described above, the switch SW1 is in a cut-off state when the inner frame 12 is closed, and is in a conductive state when the inner frame 12 is opened. However, the structure of the switch SW1 is not limited to the shape shown in FIG. 5, and when the inner frame 12 is closed, the switch SW1 is in a cut-off state, while in the state where the inner frame 12 is opened, Any structure may be used as long as the switch SW1 is in a conductive state. The same applies to the structure of the switch SW2.

  Next, the electrical configuration of the pachinko machine 10 will be described with reference to FIG. FIG. 6 is a block diagram showing an electrical configuration of the pachinko machine 10.

  The main controller 110 is equipped with an MPU 201 as a one-chip microcomputer that is an arithmetic unit. The MPU 201 includes a ROM 202 that stores various control programs executed by the MPU 201 and fixed value data, and a memory that temporarily stores various data when the control program stored in the ROM 202 is executed. A certain RAM 203 and various other circuits such as an interrupt circuit, a timer circuit, and a data transmission / reception circuit are incorporated. Various commands are transmitted from the main control device 110 to the sub control device by the data transmission / reception circuit in order to instruct the sub control device such as the payout control device 111 and the sound lamp control device 113 to operate. Such a command is transmitted from the main controller 110 to the sub controller only in one direction.

  The RAM 203 stores the contents of the internal registers of the MPU 201, the return address of the control program executed by the MPU 201, and the work area (work area for storing various flags and counters, I / O values, etc. Area). The RAM 203 is configured to hold (backup) data by being supplied with a backup voltage from the power supply device 115 even after the power of the pachinko machine 10 is shut off, and all data stored in the RAM 203 is backed up.

  When the power is shut down due to the occurrence of a power failure or the like, the stack pointer and the value of each register when the power is shut off (including when the power failure occurs, the same applies hereinafter) are stored in RAM 203. On the other hand, at the time of power-on (including power-on due to power failure cancellation, the same applies hereinafter), the state of the pachinko machine 10 is restored to the state before power-off based on information stored in the RAM 203. Writing to the RAM 203 is executed when the power is shut off by the main process (see FIG. 12), and restoration of each value written in the RAM 203 is executed in a startup process (see FIG. 11) when the power is turned on. Note that the power failure signal SG1 from the power failure monitoring circuit 252 is input to the NMI terminal (non-maskable interrupt terminal) of the MPU 201 when the power is interrupted due to the occurrence of a power failure or the like. Is input immediately, the NMI interrupt process (see FIG. 17) as a power failure process is immediately executed.

  An input / output port 205 is connected to the MPU 201 of the main control device 110 via a bus line 204 composed of an address bus and a data bus. The input / output port 205 includes a payout control device 111, a sound lamp control device 113, a first symbol display device 37, a second symbol display device 82, various switches 208 including a switch group and a sensor group (not shown), and a specific prize. A solenoid 209 comprising a large opening solenoid for opening and closing the front side with the lower side of the opening and closing plate of the opening 65a as an axis, a solenoid for driving an electric accessory, and the like is connected.

  The main controller 110 is also provided with a frame opening detection circuit 260 that detects opening of the inner frame 12 when the switch SW1 is turned on and detects opening of the front frame 14 when the switch SW2 is turned on. Yes. Connected to the frame opening detection circuit 260 are a switch SW1 for detecting the opening of the inner frame 12, a switch SW2 for detecting the opening of the front frame 14, and an external output terminal plate 261 configured to be connectable to the hall computer 262. Has been. It should be noted that an input / output unit (input / output port 205 and an input / output port) that inputs and outputs signals is used to connect the switches SW1 and SW2 to the frame opening detection circuit 260 and to connect the frame opening detection circuit 260 and the external output terminal plate 261. Are connected via different input / output ports (not shown). The frame open detection circuit 260 maintains the output from the external output terminal board 261 to the hall computer 262 in a high state when the inner frame 12 and the front frame 14 are closed and the switch SW1 and the switch SW2 are shut off. . That is, the frame open detection circuit 260 outputs a high signal from the external output terminal board 261 to the hall computer 262 when the inner frame 12 and the front frame 14 are closed.

  On the other hand, when the inner frame 12 is opened and the switch SW1 is turned on, or when the front frame 14 is opened and the switch SW2 is turned on, the frame opening detection circuit 260 has an external output terminal for about 10 ms after the opening. The output from the board 261 to the hall computer 262 is switched from the high state to the low state. In other words, the frame open detection circuit 260, when either one or both of the inner frame 12 and the front frame 14 are opened, from the external output terminal board 261 to the hall computer 262 for about 10 ms from the opening. Stop the high signal being output. The stop of the high signal is stored in the hall computer 262 that continues to operate for 24 hours. Therefore, by analyzing the information stored in the hall computer 262, the opening of the inner frame 12 or the front frame 14 can be detected.

  Here, the frame opening detection circuit 260 is configured not to be connected to the MPU 201 or the input / output port 205 (input / output port of the MPU 201) of the main controller 110. Therefore, the frame opening detection circuit 260 may be configured to be mounted on a device (circuit board) other than the main control device 110. For example, it may be mounted on a device (circuit board) on which an arithmetic device such as an MPU or CPU is not mounted, or a dedicated substrate for the frame opening detection circuit 260 may be provided and mounted thereon. More preferably, like the main control device 110, the payout control device 111, and the launch control device 112, the frame opening detection circuit 260 is accommodated in the substrate box, and the box base and the box cover provided on the substrate box are connected. The seal unit (not shown) is connected so that it cannot be opened (connection by caulking structure). A sealing seal (not shown) may be attached to the connecting portion between the box base and the box cover so as to extend over the box cover and the box base.

  The payout control device 111 drives the payout motor 216 to perform payout control of prize balls and rental balls. The MPU 211, which is an arithmetic unit, includes a ROM 212 that stores a control program executed by the MPU 211, fixed value data, and the like, and a RAM 213 that is used as a work memory or the like.

  The RAM 213 of the payout control device 111, like the RAM 203 of the main control device 110, has a stack area for storing the contents of the internal registers of the MPU 211, the return address of the control program executed by the MPU 211, and various flags and counters. And a work area (work area) in which values such as I / O are stored. The RAM 213 is configured to be able to retain (backup) data by being supplied with a backup voltage from the power supply device 115 even after the power of the pachinko machine 10 is cut off, and all data stored in the RAM 213 is backed up. As with the MPU 201 of the main controller 110, the power failure signal SG1 is also input to the NMI terminal of the MPU 211 from the power failure monitoring circuit 252 when the power is interrupted due to the occurrence of a power failure or the like. When input to the MPU 211, an NMI interrupt process (see FIG. 17) is immediately executed as a power failure process.

  An input / output port 215 is connected to the MPU 211 of the payout control device 111 via a bus line 214 composed of an address bus and a data bus. The main control device 110, the payout motor 216, the firing control device 112, and the like are connected to the input / output port 215, respectively. Although not shown, the payout control device 111 is connected to a prize ball detection switch for detecting a prize ball that has been paid out. The prize ball detection switch is connected to the payout control device 111 but is not connected to the main control device 110.

  The launch control device 112 controls the ball launch unit 112a so that the launch strength of the ball according to the rotational operation amount of the operation handle 51 is obtained when the main control device 110 gives an instruction to launch a ball. The ball launching unit 112a includes a launching solenoid and an electromagnet (not shown), and the firing solenoid and the electromagnet are permitted to be driven when predetermined conditions are met. Specifically, the operation handle 51 is detected on the condition that the touch sensor 51a detects that the player is touching the operation handle 51 and the stop switch 51b for stopping the ball firing is turned off (not operated). The firing solenoid is excited in accordance with the amount of rotation 51, and a ball is launched with a strength corresponding to the amount of operation of the operation handle 51.

  The voice lamp control device 113 is a voice output in a voice output device (such as a speaker not shown) 226, an output of lighting and extinguishing in a lamp display device (such as the illumination units 29 to 33 and the display lamp 34), and the display control device 114. The setting of the display mode of the 3rd symbol display apparatus 81 performed etc. is controlled. The MPU 221 that is an arithmetic unit includes a ROM 222 that stores a control program executed by the MPU 221, fixed value data, and the like, and a RAM 223 that is used as a work memory or the like.

  An input / output port 225 is connected to the MPU 221 of the sound lamp control device 113 via a bus line 224 including an address bus and a data bus. The main control device 110, the display control device 114, the audio output device 226, the lamp display device 227, and the like are connected to the input / output port 225, respectively.

  The display control device 114 controls the change display of the third symbol on the third symbol display device (LCD) 81. The display control device 114 includes an MPU 231, a ROM (program ROM) 232, a work RAM 233, a video RAM 234, a character ROM 235, an image controller 236, an input port 237, an output port 238, and bus lines 239 and 240. have. The input side of the input port 237 is connected to the output side of the sound lamp control device 113, and the output side of the input port 237 is connected to the MPU 231, ROM 232, work RAM 233, and image controller 236. A video RAM 234 and a character ROM 235 are connected to the image controller 236, and an output port 238 is connected via a bus line 240. A third symbol display device 81 is connected to the output side of the output port 238. Even if the pachinko machine 10 is a different model with different winning probability for winning the jackpot and the number of prize balls to be paid out in one jackpot, there is a model having the same specifications as the symbols displayed on the third symbol display device 81. Therefore, the display control device 114 is made into a common part to reduce the cost.

  The MPU 231 of the display control device 114 controls the display content of the third symbol display device 81 based on the symbol display command input from the sound lamp control device 113. The ROM 232 is a memory for storing various control programs executed by the MPU 231 and fixed value data. The work RAM 233 is a memory for temporarily storing work data and flags used when the MPU 231 executes various programs. The character ROM 235 is a memory that stores data for effects such as symbols (background symbols and third symbols) displayed on the third symbol display device 81. The video RAM 234 is a memory for storing effect data displayed on the third symbol display device 81, and the display content of the third symbol display device 81 is changed by rewriting the contents of the video RAM 234.

  The image controller 236 adjusts the timing of the MPU 231, the video RAM 234, and the output port 238 to intervene in reading and writing data, and reads display data stored in the video RAM 234 at a predetermined timing to read the third symbol display device 81. Is displayed.

  The power supply device 115 includes a power supply unit 251 for supplying power to each unit of the pachinko machine 10, a power failure monitoring circuit 252 for monitoring power interruption due to a power failure, and a RAM deletion switch 122 (see FIG. 3). And an erasing switch circuit 253. The power supply unit 251 is a device that supplies a necessary operating voltage to each of the control devices 110 to 114 through a power supply path (not shown). As its outline, the power supply unit 251 takes in the voltage of AC 24 volts supplied from the outside, and drives various switches such as various switches 208, solenoids such as the solenoid 209, motors, etc. A 5 volt voltage for logic, a backup voltage for RAM backup, and the like are generated, and the 12 volt voltage, the 5 volt voltage, and the backup voltage are supplied to the control devices 110 to 114 as necessary voltages.

  The power failure monitoring circuit 252 is a circuit for outputting a power failure signal SG1 to each NMI terminal of the MPU 201 of the main control device 110 and the MPU 211 of the payout control device 111 when the power is cut off due to the occurrence of a power failure or the like. The power failure monitoring circuit 252 monitors the DC stable voltage of 24 volts, which is the maximum voltage output from the power supply unit 251, and determines that a power failure (power interruption, power interruption) occurs when this voltage falls below 22 volts. Then, the power failure signal SG1 is output to the main controller 110 and the payout controller 111. Based on the output of the power failure signal SG1, the main controller 110 and the payout controller 111 recognize the occurrence of the power failure and execute the NMI interrupt process. Note that the power supply unit 251 outputs a voltage of 5 volts, which is a drive voltage of the control system, for a time sufficient to execute the NMI interrupt processing even after the DC stable voltage of 24 volts becomes less than 22 volts. Is maintained at a normal value. Therefore, main controller 110 and payout controller 111 can normally execute and complete the NMI interrupt process (see FIG. 17).

  The RAM erase switch circuit 253 is a circuit for outputting a RAM erase signal SG2 for clearing backup data to the main controller 110 when the RAM erase switch 122 is pressed. When the RAM erase signal SG2 is input when the pachinko machine 10 is turned on, the main control device 110 and the payout control device 111 clear the respective backup data and the payout control device 111 for clearing the backup data. A payout initialization command is transmitted to the payout control device 111.

  Next, the frame opening detection circuit 260 and the external output terminal plate 261 will be described with reference to FIG. FIG. 7 is a circuit diagram showing the electrical configuration of the frame opening detection circuit 260 and the external output terminal plate 261. In FIG. 7, the frame opening detection circuit 260 is described first, and then the external output terminal plate 261 is described.

  A frame opening detection circuit 260 that detects opening of the inner frame 12 or opening of the front frame 14 includes a DC power supply DC1 that supplies a DC voltage of 12 volts, a diode D1, a storage battery SB1, capacitors CD2 to CD5, and a resistor R1. ˜R4, a timer IC1 (LMC555 manufactured by National Semiconductor), an exclusive OR circuit (hereinafter referred to as “EXOR circuit”) IC2, an internal resistor R5 and an internal resistor R6 are provided. The transistor TR1 is mainly included.

  In order to detect the opening of the inner frame 12 when the switch SW1 is turned on and to detect the opening of the front frame 14 when the switch SW2 is turned on, the frame opening detection circuit 260 has the above components shown in FIG. Connected according to circuit diagram.

  The DC power source DC1 is a power source that supplies a DC voltage of 12 volts to the open frame detection circuit 260 and the external output terminal board 261. Power (power) to the DC power supply DC1 is supplied from a power supply unit 251 provided in the power supply device 115 through a power supply path (not shown). This DC power supply DC1 is connected to the anode terminal of the diode D1. The positive terminal of the storage battery SB1 is connected to the cathode terminal of the diode D1. The negative terminal of the storage battery SB1 is grounded. The positive terminal of the storage battery SB1 is connected to one end of the switch SW1, one end of the switch SW2, the VDD terminal and the RES terminal of the timer IC1, and one end of the resistor R7 of the external output terminal plate 261.

  The storage battery SB1 supplies a DC voltage to the open frame detection circuit 260 and the external output terminal plate 261 when the power supply to the pachinko machine 10 is cut off and a DC voltage of 12 volts is not supplied from the DC power supply DC1. Next battery.

  The storage battery SB1 is supplied with power to the pachinko machine 10, and when a DC voltage of 12 volts is supplied from the DC power supply DC1, the DC voltage applied to the storage battery SB1 (12 supplied from the DC power supply DC1). Charging is performed by approximately 11.3 volts minus a voltage drop of approximately 0.7 volts at the diode D1.

  On the other hand, the storage battery SB1 has, for example, a frame open detection circuit when the business hours of the amusement hall are over and the power supply to the pachinko machine 10 is cut off and a DC voltage of 12 volts is not supplied from the DC power supply DC1. A DC voltage having an electromotive force of approximately 11.3 volts is supplied to 260 and the external output terminal plate 261. The storage battery SB1 has a capacity capable of supplying a DC voltage of about 11.3 volts to the open frame detection circuit 260 and the external output terminal plate 261 for at least 15 hours when fully charged. Note that the capacitor is not limited to the storage battery SB1, and a sufficiently large capacitor capable of supplying a DC voltage of about 11.3 volts to the open frame detection circuit 260 and the external output terminal plate 261 for at least 15 hours may be used.

  Therefore, the frame opening detection circuit 260 operates naturally when power is supplied to the pachinko machine 10 and a DC voltage of 12 volts is supplied from the DC power supply DC1, and further, for example, a game hall business Even when the power supply to the pachinko machine 10 is interrupted and the DC voltage of 12 volts is not supplied from the DC power supply DC1, the frame open detection circuit 260 and the external output terminal board are used by the storage battery SB1. It can operate by supplying a DC voltage (about 11.3 volts) to H.261. Therefore, the frame opening detection circuit 260 is supplied with power to the pachinko machine 10 and supplied with a DC voltage of 12 volts from the DC power supply DC1, and the power supply to the pachinko machine 10 is cut off. Even when a DC voltage of 12 volts is not supplied from the power source DC1, the opening of the inner frame 12 and the opening of the front frame 14 can be detected.

  Note that the cathode terminal of the diode D1 is connected to the positive terminal of the storage battery SB1, and this diode D1 functions to prevent the backflow of current, so that the storage battery SB1 is connected to the frame open detection circuit 260 and the external output terminal plate 261. Even when the DC voltage (about 11.3 volts) is supplied, the DC voltage (about 11.3 volts) supplied by the storage battery SB1 is applied to the DC power source DC1, and the DC power source DC1 is not damaged.

  The timer IC1 is a CMOS timer and detects the opening of the inner frame 12 or the opening of the front frame 14 by connecting the resistors R1 and R2 of 100 kΩ and the capacitors CD3 to CD5 of 0.1 μF, and the external output terminal plate 261 Functions as a circuit that cuts off the energization of the photocoupler PR1 for about 10 ms.

  The operating voltage range of the timer IC 1 is that of the MPU 201 mounted on the main control device 110, the MPU 211 mounted on the payout control device 111, the MPU 221 mounted on the sound lamp control device 113, and the MPU 231 mounted on the display control device 114. It is set in a wider range than each operating voltage range. Specifically, the operating voltage range of the timer IC 1 is about 1.5 volts to about 12.0 volts, while the operating voltage ranges of the MPUs 201, 211, 2221, and 231 are about 4.5 volts. It is about 5.5 volts (each operating voltage in this embodiment is about 5.0 volts). Therefore, the timer IC 1 can operate at a voltage lower than the operating voltages of the MPUs 201, 211, 211, 231. Therefore, even if the charged amount of the storage battery SB1 decreases and the voltage supplied by the storage battery SB1 drops below about 4.5 volts, the timer IC1 can operate sufficiently. Further, for example, when the business hours of the amusement hall are over and the power supply to the pachinko machine 10 is shut off and the DC voltage of 12 volts is not supplied from the DC power source DC1, that is, the timer IC1 is switched to DC by the storage battery SB1. The case where the voltage is supplied and the case where the power supply to the pachinko machine 10 is performed and the DC voltage of 12 volts is supplied from the DC power source DC1 are combined. Therefore, of course, the timer IC 1 can operate at a DC voltage of 12 volts or less supplied to the frame opening detection circuit 260 when power is supplied to the pachinko machine 10. Furthermore, since the timer IC1 is a timer composed of a C-MOS semiconductor, power consumption during operation can be suppressed and operation can be performed for a long time.

  The VDD terminal of the timer IC1 is a terminal for inputting a DC voltage supplied to the timer IC1, and is connected to the plus terminal of the storage battery SB1. The VDD terminal of the timer IC1 is connected to one end of a 0.1 μF capacitor CD4, and the other end of the capacitor CD4 is connected to the GND terminal of the grounded timer IC1. The capacitor CD4 reduces the noise generated at the VDD terminal of the timer IC1 when the inner frame 12 and the front frame 14 are opened or closed and the switch SW1 and the switch SW2 are turned on or off.

  The RES terminal of the timer IC 1 is a terminal for operating a reset function for forcibly stopping the voltage output from the OUT terminal (zero volts) when a pulse signal is input to the RES terminal. However, since this frame open detection circuit 260 does not use this reset function, the RES terminal of the timer IC 1 is connected to the plus terminal of the storage battery SB 1 so that the reset function is not activated. Since the VDD terminal of timer IC1 and the RES terminal of timer IC1 are connected to the positive terminal of storage battery SB1 as described above, a DC voltage of about 11.3 volts is applied to the VDD terminal and RES terminal of timer IC1. Is applied.

  When the switch SW1 and the switch SW2 are cut off (when the inner frame 12 and the front frame 14 are closed), the TRG terminal of the timer IC1 reduces the voltage output from the OUT terminal of the timer IC1. When one of the switches SW1 and SW2 or both of the switches SW1 and SW2 is in a conductive state (either the inner frame 12 or the front frame 14, Or, when both the inner frame 12 and the front frame 14 are in an open state), the voltage output from the OUT terminal of the timer IC 1 is a terminal for setting from about 10.6 volts to zero volts after about 10 ms. . The TRG terminal of the timer IC1 is connected to one input terminal of the EXOR circuit IC2, one end of the resistor R2, one end of the capacitor CD5, the other end of the switch SW1, the other end of the switch SW2, and one end of the resistor R1. The other end of the resistor R2 and the other end of the capacitor CD5 are grounded.

  The resistor R2 connected to the TRG terminal of the timer IC1 is connected to the timer IC1 when the switch SW1 and the switch SW2 are in the conductive state (see FIG. 5B), that is, when the inner frame 12 and the front frame 14 are in the open state. This is a resistor for applying a DC voltage (about 11.3 volts) to the TRG terminal. The capacitor CD5 is a capacitor for reducing noise generated in the resistor R2 when the switch SW1 and the switch SW2 are turned on or off (when the inner frame 12 and the front frame 14 are opened or closed). is there.

  With the above connection, when the inner frame 12 and the front frame 14 are in the closed state and the switch SW1 and the switch SW2 are in the cut-off state, no voltage is supplied to the resistor R2 and the capacitor CD5, so that the voltage is applied to the resistor R2 and the capacitor CD5. That is, the voltage applied to the TRG terminal of the timer IC1 is zero volts. At this time, the voltage output from the OUT terminal of the timer IC 1 is about 10.6 volts.

  On the other hand, either the inner frame 12 or the front frame 14, or both the inner frame 12 and the front frame 14 are in an open state, and either the switch SW1 or the switch SW2 or both the switch SW1 and the switch SW2 are conductive. Since the voltage is supplied to the resistor R2 and the capacitor CD5 when in the state, the voltage applied to the resistor R2 and the capacitor CD5, that is, the voltage applied to the TRG terminal of the timer IC1 is the voltage of the positive terminal of the storage battery SB1. The same as that of about 11.3 volts. At this time, the voltage output from the OUT terminal of the timer IC 1 is about 10.3 for about 10 ms after either the switch SW 1 or the switch SW 2 or both the switch SW 1 and the switch SW 2 are in the conductive state. 6 volts, then zero volts.

  In this way, the voltage output from the OUT terminal of the timer IC 1 can be set to about 10.6 volts or zero volts by the voltage applied to the TRG terminal of the timer IC 1. When the inner frame 12 or the front frame 14 is opened, the switch SW1 or the switch SW2 is turned on, and the voltage applied to the TRG terminal of the timer IC 1 rises from zero volts to about 11.3 volts, the voltage rises. About 10 ms later, the voltage of about 10.6 volts output from the OUT terminal of the LMC 555 falls to zero volts. As will be described in detail later, the collector of the transistor TR1 is obtained by the time difference (about 10 ms) between the rising edge of the voltage applied to the TRG terminal of the timer IC1 and the falling edge of the voltage output from the OUT terminal of the timer IC1. The conduction between the terminal c and the emitter terminal e can be cut off for about 10 ms, and the conduction of the photocoupler PR1 on the external output terminal plate 261 can be cut off for about 10 ms.

  When the inner frame 12 and the front frame 14 are closed, the switch SW1 and the switch SW2 are shut off, and the voltage applied to the TRG terminal of the timer IC1 becomes zero volts, the OUT terminal of the timer IC1 has a voltage of about 10.6 volts. Is output, the inner frame 12 or the front frame 14 is opened, the switch SW1 or the switch SW2 is turned on, and the voltage applied to the TRG terminal of the timer IC1 rises from zero volts to about 11.3 volts. This is a terminal for setting the output voltage of about 10.6 volts to zero volts with a delay of about 10 ms. This OUT terminal is connected to the other input terminal of the EXOR circuit IC2 (an input terminal not connected to the TRG terminal of the timer IC1). The output terminal of the EXOR circuit IC2 is connected to one end of the resistor R3.

  The EXOR circuit IC2 has a voltage at the TRG terminal of the timer IC1 (about 11.3 volts in the high state and zero volts at the low state) and a voltage at the OUT terminal of the timer IC1 (about 10.6 volts in the high state and zero volts in the low state). ) Is a circuit that outputs approximately 11.3 volts from the output terminal, and otherwise outputs zero volts from the output terminal.

  The EXOR circuit IC2 has one input terminal connected to the TRG terminal of the timer IC1, the other input terminal connected to the OUT terminal of the timer IC1, and an output terminal connected to one end of the resistor R3. And although this EXOR circuit IC2 is not shown in figure, the power supply terminal is connected to the plus terminal of storage battery SB1.

  Therefore, when the voltage output from the OUT terminal of the timer IC 1 is about 10.6 volts and the voltage applied to the TRG terminal of the timer IC 1 is zero volts, that is, the inner frame 12 and the front frame 14 are closed. Or when the voltage output from the OUT terminal of the timer IC1 is zero volts and the voltage applied to the TRG terminal of the timer IC1 is about 10.6 volts, that is, the inner frame 12 or the front frame. When about 10 ms elapses after 14 is opened, the output of the EXOR circuit IC2 becomes a high state (about 11.3 volt state). When the output of the EXOR circuit IC2 becomes a high state, the collector terminal c and the emitter terminal e of the transistor TR1 are brought into conduction, and a high signal which is a continuous signal is output from the photocoupler PR1 to the hall computer 262.

  On the other hand, when the voltage output from the OUT terminal of the timer IC 1 is about 10.6 volts and the voltage applied to the TRG terminal of the timer IC 1 is about 11.3 volts, that is, the inner frame 12 or the front frame. If within 14 ms after 14 is opened, the output of the EXOR circuit IC2 is in a low state (zero volt state). When the output of the EXOR circuit IC2 becomes a low state, the collector terminal c and the emitter terminal e of the transistor TR1 are cut off, and the high signal output from the photocoupler PR1 to the hall computer 262 is stopped.

  The resistor R3 connected to the output terminal of the EXOR circuit IC2 and the resistor R4 connected to the resistor R3 are voltage dividing resistors for dividing the voltage output from the output terminal of the EXOR circuit IC2. One end of the resistor R3 is connected to the output terminal of the EXOR circuit IC2, and the other end of the resistor R3 is connected to one end of the capacitor CD2 and one end of the resistor R4. The other end of the capacitor CD2 and the other end of the resistor R4 are grounded. Therefore, the voltage output from the output terminal of the EXOR circuit IC2 is divided into the resistor R3 and the resistor R4 according to the ratio between the resistance value of the resistor R3 and the resistance value of the resistor R4. Since both the resistor R3 and the resistor R4 are 10 kΩ, the voltage of about 11.3 volts output from the output terminal of the EXOR circuit IC2 is about 5.7 volts maximum by the resistors R3 and R4, respectively. Divided pressure.

  The 10 μF capacitor CD2 connected in parallel with the resistor R4 is a capacitor for stabilizing the voltage applied to the resistor R4. The capacitor CD2 stabilizes the voltage applied to the resistor R4, stabilizes the bias voltage applied between the base terminal b of the transistor TR1 and the emitter terminal e of the transistor TR1, and operates the transistor TR1. Can be stabilized.

  The transistor TR1 is a switching element that switches between the conduction terminal and the interruption terminal between the collector terminal c of the transistor TR1 and the emitter terminal e of the transistor TR1 based on the voltage applied to the resistor R4. The transistor TR1 is provided with a 10 kΩ internal resistor R5 connected in series to the base terminal b. One end of the internal resistor R5 is connected to one end of the resistor R4, and the other end of the internal resistor R5 is connected to the base terminal b. Further, the transistor TR1 is provided with an internal resistance R6 of 10 kΩ between the other end of the internal resistance R5 and the emitter terminal e. The other end of the internal resistor R5 is connected to one end of the internal resistor R6, and the emitter terminal e is connected to the other end of the internal resistor R6.

  Therefore, when a voltage of about 11.3 volts is output from the output terminal of the EXOR circuit IC2 (when the inner frame 12 and the front frame 14 are closed, and the inner frame 12 or the front frame 14 is opened). When about 10 ms has passed), the voltage is divided by the resistors R3 and R4, and the voltage (about 5.7 volts) applied to the resistor R4 is connected to one end of the internal resistor R5 of the transistor TR1 and the transistor Applied between the emitter terminal e of TR1. As a result, the terminals of the collector terminal c of the transistor TR1 and the emitter terminal e of the transistor TR1 become conductive, and a current is supplied to one end of the resistor R7 of the external output terminal plate 261. If a current is supplied to one end of the resistor R7, the photocoupler PR1 of the external output terminal plate 261 can be energized to set the output to the hall computer 262 to a high state (a continuous signal from the photocoupler PR1 to the hall computer 262). Can output a high signal).

  On the other hand, when the voltage at the output terminal of the EXOR circuit IC2 is zero volts (within about 10 ms after the inner frame 12 or the front frame 14 is opened), no voltage is applied to the resistor R4. No voltage is applied between one end of the resistor R5 and the emitter terminal e of the transistor TR1. As a result, the terminal between the collector terminal c of the transistor TR1 and the emitter terminal e of the transistor TR1 is blocked, and no current is supplied to one end of the resistor R7 of the external output terminal plate 261. Therefore, the photocoupler PR1 on the external output terminal plate 261 is not energized, and the output to the hall computer 262 is in a low state (the high signal output from the photocoupler PR1 to the hall computer 262 is stopped).

  As described above, when the inner frame 12 or the front frame 14 is opened, the energization of the external output terminal plate 261 to the photocoupler PR1 can be cut off for about 10 ms. Therefore, when the inner frame 12 or the front frame 14 is in the open state, the high signal output from the external output terminal board 261 to the hall computer 262 is stopped for about 10 ms after the opening. Can do.

  The TH terminal of the timer IC1 is a terminal that measures a voltage applied to the TH terminal, and is connected to the other end of the resistor R1, one end of the capacitor CD3, and the DCH terminal of the timer IC1. The DCH terminal of the timer IC1 has a voltage (about 7.5 volts) that is 2/3 of the direct current voltage (about 11.3 volts) applied to the VDD terminal of the timer IC1. In this case, the terminal switches the impedance of the DCH terminal from an infinite state to a zero state. When the impedance of the DCH terminal becomes zero (ground state), a voltage cannot be applied to the capacitor CD3. On the other hand, when the impedance of the DCH terminal is infinite, a voltage can be applied to the capacitor CD3.

  The resistor R1 and the capacitor CD3 connected to the TH terminal of the timer IC1 and the DCH terminal of the timer IC1 are based on a time constant that is the product of the resistance value of the resistor R1 and the capacitance value of the capacitor CD3. This is a component for determining the time until the voltage of about 10.6 volts output from the OUT terminal of the timer IC1 is switched to zero volts to about 10 ms when 14 is opened. One end of the resistor R1 is connected to one of the other end of the switch SW1, the other end of the switch SW2, one end of the capacitor CD5, one end of the resistor R2, the TRG terminal of the timer IC1, and the input terminal of the EXOR circuit IC2. The other end of the resistor R1 is connected to the TH terminal of the timer IC1, the DCH terminal of the timer IC1, and one end of the capacitor CD3. The other end of the capacitor CD3 is grounded.

  Here, the resistor R1 and the capacitor CD3 will be described together with the TRG terminal of the timer IC1, the TH terminal of the timer IC1, the DCH terminal of the timer IC1, and the OUT terminal of the timer IC1.

  When the inner frame 12 and the front frame 14 are in the closed state (when the switch SW1 and the switch SW2 are in the cut-off state), no voltage is supplied to the resistor R1, so the voltage applied to the TH terminal of the timer IC1 is zero volts (about 7.5 volts). Thus, the impedance of the DCH terminal of the timer IC 1 is set to an infinite state. Therefore, a voltage can be applied to the capacitor CD3, and the capacitor CD3 is in a chargeable state (a state in which charge can be stored). However, when the switch SW1 and the switch SW2 are cut off, the connection between the positive terminal of the storage battery SB1 and the resistor R1 is cut off, so that no voltage is applied to the capacitor CD3, and the voltage applied to the capacitor CD3 is Zero volts. Thus, the capacitor CD3 is in a chargeable state, but is not charged. At this time, the voltage at the TRG terminal of the timer IC1 is zero volts (low state), and the voltage at the OUT terminal of the timer IC1 is approximately 10.6 volts (high state), so the output terminal of the EXOR circuit IC2 Is about 11.3 volts (high state), and the collector terminal c and the emitter terminal e of the transistor TR1 are electrically connected. Therefore, a current is supplied to one end of the resistor R7 of the external output terminal plate 261, and the photocoupler PR1 of the external output terminal plate 261 is energized. Therefore, a high signal is output from the external output terminal board 261 to the hall computer 262.

  Next, when the inner frame 12 or the front frame 14 is in an open state (see FIG. 5B) and the switch SW1 or the switch SW2 is in a conductive state, the voltage applied to the TRG terminal of the timer IC1 is zero volts (low state). ) To about 11.3 volts (high state). At this time, since the voltage at the OUT terminal of the timer IC1 is about 10.6 volts (low state), the voltage at the output terminal of the EXOR circuit IC2 becomes zero volts (low state), and the collector terminal c and emitter terminal of the transistor TR1. Connection with e is cut off. Then, the current supply to one end of the resistor R7 of the external output terminal plate 261 is stopped, and the energization of the external output terminal plate 261 to the photocoupler PR1 is also stopped. Therefore, the high signal output from the external output terminal board 261 to the hall computer 262 is stopped (the output from the external output terminal board 261 to the hall computer 262 is low).

  Further, at the same time when the voltage applied to the TRG terminal of the timer IC1 is switched from zero volts to about 11.3 volts, the voltage is applied to the capacitor CD3, and charging of the capacitor CD3 is started. At this time, the voltage applied to the TH terminal of the timer IC1 starts to rise.

  The voltage at the OUT terminal of the timer IC1 is 2 / of the voltage (about 11.3 volts) applied to the VDD terminal of the timer IC1 (the voltage applied to the capacitor CD3) applied to the TH terminal of the timer IC1. Continue to maintain about 10.6 volts until equal to a voltage of 3, ie, about 7.5 volts. When the voltage applied to the TH terminal of the timer IC1 (the voltage applied to the capacitor CD3) rises and becomes equal to about 7.5 volts, the impedance of the DCH terminal of the timer IC1 is changed from an infinite state to a zero state (ground To the ( Then, the voltage applied to the capacitor CD3 becomes a zero volt state, and the electric charge stored in the capacitor CD3 is discharged. As a result, the voltage applied to the TH terminal of the timer IC 1 is switched from about 7.5 volts to zero volts. By switching the voltage applied to the TH terminal of the timer IC1, the voltage at the OUT terminal of the timer IC1 switches from about 10.6 volts (high state) to zero volts (low state). At this time, since the voltage at the TRG terminal of the timer IC1 is about 11.3 volts (high state), the voltage at the output terminal of the EXOR circuit IC2 is switched from zero volts (low state) to about 11.3 volts (high state). Instead, the collector terminal c and the emitter terminal e of the transistor TR1 are brought into conduction again. Therefore, the current supply to one end of the resistor R7 of the external output terminal plate 261 is resumed, and the energization of the external output terminal plate 261 to the photocoupler PR1 is also resumed. Therefore, a high signal is output again from the external output terminal board 261 to the hall computer 262.

  As described above, when the inner frame 12 or the front frame 14 is in an open state and the switch SW1 or the switch SW2 is in a conductive state (see FIG. 5B), about 10 output from the OUT terminal of the timer IC1. The time until the voltage of .6 volts is switched to zero volts, that is, the time until the voltage applied to the TH terminal of the timer IC1 (the voltage applied to the capacitor CD3) is changed from zero volts to about 7.5 volts. Based on the time constant which is the product of the resistance value of R1 and the capacitance value of the capacitor CD3, it is determined to be about 10 ms. Then, when the inner frame 12 or the front frame 14 is opened, the current supplied to one end of the resistor R7 of the external output terminal plate 261 is stopped for about 10 ms, and the photo of the external output terminal plate 261 is stopped. Energization of the coupler PR1 can be stopped for about 10 ms. Therefore, when the inner frame 12 or the front frame 14 is in the open state, the high signal output from the external output terminal board 261 to the hall computer 262 is stopped for about 10 ms after the opening. Can do.

  When the inner frame 12 and the front frame 14 are changed from the open state to the closed state, and the switch SW1 and the switch SW2 are changed from the conductive state to the cutoff state, the voltage applied to the TRG terminal of the timer IC1 is about 11.3 volts (high state). ) To zero volts (low state), the voltage at the OUT terminal of the timer IC 1 switches from zero volts (low state) to about 10.6 volts (high state). However, since the voltage at the output terminal of the EXOR circuit IC2 remains at about 11.3 volts (high state), the collector terminal c and the emitter terminal e of the transistor TR1 remain conductive. Therefore, the current continues to be supplied to one end of the resistor R7 of the external output terminal plate 261, and the energization of the photocoupler PR1 of the external output terminal plate 261 is still performed. Accordingly, even when the inner frame 12 and the front frame 14 are changed from the open state to the closed state, and the switches SW1 and SW2 are changed from the conductive state to the closed state, a high signal is continuously output from the external output terminal board 261 to the hall computer 262. Will remain.

  As described above, when the inner frame 12 or the front frame 14 is opened, the resistor R7 of the external output terminal plate 261 is based on the time constant that is the product of the resistance value of the resistor R1 and the capacitance value of the capacitor CD3. Since the current supplied to one end of the output terminal plate 261 can be cut off for about 10 ms, the energization of the external output terminal plate 261 to the photocoupler PR1 can also be stopped for about 10 ms. Thereby, when the inner frame 12 or the front frame 14 is opened, the high signal output from the external output terminal board 261 to the hall computer 262 can be stopped for about 10 ms from the opening. .

  Returning to the description of FIG. The CNT terminal of the timer IC 1 is a terminal that adjusts the output time of the voltage output from the OUT terminal of the timer IC 1 by a signal input to the CNT terminal. However, since the frame open detection circuit 260 does not adjust the output time of the voltage output from the OUT terminal of the timer IC1, the CNT terminal of the timer IC1 is any component of the frame open detection circuit 260 and the external output terminal plate 261. It is not connected to and is open.

  As described above, when the inner frame 12 or the front frame 14 is in the open state and the switch SW1 or the switch SW2 is in the conductive state (see FIG. 5B), the frame open detection circuit 260 is about For 10 ms, the terminal between the collector terminal c of the transistor TR1 and the emitter terminal e of the transistor TR1 is cut off, and the current supply to one end of the resistor R7 of the external output terminal plate 261 is stopped. On the other hand, the frame open detection circuit 260 conducts the connection between the collector terminal c of the transistor TR1 and the emitter terminal e of the transistor TR1 from the cut-off state after about 10 ms has passed since the inner frame 12 or the front frame 14 is opened. The state is switched to, and the current supply to one end of the resistor R7 of the external output terminal plate 261 is resumed. Thereby, the energization of the external output terminal plate 261 to the photocoupler PR1 is stopped for about 10 ms after the inner frame 12 or the front frame 14 is opened. Therefore, when the inner frame 12 or the front frame 14 is opened, a high signal output from the external output terminal board 261 to the hall computer 262 is output for about 10 ms after the inner frame 12 or the front frame 14 is opened. During this time, it can be stopped.

  The door opening detection circuit 260 uses the LMC 555 for the timer IC 1 to detect the opening of the inner frame 12 or the opening of the front frame 14 and realize a circuit that stops energization of the photocoupler PR1 for about 10 ms. However, it is not limited to this. That is, by using another integrated circuit or the like for the timer IC 1, a circuit that generates one pulse signal for one opening of the inner frame 12 or one opening of the front frame 14 is realized. What is necessary is just to stop energization to the photocoupler PR1 for a predetermined period based on the pulse signal.

  Next, the external output terminal board 261 connected to the frame opening detection circuit 260 and connected to the hall computer 262 will be described. The external output terminal plate 261 has a function of outputting a high signal to the hall computer 262, and is mainly composed of a 1 kΩ resistor R7 and a photocoupler PR1.

  The resistor R7 is a resistor that limits the current supplied to the photocoupler PR1, and one end of the resistor R7 is a positive terminal of the storage battery SB1, one end of the switch SW1, one end of the switch SW2, one end of the capacitor CD4, VDD of the timer IC1 The other end of the resistor R7 is connected to the primary side of the photocoupler PR1 (the anode terminal of the light emitting diode). The photocoupler PR1 is a current switch including a light emitting diode and a light receiving element (phototransistor) that receives light emitted from the light emitting diode. As described above, the light emitting diode which is the primary side of the photocoupler PR1 has an anode terminal connected to one end of the resistor R7 and a cathode terminal connected to the collector terminal c of the transistor TR1 of the frame open detection circuit 260. The light receiving element (phototransistor) that is the secondary side of the photocoupler PR1 is connected to the hall computer 262.

  Therefore, when the inner frame 12 and the front frame 14 are closed, and when about 10 ms has elapsed since the inner frame 12 or the front frame 14 was opened, the collector terminal c of the transistor TR1 and the emitter of the transistor TR1. The terminal e is electrically connected to the terminal e, and a current is supplied to the primary light emitting diode of the photocoupler PR1 through the resistor R7. Thereby, the light emitting diode on the primary side of the photocoupler PR1 emits light. Then, the secondary light receiving element (phototransistor) of the photocoupler PR1 receives the emitted light, converts the received light into an electrical signal, and outputs the electrical signal to the hall computer 262 as a high signal.

  On the other hand, when the inner frame 12 or the front frame 14 is in an open state, the collector terminal c of the transistor TR1 and the emitter of the transistor TR1 are approximately 10 ms after the inner frame 12 or the front frame 14 is opened. The connection between the terminal e and the terminal is interrupted. Then, since the current to one end of the resistor R7 is stopped for about 10 ms, the current to the light emitting diode which is the primary side of the photocoupler PR1 is also stopped for about 10 ms. Therefore, the high signal output to the hall computer 262 from the light receiving element (phototransistor) on the secondary side of the photocoupler PR1 is also stopped for about 10 ms. This stoppage of the high signal is stored in the hall computer 262 that continues to operate for 24 hours.

  Here, an advantage of using the photocoupler PR1 for the external output terminal plate 261 connected to the hall computer 262 will be described. The photocoupler PR1 is configured to convert a current supplied to the light emitting diode on the primary side into light, receive the light in a light receiving element (phototransistor) on the secondary side, and output an electrical signal (from the light emitting diode to the light receiving element). To transmit a signal in one direction. Therefore, an electrical signal cannot be transmitted from the light receiving element (phototransistor) on the secondary side to the light emitting diode on the primary side. As a result, even if the open frame detection circuit 260 is connected to the light emitting diode on the primary side of the photocoupler PR1, and the hall computer 262 is connected to the light receiving element (phototransistor) on the secondary side of the photocoupler PR1, the hall computer 262 is connected. Cannot be transmitted to the main controller 110 or the like provided with the frame opening detection circuit 260 or the frame opening detection circuit 260. Therefore, by using the photocoupler PR1, signals from the external output terminal board 261 to the hall computer 262 can be prevented while preventing unauthorized transmission of electrical signals from the hall computer 262 to the frame opening detection circuit 260, the main controller 110, and the like. Can be transmitted.

  Further, in the photocoupler PR1, the primary side light emitting diode and the secondary side light receiving element (phototransistor) are electrically insulated. Therefore, for example, even if an electric noise is included in the current supplied to the light emitting diode of the photocoupler PR1, the electric noise is not transmitted to the secondary side phototransistor. Therefore, by using the photocoupler PR1, the external output terminal board 261 has an advantage that it can output an accurate signal to the hall computer 262.

  As described above, according to the pachinko machine 10 of the present embodiment, when the inner frame 12 or the front frame 14 is opened, about 10 ms from when the inner frame 12 or the front frame 14 is opened. Meanwhile, the conduction between the collector terminal c of the transistor TR1 and the emitter terminal e of the transistor TR1 is cut off. Then, since the current to one end of the resistor R7 is stopped for about 10 ms, the current to the light emitting diode which is the primary side of the photocoupler PR1 is also stopped for about 10 ms. Therefore, the high signal output from the light receiving element (phototransistor) on the secondary side of the photocoupler PR1 to the hall computer 262 is stopped for about 10 ms. This stoppage of the high signal is stored in the hall computer 262 that continues to operate for 24 hours. Therefore, by using the frame opening detection circuit 260 and the external output terminal board 261, the hall computer 262 can memorize that the inner frame 12 has been opened or the front frame 14 has been opened.

  Here, in general, the amusement hall has a security contract with a private security company, and if there is an intruder into the amusement hall, the security company's guards immediately rush to the amusement hall. However, since the cheating is carried out in a short time, in most cases when the guards rush to the intruder, the intruder has already escaped from the playground, and it is impossible to determine which pachinko machine 10 was cheated. There was a problem. The pachinko machine 10 that has been cheated must return to a normal state, but if it is not known which pachinko machine 10 has been cheated, the inner frame 12 and the front frame 14 of all the pachinko machines 10 are Opening them and inspecting them one by one was a heavy hard work to do in a game hall where many pachinko machines 10 were installed.

  However, according to the pachinko machine 10 of the present embodiment, when the opening of the inner frame 12 or the opening of the front frame 14 is detected by the frame opening detection circuit 260, the output is output from the external output terminal plate 261 to the hall computer 262. The high signal is stopped for about 10 ms. The high signal stop state is stored in the hall computer 262. Therefore, the pachinko machine 10 in which the inner frame 12 or the front frame 14 is opened can be identified by the high signal stop state stored in the hall computer 262. Further, the hall computer 262 stores the stop state of the high signal output from the external output terminal board 261 and also stores the time when the high signal is stopped, thereby identifying the inner frame of the identified pachinko machine 10. 12 opening times or the opening time of the front frame 14 can be detected.

  Further, according to the pachinko machine 10 of the present embodiment, when the inner frame 12 and the front frame 14 are closed, and when about 10 ms has elapsed since the inner frame 12 or the front frame 14 was opened, A high signal is output from the light receiving element (phototransistor) on the secondary side of the photocoupler PR1 of the external output terminal plate 261 to the hall computer 262. On the other hand, as described above, when the inner frame 12 or the front frame 14 is in the open state, the high signal output from the phototransistor to the hall computer 262 is in the stop state, but the period in which the high signal is in the stop state. Is about 10 ms.

  Here, the light receiving element (phototransistor) on the secondary side of the photocoupler PR1 of the external output terminal plate 261 is connected to the hall computer 262 using a communication cable (not shown). When the signal is cut (damaged) by, the high signal output from the phototransistor to the hall computer 262 exceeds about 10 ms and is always stopped.

  Therefore, when the high signal output to the hall computer 262 from the light receiving element (phototransistor) that is the secondary side of the photocoupler PR1 of the external output terminal plate 261 is stopped for more than about 10 ms, The disconnection (breakage) of the communication cable connecting the transistor and the hall computer 262 can be detected. Therefore, in addition to being able to detect the opening of the inner frame 12 or the front frame 14 from the high signal stop state period stored in the hall computer 262, the communication cable connecting the phototransistor and the hall computer 262 is disconnected (damaged). Etc. can also be detected.

  In addition, the semiconductor components used for the open frame detection circuit 260 and the external output terminal board 261 may be destroyed by impact, static electricity, or the like. This destruction destroys the semiconductor used for the semiconductor components. Therefore, in general, an open breakdown (a breakdown in which the terminals of the semiconductor components are opened) is more likely to occur than a short breakdown (a breakdown in which the terminals of the semiconductor components are in a short circuit). When the semiconductor component is open broken, no current is supplied to the semiconductor component, so that no normal voltage is output from the semiconductor component. Then, since a normal current is not supplied to the photocoupler PR1, there is no abnormality in the communication cable connecting the light receiving element (phototransistor) on the secondary side of the photocoupler PR1 of the external output terminal plate 261 and the hall computer 262. However, the high signal output from the phototransistor to the hall computer 262 exceeds about 10 ms and is always stopped.

  Therefore, although there is no abnormality in the communication cable that connects the light receiving element (phototransistor) that is the secondary side of the photocoupler PR1 of the external output terminal plate 261 and the hall computer 262, the high output that is output from the phototransistor to the hall computer 262. When the signal is stopped after approximately 10 ms, the breakage of the frame opening detection circuit 260 or the external output terminal board 261 can be detected. Therefore, in addition to being able to detect the opening of the inner frame 12 or the front frame 14 from the high signal stop state period stored in the hall computer 262, the frame opening detection circuit 260 or the external output terminal plate 261 is also destroyed (abnormal). Can be detected.

  Further, according to the pachinko machine 10 of the present embodiment, the frame open detection circuit 260 is provided with the storage battery SB1, so that power is supplied to the pachinko machine 10 and a DC voltage of 12 volts from the DC power supply DC1. In addition to the case where, for example, the business hours of the amusement hall are over, the power supply to the pachinko machine 10 is cut off, and the DC voltage of 12 volts is not supplied from the DC power supply DC1. The frame opening detection circuit 260 can detect the opening of the inner frame 12 and the opening of the front frame 14.

  Next, referring to FIG. 8, the TRG terminal voltage of timer IC1 that changes according to the state of switch SW1 (the state of inner frame 12) and the state of switch SW2 (the state of front frame 14), The relationship between the OUT terminal voltage, the voltage of the output terminal of the EXOR circuit IC2, and the output of the external output terminal plate 261 (input of the hall computer 262) will be described. FIG. 8 shows the state of the switch SW1 (the state of the inner frame 12), the state of the switch SW2 (the state of the front frame 14), the TRG terminal voltage of the timer IC1, the OUT terminal voltage of the timer IC1, and the voltage of the output terminal of the EXOR circuit IC2. 4 is a timing chart showing the relationship between the output of the external output terminal board 261 (the input of the hall computer 262).

  As shown in FIG. 8 (a), when the switch SW1 is in a conducting state (the inner frame 12 is in an open state) from time t1 to time t2, as shown in FIG. 8 (c), the TRG terminal voltage of the timer IC1 is Between t1 and t2, it switches from zero volts (low state) to about 11.3 volts (high state). At this time, as shown in FIG. 8D, the timer IC1 continues to output a voltage of about 10.6 volts from the OUT terminal until about 10 ms elapse from t1. Therefore, as shown in FIG. 8E, the voltage at the output terminal of the EXOR circuit IC2 is about 11.3 volts when the TRG terminal voltage is switched to about 11.3 volts (high state) (at t1). (High state) switches to zero volts (Low state). During this time, the terminal between the collector terminal c of the transistor TR1 and the emitter terminal e (see FIG. 7) of the transistor TR1 of the open frame detection circuit 260 is cut off, and the current to one end of the resistor R7 of the external output terminal plate 261 Supply stops. Accordingly, as shown in FIG. 8F, the high signal output from the external output terminal board 261 to the hall computer 262 is stopped (at time t1).

  Next, after about 10 ms has elapsed since the switch SW1 is in a conductive state (the inner frame 12 is in an open state), that is, after the TRG terminal voltage has been switched from zero volts to about 11.3 volts (from t1), As shown in FIG. 8D, the timer IC1 switches the voltage at the OUT terminal from about 10.6 volts (high state) to zero volts (low state). Then, as shown in FIG. 8 (e), the voltage at the output terminal of the EXOR circuit IC2 switches from zero volts (low state) to about 11.3 volts (high state) again (after about 10 ms has elapsed since t1). . As a result, the terminal between the collector terminal c of the transistor TR1 and the emitter terminal e (see FIG. 7) of the transistor TR1 of the open frame detection circuit 260 is brought into conduction, and current is supplied to one end of the resistor R7 of the external output terminal plate 261. Is done. Therefore, as shown in FIG. 8F, a high signal is output again from the external output terminal board 261 to the hall computer 262 (after about 10 ms has elapsed since t1).

  As described above, for about 10 ms after the switch SW1 becomes conductive (the inner frame 12 is open), that is, after the TRG terminal voltage is switched from zero volts to about 11.3 volts (from t1). When the current supply to one end of the resistor R7 is stopped, the current supply to the light emitting diode (see FIG. 7) on the primary side of the photocoupler PR1 of the external output terminal plate 261 is also stopped for about 10 ms from t1. Is done. As a result, as shown in FIG. 8F, the output of the external output terminal plate 261 switches from the high state to the low state for about 10 ms. That is, the high signal output from the external output terminal board 261 to the hall computer 262 is stopped for about 10 ms from t1. The high signal stop state is stored in the hall computer 262.

  As shown in FIG. 8A, when the switch SW1 is in a cut-off state (the inner frame 12 is closed) at t2, as shown in FIG. 8C, the TRG terminal voltage of the timer IC1 is t2. Is switched from about 11.3 volts to zero volts, so that the OUT terminal voltage of the timer IC1 is switched from zero volts to about 10.6 volts as shown in FIG. 8D (at time t2). As a result, the frame opening detection circuit 260 is set again to a state in which the inner frame 12 and the front frame 14 can be detected (at time t2).

  Next, as shown in FIG. 8 (b), when the switch SW2 is in a conducting state (front frame 14 is in an open state) from time t3 to time t4, as shown in FIG. 8 (c), the TRG terminal of the timer IC1. The voltage switches from zero volts (low state) to about 11.3 volts (high state) between t3 and t4. At this time, as shown in FIG. 8D, the timer IC1 continues to output a voltage of about 10.6 volts from the OUT terminal until about 10 ms elapse from t3. Therefore, as shown in FIG. 8E, the voltage at the output terminal of the EXOR circuit IC2 is about 11.3 volts when the TRG terminal voltage is switched to about 11.3 volts (high state) (at t3). (High state) switches to zero volts (Low state). During this time, the terminal between the collector terminal c of the transistor TR1 and the emitter terminal e (see FIG. 7) of the transistor TR1 of the open frame detection circuit 260 is cut off, and the current to one end of the resistor R7 of the external output terminal plate 261 Supply stops. Accordingly, as shown in FIG. 8F, the high signal output from the external output terminal board 261 to the hall computer 262 is stopped (at time t3).

  Next, after the switch SW1 is in a conductive state (the inner frame 12 is in an open state), that is, after the TRG terminal voltage is switched from zero volts to about 11.3 volts (from t3), about 10 ms elapses. As shown in FIG. 8D, the timer IC1 switches the voltage at the OUT terminal from about 10.6 volts (high state) to zero volts (low state). Then, as shown in FIG. 8 (e), the voltage at the output terminal of the EXOR circuit IC2 switches from zero volts (low state) to about 11.3 volts (high state) again (after about 10 ms has elapsed since t3). . As a result, the terminal between the collector terminal c of the transistor TR1 and the emitter terminal e (see FIG. 7) of the transistor TR1 of the open frame detection circuit 260 is brought into conduction, and current is supplied to one end of the resistor R7 of the external output terminal plate 261. Is done. Therefore, as shown in FIG. 8F, a high signal is output again from the external output terminal board 261 to the hall computer 262 (after about 10 ms has elapsed since t3).

  As described above, for about 10 ms after the switch SW2 is in a conductive state (the front frame 14 is in an open state), that is, after the TRG terminal voltage is switched from zero volts to about 11.3 volts (from t3 time). When the current supply to one end of the resistor R7 is stopped, the current supply to the light emitting diode (see FIG. 7) on the primary side of the photocoupler PR1 of the external output terminal plate 261 is also stopped for about 10 ms. As a result, as shown in FIG. 8F, the output of the external output terminal plate 261 switches from the high state to the low state for about 10 ms from t3. That is, the high signal output from the external output terminal board 261 to the hall computer 262 is stopped for about 10 ms from t3. The high signal stop state is stored in the hall computer 262.

  As shown in FIG. 8B, when the switch SW2 is in a cut-off state (the front frame 14 is in a closed state) at t4, as shown in FIG. 8C, the TRG terminal voltage of the timer IC1 at t4. Is switched from about 11.3 volts to zero volts, so that the OUT terminal voltage of the timer IC1 is switched from zero volts to about 10.6 volts as shown in FIG. 8D (at t4). As a result, the frame opening detection circuit 260 is set again to a state in which the inner frame 12 and the front frame 14 can be detected (at time t4).

  Finally, a case will be described in which the switch SW2 is in a conductive state (the front frame 14 is in an open state) when the switch SW1 is in a conductive state (the inner frame 12 is in an open state). As shown in FIG. 8A, when the switch SW1 is in the conductive state (the inner frame 12 is in the open state) (between t5 and t7), as shown in FIG. 8B, the switch SW2 is in the conductive state. When the front frame 14 is in the open state (between t6 and t8), the TRG terminal voltage of the timer IC1 is changed from zero volts to about 11.3 volts between t5 and t8, as shown in FIG. 8C. Switch. At this time, as shown in FIG. 8D, the timer IC1 continues to output a voltage of about 10.6 volts from the OUT terminal until about 10 ms elapses from t5. Therefore, as shown in FIG. 8E, the voltage at the output terminal of the EXOR circuit IC2 is about 11.3 volts when the TRG terminal voltage is switched to about 11.3 volts (high state) (at t5). (High state) switches to zero volts (Low state). During this time, the terminal between the collector terminal c of the transistor TR1 and the emitter terminal e (see FIG. 7) of the transistor TR1 of the open frame detection circuit 260 is cut off, and the current to one end of the resistor R7 of the external output terminal plate 261 Supply stops. Therefore, as shown in FIG. 8F, the high signal output from the external output terminal board 261 to the hall computer 262 is stopped (at time t5).

  Next, after the switch SW1 is turned on (the inner frame 12 is in an open state), that is, after the TRG terminal voltage is switched from zero volts to about 11.3 volts (from t5), about 10 ms elapses. As shown in FIG. 8D, the timer IC1 switches the voltage at the OUT terminal from about 10.6 volts (high state) to zero volts (low state). Then, as shown in FIG. 8 (e), the voltage at the output terminal of the EXOR circuit IC2 switches from zero volts (low state) to about 11.3 volts (high state) again (after about 10 ms has elapsed since t5). . As a result, the terminal between the collector terminal c of the transistor TR1 and the emitter terminal e (see FIG. 7) of the transistor TR1 of the open frame detection circuit 260 is brought into conduction, and current is supplied to one end of the resistor R7 of the external output terminal plate 261. Is done. Therefore, as shown in FIG. 8F, a high signal is output again from the external output terminal board 261 to the hall computer 262 (after about 10 ms has elapsed since t5).

  As described above, after the switch SW1 is turned on (the inner frame 12 is open), that is, for about 10 ms after the TRG terminal voltage is switched from zero volts to about 11.3 volts (from t5). When the current supply to one end of the resistor R7 is stopped, the current supply to the light emitting diode (see FIG. 7) on the primary side of the photocoupler PR1 of the external output terminal plate 261 is also stopped for about 10 ms. As a result, as shown in FIG. 8 (f), the output of the external output terminal plate 261 switches from the high state to the low state for about 10 ms from t5. That is, the high signal output from the external output terminal board 261 to the hall computer 262 is stopped for about 10 ms from t5. The high signal stop state is stored in the hall computer 262.

  As shown in FIG. 8 (a), at time t7, the switch SW1 is in the cut-off state (the inner frame 12 is closed), and as shown in FIG. 8 (b), at time t8, the switch SW2 is in the cut-off state. When the front frame 14 is closed, the TRG terminal voltage of the timer IC 1 is switched from about 11.3 volts to zero volts at time t8 as shown in FIG. 8C. Thus, the OUT terminal voltage of the timer IC 1 switches from zero volts to about 10.6 volts (at time t8). As a result, the frame opening detection circuit 260 is set again to a state in which the inner frame 12 and the front frame 14 can be detected (at time t8).

  As described above, even when the switch SW1 is in the conductive state (the inner frame 12 is in the open state) and the switch SW2 is in the conductive state (the front frame 14 is in the open state), the timer IC1 is in the conductive period of the switch SW1. Regardless of the length of the inner frame 12 (the length of the opening period of the inner frame 12) and the length of the conduction period of the switch SW2 (the length of the opening period of the front frame 14), either the switch SW1 or the switch SW2 is in the conductive state. When about 10 ms elapses from when either the inner frame 12 or the front frame 14 is open, the voltage at the OUT terminal is switched from about 10.6 volts to zero volts. As a result, the output of the external output terminal plate 261 switches from the high state to the low state for about 10 ms. That is, the high signal output from the external output terminal plate 261 to the hall computer 262 is in a state where either the switch SW1 or the switch SW2 is in a conductive state (either the inner frame 12 or the front frame 14 is open). It will be stopped only for about 10 ms from time.

  As described above, when either the inner frame 12 or the front frame 14 is in an open state (one of the switch SW1 or switch SW2 is conductive), or the inner frame 12 and the front frame 14 are in an open state (switch SW1 and switch SW1). When SW2 becomes conductive, the open frame detection circuit 260 switches the voltage of the TRG terminal from zero volts to about 11.3 volts. Then, regardless of the period of the open state of the inner frame 12 and the front frame 14 (the conductive state of the switch SW1 and the switch SW2), the frame open detection circuit 260 detects that the timer IC 1 The voltage at the OUT terminal is switched from about 10.6 volts to zero volts. By the operation of the frame opening detection circuit 260, the connection between the collector terminal c of the transistor TR1 and the emitter terminal e (see FIG. 7) of the transistor TR1 of the frame opening detection circuit 260 is blocked for about 10 ms. Thus, a high signal output from the external output terminal board 261 to the hall computer 262 is when one of the inner frame 12 or the front frame 14 is in an open state (one of the switch SW1 or the switch SW2 is in a conductive state), or When the inner frame 12 and the front frame 14 are in the open state (the switches SW1 and SW2 are in the conductive state), they are stopped only for about 10 ms.

  The stop state of the high signal is stored in the hall computer 262 that continues to operate for 24 hours. Therefore, the pachinko machine 10 in which the inner frame 12 or the front frame 14 is opened can be identified by the high signal stop state stored in the hall computer 262. Further, the hall computer 262 stores the stop state of the high signal output from the external output terminal board 261 and also stores the time when the high signal is stopped, thereby identifying the inner frame of the identified pachinko machine 10. 12 opening times or the opening time of the front frame 14 can be detected.

  In the present embodiment, when the inner frame 12 or the front frame 14 is opened and the switch SW1 or the switch SW2 is turned on, a high signal output from the external output terminal plate 261 to the hall computer 262 is about 10 ms. However, this is not a limitation. That is, when the connection of each component of the frame open detection circuit 260 is changed, the inner frame 12 or the front frame 14 is opened, and the opened inner frame 12 or the front frame 14 is closed, the photocoupler PR1 is connected. The supplied current may be stopped for about 10 ms, and the high signal output from the external output terminal board 261 to the hall computer 262 may be stopped for about 10 ms.

  However, in the frame open detection circuit 260 of this embodiment, when the inner frame 12 or the front frame 14 is opened and the switch SW1 or the switch SW2 is turned on, the output is output from the external output terminal plate 261 to the hall computer 262. Since the high signal is stopped for about 10 ms, the opening of the inner frame 12 or the front frame 14 can be detected quickly. Therefore, the opening of the inner frame 12 or the front frame 14 can be detected before the inner frame 12 or the front frame 14 is opened and an illegal act is performed on the main controller 110 or the game board 13. Accordingly, it is possible to prevent an abnormal operation due to an illegal act occurring when power is supplied to the pachinko machine 10.

  Further, when the inner frame 12 and the front frame 14 are closed, and when about 10 ms has elapsed since the inner frame 12 or the front frame 14 was opened, the collector terminal c of the transistor TR1 and the emitter of the transistor TR1. The terminal e is electrically connected to the terminal e, and a current is supplied to the primary light emitting diode of the photocoupler PR1 through the resistor R7. As a result, a high signal is continuously output from the external output terminal board 261 to the hall computer 262. Here, when the inner frame 12 and the front frame 14 are closed, and when about 10 ms elapses after the inner frame 12 or the front frame 14 is opened, the frame open detection circuit 260 and the external output terminal plate 261. When it is desired to suppress the power consumed by the resistor R3, the resistor R4, the internal resistor R5, and the internal resistor R6, the resistance values of the resistor R7 and the resistor R7 may be set to be larger than 10 kΩ.

  Further, when it is desired to separately store in the hall computer 262 which of the inner frame 12 and the front frame 14 is opened, the following configuration may be used. First, the frame opening detection circuit 260 and the external output terminal plate 261 used in this embodiment are newly provided one by one, the switch SW2 connected in parallel to the switch SW1 is disconnected, and the disconnected switch SW2 is newly installed. It may be connected to the provided frame opening detection circuit 260. Specifically, one end of the disconnected switch SW2 is connected to the positive terminal of the storage battery SB1 of the newly provided frame opening detection circuit 260, the VDD terminal of the timer IC1, the one end of the capacitor CD4, the RES terminal of the timer IC1, and the external output terminal plate. 261 is connected to one end of the resistor R7, and the other end of the disconnected switch SW2 is connected to one end of the capacitor CD5 of the newly provided frame opening detection circuit 260, one end of the resistor R2, the TRG terminal of the timer IC1, and the EXOR circuit IC2. It may be connected to one of the input terminals and one end of the resistor R1. Thus, the frame opening detection circuit 260 and the external output terminal board 261 are newly provided, and only the switch SW2 is connected to the newly provided frame opening detection circuit 260, and the existing frame opening detection circuit 260 has a switch By connecting only SW1, if the switch SW1 is conductive (the inner frame 12 is opened), the high signal output from the existing external output terminal board 261 to the hall computer 262 is stopped, and the switch SW2 is turned off. When there is continuity (opening of the front frame 14), the high signal output from the newly provided external output terminal board 261 to the hall computer 262 can be stopped. Here, the hall computer 262 includes an input terminal for a high signal output from the existing external output terminal board 261 (for detecting conduction of the switch SW1 (for detecting opening of the inner frame 12)), and a newly provided external output terminal. A high signal input terminal output from the plate 261 (for detecting the conduction of the switch SW2 (for detecting the opening of the front frame 14)) is set separately. With this configuration, the conduction of the switch SW1 (opening of the inner frame 12) and the conduction of the switch SW2 (opening of the front frame 14) can be distinguished and stored in the hall computer 262. Therefore, depending on the stop state of the high signal stored in the hall computer 262, the switch SW1 is conductive (the inner frame 12 is opened), the switch SW2 is conductive (the front frame 14 is opened), or both It is possible to accurately detect whether or not there has been.

  In addition, when power is supplied to the pachinko machine 10, the hall computer 262 separately stores which of the inner frame 12 and the front frame 14 is opened, and between the inner frame 12 and the front frame 14. When it is desired to notify the pachinko machine 10 when one of them is opened, the following configuration may be used. First, the frame opening detection circuit 260 and the external output terminal plate 261 used in this embodiment are newly provided one by one, the switch SW2 connected in parallel to the switch SW1 is disconnected, and the disconnected switch SW2 is newly installed. Connected to the provided frame opening detection circuit 260. Next, the male switches SW1b and SW2b and the female switches SW1a and SW2a are newly provided for the switch SW1 and the switch SW2, respectively. Then, when the inner frame 12 or the front frame 14 is opened using the newly provided male switches SW1b and SW2b and the female switches SW1a and SW2a and the switch SW1 or the switch SW2 is turned on, a signal is sent to the MPU 201. What is necessary is just to comprise so that it may be input.

  Specifically, one end of the disconnected switch SW2 is connected to the positive terminal of the storage battery SB1 of the newly provided frame opening detection circuit 260, the VDD terminal of the timer IC1, the one end of the capacitor CD4, the RES terminal of the timer IC1, and the external output terminal plate. 261 is connected to one end of the resistor R7, and the other end of the disconnected switch SW2 is connected to one end of the capacitor CD5 of the newly provided frame opening detection circuit 260, one end of the resistor R2, the TRG terminal of the timer IC1, and the EXOR circuit IC2. It may be connected to one of the input terminals and one end of the resistor R1. Thus, the frame opening detection circuit 260 and the external output terminal board 261 are newly provided, and only the switch SW2 is connected to the newly provided frame opening detection circuit 260, and the existing frame opening detection circuit 260 has a switch By connecting only SW1, if the switch SW1 is conductive (the inner frame 12 is opened), the high signal output from the existing external output terminal board 261 to the hall computer 262 is stopped, and the switch SW2 is turned off. When there is continuity (opening of the front frame 14), the high signal output from the newly provided external output terminal board 261 to the hall computer 262 can be stopped.

  Next, male switch SW1b and male switch SW2b are further provided for switch SW1 and switch SW2, respectively, and male switch SW1b and male switch SW2b disposed in switch SW1 and switch SW2 are respectively provided in two. To do. Correspondingly, the female switch SW1a and the female switch SW2a are further provided in the switch SW1 and the switch SW2, respectively, and the female switch SW1a and the female switch SW2a provided in the switch SW1 and the switch SW2 are respectively 2 One by one. As a result, one new combination of the male switch SW1b and the female switch SW1a is added to the switch SW1. Similarly to the switch SW1, one combination of the male switch SW2b and the female switch SW2a is added to the switch SW2. Then, one end of a pair of terminal pairs SW1c built in the newly added female switch SW1a is connected to the DC power source DC1 of the existing frame opening detection circuit 260, and built into the newly added female switch SW1a. The other end of the paired terminal pair SW1c is connected to the input / output port 205 of the MPU 201 via a voltage dividing circuit constituted by resistors. Similarly, one end of a pair of terminal pairs SW2c incorporated in the newly added female switch SW2a is connected to the DC power source DC1 of the newly provided frame opening detection circuit 260, and the newly added female type The other end of the pair of terminals SW2c built in the switch SW2a is connected to the input / output port 205 of the MPU 201 via a voltage dividing circuit constituted by a resistor and to a port different from the other end of the terminal pair SW1c. Further, the MPU 201 is supplied from the DC power source DC1 by a voltage of 5 volts (the voltage dividing circuit detects the opening of the inner frame 12 when the inner frame 12 or the front frame 14 is opened and the switch SW1 or the switch SW2 is turned on. 12 volt voltage is reduced to 5 volts) or 5 volt voltage to detect the opening of the inner frame 14 (12 volt voltage supplied from the DC power supply DC1 is lowered to 5 volt by the voltage dividing circuit) ) Is input to the input / output port 205, a command indicating that the opening of the inner frame 12 or the front frame 14 is detected is transmitted to the audio lamp control device 113 and the display control device 114. At this time, the command transmitted from the MPU 201 includes a command when the opening of the inner frame 12 is detected (hereinafter referred to as “inner frame command”) and a command when the front frame 14 is released (hereinafter referred to as “ It is called “front frame command”). Then, the voice lamp control device 113 that has received each command performs notification in a different manner depending on whether the inner frame command is received or the front frame command is received. For example, a different warning sound is emitted from the audio output device 226 or the lighting mode of the lamp display device 227 is changed. In addition, the display control device 114 that has received each command displays different modes depending on whether the inner frame command is received or the front frame command is received. For example, when the display control device 114 receives an inner frame command, the third symbol display device 81 displays “the inner frame is open” or the display control device 114 receives a front frame command. The third symbol display device 81 may be configured to display “front frame is open”.

  In this way, a new combination of the male switch SW1b and the female switch SW1a is added to the switch SW1, and a new combination of the male switch SW2b and the female switch SW2a is added to the switch SW2 as well as the switch SW1. When one switch is used and the switch SW1 is turned on (when the inner frame 12 is opened), the MPU 201 sends an inner frame command to the audio lamp control device 113 and the display control device 114. Configure to send. Further, when the switch SW2 is turned on (when the front frame 14 is opened), the MPU 201 is configured to transmit a front frame command to the audio lamp control device 113 and the display control device 114. By configuring in this way, notification of a different aspect between when the inner frame 12 is opened and when the front frame 14 is opened is performed using the audio lamp control device 113 and the display control device 114. Can do. This makes it possible to accurately determine whether the switch SW1 is conductive (the inner frame 12 is opened), the switch SW2 is conductive (the front frame 14 is opened), or both, using the pachinko machine 10. Can be detected.

  Further, a frame opening detection circuit 260 and an external output terminal plate 261 are newly provided, and only the switch SW2 is connected to the newly provided frame opening detection circuit 260, and the existing frame opening detection circuit 260 has a switch SW1. When the switch SW1 is connected (the inner frame 12 is opened) by connecting only the switch SW2, the high signal output from the existing external output terminal board 261 to the hall computer 262 is stopped, and the switch SW2 is connected. When (the front frame 14 is opened), the high signal output from the newly provided external output terminal board 261 to the hall computer 262 can be stopped. Therefore, depending on the stop state of the high signal stored in the hall computer 262, the switch SW1 is conductive (the inner frame 12 is opened), the switch SW2 is conductive (the front frame 14 is opened), or both It is possible to accurately detect whether or not there has been.

  In the present embodiment, the high signal output from the external output terminal board 261 is output to the hall computer 262 having a different installation location from the pachinko machine 10, but the present invention is not limited to this. A dedicated storage device having the function of the hall computer 262 may be provided for each pachinko machine 10, and the dedicated storage device may be provided on the back side of each pachinko machine 10 provided with the main controller 110 and the like. In this case, more preferably, a dedicated storage device such as the main control device 110, the payout control device 111, and the launch control device 112 is stored in the substrate box, and the box base and the box cover provided in the substrate box are stored. Are connected by a sealing unit (not shown) so that they cannot be opened (connection by caulking structure). Then, a seal seal (not shown) is pasted on the connecting portion between the box base and the box cover over the box cover and the box base.

  Next, the display content of the third symbol display device 81 will be described with reference to FIG. FIG. 9 is a diagram for explaining the display screen of the third symbol display device 81, and FIG. 9A is a diagram schematically showing the area division setting and the effective line setting of the display screen, FIG. 9B is a diagram illustrating an actual display screen.

  The third symbol is composed of ten types of main symbols with numbers from “0” to “9” and one type of sub-shaped petal shape formed smaller than this main symbol. Each main symbol is composed of numbers from “0” to “9” on the rear symbol consisting of a wooden box, of which the main symbols with odd numbers (1, 3, 5, 7, 9) are A large number is added to almost the front of the wooden box. On the other hand, the main symbols with even numbers (0, 2, 4, 6, 8) are attached to the front of the wooden box almost fully, and attached symbols imitating characters such as furoshiki and helmets are added. An even number is small in green on the lower right side of the attached symbol and is added so as to be displayed on the front side of the attached symbol.

  Further, in the pachinko machine 10 according to the present embodiment, when the lottery result by the main controller 110 is a big win, a variable display in which the same main symbols are arranged is performed, and a big hit occurs after the variable display is finished. It is configured to When shifting to the high probability state (probability variation state) after the big hit, the variable display in which the main symbols (corresponding to “high probability symbols”) to which odd numbers are added is arranged. On the other hand, when shifting to the low probability state after the big hit, the variable display is performed in which the main symbols to which the even numbers are added (corresponding to “low probability symbols”) are arranged. Here, the high probability state refers to a state in which the subsequent jackpot probability is increased as an added value after the jackpot ends, that is, a so-called probability fluctuation (probability change). Further, the normal state (low probability state) refers to a time when the probability of hitting is not probable, and refers to a state where the probability of jackpot is normal, that is, a state where the probability of jackpot is lower than that during probability change.

  As shown in FIG. 9 (a), the display screen of the third symbol display device 81 is roughly divided into two vertically, and the lower 2/3 is the main display area Dm in which the third symbol is variably displayed, and the others. The upper third is a sub display area Ds for displaying a notice effect and a character.

  In the main display area Dm, three symbol rows Z1, Z2, and Z3 of left, middle, and right are displayed. In each symbol row Z1 to Z3, the above-described third symbols are displayed in a prescribed order. That is, in each symbol row Z1 to Z3, main symbols are arranged in ascending or descending numerical order, and one sub symbol is arranged between each main symbol. For this reason, a total of 20 third symbols of 10 main symbols and 10 sub-designs are set in each symbol row, and each symbol row Z1 to Z3 scrolls from top to bottom with periodicity. The display is changed. In particular, the left symbol row Z1 is arranged so that the numbers of the main symbols appear in descending order, and the middle symbol row Z2 and the right symbol row Z3 are arranged so that the numbers of the main symbols appear in ascending order.

  In the main display area Dm, the third symbols are displayed in the upper, middle, and lower three rows for each symbol row Z1 to Z3. Accordingly, the third symbol display device 81 displays a total of nine third symbols of 3 rows × 3 columns. In the main display area Dm, five effective lines, that is, an upper line L1, a middle line L2, a lower line L3, a right rising line L4, and a left rising line L5 are set. In each game, the variable display stops in the order of the left symbol row Z1 → the right symbol row Z3 → the middle symbol row Z2, and the combination of jackpot symbols on any active line at the time of the stop (in this embodiment, A jackpot moving image is displayed as a jackpot if the same combination of main symbols is arranged.

  The sub display area Ds is horizontally long above the main display area Dm, and is further equally divided into three notice areas Ds1 to Ds3 in the left-right direction. Here, the left and right notice areas Ds1, Ds3 are usually covered with double-open opaque doors that are electrically opened and closed by solenoids (not shown), and sometimes the solenoids are excited and the doors are on the front side. It is a display area that is visible to the player when it is opened. The center notice area Ds2 is a display area that is always visible without being covered by the door.

  As shown in FIG. 9B, on the actual display screen, a total of nine main symbols and sub-designs of the third symbol are displayed in the main display area Dm. In the sub display area Ds, the left and right doors are closed, and the left and right notice areas Ds1, Ds3 are covered and the display screen cannot be visually recognized. If either one of the left and right doors or both doors are opened during the variable display, a video is displayed in the left and right notice areas Ds1 and Ds3, and it is easy for the player to change to a big hit than usual. It is suggested. In the notice area Ds2 in the center, a predetermined character (a boy with a bee in this embodiment) usually performs a predetermined action, sometimes performs a special action different from the predetermined action, or another character A notice effect is performed by appearing. The display screen of the third symbol display device 81 is divided into upper and lower display areas Dm and Ds in principle, but the third symbol and characters are displayed larger across the display areas Dm and Ds. A display effect can be performed.

  Next, a counter and the like provided in the RAM 203 of the main controller 110 will be described with reference to FIG. These counters and the like are used by the MPU 201 of the main control device 110 to perform jackpot lottery, display setting of the first symbol display device 37, lottery of display results of the second symbol display device 82, and the like.

  For the jackpot lottery or display setting of the first symbol display device 37, the first hit random number counter C1 used for the jackpot lottery, the first hit type symbol counter C2 used for the jackpot symbol selection, and the stop pattern selection counter C3, a first initial value random number counter CINI1 used for setting the initial value of the first random number counter C1, and variation type counters CS1, CS2, and CS3 used for variation pattern selection are used. The second symbol random number counter C4 is used for the lottery of the second symbol display device 82, and the second initial random number counter CINI2 is used for setting the initial value of the second random number counter C4. Each of these counters is a loop counter that adds 1 to the previous value every time it is updated and returns to 0 after reaching the maximum value.

  Each counter is updated at an interval of 4 ms, which is an execution interval of the main process (see FIG. 12), or at an interval of 2 ms, an execution interval of the timer interrupt process (see FIG. 15), and the updated value is set in a predetermined area of the RAM 203. Stored in the counter buffer. The RAM 203 is provided with a holding ball storage area composed of one execution area and four holding areas (holding first to fourth areas). The values of the first per-random number counter C1, the first per-type counter C2, and the stop pattern selection counter C3 are stored in accordance with the ball winning timing.

  Each counter will be described in detail. The first random number counter C1 is configured so that, for example, 1 is added in order within a range of 0 to 738, and after reaching the maximum value (that is, 738), it returns to 0. In particular, when the first random number counter C1 makes one round, the value of the first initial value random number counter CINI1 at that time is read as the initial value of the first random number counter C1. The first initial value random number counter CINI1 is configured as a loop counter that is updated in the same range as the first per-random number counter C1 (value = 0 to 738), and each time the timer interrupt process (see FIG. 15) is executed. It is updated once and updated repeatedly within the remaining time of the main process (see FIG. 12). The value of the first per-random number counter C1 is updated, for example, periodically (in this embodiment, once for each timer interrupt process), and the stored ball is stored in the RAM 203 at the timing when the ball wins the first entrance 64. Stored in the area. The number of random number values that are jackpots is set at low probability and high probability, and the number of random numbers that are jackpots at low probability is 2, and the value is “373, 727” There are 14 random numbers that are big hits at high probability, and the values are "59, 109, 163, 211, 263, 317, 367, 421, 479, 523, 631, 683, 733".

  The first hit type counter C2 determines the display mode of the first symbol display device 37 at the time of the big hit. In the present embodiment, the first hit type counter C2 is incremented one by one within the range of 0 to 4, and the maximum value ( That is, it is configured to return to 0 after reaching 4). The value of the first hit type counter C2 is updated, for example, periodically (once every timer interruption process in this embodiment), and the stored ball is stored in the RAM 203 at the timing when the ball wins the first entrance 64. Stored in the area. In addition, the value of the random number that becomes the high probability state after the big hit is “1, 2, 3”, the value of the random number that becomes the low probability state after the big hit is “0, 4”, and two types of hit types are determined. The Therefore, the display mode corresponding to the stop symbol displayed on the first symbol display device 37 is a display mode corresponding to two types of jackpots of a high probability state and a low probability state, and one type of display mode corresponding to a deviation. Any one of the three display modes is selected.

  The stop pattern selection counter C3 is, for example, incremented by 1 in the range of 0 to 238, and returns to 0 after reaching the maximum value (that is, 238). In the present embodiment, the stop pattern selection counter C3 selects the effect pattern displayed on the third symbol display device 81, and after reaching, the final stop symbol is shifted by one before and after the reach symbol. “Stop before and after detachment reach” (for example, a range of 0 to 8), and “Leach other than detachment before and after detachment” (for example, a range of 9 to 38) after the reach has occurred and the final stop symbol stops other than before and after the reach design. The three stop (effect) patterns are selected as “completely out” (for example, a range of 39 to 238) that does not cause reach. The value of the stop pattern selection counter C3 is updated, for example, periodically (once every timer interrupt process in this embodiment), and the reserved ball storage area of the RAM 203 at the timing when the ball wins the first entrance 64. Stored in

  Further, the stop pattern selection counter C3 is provided with a plurality of tables having different ranges of random number values from which the stop pattern is selected. This depends on whether the current state of the pachinko machine 10 is a high probability state or a low probability state, in which area of the reserved ball storage area each random number value is stored (ie, the number of reserved balls), etc. This is to change the stop pattern selection ratio.

  For example, in a high probability state, a table with a wide random value range of 10 to 238 corresponding to the stop pattern of “completely out” is selected so that a jackpot is likely to occur and a reach effect is not selected more than necessary. It becomes easy to select “completely off”. In this table, “front / rear out of reach” is narrowed to 0-5, and “reach other than front / rear out of reach” is also narrowed to 6-9, making it difficult to select “rear out of front / rear out of reach” or “reach out of front / rear out of reach”. Further, if each random number value is not stored in the holding ball storage area in a low probability state, a disturbance corresponding to the stop pattern of “completely off” in order to secure the time for the ball to enter the first entrance 64. A table with a narrow numerical value range of 51 to 238 is selected, and “completely out” is difficult to select. In this table, the range of random numbers corresponding to the stop pattern of “reach other than front / rear deviation” is as wide as 9 to 50, and “reach other than front / rear deviation” is easily selected. Therefore, in the low probability state, the ball entry time to the first entrance 64 can be secured, and therefore, the variable display by the third symbol display device 81 is easily performed continuously.

  Of the two variation type counters CS1 and CS2, one variation type counter CS1 is incremented one by one within a range of 0 to 198, for example, and reaches a maximum value (that is, 198) and then returns to 0. On the other hand, the other variation type counter CS2 is, for example, incremented one by one within a range of 0 to 240, and returns to 0 after reaching the maximum value (that is, 240). In the following description, CS1 is also referred to as “first variation type counter”, and CS2 is also referred to as “second variation type counter”.

  Rough display modes such as so-called normal reach, super reach, and premium reach are determined by the first variation type counter CS1. Specifically, the display mode is determined by determining the variation time of the symbol variation. Further, the second variation type counter CS2 determines a variation time (in other words, the number of variation symbols) until the final stop symbol (in the present embodiment, the middle symbol) stops after the occurrence of reach. Based on the variation time determined by the variation type counters CS1 and CS2, the display control device 114 determines the reach type of the third symbol displayed on the third display device 81 and the detailed symbol variation mode. Therefore, a variety of variation patterns can be easily realized by combining these variation type counters CS1 and CS2. It is also possible to determine the symbol variation mode only by the first variation type counter CS1, or to determine the symbol variation mode similarly by combining the first variation type counter CS1 and the stop symbol. The values of the variation type counters CS1 and CS2 are updated once every time a main process (see FIG. 12) described later is executed once, and are repeatedly updated within the remaining time in the main process.

  For example, the value of the variation type counter CS3 is sequentially incremented by 1 within a range of 0 to 162, and returns to 0 after reaching the maximum value (that is, 162). In the following description, CS3 is also referred to as a “third variation type counter”. The 3rd symbol display device 81 of this Embodiment performs the decorative production according to the display mode of the 1st symbol display device 37, and can slide the symbol which is changing in addition to the variation of a symbol. A notice effect such as passing a notice character for notifying the occurrence of the reach effect is performed. The effect pattern of the notice effect is selected by the variation type counter CS3. Specifically, the time required for the notice effect is added to the variable time, or on the contrary, the variable time is subtracted to shorten the variable display time, or an effect pattern that does not add or subtract the variable time is selected. . As with the stop pattern selection counter C3, the variation type counter CS3 is provided with a plurality of tables with different ranges of random values from which the production pattern is selected, and whether the current state of the pachinko machine 10 is in a high probability state. Depending on the low probability state or in which area of the reserved ball storage area each random value is stored, the selection ratio of each effect pattern is different.

  As described above, the variation time of the symbol variation is determined by the variation type counters CS1 and CS2, and the time to be added to or subtracted from the variation time is determined by the variation type counter CS3. Therefore, the final fluctuation time until the final stop symbol stops is determined by the fluctuation type counters CS1, CS2, CS3.

  The second random number counter C4 is configured as a loop counter that is incremented one by one within a range of 0 to 250, for example, and returns to 0 after reaching the maximum value (that is, 250). In this embodiment, the value of the second random number counter C4 is updated periodically, for example, every timer interrupt process, and the ball has passed through the second entrance (through gate) 67 on either the left or right side. Obtained when detected. The number of random number values to be won is 149, and the range is “5 to 153”. The second initial value random number counter CINI2 is configured as a loop counter that is updated in the same range as the second per-random number counter C4 (value = 0 to 250), and is once per timer interrupt process (see FIG. 15). In addition to being updated, it is repeatedly updated within the remaining time of the main process (see FIG. 12).

  Next, each control process executed by the MPU 201 in the main controller 110 will be described with reference to the flowcharts of FIGS. 11 to 17. The processing of the MPU 201 is roughly divided into a startup process that is started when the power is turned on, a main process that is executed after the startup process, and a timer that is started periodically (in this embodiment, at a cycle of 2 ms). There are an interrupt process and an NMI interrupt process activated by the input of the power failure signal SG1 to the NMI terminal. For convenience of explanation, the timer interrupt process and the NMI interrupt process are described first, and then the startup process The main process will be described.

  FIG. 15 is a flowchart showing the timer interrupt process. The timer interrupt process is executed by the MPU 201 of the main control device 110, for example, every 2 ms. In the timer interrupt process, first, a process for reading various winning switches is executed (S501). That is, the state of various switches connected to the main controller 110 is read, and the state of the switch is determined and the detection information (winning detection information) is stored.

  Next, the first initial value random number counter CINI1 and the second initial value random number counter CINI2 are updated (S502). Specifically, the first initial value random number counter CINI1 is incremented by 1 and cleared to 0 when the counter value reaches the maximum value (738 in the present embodiment). Then, the updated value of the first initial value random number counter CINI 1 is stored in the corresponding buffer area of the RAM 203. Similarly, 1 is added to the second initial value random number counter CINI2, and when the counter value reaches the maximum value (250 in the present embodiment), it is cleared to 0, and the second initial value random number counter CINI2 is updated. The value is stored in the corresponding buffer area of the RAM 203.

  Further, the first per-random number counter C1, the first per-type counter C2, the stop pattern selection counter C3, and the second per-random number counter C4 are updated (S503). Specifically, 1 is added to each of the first per-random number counter C1, the first per-type counter C2, the stop pattern selection counter C3, and the second per-random number counter C4, and these counter values are the maximum values (this embodiment) Then, when they reach 738, 4, 238, 250), they are cleared to 0. Then, the updated values of the counters C1 to C4 are stored in the corresponding buffer area of the RAM 203.

  Thereafter, a start winning process (see FIG. 16) associated with winning in the first entrance 64 is executed (S504), a firing control process is executed (S505), and the timer interrupt process is terminated. Note that the launch control process detects that the player is touching the operation handle 51 with the touch sensor 51a and turns on the ball launch on the condition that the stop switch 51b for stopping the launch is not operated. This is a process for determining / off. The main controller 110 instructs the launch controller 112 to launch a sphere when the launch of the sphere is on.

  Here, the start winning process executed in the process of S504 will be described with reference to the flowchart of FIG. FIG. 16 is a flowchart showing the start winning process (S504) executed in the timer interrupt process (see FIG. 15).

  When this start winning process is executed, first, it is determined whether or not the ball has won a first winning opening 64 (start winning) (S601). If it is determined that the ball has won the first entrance 64 (S601: Yes), whether or not the number N of the operation reserved balls of the first symbol display device 37 is less than the upper limit (4 in the present embodiment). Is determined (S602). If there is a winning at the first entrance 64 and the number of operation-reserved balls N <4 (S602: Yes), the number N of operation-reserved balls is incremented by 1 (S603), and further updated in step S503. The values of the first per-random number counter C1, the first per-type counter C2, and the stop pattern selection counter C3 are stored in the first area among the free reserved areas in the reserved ball storage area of the RAM 203 (S604). On the other hand, if there is no winning at the first entrance 64 (S601: No), or even if there is a winning at the first entrance 64, if the number N of operational reserves is not N <4 (S602: No). , S603 and S604 are skipped, the start winning process is terminated, and the process returns to the timer interrupt process.

  FIG. 17 is a flowchart showing NMI interrupt processing. The NMI interruption process is a process executed by the MPU 201 of the main controller 110 when the power of the pachinko machine 10 is shut down due to the occurrence of a power failure or the like. By this NMI interrupt processing, the information on the occurrence of power interruption is stored in the RAM 203. That is, when the power of the pachinko machine 10 is cut off due to the occurrence of a power failure or the like, the power failure signal SG1 is output from the power failure monitoring circuit 252 to the NMI terminal of the MPU 201 in the main controller 110. Then, the MPU 201 interrupts the control being executed and starts the NMI interrupt process, stores the power-off occurrence information in the RAM 203 as a setting of the power-off occurrence information (S701), and ends the NMI interrupt process. To do.

  The above NMI interrupt process is executed in the same manner in the payout and emission control device 111, and information on the occurrence of power interruption is stored in the RAM 213 by the NMI interrupt process. That is, when the power of the pachinko machine 10 is cut off due to the occurrence of a power failure or the like, the power failure signal SG1 is output from the power failure monitoring circuit 252 to the NMI terminal of the MPU 211 in the payout and emission control device 111, and the MPU 211 interrupts the control being executed. Then, the NMI interrupt process is started.

  Next, referring to FIG. 11, a startup process when the main controller 110 is turned on will be described. FIG. 11 is a flowchart showing start-up processing executed by the MPU 201 in the main controller 110. This start-up process is activated by a reset at power-on. In the start-up process, first, an initial setting process associated with power-on is executed (S101). Specifically, a predetermined value set in advance in the stack pointer is set, and the sub-side control devices (peripheral control devices such as the audio lamp control device 113 and the payout control device 111) become operable. In order to wait, a wait process (1 second in this embodiment) is executed. Next, access to the RAM 203 is permitted (S103).

  Thereafter, it is determined whether or not the RAM erase switch 122 (see FIG. 3) provided in the power supply device 115 is turned on (S104). If it is turned on (S104: Yes), the process proceeds to S110. On the other hand, if the RAM erasure switch 122 is not turned on (S104: No), it is further determined whether or not the information on occurrence of power interruption is stored in the RAM 203 (S105), and if not stored (S105: No). Since there is a possibility that the process at the time of the previous power shutdown has not been completed normally, the process proceeds to S110 also in this case.

  If power failure occurrence information is stored in the RAM 203 (S105: Yes), a RAM determination value is calculated (S106). If the calculated RAM determination value is not normal (S107: No), that is, the calculated RAM If the determination value does not match the RAM determination value stored at the time of power-off, the backed up data has been destroyed. In such a case as well, the process proceeds to S110. Note that, as will be described later in the processing of S213 in FIG. Instead of the RAM determination value, the validity of the backup may be determined based on whether or not the keyword written in a predetermined area of the RAM 203 is correctly stored.

  In the process of S111, a payout initialization command is transmitted in order to initialize the payout control device 111 as a sub-side control device (peripheral control device) (S111). Upon receiving this payout initialization command, the payout control device 111 clears an area (work area) other than the stack area of the RAM 213, sets an initial value, and enters a state in which game ball payout control can be started. After transmitting the payout initialization command, main controller 110 executes initialization processing (S112, S113) of RAM 203.

  As described above, in the pachinko machine 10, when RAM data is initialized when the power is turned on, for example, when the hall starts business, the power is turned on while the RAM erase switch 122 is pressed. Therefore, if the RAM erase switch 122 is pressed during the start-up process, the RAM initialization process (S112, S113) is executed. Similarly, initialization processing (S112, S113) of the RAM 203 is executed even when the information on occurrence of power interruption is not set or when a backup abnormality is confirmed by the RAM determination value (checksum value or the like). . In the RAM initialization process (S112, S113), the used area of the RAM 203 is cleared to 0 (S112), and then the initial value of the RAM 203 is set (S113). After executing the initialization process of the RAM 203, the process proceeds to S110.

  On the other hand, if the RAM erase switch 122 is not turned on (S104: No), the information on occurrence of power interruption is stored (S105: Yes), and the RAM judgment value (checksum value etc.) is normal ( S107: Yes), the information on the occurrence of power interruption is cleared while the backed up data is held in the RAM 203 (S108). Next, a payout return command at the time of power recovery for returning the sub-side control device (peripheral control device) to the gaming state at the time of driving power interruption is transmitted (S109), and the process proceeds to S110. When the payout control device 111 receives this payout return command, the payout control device 111 is in a state where the payout control of the game ball can be started while holding the data stored in the RAM 213. In the process of S110, the interruption is permitted and the process proceeds to a main process described later.

  Next, with reference to FIG. 12, the main process executed after the above-described startup process will be described. FIG. 12 is a flowchart showing main processing executed by the MPU 201 in the main controller 110. In this main process, the main process of the game is executed. As an outline, each process of S201 to S206 is executed as a periodic process with a period of 4 ms, and the counter update process of S209 and S210 is executed in the remaining time.

  In the main process, first, output data such as a command updated in the previous process is transmitted to each control device (peripheral control device) on the sub-side (S201). Specifically, the presence / absence of winning detection information detected in the switch reading process of S501 is determined, and if there is winning detection information, a winning ball command corresponding to the number of acquired balls is transmitted to the payout control device 111. In addition, by this external output process, a variation pattern command, a stop symbol command, a stop command, an effect time addition command, etc. necessary for the third symbol variation display by the third symbol display device 81 are transmitted to the sound lamp control device 113. Further, when launching a sphere, a sphere launch signal is transmitted to the launch controller 112.

  Next, each value of the variation type counters CS1, CS2, CS3 is updated (S202). Specifically, 1 is added to the variation type counters CS1, CS2, and CS3, and when the counter values reach the maximum values (198, 240, and 162 in this embodiment), they are cleared to 0, respectively. Then, the update values of the variation type counters CS 1, CS 2, and CS 3 are stored in the corresponding buffer area of the RAM 203.

  When the update of the variation type counters CS1, CS2 and CS3 is completed, the winning ball counting signal and the payout abnormality signal received from the payout control device 111 are read (S203), and the process for displaying on the first symbol display device 37 is performed. A variation process for setting a variation pattern of the third symbol and the like by the three symbol display device 81 is executed (S204). Details of the variation process will be described later with reference to FIG.

  After the end of the variation process, a large opening opening / closing process for opening or closing the specific winning opening (large opening) 65a of the variable winning device 65 is executed in the case of the big win state (S205). That is, the specific winning opening 65a is opened for each round of the big hit state, and it is determined whether the maximum opening time of the specific winning opening 65a has elapsed or whether a specified number of balls have won the specific winning opening 65a. When any of these conditions is met, the specific winning opening 65a is closed. The opening and closing of the specific winning opening 65a is repeated for a predetermined number of rounds.

  Next, a display control process of the second symbol (for example, the symbol “◯” or “x”) by the second symbol display device 82 is executed (S206). Briefly, on the condition that the ball has passed through the second entrance (through gate) 67, the value of the second random number counter C4 is acquired at the timing of the passage, and the second symbol display device 82 is obtained. In the display unit 83, the second symbol variation display is performed. Then, the lottery of the second symbol is performed according to the value of the second winning random number counter C4, and when the winning state of the second symbol is reached, the electric accessory attached to the first entrance 64 is released for a predetermined time.

  Thereafter, it is determined whether or not the power failure occurrence information is stored in the RAM 203 (S207). If the power failure occurrence information is not stored in the RAM 203 (S207: No), a power failure signal is output from the power failure monitoring circuit 252. SG1 is not output and the power supply is not shut off. Therefore, in such a case, it is determined whether or not the execution timing of the next main process has been reached, that is, whether or not a predetermined time (4 ms in the present embodiment) has elapsed since the start of the previous main process (S208). If the predetermined time has already elapsed (S208: Yes), the process proceeds to S201, and the processes after S201 described above are repeatedly executed.

  On the other hand, if the predetermined time has not yet elapsed since the start of the previous main process (S208: No), the first time is reached until the predetermined time, that is, within the remaining time until the next main process execution timing. The updating of the initial value random number counter CINI1, the second initial value random number counter CINI2, and the variation type counters CS1, CS2, and CS3 is repeatedly executed (S209, S210).

  First, the first initial value random number counter CINI1 and the second initial value random number counter CINI2 are updated (S209). Specifically, 1 is added to the first initial value random number counter CINI1 and the second initial value random number counter CINI2, and when the counter value reaches the maximum value (738, 250 in this embodiment), it is cleared to 0. To do. Then, the updated values of the first initial value random number counter CINI1 and the second initial value random number counter CINI2 are stored in the corresponding buffer areas of the RAM 203, respectively.

  Next, the fluctuation type counters CS1, CS2, and CS3 are updated (S210). Specifically, 1 is added to the variation type counters CS1, CS2, and CS3, and when the counter values reach the maximum values (198, 240, and 162 in this embodiment), they are cleared to 0, respectively. Then, the update values of the variation type counters CS1, CS2, and CS3 are stored in the corresponding buffer areas of the RAM 203, respectively.

  Here, since the execution time of each process of S201-S206 changes according to the state of the game, the remaining time until the next main process execution timing is not constant and varies. Therefore, by repeatedly performing the update of the first initial value random number counter CINI1 and the second initial value random number counter CINI2 using the remaining time, the first initial value random number counter CINI1 and the second initial value random number counter CINI2 (that is, , The initial value of the first per-random number counter C1 and the initial value of the second per-random number counter C4) can be updated at random. Similarly, the variation type counters CS1, CS2, and CS3 can be updated at random.

  In the process of S207, if the power failure occurrence information is stored in the RAM 203 (S207: Yes), the power failure is caused by the occurrence of a power failure or the power is turned off, and the power failure monitoring circuit 252 outputs the power failure signal SG1. As a result, since the NMI interrupt process of FIG. 17 has been executed, the power-off process after S211 is executed. First, the generation of each interrupt process is prohibited (S211), and a power-off notification command indicating that the power has been cut off is sent to other control devices (peripheral control devices such as the payout control device 111 and the sound lamp control device 113). It transmits to (S212). Then, the RAM determination value is calculated and stored (S213), access to the RAM 203 is prohibited (S214), and the infinite loop is continued until the power supply is completely shut down and the process cannot be executed. Here, the RAM determination value is, for example, a checksum value in the stack area and work area to be backed up in the RAM 203.

  Note that the processing of S207 is performed at the timing when the series of processing corresponding to the game state change performed in S201 to S206 is completed, or at the end of one cycle of the processing of S209 and S210 performed within the remaining time. It is running. Therefore, in the main process of the main controller 110, the occurrence information of the power supply interruption is confirmed at the timing when each setting is completed. Therefore, when returning from the power interruption state, the process is performed after the start-up process is completed. It can start from the process of S201. That is, the process can be started from the process of S201 as in the case where the process is initialized in the startup process. Therefore, in the process at power-off, the stack pointer is not stored in the initial setting process (S101) without saving the contents of each register used by the MPU 201 to the stack area or saving the value of the stack pointer. By setting to a predetermined value (initial value), it is possible to start from the process of S201. Therefore, it is possible to reduce the control burden on the main control device 110 and to perform accurate control without causing the main control device 110 to malfunction or run away.

  Next, the fluctuation process (S204) will be described with reference to FIG. FIG. 13 is a flowchart showing the variation process (S204) executed in the main process (see FIG. 12). In this variation process, first, it is determined whether or not a big hit is currently being made (S301). The jackpot includes the jackpot game displayed on the third symbol display device 81 and the first symbol display device 37 in the jackpot and the middle of a predetermined time after the jackpot game ends. As a result of the determination, if it is a big hit (S301: Yes), this processing is terminated as it is.

  If it is not a big hit (S301: No), it is determined whether or not the display mode of the first symbol display device 37 is changing (S302), and if the display mode of the first symbol display device 37 is not changing. (S302: No), it is determined whether or not the number N of active suspension balls is greater than 0 (S303). If the number N of active balls is 0 (S303: No), this process is terminated. If the number of the operation hold balls N> 0 (S303: Yes), the operation hold ball number N is decremented by 1 (S304), and the data stored in the hold ball storage area is shifted (S305). This data shift process is a process of sequentially shifting the data stored in the reserved first to fourth areas of the reserved ball storage area to the execution area side, and the reserved first area → execution area, reserved second area → The data in each area is shifted such as the first hold area, the third hold area → the second hold area, the fourth hold area → the third hold area. After the data shift process, the fluctuation start process of the first symbol display device 37 is executed (S306). The variation start process will be described later with reference to FIG.

  In the process of S302, if it is determined that the display mode of the first symbol display device 37 is changing (S302: Yes), it is determined whether or not the change time has elapsed (S307). The display time during the change of the first symbol display device 37 is determined according to the change pattern selected by the change type counters CS1 and CS2 and the addition time selected by the change type counter CS3. If it has not elapsed (S307: No), the display of the first symbol display device 37 is updated (S308).

  In the present embodiment, among the LEDs 37a of the first symbol display device 37, for example, if the currently lit LED is red until the variation time elapses after the variation starts, the red LED is Turn off and turn on the green LED. If the green LED is on, turn off the green LED and turn on the blue LED. If the blue LED is on, turn on the blue LED. A display mode for turning off the red LED and turning on the red LED is set.

  Note that the variation process is executed every 4 ms, but if the LED lighting color is changed every time the variation process is executed, the player cannot confirm the change in the LED lighting color. Therefore, a counter (not shown) is counted once each time the variation process is executed so that the player can confirm the change in the lighting color of the LED. Change the lighting color of. That is, the lighting color of the LED is changed every 0.4 s. The counter value is reset to 0 when the lighting color of the LED is changed.

  On the other hand, if the variation time of the first symbol display device 37 has elapsed (S307: Yes), a display mode corresponding to the stop symbol of the first symbol display device 37 is set (S309). In the setting of the stop symbol, whether or not a big hit is determined according to the value of the first per-random number counter C1, and in the case of a big hit, a symbol that becomes a high probability state after the big hit by the value of the first per-type type counter C2 Or a symbol that is in a low probability state is determined. In this embodiment, a red LED is turned on when a high probability state is reached after a big hit, a green LED is turned on when a low probability state is reached, and a blue LED is turned on when it is out of place. . In addition, although the lighting of each LED is released when the next fluctuation display is started, it may be turned on only for a few seconds after the fluctuation stops.

  When the display mode of the first symbol display device 37 corresponding to the stop symbol is set in the processing of S309, the variation stop of the third symbol display device 81 is stopped to synchronize with the lighting of the LED in the first symbol display device 37. A command is set (S310). When the sound lamp control device 113 receives this stop command, it instructs the display control device 114 to stop. When the variation time elapses, the third symbol display device 81 stops the variation, and receives the stop command, whereby one variation effect in the third symbol display device 81 ends.

  Next, the variation start process will be described with reference to FIG. FIG. 14 is a flowchart showing the change start process (S306) executed in the change process (see FIG. 13). In the variation start process (S306), first, it is determined whether or not a big hit is made based on the value of the first hit random number counter C1 stored in the execution area of the reserved ball storage area (S401). Whether or not it is a big hit is determined based on the relationship between the value of the first random number counter C1 and the mode at that time. As described above, “373,727” is a winning value among the numerical values 0 to 738 of the first random number counter C1 at the normal low probability, and “59, 109, 163, 211, 263, 317, 367, "421,479,523,631,683,733" is the winning value.

  When it is determined that it is a big hit (S401: Yes), the value of the first hit type counter C2 stored in the execution area of the reserved ball storage area is confirmed, and the display mode for the big hit is set (S402). ). In the process of S402, based on the value of the first hit type counter C2, whether to shift to the high probability state or shift to the low probability state after the big hit is set. When the transition state after the big hit is set, the display mode of the first symbol display device 37 (the lighting state of the LED 37a) is set. Further, based on the transition state after the jackpot, the jackpot stop symbol stopped and displayed on the third symbol display device 81 is set by the sound lamp control device 113 and the display control device 114. That is, the stop symbol in the third symbol display device 81 is set by setting the transition state after the big hit by the process of S402. Of the numerical values 0 to 4 of the first hit type counter C2, when “0, 4”, the state shifts to the low probability state, and when “1, 2, 3”, the state shifts to the high probability state. .

  Next, a variation pattern at the time of jackpot is determined (S403). When the variation pattern is set in the process of S403, the display time of the first symbol display device 37 is set and the variation time of the third symbol until the third symbol display device 81 stops at the jackpot symbol is determined. The At this time, the values of the fluctuation type counters CS1 and CS2 stored in the counter buffer of the RAM 203 are confirmed, and rough symbol fluctuations such as normal reach, super reach, and premium reach are determined based on the value of the first fluctuation type counter CS1. In addition to determining the variation time, the variation time (in other words, the number of variation symbols) until the final stop symbol (in the present embodiment, the middle symbol Z2) stops after the occurrence of reach is determined based on the value of the second variation type counter CS2. decide.

  The relationship between the numerical value of the first variation type counter CS1 and the variation time, and the relationship between the numerical value of the second variation type counter CS2 and the variation time are respectively defined in advance by a table or the like. However, the fluctuation time can be set using only the value of the first fluctuation type counter CS1 without using the value of the second fluctuation type counter CS2, and can be set only with the value of the first fluctuation type counter CS1. Whether or not to set with both values of both variation type counters CS1 and CS2 is appropriately determined according to the value of the first variation type counter CS1 and the game conditions each time.

  If it is determined in the process of S401 that it is not a big hit (S401: No), the display mode at the time of disconnection is set (S404). In the process of S404, the display mode of the first symbol display device 37 is set to the display mode corresponding to the off symbol, and based on the value of the stop pattern selection counter C3 stored in the execution area of the reserved ball storage area, An effect to be displayed on the third symbol display device 81 is set to indicate whether the reach is front / rear out of reach, reach other than front / rear out, or complete out. In the present embodiment, as described above, the range of values corresponding to each stop pattern of the stop pattern selection counter C3 depends on the high probability state, the low probability state, and the operation suspension number N. Different tables are set up.

  Next, the variation pattern at the time of detachment is determined (S405), the display time of the first symbol display device 37 is set, and the variation time of the third symbol until the third symbol display device 81 stops at the detachment symbol. Is determined. At this time, as in the process of S403, the values of the variation type counters CS1 and CS2 stored in the counter buffer of the RAM 203 are confirmed, and the normal reach, super reach, and premium reach are determined based on the value of the first variation type counter CS1. In addition to determining the fluctuation time of the rough symbol variation such as, the variation time until the final stop symbol (the middle symbol Z2 in the present embodiment) stops after the reach occurs based on the value of the second variation type counter CS2 (in other words, paraphrase) For example, the number of fluctuation symbols) is determined.

  When the process of S403 or the process of S405 is completed, the effect time to be added to or subtracted from the variation time determined by the first and second type counters CS1 and CS2 is determined (S406). At this time, the addition / subtraction of effect time is determined based on the value of the third type counter CS3 stored in the counter buffer of the RAM 203, the display time of the first symbol display device 37 is set, and the third symbol display The variation time of the device 81 is set. In the present embodiment, the effect time addition / subtraction is determined according to the value of the third variation type counter CS3 when the variation display time is not changed and when the variation display time is added for one second, the variation display time is set to 2. In the case of adding seconds, four types of addition values are determined for the case of subtracting 1 second from the variable display time.

  In addition, when the variable display time is added or subtracted, a notice effect that increases the expected value of the jackpot on the third symbol display device 81 (for example, a slip effect that causes the change time of the variable symbol to be longer than usual and is accompanied by a slip) An effect of displaying a notice character is produced, for example, an effect of making the change time of one change symbol shorter than usual and stopping it immediately). In addition, when the value of the first random number counter C1 is a big hit, the probability that an added value of 2 seconds is selected is set high, so that the player expects a big hit by confirming the notice effect. Can do.

  Next, a variation pattern command is set according to the variation pattern (variation time) determined in S403 or S405 (S407), and a stop symbol command is set according to the stop symbol set in S402 or S404. (S408). Then, an effect time addition command is set according to the effect time addition value determined in the process of S406 (S409), and the process returns to the variation process.

  As described above, according to the pachinko machine 10 of the present embodiment, when the inner frame 12 or the front frame 14 is opened, the inner frame 12 or the front frame 14 is opened. For about 10 ms, conduction between the collector terminal c of the transistor TR1 and the emitter terminal e of the transistor TR1 is cut off. Then, since the current to one end of the resistor R7 is stopped for about 10 ms, the current to the light emitting diode which is the primary side of the photocoupler PR1 is also stopped for about 10 ms. Therefore, the high signal output from the light receiving element (phototransistor) on the secondary side of the photocoupler PR1 to the hall computer 262 is stopped for about 10 ms. This stoppage of the high signal is stored in the hall computer 262 that continues to operate for 24 hours. Therefore, by using the frame opening detection circuit 260 and the external output terminal board 261, the hall computer 262 can memorize that the inner frame 12 has been opened or the front frame 14 has been opened.

  Further, according to the pachinko machine 10 of the present embodiment, when the inner frame 12 and the front frame 14 are closed, and when about 10 ms has elapsed since the inner frame 12 or the front frame 14 was opened, A high signal is output from the light receiving element (phototransistor) on the secondary side of the photocoupler PR1 of the external output terminal plate 261 to the hall computer 262. On the other hand, as described above, when the inner frame 12 or the front frame 14 is in the open state, the high signal output from the phototransistor to the hall computer 262 is in the stop state, but the period in which the high signal is in the stop state. Is about 10 ms.

  Here, the light receiving element (phototransistor) on the secondary side of the photocoupler PR1 of the external output terminal plate 261 is connected to the hall computer 262 using a communication cable (not shown). When the signal is cut (damaged) by, the high signal output from the phototransistor to the hall computer 262 exceeds about 10 ms and is always stopped.

  Therefore, when the high signal output to the hall computer 262 from the light receiving element (phototransistor) that is the secondary side of the photocoupler PR1 of the external output terminal plate 261 is stopped for more than about 10 ms, The disconnection (breakage) of the communication cable connecting the transistor and the hall computer 262 can be detected. Therefore, in addition to being able to detect the opening of the inner frame 12 or the front frame 14 from the high signal stop state period stored in the hall computer 262, the communication cable connecting the phototransistor and the hall computer 262 is disconnected (damaged). Etc. can also be detected.

  In addition, the semiconductor components used for the open frame detection circuit 260 and the external output terminal board 261 may be destroyed by impact, static electricity, or the like. This destruction destroys the semiconductor used for the semiconductor components. Therefore, in general, an open breakdown (a breakdown in which the terminals of the semiconductor components are opened) is more likely to occur than a short breakdown (a breakdown in which the terminals of the semiconductor components are in a short circuit). When the semiconductor component is open broken, no current is supplied to the semiconductor component, so that no normal voltage is output from the semiconductor component. Then, since a normal current is not supplied to the photocoupler PR1, there is no abnormality in the communication cable connecting the light receiving element (phototransistor) on the secondary side of the photocoupler PR1 of the external output terminal plate 261 and the hall computer 262. However, the high signal output from the phototransistor to the hall computer 262 exceeds about 10 ms and is always stopped.

  Therefore, although there is no abnormality in the communication cable that connects the light receiving element (phototransistor) that is the secondary side of the photocoupler PR1 of the external output terminal plate 261 and the hall computer 262, the high output that is output from the phototransistor to the hall computer 262. When the signal is stopped after approximately 10 ms, the breakage of the frame opening detection circuit 260 or the external output terminal board 261 can be detected. Therefore, in addition to being able to detect the opening of the inner frame 12 or the front frame 14 from the high signal stop state period stored in the hall computer 262, the frame opening detection circuit 260 or the external output terminal plate 261 is also destroyed (abnormal). Can be detected.

  Further, according to the pachinko machine 10 of the present embodiment, the frame open detection circuit 260 is provided with the storage battery SB1, so that power is supplied to the pachinko machine 10 and a DC voltage of 12 volts from the DC power supply DC1. In addition to the case where, for example, the business hours of the amusement hall are over, the power supply to the pachinko machine 10 is cut off, and the DC voltage of 12 volts is not supplied from the DC power supply DC1. The frame opening detection circuit 260 can detect the opening of the inner frame 12 and the opening of the front frame 14.

  Next, a pachinko machine according to a second embodiment will be described with reference to FIGS. 18 and 19. The pachinko machine of the second embodiment is obtained by changing the frame opening detection circuit 260 of the pachinko machine 10 of the first embodiment to a frame opening detection circuit 270 having another configuration. The frame opening detection circuit 270 of the second embodiment has a simplified circuit configuration compared to the frame opening detection circuit 260 of the first embodiment. Specifically, the frame opening detection circuit 270 of the second embodiment removes the timer IC1, the resistors R1 to R3, the capacitors CD3 to CD5, and the EXOR circuit IC2 from the frame opening detection circuit 260 of the first embodiment, and the resistor R8. The circuit configuration is simplified by adding a resistor R9 and changing the connection of each component.

  According to the frame open detection circuit 270 of the second embodiment, the period during which the high signal output from the light receiving element (phototransistor) on the secondary side of the photocoupler PR1 to the hall computer 262 is stopped is set to the inner frame 12. Or it can change according to the open period of the front frame 14. Therefore, in addition to being able to detect the opening of the inner frame 12 or the front frame 14, it is also possible to detect the opening period of the inner frame 12 or the front frame 14.

  FIG. 18 is a circuit diagram showing an electrical configuration of the frame opening detection circuit 270 of the second embodiment. In addition, the same number is attached | subjected to the part same as the frame open | release detection circuit 260 of 1st Embodiment mentioned above in FIG. 7, the description is abbreviate | omitted, and only a different part is demonstrated.

  The positive terminal of the storage battery SB1 is connected to one end of a 6 kΩ resistor R9 and to one end of a resistor R7 of the external output terminal plate 261. The other end of the resistor R9 is connected to one ends of the switch SW1 and the switch SW2, and is connected to one end of a 10 kΩ resistor R8. The other end of the resistor R8 is connected to one end of the capacitor CD2, one end of the resistor R4, and one end of the resistor R5. Note that the other ends of the switch SW1 and the switch SW2 are grounded.

  The resistor R9 is a voltage (about 11) applied to the resistor R8 and the resistor R4 when the inner frame 12 and the front frame 14 are in the closed state and the switch SW1 and the switch SW2 are in the cutoff state (see FIG. 5A). .0 volts) is a pull-up resistor. The voltage applied to the resistor R8 and the resistor R4 is about 11.3 volts (the voltage at the plus terminal of the storage battery SB1) (the voltage drop at the diode D1 is about 0.7 volts from the 12 volts supplied from the DC power source DC1). Is approximately 11.0 volts minus a voltage drop of about 0.3 volts at resistor R9.

  Therefore, when the inner frame 12 and the front frame 14 are in the closed state and the switch SW1 and the switch SW2 are in the cut-off state (see FIG. 5A), the voltage applied to the resistor R8 and the resistor R4 is the plus of the storage battery SB1. The voltage is about 11.0 volts which is the same as the terminal voltage. The resistor R8 and the resistor R4 constitute a circuit that divides the voltage applied to the resistor R8 and the resistor R4. As described above, the resistance values of the resistor R8 and the resistor R4 are each 10 kΩ. Accordingly, when the inner frame 12 and the front frame 14 are in the closed state and the switch SW1 and the switch SW2 are in the cut-off state (see FIG. 5A), a voltage of about 11.0 volts applied to the resistor R8 and the resistor R4. Is divided by resistors R8 and R4 to a maximum value of about 5.5 volts respectively.

  Thus, when the inner frame 12 and the front frame 14 are in the closed state and the switch SW1 and the switch SW2 are in the cut-off state (see FIG. 5A), the DC voltage is applied to the resistor R4. The collector terminal c and the emitter terminal e of the transistor TR1 are electrically connected, and a high signal is output from the secondary light receiving element (phototransistor) of the photocoupler PR1 to the hall computer 262.

  On the other hand, when either the inner frame 12 or the front frame 14 is in an open state and either the switch SW1 or the switch SW2 is in a conductive state, or both the inner frame 12 and the front frame 14 are in an open state. When both the switch SW1 and the switch SW2 are in the conductive state (see FIG. 5B), the voltage applied to the resistor R8 and the resistor R4 is zero volts.

  Thus, when either the inner frame 12 or the front frame 14 is in an open state and either the switch SW1 or the switch SW2 is in a conductive state, or both the inner frame 12 and the front frame 14 are open. When the switch SW1 and the switch SW2 are both in a conductive state (see FIG. 5B), the DC voltage supplied to the resistor R4 is cut off during the open period, and the collector terminal c of the transistor TR1 And the emitter terminal e of the transistor TR1 are disconnected. Then, during this open period, the current supplied to the light emitting diode on the primary side of the photocoupler PR1 is cut off. As a result, either the inner frame 12 or the front frame 14 is open, and either the switch SW1 or the switch SW2 is in a conductive state, or both the inner frame 12 and the front frame 14 are open. During the period when both the switch SW1 and the switch SW2 are in the conductive state, the high signal output from the light receiving element (phototransistor) on the secondary side of the photocoupler PR1 to the hall computer 262 is stopped.

  Therefore, according to the frame open detection circuit 270 of the second embodiment, the period during which the high signal output from the light receiving element (phototransistor) on the secondary side of the photocoupler PR1 to the hall computer 262 is in the stopped state is 12 or the opening period of the front frame 14 can be changed. The stop state of the high signal is stored in the hall computer 262 that continues to operate for 24 hours. Therefore, according to the frame opening detection circuit 270 of the second embodiment, in addition to detecting the opening of the inner frame 12 or the front frame 14, it is also possible to detect the opening period of the inner frame 12 or the front frame 14. .

  Further, since the frame opening detection circuit 270 is provided with the storage battery SB1, the frame opening detection circuit 270 is supplied with power to the pachinko machine and supplied with a DC voltage of 12 volts from the DC power supply DC1. In addition to the case, for example, even when the business hours of the amusement hall are over and the power supply to the pachinko machine is cut off and the DC voltage of 12 volts is not supplied from the DC power supply DC1, In addition to being able to detect the opening of the frame 14, the opening period of the inner frame 12 or the front frame 14 can also be detected.

  Next, referring to FIG. 19, the voltage (A) of the frame open detection circuit 270 changes according to the state of the switch SW1 (the state of the inner frame 12) and the state of the switch SW2 (the state of the front frame 14). 18) and the output of the external output terminal board 261 (input of the hall computer 262) will be described. FIG. 19 shows the state of the switch SW1 (the state of the inner frame 12), the state of the switch SW2 (the state of the front frame 14), the voltage A of the frame open detection circuit 270, and the output of the external output terminal plate 261 (of the hall computer 262). 6 is a timing chart showing a relationship of (input). Each time from t1 to t8 shown in FIG. 19 is the same as each time from t1 to t8 shown in the timing chart of the frame opening detection circuit 260 of the first embodiment shown in FIG. is there.

  As shown in FIG. 19A, when the switch SW1 is in a conductive state (the inner frame 12 is in an open state) at t1, the frame open detection circuit 270 follows this, as shown in FIG. 19C. The voltage of A (see FIG. 18) switches from about 11.0 volts to zero volts (at time t1). As a result, the terminal between the collector terminal and the emitter terminal of the transistor TR1 of the frame opening detection circuit 270 is cut off, and the current supply to one end of the resistor R7 of the external output terminal plate 261 is stopped. Accordingly, as shown in FIG. 19D, the output of the secondary light receiving element (phototransistor) of the photocoupler PR1, that is, the output of the external output terminal plate 261 switches from the high state to the low state (t1). Time). Accordingly, the high signal output from the external output terminal board 261 to the hall computer 262 is stopped.

  Then, as shown in FIG. 19A, when the switch SW1 is in the cut-off state (the inner frame 12 is closed) at t2, as shown in FIG. 19C, the voltage of A of the frame open detection circuit 270 is obtained. Switches from zero volts to about 11.0 volts (at t2). As a result, the collector terminal and the emitter terminal of the transistor TR1 of the frame open detection circuit 270 are turned on again, and the current supply to one end of the resistor R7 of the external output terminal plate 261 is resumed. Therefore, as shown in FIG. 19D, the output of the external output terminal plate 261 switches from the low state to the high state (at time t2). Therefore, a high signal is output again from the external output terminal board 261 to the hall computer 262.

  As described above, when the inner frame 12 is opened and the switch SW1 is turned on (from time t1 to time t2), the high signal output from the external output terminal board 261 to the hall computer 262 during the period is in the stopped state. (From t1 to t2). The high signal stop state is stored in the hall computer 262.

  Next, as shown in FIG. 19 (b), when the switch SW2 becomes conductive at time t3 (the front frame 14 is in the open state), the frame opens as shown in FIG. 19 (c). The voltage of A in the detection circuit 270 (see FIG. 18) is switched from about 11.0 volts to zero volts (at time t3). As a result, the terminal between the collector terminal and the emitter terminal of the transistor TR1 of the frame opening detection circuit 270 is cut off, and the current supply to one end of the resistor R7 of the external output terminal plate 261 is stopped. Accordingly, as shown in FIG. 19D, the output of the light receiving element (phototransistor) on the secondary side of the photocoupler PR1, that is, the output of the external output terminal plate 261 switches from the high state to the low state (t3). Time). Accordingly, the high signal output from the external output terminal board 261 to the hall computer 262 is stopped.

  Then, as shown in FIG. 19B, when the switch SW2 is in the cut-off state (the front frame 14 is closed) at t4, as shown in FIG. 19C, the voltage of A of the frame open detection circuit 270 Switches from zero volts to about 11.0 volts (at t4). As a result, the collector terminal and the emitter terminal of the transistor TR1 of the frame open detection circuit 270 are turned on again, and the current supply to one end of the resistor R7 of the external output terminal plate 261 is resumed. Therefore, as shown in FIG. 19D, the output of the external output terminal plate 261 switches from the low state to the high state (at time t4). Therefore, a high signal is output again from the external output terminal board 261 to the hall computer 262.

  As described above, when the front frame 14 is opened and the switch SW2 is turned on (from time t3 to time t4), the high signal output from the external output terminal board 261 to the hall computer 262 during the period is in the stopped state. (From t3 to t4). The high signal stop state is stored in the hall computer 262.

  Finally, a case will be described in which the switch SW2 is in a conductive state (the front frame 14 is in an open state) when the switch SW1 is in a conductive state (the inner frame 12 is in an open state). As shown in FIG. 19A, at time t5, the switch SW1 becomes conductive (inner frame 12 is open), and as shown in FIG. 19B, at time t6, switch SW2 becomes conductive (front surface). When the frame 14 is in the open state), as shown in FIG. 19C, the voltage A (see FIG. 18) of the frame open detection circuit 270 switches from about 11.0 volts to zero volts at t5. As a result, the terminal between the collector terminal and the emitter terminal of the transistor TR1 of the frame opening detection circuit 270 is cut off, and the current supply to one end of the resistor R7 of the external output terminal plate 261 is stopped. Accordingly, as shown in FIG. 19D, the output of the light receiving element (phototransistor) on the secondary side of the photocoupler PR1, that is, the output of the external output terminal plate 261 switches from the high state to the low state (t5). Time). Accordingly, the high signal output from the external output terminal board 261 to the hall computer 262 is stopped.

  As shown in FIG. 19 (a), at time t7, the switch SW1 is in the cut-off state (the inner frame 12 is closed), and as shown in FIG. 19 (b), at time t8, the switch SW2 is in the cut-off state. When the front frame 14 is in the closed state, as shown in FIG. 19C, the voltage of A in the frame open detection circuit 270 switches from zero volts to about 11.0 volts at t8. As a result, the collector terminal and the emitter terminal of the transistor TR1 of the frame open detection circuit 270 are turned on again, and the current supply to one end of the resistor R7 of the external output terminal plate 261 is resumed. Accordingly, as shown in FIG. 19D, the output of the external output terminal plate 261 switches from the low state to the high state (at time t8). Therefore, a high signal is output again from the external output terminal board 261 to the hall computer 262.

  As described above, after the inner frame 12 is opened and the switch SW1 is turned on, the front frame 14 is closed and the switch SW2 is turned off (from t5 to t8). The high signal output from the terminal board 261 to the hall computer 262 is stopped (from t5 to t8). The high signal stop state during the period from t5 to t8 is stored in the hall computer 262 that continues to operate for 24 hours. As described above, when the switch SW1 and the switch SW2 are in the conductive state (the inner frame 12 and the front frame 14 are in the open state), the frame open detection circuit 270 has either one of the switch SW1 or the switch SW2 in the conductive state (the inner frame 12). 12 until the switch SW1 and the switch SW2 are both shut off (both the inner frame 12 and the front frame 14 are closed). The high signal output from the output terminal board 261 to the hall computer 262 can be stopped.

  As described above, according to the pachinko machine of the second embodiment, the period in which the high signal output from the light receiving element (phototransistor) on the secondary side of the photocoupler PR1 to the hall computer 262 is stopped is set to the inner frame 12. Or it can change according to the open period of the front frame 14. As described above, the stop state of the high signal is stored in the hall computer 262 that continues to operate for 24 hours. Therefore, according to the frame opening detection circuit 270 of the second embodiment, in addition to detecting the opening of the inner frame 12 or the front frame 14, it is also possible to detect the opening period of the inner frame 12 or the front frame 14. .

  Further, the pachinko machine in which the inner frame 12 or the front frame 14 is opened can be identified by the high signal stop state stored in the hall computer 262. Furthermore, by causing the hall computer 262 to stop the high signal from the external output terminal board 261 and to store the stop time of the high signal, the opening time of the inner frame 12 of the specified pachinko machine or the front frame 14 The opening time can also be detected.

  Further, according to the pachinko machine of the second embodiment, as described above, when the inner frame 12 or the front frame 14 is in an open state, and then the inner frame 12 or the front frame 14 that is in an open state is closed. The high signal is again output from the light receiving element (phototransistor) on the secondary side of the photocoupler PR1 of the external output terminal plate 261 to the hall computer 262.

  Here, the light receiving element (phototransistor) on the secondary side of the photocoupler PR1 of the external output terminal plate 261 is connected to the hall computer 262 using a communication cable (not shown). When the inner frame 12 and the front frame 14 are closed, the high signal output from the phototransistor to the hall computer 262 is always stopped.

  Therefore, a high signal output from the light receiving element (phototransistor) that is the secondary side of the photocoupler PR1 of the external output terminal plate 261 to the hall computer 262 is associated with the inner frame 12 and the front frame 14 being closed. In the case of the stop state, it is possible to detect disconnection (damage) of the communication cable connecting the phototransistor and the hall computer 262.

  In addition, the semiconductor components used for the open frame detection circuit 270 and the external output terminal board 261 may be broken by impact, static electricity, or the like. This breakage destroys the semiconductor used for the semiconductor components. Therefore, in general, an open breakdown (a breakdown in which the terminals of the semiconductor components are opened) is more likely to occur than a short breakdown (a breakdown in which the terminals of the semiconductor components are in a short circuit). When the semiconductor component is open broken, no current is supplied to the semiconductor component, so that no normal voltage is output from the semiconductor component. Then, since a normal current is not supplied to the photocoupler PR1, there is no abnormality in the communication cable connecting the light receiving element (phototransistor) on the secondary side of the photocoupler PR1 of the external output terminal plate 261 and the hall computer 262. Even if the inner frame 12 and the front frame 14 are closed, the high signal output from the phototransistor to the hall computer 262 is always stopped.

  Therefore, there is no abnormality in the communication cable connecting the light receiving element (phototransistor) that is the secondary side of the photocoupler PR1 of the external output terminal plate 261 and the hall computer 262, and the inner frame 12 and the front frame 14 are closed. Nevertheless, when the high signal output from the phototransistor to the hall computer 262 is in a stopped state, the breakage of the frame opening detection circuit 270 or the external output terminal plate 261 can be detected.

  Further, since the frame open detection circuit 270 is provided with the storage battery SB1, the frame open detection circuit 270 is supplied with power to the pachinko machine and supplied with a DC voltage of 12 volts from the DC power supply DC1. In addition to the case, for example, even when the business hours of the amusement hall are over and the power supply to the pachinko machine is cut off and the DC voltage of 12 volts is not supplied from the DC power supply DC1, In addition to being able to detect the opening of the frame 14, the opening period of the inner frame 12 or the front frame 14 can also be detected.

  Next, a pachinko machine according to a third embodiment will be described with reference to FIGS. The pachinko machine of the third embodiment is obtained by changing the frame opening detection circuit 260 of the pachinko machine 10 of the first embodiment to a frame opening detection circuit 280 having another configuration. The frame opening detection circuit 280 of the third embodiment has a circuit configuration changed from that of the frame opening detection circuit 260 of the first embodiment. Specifically, the frame opening detection circuit 280 of the third embodiment removes the resistor R2, the EXOR circuit IC2, the capacitors CD4 and CD5 from the frame opening detection circuit 260 of the first embodiment, and the resistor R1, the capacitor CD3, the resistor R3, resistor R7, switch SW1 and switch SW2 are connected to change, so that timer IC1 functions as a monostable multivibrator, integrating circuit 281 including resistor 10 and capacitor CD7 before the TRG terminal of timer IC1. And a NOT circuit IC3, which is a logic negation circuit, is connected to the OUT terminal of the timer IC1 to change the circuit configuration. Then, the frame open detection circuit 280 of the third embodiment is outputted from the frame open detection circuit 260 of the first embodiment from the mode of the voltage applied to the TRG terminal of the timer IC1 and the OUT terminal of the timer IC1. The mode of voltage is changed.

  According to the frame open detection circuit 280 of the third embodiment, the integration circuit 281 makes the falling period of the voltage applied to the TRG terminal of the timer IC 1 constant regardless of the open period of the inner frame 12 or the front frame 14. By setting the period (about 2 ms), the falling period of the voltage applied to the TRG terminal of the timer IC1 is made longer than the period (about 10 ms) in which a voltage of about 9.6 volts is output from the OUT terminal of the timer IC1. Can be adjusted short. Thus, regardless of the opening period of the inner frame 12 or the front frame 14, the timer IC 1 functioning as a monostable multivibrator is always operated normally, and the high signal output from the external output terminal board 261 to the hall computer 262 is The stop period can be about 10 ms. Therefore, the frame opening detection circuit 280 is not related to the frame opening detection circuit 260 and does not employ a special circuit configuration, and is related to the opening period of the inner frame 12 or the front frame 14 similarly to the frame opening detection circuit 260. First, the high signal output period output from the external output terminal board 261 to the hall computer 262 can be about 10 ms.

  FIG. 20 is a circuit diagram showing an electrical configuration of the frame opening detection circuit 280 of the third embodiment. In addition, the same number is attached | subjected to the part same as the frame open | release detection circuit 260 of 1st Embodiment mentioned above in FIG. 7, the description is abbreviate | omitted, and only a different part is demonstrated.

  When the power supply to the pachinko machine is cut off and the DC voltage of 12 volts is not supplied from the DC power supply DC1, the plus terminal of the storage battery SB1 that supplies the DC voltage to the frame open detection circuit 280 and the external output terminal plate 261 is Are connected to one end of a 100 kΩ resistor R10 and to the VDD terminal of the timer IC1, one end of a 100 KΩ resistor R1a, the RES terminal of the timer IC1 and one end of a 1 KΩ resistor R7a.

  The other end of the resistor R1a is connected to one end of a 0.1 μF capacitor CD3a and to the DCH terminal of the timer IC1 and the TH terminal of the timer IC1. The other end of the capacitor CD3a is grounded. Due to the connection between the capacitor CD3a and the resistor R1a, the timer IC1 opens the inner frame 12 or the front frame 14, whereby the switch SW1 or the switch SW2 is turned on, and the voltage applied to the TRG terminal of the timer IC1 is increased. When it falls to zero volts, it functions as a monostable multivibrator that raises the voltage at the OUT terminal of the timer IC1 from zero volts to about 9.6 volts for about 10 ms. Note that about 10 ms, which is a period for raising the voltage at the OUT terminal of the timer IC1 from zero volts to about 9.6 volts, is the product of the resistance value of the resistor R1a (100 kΩ) and the capacitance value of the capacitor CD3a (0.1 μF). It is determined by a certain time constant.

  The NOT circuit IC3, which is a logic negation circuit, is a circuit that inverts and outputs the voltage output from the OUT terminal of the timer IC1, and the input terminal of the NOT circuit IC3 is connected to the OUT terminal of the timer IC1, and the NOT circuit IC3. Is connected to one end of the resistor R3a. The power supply terminal (not shown) of the NOT circuit IC3 is connected to the plus terminal of the storage battery SB1. With this connection, when the voltage at the OUT terminal of the timer IC1 is zero volts, a voltage of about 11.3 volts is output from the output terminal of the NOT circuit IC3. At this time, the collector terminal c and the emitter terminal e of the transistor TR1 become conductive, and a high signal is output from the external output terminal plate 261 to the hall computer 262. On the other hand, when the voltage at the OUT terminal of the timer IC1 is about 9.6 volts, the voltage output from the output terminal of the NOT circuit IC3 is zero volts. At this time, the collector terminal c and the emitter terminal e of the transistor TR1 are cut off, and the high signal output from the external output terminal plate 261 to the hall computer 262 is stopped. Therefore, when the voltage of the OUT terminal of the timer IC 1 rises from zero volt to about 9.6 volt for about 10 ms, the high signal output from the external output terminal board 261 to the hall computer 262 is stopped for about 10 ms. Become.

  The resistor R10 is a resistor that stabilizes the voltage applied to the TRG terminal of the timer IC1, and that constitutes the integrating circuit 281 with the capacitor CD7. As described above, one end of the resistor R10 is connected to the plus terminal of the storage battery SB1, the VDD terminal of the timer IC1, one end of the resistor R1a, the RES terminal of the timer IC1, and one end of the resistor R7a. The other end of the resistor R10 is connected to the anode terminal of the diode D2, which is a diode element. The cathode terminal of the diode D2 is connected to the TRG terminal of the timer IC1, and the limiting voltage (zener voltage) is about 10. It is connected to the cathode terminal of a Zener diode D3, which is a .5 volt Zener diode element, and to one end of each of switches SW1 and SW2 connected in parallel. Therefore, when the inner frame 12 and the front frame 14 are closed and the switch SW1 and the switch SW2 are shut off, the voltage applied to the TRG terminal of the timer IC1 is about 11.3 volts supplied from the storage battery SB1. Is approximately 10.3 volts obtained by subtracting approximately 0.3 volts of the voltage drop at the resistor R10 and approximately 0.7 volts of the voltage drop at the diode D2.

  The 0.02 μF capacitor CD7 constitutes an integrating circuit 281 with the resistor R10, and controls the voltage applied to the TRG terminal of the timer IC1. One end of the capacitor CD7 is connected to the other end of each of the switch SW1 and the switch SW2, and the other end of the capacitor CD7 is grounded. The integrating circuit 281 composed of the capacitor CD7 and the resistor R10 is applied to the TRG terminal of the timer IC1 when the inner frame 12 or the front frame 14 is opened and the switch SW1 or SW2 is turned on. This is a circuit that lowers the voltage of about 10.3 volts to zero volts and returns the TRG terminal voltage of the timer IC1 to about 10.3 volts again about 2 ms after the fall.

  Specifically, when the inner frame 12 or the front frame 14 is opened and the switch SW1 or the switch SW2 is turned on according to the opening, a voltage of about 10.3 volts supplied from the storage battery SB1 is applied to the capacitor CD7. Application is started, and charging of the capacitor CD7 is started. At the start of charging, the voltage applied to the capacitor CD7 instantaneously becomes zero volts, so that the voltage applied to the TRG terminal of the timer IC1 instantaneously becomes zero volts. As the capacitor CD7 is charged, the capacitor CD7 increases the voltage applied to the TRG terminal of the timer IC1, and finally controls the voltage applied to the TRG terminal of the timer IC1 to about 10.3 volts. It is.

  It should be noted that the period until the capacitor CD7 is fully charged, that is, the voltage of about 10.3 volts applied to the TRG terminal of the timer IC1 falls to zero volts, and from the fall, the voltage of the TRG terminal of the timer IC1 becomes Again, about 2 ms, which is a period until returning to about 10.3 volts, is determined by a time constant which is a product of the resistance value of the resistor R10 (100 kΩ) and the capacitance value of the capacitor CD7 (0.02 μF).

  Thus, the voltage applied to the TRG terminal of the timer IC1 falls, and the integration circuit 281 has a period (about 2 ms) until the TRG terminal voltage of the timer IC1 returns to about 10.3 volts after the fall. Thus, regardless of the opening period of the inner frame 12 and the front frame 14, the voltage of the OUT terminal of the timer IC 1 is adjusted to a period shorter than the period (about 10 ms) rising from zero volts to about 9.6 volts. Note that the voltage applied to the TRG terminal of the timer IC1 falls after changing the resistance value of the resistor R10 and the capacitance value of the capacitor CD7, and then the voltage of the TRG terminal of the timer IC1 is about 10.3 volts. It is possible to freely change the period until the voltage returns to (5) within about 10 ms, which is the period until the voltage of the OUT terminal of the timer IC1 rises from zero volt to about 9.6 volt.

  Here, the monostable multivibrator does not normally output a signal from the output terminal unless the input period of the signal input to the input terminal is shorter than the output period of the signal output from the output terminal (from the output terminal). Signal continues to be output). For this reason, when the timer IC1 is made to function as a monostable multivibrator without using the integrating circuit 281, the time period when a voltage of about 9.6 volts is output from the OUT terminal of the timer IC1, that is, The period until the TRG terminal voltage of the timer IC1 returns from zero volts to about 10.3 volts again from the high signal stop period output from the external output terminal board 261 to the hall computer 262, that is, the inner frame 12 and The opening period of the front frame 14 (the conduction period of the switch SW1 and the switch SW2) must be short. However, since the open periods of the inner frame 12 and the front frame 14 are completely unpredictable, the inner frames 12 and In order to always shorten the opening period of the front frame 14, the period in which a voltage of about 9.6 volts is output from the OUT terminal of the timer IC 1 must be set to a period with a sufficient margin. As described above, even if the period in which the voltage of about 9.6 volts is output from the OUT terminal of the timer IC 1 is set to a period having a sufficient margin, the opening period of the inner frame 12 and the front frame 14 is not limited to that period. If exceeded, the timer IC1 functioning as a monostable multivibrator does not operate normally even if the inner frame 12 and the front frame 14 are closed and the switch SW1 and the switch SW2 are shut off. A voltage of about 9.6 volts continues to be output from the OUT terminal. Then, the high signal output from the external output terminal board 261 to the hall computer 262 also remains in the stopped state even after the set stop period (about 10 ms) is exceeded. As a result, although the frame opening detection circuit 280 and the external output terminal plate 261 are in a normal state, either the frame opening detection circuit 280 or the external output terminal plate 261 has failed, or both of them have failed. I misunderstand. Therefore, a special circuit configuration is required to allow the timer IC1 to function as a monostable multivibrator and to operate the monostable multivibrator normally without using the integration circuit 281.

  However, by providing the integration circuit 281 in front of the TRG terminal of the timer IC1, when the inner frame 12 or the front frame 14 is opened, the timer IC1 regardless of the open period (the conduction period of the switch SW1 and the switch SW2). The period until the voltage applied to the TRG terminal of the timer IC1 falls to zero volts and then returns to about 10.3 volts is adjusted to be shorter than the period in which the voltage of about 9.6 volts is output from the OUT terminal of the timer IC1. can do. In this way, by setting the falling period of the TRG terminal voltage of the timer IC1 to a certain period (about 2 ms) regardless of the opening period of the inner frame 12 and the front frame 14, the integration circuit 281 makes the timer IC1 normal. The time period during which a voltage of about 9.6 volts is output from the OUT terminal of the timer IC 1 can be set to about 10 ms.

  When a voltage of about 9.6 volts is output from the OUT terminal of the timer IC1 for about 10 ms, the output terminal voltage of the NOT circuit IC3 becomes zero volts for about 10 ms. Then, the collector terminal c and the emitter terminal e of the transistor TR1 are cut off for about 10 ms, and the current supplied from the storage battery SB1 to the photocoupler PR1 via the resistor R7a is stopped for about 10 ms. . Thus, the high signal output from the external output terminal board 261 to the hall computer 262 is stopped for about 10 ms for each opening of the inner frame 12 or the front frame 14. As described above, even if the timer IC 1 is made to function as a monostable multivibrator, the integration circuit 281 is provided in front of the TRG terminal of the timer IC 1 so that the external output terminal plate 261 can be used without adopting a special circuit configuration. The stop period of the high signal output to the hall computer 262 can be about 10 ms.

  The TRG terminal of the timer IC1 is connected to the cathode terminal of a Zener diode D3 having a limit voltage (zener voltage) of about 10.5 volts, and the ground is connected to the anode terminal of the Zener diode D3. The zener diode D3 has the charge stored in the capacitor CD7 and the voltage supplied from the storage battery SB1 superimposed when the inner frame 12 or the front frame 14 is opened and the switch SW1 or SW2 is turned on. This is an element that prevents an overvoltage (for example, a voltage of 12.3 volts) that can break the timer IC1 from being applied to the TRG terminal of the timer IC1. Specifically, the charge stored in the capacitor CD7 due to the opening of the inner frame 12 or the front frame 14 and the conduction of the switch SW1 or the switch SW2 again becomes the inner frame 12 or the front frame within a relatively short period of time. 14 is opened, and when the switch SW1 or SW2 is turned on, the switch SW1 or the switch SW2 is discharged from the other end side to the one end side. The voltage of about 10.3 volts discharged from the capacitor CD7 and the voltage of about 10.3 volts supplied from the storage battery SB1 are superimposed, and an overvoltage large enough to destroy the timer IC1 is applied to the TRG terminal of the timer IC1. Can be applied. However, since a Zener diode D3 having a limit voltage (zener voltage) of about 10.5 volts is connected between the TRG terminal of the timer IC1 and the ground, the voltage applied to the TRG terminal of the timer IC1 The maximum value is about 10.5 volts, and an overvoltage that destroys the timer IC1 is not applied to the TRG terminal of the timer IC1. In this way, by using the Zener diode D3 that has a simple configuration and is inexpensive, it is possible to prevent an overvoltage large enough to destroy the timer IC1 from being applied to the TRG terminal of the timer IC1, and to prevent damage to the timer IC1. it can.

  As described above, since the limit voltage (zener voltage) of the Zener diode D3 is about 10.5 volts, the inner frame 12 and the front frame 14 are closed, and the switch SW1 and the switch SW2 are shut off. In this case, the current supplied from the storage battery SB1 does not flow to the ground via the Zener diode D3, and the storage battery SB1 is not consumed. In addition, the cathode terminal of the diode D2 is connected to one end of the switch SW1 and the switch SW2, and this diode D2 exhibits a function of preventing the backflow of current. Therefore, a voltage of about 10.3 volts discharged from the capacitor CD7. However, they are not applied to the VDD terminal of the storage battery SB1 or the timer IC1 and are not damaged.

  As described above, in the timer IC1 of the frame open detection circuit 280, the inner frame 12 or the front frame 14 is opened, the switch SW1 or the switch SW2 is turned on, and the voltage applied to the TRG terminal of the timer IC1 falls to zero volts. Then, it functions as a monostable multivibrator that raises the voltage at the OUT terminal of the timer IC1 from zero volts to about 9.6 volts for about 10 ms from the fall. Further, by providing an integration circuit 281 in front of the TRG terminal of the timer IC1, when the inner frame 12 or the front frame 14 is opened, the timer IC1 is connected regardless of the opening period of the inner frame 12 and the front frame 14. Adjust the period from when the voltage applied to the TRG terminal falls to zero volts until it returns to about 10.3 volts, shorter than the period when the voltage at the OUT terminal of the timer IC1 rises from zero volts to about 9.6 volts Can do. As described above, by setting the falling period of the TRG terminal voltage of the timer IC 1 to a fixed period (about 2 ms) regardless of the opening period of the inner frame 12 and the front frame 14 by the integration circuit 281, a monostable multivibrator is obtained. The functioning timer IC1 can be operated normally, and the period at which the voltage at the OUT terminal of the timer IC1 rises from zero volts to about 9.6 volts can be set. Thereby, the stop period of the high signal output from the external output terminal board 261 to the hall computer 262 can be set to about 10 ms. Therefore, the frame opening detection circuit 280 is not related to the frame opening detection circuit 260 and does not employ a special circuit configuration, and is related to the opening period of the inner frame 12 or the front frame 14 similarly to the frame opening detection circuit 260. First, the high signal output period output from the external output terminal board 261 to the hall computer 262 can be about 10 ms.

  Further, according to the pachinko machine of the present embodiment, the frame open detection circuit 280 is provided with the storage battery SB1, so that power is supplied to the pachinko machine and a DC voltage of 12 volts is supplied from the DC power supply DC1. In addition to the case where, for example, even when the game hall is closed and the power supply to the pachinko machine is shut off and no DC voltage of 12 volts is supplied from the DC power supply DC1, the frame is opened. The detection circuit 280 can detect the opening of the inner frame 12 and the opening of the front frame 14. When the opening of the inner frame 12 or the opening of the front frame 14 is detected by the frame opening detection circuit 280, a high signal output from the external output terminal plate 261 to the hall computer 262 is approximately received for each detection. It can be stopped for 10 ms. The stop state of the high signal output from the external output terminal board 261 to the hall computer 262 is stored in the hall computer 262 that continues to operate for 24 hours. Therefore, the pachinko machine in which the inner frame 12 or the front frame 14 is opened can be specified by the high signal stop state stored in the hall computer 262. Further, by causing the hall computer 262 to stop the high signal output from the external output terminal plate 261 and to store the stop time of the high signal, the opening time of the identified inner frame 12 of the pachinko machine or The opening time of the front frame 14 can be detected.

  Note that the door opening detection circuit 280 uses the LMC 555 for the timer IC 1 to detect the opening of the inner frame 12 or the opening of the front frame 14 and realize a circuit that stops energization of the photocoupler PR1 for about 10 ms. However, it is not limited to this. That is, by using another integrated circuit or the like for the timer IC 1, a circuit that generates one pulse signal for one opening of the inner frame 12 or one opening of the front frame 14 is realized. What is necessary is just to stop energization of the photocoupler PR1 for a predetermined period based on the pulse signal.

  Next, referring to FIG. 21, the voltage at the TRG terminal of timer IC1 that changes according to the state of switch SW1 (the state of inner frame 12) and the state of switch SW2 (the state of front frame 14), and timer IC1 The relationship between the voltage at the OUT terminal, the voltage at the output terminal of the NOT circuit IC3, and the output from the external output terminal plate 261 (the input of the hall computer 262) will be described. FIG. 21 shows the state of the switch SW1 (the state of the inner frame 12), the state of the switch SW2 (the state of the front frame 14), the voltage of the TRG terminal of the timer IC1, the voltage of the OUT terminal of the timer IC1, and the output terminal of the NOT circuit IC3. 6 is a timing chart showing the relationship between the voltage of the external output terminal 261 and the output of the external output terminal plate 261 (the input of the hall computer 262). Note that the times from t1 to t8 shown in FIG. 21 are the same as the times from t1 to t8 shown in the timing chart of the frame opening detection circuit 260 of the first embodiment shown in FIG. is there.

  As shown in FIG. 21A, when the switch SW1 is in a conductive state (inner frame 12 is in an open state) at time t1, charging of the capacitor CD7 is started, and as shown in FIG. The TRG terminal voltage falls from about 10.3 volts to zero volts (at time t1). Then, following this, as shown in FIG. 21 (d), the OUT terminal voltage of the timer IC1 rises from zero volts to about 9.6 volts (at time t1). As shown in FIG. 21 (e), the voltage at the output terminal of the NOT circuit IC3 falls from about 11.3 volts to zero volts (at time t1). As a result, the terminal between the collector terminal and the emitter terminal of the transistor TR1 of the frame opening detection circuit 280 is cut off, and the current supply to one end of the resistor R7a of the external output terminal plate 261 is stopped. Therefore, as shown in FIG. 21 (f), the high signal output from the external output terminal board 261 to the hall computer 262 is stopped (at time t1).

  Next, as shown in FIG. 21 (c), when about 2 ms elapses from time t1, the charging of the capacitor CD7 is completed, and the TRG terminal voltage of the timer IC1 returns from zero volts to about 10.3 volts again. However, since the voltage at the OUT terminal of the timer IC1 has risen from zero volt to about 9.6 volts (from t1), about 10 ms has not elapsed, so the OUT terminal voltage of the timer IC1 is as shown in FIG. As shown, it maintains a state of about 9.6 volts. Therefore, the voltage at the output terminal of the NOT circuit IC3 is maintained at zero volts as shown in FIG.

  Thereafter, when about 10 ms elapse from t1, the timer IC1 switches the voltage at the OUT terminal from about 9.6 volts to zero volts as shown in FIG. Then, as shown in FIG. 21 (e), the voltage at the output terminal of the NOT circuit IC3 is switched from zero volts to about 11.3 volts (after about 10 ms has elapsed since t1). As a result, the collector terminal and the emitter terminal of the transistor TR1 of the frame opening detection circuit 280 are turned on again, and the current supply to one end of the resistor R7a of the external output terminal plate 261 is resumed. Accordingly, as shown in FIG. 21 (f), a high signal is output again from the external output terminal board 261 to the hall computer 262 (after about 10 ms has elapsed since t1).

  As described above, after the switch SW1 is turned on (the inner frame 12 is open), that is, after the TRG terminal voltage is switched from about 10.3 volts to zero volts (from time t1), for about 10 ms. When the current supply to one end of the resistor R7a is stopped, the current supply to the primary light emitting diode (see FIG. 20) of the photocoupler PR1 of the external output terminal plate 261 is also stopped for about 10 ms from t1. Is done. As a result, as shown in FIG. 21 (f), the output of the external output terminal plate 261 switches from the high state to the low state for about 10 ms. That is, the high signal output from the external output terminal board 261 to the hall computer 262 is stopped for about 10 ms from t1. The high signal stop state is stored in the hall computer 262.

  As shown in FIG. 21A, when the switch SW1 is in the cut-off state (the inner frame 12 is closed) at t2, the frame opening detection circuit 280 detects the inner frame 12 and the front frame 14 again. Set to possible state.

  Next, as shown in FIG. 21B, at time t3, when the switch SW2 is in a conductive state (the front frame 14 is in an open state), charging of the capacitor CD7 is started, and as shown in FIG. The TRG terminal voltage of the timer IC1 falls from about 10.3 volts to zero volts (at time t3). Then, following this, as shown in FIG. 21 (d), the OUT terminal voltage of the timer IC1 rises from zero volts to about 9.6 volts (at time t3). As shown in FIG. 21 (e), the voltage at the output terminal of the NOT circuit IC3 falls from about 11.3 volts to zero volts (at time t3). As a result, the terminal between the collector terminal and the emitter terminal of the transistor TR1 of the frame opening detection circuit 280 is cut off, and the current supply to one end of the resistor R7a of the external output terminal plate 261 is stopped. Therefore, as shown in FIG. 21F, the high signal output from the external output terminal board 261 to the hall computer 262 is stopped (at time t3).

  The electric charge stored in the capacitor CD7 between time t1 and time t2 is instantaneously discharged through the zener diode D3 at time t3. The discharge period of the capacitor CD7 is a period that is much shorter than about 2 ms in which the voltage at the TRG terminal of the timer IC1 is changed from about 10.3 volts to zero volts and is again about 10.3 volts. It does not significantly affect the voltage applied to the terminals. In addition to this discharge, the electric charge stored in the capacitor CD7 from t1 to t2 is also discharged by self-discharge of the capacitor CD7.

  At time t3, a voltage of about 10.3 volts supplied from the storage battery SB1 and a voltage of about 10.3 volts associated with the charge stored in the capacitor CD7 are superimposed on the TRG terminal of the timer IC1, An overvoltage large enough to destroy the timer IC1 may be applied. However, since a Zener diode D3 having a limit voltage (zener voltage) of about 10.5 volts is connected to the preceding stage of the TRG terminal of the timer IC1, the maximum value of the voltage applied to the TRG terminal of the timer IC1 is The overvoltage which is about 10.5 volts and destroys the timer IC1 is not applied to the TRG terminal of the timer IC1.

  Next, as shown in FIG. 21C, when about 2 ms elapses from t3, the charging of the capacitor CD7 is completed, and the TRG terminal voltage of the timer IC1 returns from zero volts to about 10.3 volts again. However, since the voltage of the OUT terminal of the timer IC1 rises from zero volt to about 9.6 volts (from t3), about 10 ms has not elapsed, the OUT terminal voltage of the timer IC1 is shown in FIG. As shown, it maintains a state of about 9.6 volts. Therefore, the voltage at the output terminal of the NOT circuit IC3 is maintained at zero volts as shown in FIG.

  Thereafter, when about 10 ms elapses from t3, the timer IC1 switches the voltage at the OUT terminal from about 9.6 volts to zero volts as shown in FIG. 21 (d). Then, as shown in FIG. 21 (e), the voltage at the output terminal of the NOT circuit IC3 is switched from zero volts to about 11.3 volts (after about 10 ms have elapsed since t3). As a result, the collector terminal and the emitter terminal of the transistor TR1 of the frame opening detection circuit 280 are turned on again, and the current supply to one end of the resistor R7a of the external output terminal plate 261 is resumed. Therefore, as shown in FIG. 21 (f), a high signal is output again from the external output terminal board 261 to the hall computer 262 (after about 10 ms has elapsed since t3).

  As described above, after the switch SW2 is in a conductive state (the front frame 14 is in an open state), that is, for about 10 ms after the TRG terminal voltage is switched from about 10.3 volts to zero volts (from t3 time). When the current supply to one end of the resistor R7a is stopped, the current supply to the light emitting diode (see FIG. 20) on the primary side of the photocoupler PR1 of the external output terminal plate 261 is also stopped for about 10 ms from t3. Is done. As a result, as shown in FIG. 21 (f), the output of the external output terminal plate 261 switches from the high state to the low state for about 10 ms. That is, the high signal output from the external output terminal board 261 to the hall computer 262 is stopped for about 10 ms from t3. The high signal stop state is stored in the hall computer 262.

  As shown in FIG. 21 (b), when the switch SW2 is in a cut-off state (the front frame 14 is closed) at t4, the frame open detection circuit 280 detects the inner frame 12 and the front frame 14 again. Set to possible state.

  Finally, a case will be described in which the switch SW2 is in a conductive state (the front frame 14 is in an open state) when the switch SW1 is in a conductive state (the inner frame 12 is in an open state). As shown in FIG. 21 (a), at time t5, the switch SW1 becomes conductive (inner frame 12 is open), and as shown in FIG. 21 (b), at time t6, switch SW2 becomes conductive (front surface). When the frame 14 is in an open state), at time t5, charging of the capacitor CD7 is started, and as shown in FIG. 21C, the TRG terminal voltage of the timer IC1 falls from about 10.3 volts to zero volts (t5). Time). Then, following this, as shown in FIG. 21 (d), the OUT terminal voltage of the timer IC1 rises from zero volts to about 9.6 volts (at time t5). As shown in FIG. 21 (e), the voltage at the output terminal of the NOT circuit IC3 falls from about 11.3 volts to zero volts (at time t5). As a result, the terminal between the collector terminal and the emitter terminal of the transistor TR1 of the frame opening detection circuit 280 is cut off, and the current supply to one end of the resistor R7a of the external output terminal plate 261 is stopped. Therefore, as shown in FIG. 21F, the high signal output from the external output terminal board 261 to the hall computer 262 is stopped (at time t5).

  The charge stored in the capacitor CD7 between t3 and t4 has a significant effect on the voltage applied to the TRG terminal of the timer IC1, since the discharge is instantaneously completed through the zener diode D3 at t5. is not. In addition to this discharge, the charge stored in the capacitor CD7 from t3 to t4 is also discharged by self-discharge of the capacitor CD7.

  At t5, a voltage of about 10.3 volts supplied from the storage battery SB1 and a voltage of about 10.3 volts associated with the charge stored in the capacitor CD7 are superimposed on the TRG terminal of the timer IC1, An overvoltage large enough to destroy the timer IC1 may be applied. However, since the maximum value of the voltage applied to the TRG terminal of the timer IC1 is about 10.5 volts due to the Zener diode D3, an overvoltage large enough to destroy the timer IC1 is applied to the TRG terminal of the timer IC1. There is no.

  Next, as shown in FIG. 21C, when about 2 ms elapses from t5, the charging of the capacitor CD7 is completed, and the TRG terminal voltage of the timer IC1 returns from zero volts to about 10.3 volts again. However, since the voltage of the OUT terminal of the timer IC1 rises from zero volt to about 9.6 volts (from t5), about 10 ms has not elapsed, the OUT terminal voltage of the timer IC1 is shown in FIG. As shown, it maintains a state of about 9.6 volts. Therefore, the voltage at the output terminal of the NOT circuit IC3 is maintained at zero volts as shown in FIG.

  Thereafter, when about 10 ms elapses from t5, as shown in FIG. 21D, the timer IC1 switches the voltage of the OUT terminal from about 9.6 volts to zero volts. Then, as shown in FIG. 21 (e), the voltage at the output terminal of the NOT circuit IC3 is switched from zero volts to about 11.3 volts (after about 10 ms has elapsed from t5). As a result, the collector terminal and the emitter terminal of the transistor TR1 of the frame opening detection circuit 280 are turned on again, and the current supply to one end of the resistor R7a of the external output terminal plate 261 is resumed. Accordingly, as shown in FIG. 21 (f), a high signal is output again from the external output terminal board 261 to the hall computer 262 (after about 10 ms has elapsed since t5).

  As described above, after switch SW1 becomes conductive (inner frame 12 is open), that is, for about 10 ms after the TRG terminal voltage is switched from about 10.3 volts to zero volts (from t5). When the current supply to one end of the resistor R7a is stopped, the current supply to the light emitting diode (see FIG. 20) on the primary side of the photocoupler PR1 of the external output terminal plate 261 is also stopped for about 10 ms from t5. Is done. As a result, as shown in FIG. 21 (f), the output of the external output terminal plate 261 switches from the high state to the low state for about 10 ms. That is, the high signal output from the external output terminal board 261 to the hall computer 262 is stopped for about 10 ms from t5. The high signal stop state is stored in the hall computer 262.

  As shown in FIG. 21 (a), at time t7, the switch SW1 is turned off (the inner frame 12 is closed), and as shown in FIG. 21 (b), at time t8, the switch SW2 is turned off. When the front frame 14 is in the closed state, the frame open detection circuit 280 is set again to a state in which the inner frame 12 and the front frame 14 can be detected.

  Thus, even when the switch SW1 is in the conductive state (the inner frame 12 is in the open state) and the switch SW2 is in the conductive state (the front frame 14 is in the open state), the frame open detection circuit 280 is the switch SW1. Regardless of the conduction period (the opening period of the inner frame 12) and the conduction period of the switch SW2 (the opening period of the front frame 14), either the switch SW1 or the switch SW2 is in the conduction state (the inner frame 12 or the front frame 14). When either one is open) and the TRG terminal voltage of the timer IC1 falls from about 10.3 volts to zero volts, about 10 ms elapses, the voltage at the OUT terminal of the timer IC1 is switched from about 9.6 volts to zero volts. . By the operation of the frame opening detection circuit 280, the terminal between the collector terminal c of the transistor TR1 and the emitter terminal e (see FIG. 20) of the transistor TR1 of the frame opening detection circuit 280 is cut off for about 10 ms. As a result, the high signal output from the external output terminal board 261 to the hall computer 262 starts when one of the inner frame 12 or the front frame 14 is in an open state (one of the switch SW1 or the switch SW2 is conductive). It will be stopped only for about 10 ms.

  The stop state of the high signal is stored in the hall computer 262 that continues to operate for 24 hours. Therefore, the pachinko machine in which the inner frame 12 or the front frame 14 is opened can be specified by the high signal stop state stored in the hall computer 262.

  As described above, according to the pachinko machine of the third embodiment, when the inner frame 12 or the front frame 14 is in an open state and the switch SW1 or the switch SW2 is in a conductive state, the integrating circuit 281 Regardless of the open period of 12 or the front frame 14, the falling period of the voltage applied to the TRG terminal of the timer IC1 is set to a certain period (about 2 ms). Then, the timer IC1 functioning as a monostable multivibrator operates normally, and the voltage at the OUT terminal of the timer IC1 is reduced from zero volts to about 10 ms after the TRG terminal voltage of the timer IC1 falls to zero volts. Raise to 9.6 volts. Then, the output terminal voltage of the NOT circuit IC3 becomes zero volts for about 10 ms. As a result, the collector terminal c and the emitter terminal e of the transistor TR1 are cut off for about 10 ms, and the current supplied from the storage battery SB1 to the photocoupler PR1 of the external output terminal plate 261 via the resistor R7a is about 10 ms. During this period, it will be stopped. Therefore, according to the pachinko machine of the third embodiment, when the opening of the inner frame 12 or the opening of the front frame 14 is detected by the frame opening detection circuit 280, from the external output terminal plate 261 for each detection. The high signal output to the hall computer 262 can be stopped for about 10 ms. The stop state of the high signal output from the external output terminal board 261 to the hall computer 262 is stored in the hall computer 262 that continues to operate for 24 hours. Therefore, the pachinko machine in which the inner frame 12 or the front frame 14 is opened can be specified by the high signal stop state stored in the hall computer 262. Further, by causing the hall computer 262 to stop the high signal output from the external output terminal plate 261 and to store the stop time of the high signal, the opening time of the identified inner frame 12 of the pachinko machine or The opening time of the front frame 14 can be detected.

  Further, according to the pachinko machine of the third embodiment, when the inner frame 12 and the front frame 14 are closed, and when about 10 ms has elapsed since the inner frame 12 or the front frame 14 was opened, A high signal is output from the light receiving element (phototransistor) on the secondary side of the photocoupler PR1 of the external output terminal plate 261 to the hall computer 262. On the other hand, as described above, when the inner frame 12 or the front frame 14 is in the open state, the high signal output from the phototransistor to the hall computer 262 is in the stop state, but the period in which the high signal is in the stop state. Is about 10 ms.

  Here, the light receiving element (phototransistor) on the secondary side of the photocoupler PR1 of the external output terminal plate 261 is connected to the hall computer 262 using a communication cable (not shown). When the signal is cut (damaged) by, the high signal output from the phototransistor to the hall computer 262 exceeds about 10 ms and is always stopped.

  Therefore, when the high signal output to the hall computer 262 from the light receiving element (phototransistor) that is the secondary side of the photocoupler PR1 of the external output terminal plate 261 is stopped for more than about 10 ms, The disconnection (breakage) of the communication cable connecting the transistor and the hall computer 262 can be detected. Therefore, in addition to being able to detect the opening of the inner frame 12 or the front frame 14 from the high signal stop state period stored in the hall computer 262, the communication cable connecting the phototransistor and the hall computer 262 is disconnected (damaged). Etc. can also be detected.

  In addition, the semiconductor components used for the open frame detection circuit 280 and the external output terminal board 261 may be destroyed by impact, static electricity, or the like. This destruction destroys the semiconductor used for the semiconductor components. Therefore, in general, an open breakdown (a breakdown in which the terminals of the semiconductor components are opened) is more likely to occur than a short breakdown (a breakdown in which the terminals of the semiconductor components are in a short circuit). When the semiconductor component is open broken, no current is supplied to the semiconductor component, so that no normal voltage is output from the semiconductor component. Then, since a normal current is not supplied to the photocoupler PR1, there is no abnormality in the communication cable connecting the light receiving element (phototransistor) on the secondary side of the photocoupler PR1 of the external output terminal plate 261 and the hall computer 262. However, the high signal output from the phototransistor to the hall computer 262 exceeds about 10 ms and is always stopped.

  Therefore, although there is no abnormality in the communication cable that connects the light receiving element (phototransistor) that is the secondary side of the photocoupler PR1 of the external output terminal plate 261 and the hall computer 262, the high output that is output from the phototransistor to the hall computer 262. When the signal is stopped after approximately 10 ms, the breakage of the frame opening detection circuit 280 or the external output terminal plate 261 can be detected. Therefore, in addition to being able to detect the opening of the inner frame 12 or the front frame 14 from the high signal stop state period stored in the hall computer 262, the frame opening detection circuit 280 or the external output terminal plate 261 is also destroyed (abnormal). Can be detected.

  Further, according to the pachinko machine of the present embodiment, the frame open detection circuit 280 is provided with the storage battery SB1, so that power is supplied to the pachinko machine and a DC voltage of 12 volts is supplied from the DC power supply DC1. In addition to the case where, for example, even when the game hall is closed and the power supply to the pachinko machine is shut off and no DC voltage of 12 volts is supplied from the DC power supply DC1, the frame is opened. The detection circuit 280 can detect the opening of the inner frame 12 and the opening of the front frame 14.

  In the present embodiment, when the inner frame 12 or the front frame 14 is opened and the switch SW1 or the switch SW2 is turned on, a high signal output from the external output terminal plate 261 to the hall computer 262 is about 10 ms. However, this is not a limitation. That is, when the connection of each component of the frame opening detection circuit 280 is changed, the inner frame 12 or the front frame 14 is opened, and the opened inner frame 12 or the front frame 14 is closed, the photocoupler PR1 is connected. The supplied current may be stopped for about 10 ms, and the high signal output from the external output terminal board 261 to the hall computer 262 may be stopped for about 10 ms.

  However, in the frame open detection circuit 280 of this embodiment, when the inner frame 12 or the front frame 14 is opened and the switch SW1 or the switch SW2 is turned on, it is output from the external output terminal plate 261 to the hall computer 262. Since the high signal is stopped for about 10 ms, the opening of the inner frame 12 or the front frame 14 can be detected quickly. Therefore, the opening of the inner frame 12 or the front frame 14 can be detected before the inner frame 12 or the front frame 14 is opened and an illegal act is performed on the main controller 110 or the game board 13. Therefore, it is possible to prevent an abnormal operation due to an illegal act that occurs when power is supplied to the pachinko machine.

  Further, when the inner frame 12 and the front frame 14 are closed, and when about 10 ms has elapsed since the inner frame 12 or the front frame 14 was opened, the collector terminal c of the transistor TR1 and the emitter of the transistor TR1. The terminal e is electrically connected to the terminal e, and a current is supplied to the light emitting diode on the primary side of the photocoupler PR1 through the resistor R7a. As a result, a high signal is continuously output from the external output terminal board 261 to the hall computer 262. Here, when the inner frame 12 and the front frame 14 are closed, and when about 10 ms has elapsed since the inner frame 12 or the front frame 14 was opened, the frame open detection circuit 280 and the external output terminal plate 261 are used. When it is desired to suppress the power consumed by the resistor R3a, the resistor R4, the internal resistor R5 and the internal resistor R6, the resistance value of the resistor R7a should be larger than 10 kΩ and the resistance value of the resistor R7a should be larger than 1 kΩ.

  Further, when it is desired to separately store in the hall computer 262 which of the inner frame 12 and the front frame 14 is opened, the following configuration may be used. First, the frame opening detection circuit 280 and the external output terminal plate 261 used in this embodiment are newly provided one by one, the switch SW2 connected in parallel to the switch SW1 is disconnected, and the disconnected switch SW2 is newly installed. It may be connected to the provided frame opening detection circuit 280. Specifically, one end of the disconnected switch SW2 is connected to the cathode terminal of the diode D2 of the newly provided frame opening detection circuit 280, the cathode terminal of the Zener diode D3, and the TRG terminal of the timer IC1, and the disconnected switch SW2 is disconnected. May be connected to one end of the capacitor CD7 of the newly provided frame opening detection circuit 280. Thus, the frame opening detection circuit 280 and the external output terminal plate 261 are newly provided, and only the switch SW2 is connected to the newly provided frame opening detection circuit 280, and the existing frame opening detection circuit 280 includes a switch By connecting only SW1, if the switch SW1 is conductive (the inner frame 12 is opened), the high signal output from the existing external output terminal board 261 to the hall computer 262 is stopped, and the switch SW2 is turned off. When there is continuity (opening of the front frame 14), the high signal output from the newly provided external output terminal board 261 to the hall computer 262 can be stopped. Here, the hall computer 262 includes an input terminal for a high signal output from the existing external output terminal board 261 (for detecting conduction of the switch SW1 (for detecting opening of the inner frame 12)), and a newly provided external output terminal. A high signal input terminal output from the plate 261 (for detecting the conduction of the switch SW2 (for detecting the opening of the front frame 14)) is set separately. With this configuration, the conduction of the switch SW1 (opening of the inner frame 12) and the conduction of the switch SW2 (opening of the front frame 14) can be distinguished and stored in the hall computer 262. Therefore, depending on the stop state of the high signal stored in the hall computer 262, the switch SW1 is conductive (the inner frame 12 is opened), the switch SW2 is conductive (the front frame 14 is opened), or both It is possible to accurately detect whether or not there has been.

  Further, when power is supplied to the pachinko machine, the hall computer 262 separately stores which of the inner frame 12 and the front frame 14 is opened, and which of the inner frame 12 and the front frame 14 is stored. If you want to be notified by a pachinko machine when it opens, the following configuration may be used. First, the frame opening detection circuit 280 and the external output terminal plate 261 used in this embodiment are newly provided one by one, the switch SW2 connected in parallel to the switch SW1 is disconnected, and the disconnected switch SW2 is newly installed. Connected to the provided frame opening detection circuit 280. Next, the male switches SW1b and SW2b and the female switches SW1a and SW2a are newly provided for the switch SW1 and the switch SW2, respectively. Then, when the inner frame 12 or the front frame 14 is opened using the newly provided male switches SW1b and SW2b and the female switches SW1a and SW2a and the switch SW1 or the switch SW2 is turned on, a signal is sent to the MPU 201. What is necessary is just to comprise so that it may be input.

  Specifically, one end of the disconnected switch SW2 is connected to the cathode terminal of the diode D2 of the newly provided frame opening detection circuit 280, the cathode terminal of the Zener diode D3, and the TRG terminal of the timer IC1, and the disconnected switch SW2 is disconnected. May be connected to one end of the capacitor CD7 of the newly provided frame opening detection circuit 280. Thus, the frame opening detection circuit 280 and the external output terminal plate 261 are newly provided, and only the switch SW2 is connected to the newly provided frame opening detection circuit 280, and the existing frame opening detection circuit 280 includes a switch By connecting only SW1, if the switch SW1 is conductive (the inner frame 12 is opened), the high signal output from the existing external output terminal board 261 to the hall computer 262 is stopped, and the switch SW2 is turned off. When there is continuity (opening of the front frame 14), the high signal output from the newly provided external output terminal board 261 to the hall computer 262 can be stopped.

  Next, male switch SW1b and male switch SW2b are further provided for switch SW1 and switch SW2, respectively, and male switch SW1b and male switch SW2b disposed in switch SW1 and switch SW2 are respectively provided in two. To do. Correspondingly, the female switch SW1a and the female switch SW2a are further provided in the switch SW1 and the switch SW2, respectively, and the female switch SW1a and the female switch SW2a provided in the switch SW1 and the switch SW2 are respectively 2 One by one. As a result, one new combination of the male switch SW1b and the female switch SW1a is added to the switch SW1. Similarly to the switch SW1, one combination of the male switch SW2b and the female switch SW2a is added to the switch SW2. Then, one end of a pair of terminal pairs SW1c built in the newly added female switch SW1a is connected to the DC power source DC1 of the existing frame opening detection circuit 280, and built into the newly added female switch SW1a. The other end of the pair of terminal pairs SW1c thus connected is connected to the input / output port 205 of the MPU 201 via a voltage dividing circuit constituted by resistors. Similarly, one end of a pair of terminal pairs SW2c incorporated in the newly added female switch SW2a is connected to the DC power source DC1 of the newly provided frame opening detection circuit 280, and the newly added female type The other end of the pair of terminals SW2c built in the switch SW2a is connected to the input / output port 205 of the MPU 201 via a voltage dividing circuit constituted by a resistor and to a port different from the other end of the terminal pair SW1c. Further, the MPU 201 is supplied from the DC power source DC1 by a voltage of 5 volts (the voltage dividing circuit detects the opening of the inner frame 12 when the inner frame 12 or the front frame 14 is opened and the switch SW1 or the switch SW2 is turned on. 12 volt voltage is reduced to 5 volts) or 5 volt voltage to detect the opening of the inner frame 14 (12 volt voltage supplied from the DC power supply DC1 is lowered to 5 volt by the voltage dividing circuit) ) Is input to the input / output port 205, a command indicating that the opening of the inner frame 12 or the front frame 14 is detected is transmitted to the audio lamp control device 113 and the display control device 114. At this time, the command transmitted from the MPU 201 includes a command when the opening of the inner frame 12 is detected (hereinafter referred to as “inner frame command”) and a command when the front frame 14 is released (hereinafter referred to as “ It is called “front frame command”). Then, the voice lamp control device 113 that has received each command performs notification in a different manner depending on whether the inner frame command is received or the front frame command is received. For example, a different warning sound is emitted from the audio output device 226 or the lighting mode of the lamp display device 227 is changed. In addition, the display control device 114 that has received each command displays different modes depending on whether the inner frame command is received or the front frame command is received. For example, when the display control device 114 receives an inner frame command, the third symbol display device 81 displays “the inner frame is open” or the display control device 114 receives a front frame command. The third symbol display device 81 may be configured to display “front frame is open”.

  In this way, a new combination of the male switch SW1b and the female switch SW1a is added to the switch SW1, and a new combination of the male switch SW2b and the female switch SW2a is added to the switch SW2 as well as the switch SW1. When one switch is used and the switch SW1 is turned on (when the inner frame 12 is opened), the MPU 201 sends an inner frame command to the audio lamp control device 113 and the display control device 114. Configure to send. Further, when the switch SW2 is turned on (when the front frame 14 is opened), the MPU 201 is configured to transmit a front frame command to the audio lamp control device 113 and the display control device 114. By configuring in this way, notification of a different aspect between when the inner frame 12 is opened and when the front frame 14 is opened is performed using the audio lamp control device 113 and the display control device 114. Can do. This makes it possible to accurately determine whether the switch SW1 is conductive (the inner frame 12 is opened), the switch SW2 is conductive (the front frame 14 is opened), or both, using a pachinko machine. Can be detected.

  Further, a frame opening detection circuit 280 and an external output terminal plate 261 are newly provided, and only the switch SW2 is connected to the newly provided frame opening detection circuit 280, and the switch SW1 is connected to the existing frame opening detection circuit 280. When the switch SW1 is connected (the inner frame 12 is opened) by connecting only the switch SW2, the high signal output from the existing external output terminal board 261 to the hall computer 262 is stopped, and the switch SW2 is connected. When (the front frame 14 is opened), the high signal output from the newly provided external output terminal board 261 to the hall computer 262 can be stopped. Therefore, depending on the stop state of the high signal stored in the hall computer 262, the switch SW1 is conductive (the inner frame 12 is opened), the switch SW2 is conductive (the front frame 14 is opened), or both It is possible to accurately detect whether or not there has been.

  In the present embodiment, the high signal output from the external output terminal board 261 is output to the hall computer 262 having a different installation location from the pachinko machine, but is not limited thereto. A dedicated storage device having the function of the hall computer 262 may be provided for each pachinko machine, and the dedicated storage device may be provided on the back side of each pachinko machine in which the main controller 110 and the like are provided. In this case, more preferably, a dedicated storage device such as the main control device 110, the payout control device 111, and the launch control device 112 is stored in the substrate box, and the box base and the box cover provided in the substrate box are stored. Are connected by a sealing unit (not shown) so that they cannot be opened (connection by caulking structure). Then, a seal seal (not shown) is pasted on the connecting portion between the box base and the box cover over the box cover and the box base.

  In the first embodiment, the wiring from the connection point where the plus terminal of the storage battery SB1 and the RES terminal of the timer IC1 are connected to the resistor R7 is disconnected, and a logic negation circuit (NOT circuit) is provided in the frame opening detection circuit 260. And the output terminal of the NOT circuit is connected to one end of the resistor R7, and the input terminal of the NOT circuit is connected to a connection point where the plus terminal of the storage battery SB1 and the RES terminal of the timer IC1 are connected, and supplied to the resistor R7. The current that is generated may be reversed. In this case, when the inner frame 12 and the front frame 14 are closed, no pulse signal is output to the hall computer 262, while when the inner frame 12 or the front frame 14 is opened, the hall computer 262 is opened. A pulse signal having a pulse width of 10 ms is output.

  Similarly, in the second embodiment, the wiring from the connection point where the plus terminal of the storage battery SB1 and one end of the resistor R9 are connected to the resistor R7 is disconnected, and a logic negation circuit (NOT circuit) is provided to the frame opening detection circuit 270. The output terminal of the NOT circuit is connected to one end of the resistor R7, the input terminal of the NOT circuit is connected to a connection point where the plus terminal of the storage battery SB1 and one end of the resistor R9 are connected, and the resistor R7 is supplied. The current that is generated may be reversed. In this case, no pulse signal is output to the hall computer 262 when the inner frame 12 and the front frame 14 are closed, while a high signal is output when the inner frame 12 or the front frame 14 is opened. Is done. Further, in the third embodiment, the wiring from the connection point where the plus terminal of the storage battery SB1 and the RES terminal of the timer IC1 are connected to the resistor R7a is disconnected, and a logic negation circuit (NOT circuit) is provided to the frame opening detection circuit 280. The output terminal of the NOT circuit is connected to one end of the resistor R7a, the input terminal of the NOT circuit is connected to a connection point where the plus terminal of the storage battery SB1 and the RES terminal of the timer IC1 are connected, and the resistor R7a is connected. The supplied current may be reversed. In this case, when the inner frame 12 and the front frame 14 are closed, no pulse signal is output to the hall computer 262, while when the inner frame 12 or the front frame 14 is opened, the hall computer 262 is opened. A pulse signal having a pulse width of 10 ms is output.

  In the first to third embodiments, the external output terminal plate 261 and the hall computer 262 are connected, the signal output from the external output terminal plate 261 to the hall computer 262 is stopped, and the hall computer 262 is connected. The opening of the inner frame 12 or the front frame 14 is stored, but the present invention is not limited to this. For example, a pachinko machine is provided with an EEPROM (Electronically Erasable and Programmable Read Only Memory) and a backup RAM. Then, an external output terminal plate 261 is connected to the EEPROM or backup RAM. With this configuration, the opening of the inner frame 12 or the front frame 14 can be stored in the EEPROM or the backup RAM. When the power of the pachinko machine is turned on, the MPU 201 confirms the storage of the EEPROM and the backup RAM. Thereby, opening of the inner frame 12 or the front frame 14 can be detected using a pachinko machine. That is, the role of the hall computer 262 can be assigned to the EEPROM or the backup RAM (the role of the “specific device” described in the claims can be assigned to the EEPROM or the backup RAM). Note that the RAM 203 may be used as the backup RAM.

  The present invention has been described above based on one embodiment. However, the present invention is not limited to the above embodiment, and various modifications and improvements can be easily made without departing from the spirit of the present invention. Can be inferred.

  For example, in each of the above embodiments, each command is transmitted from the main control device 110 to the sound lamp control device 113, and the sound lamp control device 113 issues a display instruction to the display control device 114. However, the command may be directly transmitted from the main control device 110 to the display control device 114. Further, an audio lamp control device may be connected to the display control device, and a command instructing the output of each sound and the lighting of the lamp may be transmitted from the display control device to the audio lamp control device. Furthermore, the sound lamp control device and the display control device may be configured as one control device.

  Moreover, in the said embodiment, although it was comprised so that the winning to the 1st entrance 64 and the passage of the 2nd entrance 67 might be held up to 4 times, respectively, the maximum number of times of holding was 4 times. It is not limited and may be set to 3 times or less, or 5 times or more (for example, 8 times). In addition, the number of times the variable display is held based on the winning at the first entrance 64 is different for the part of the third symbol display device 81 by a number or by dividing the number of four divided areas by the number of times of the hold. It may be displayed in a mode (for example, color or lighting pattern), and a light emitting member such as a lamp is provided separately from the first symbol display device 37, and the number of holding times is notified by the light emitting member. You may do it.

  Further, as shown in the above embodiment, the variable display, which is a kind of dynamic display, is not limited to the one that scrolls the symbol as identification information in the vertical direction on the display screen of the third symbol display device 81, It may be performed by moving and displaying symbols along a predetermined route such as a horizontal direction or an L shape. In addition, the dynamic display of the identification information is not limited to the display of variation of the symbol. For example, one or a plurality of characters may be displayed in various manners together with the symbol or displayed in a variety of manners separately from the symbol. The effect display etc. which are displayed are also included. In this case, one or more characters are used as the third symbol.

  You may implement this invention in the pachinko machine etc. of a type different from the said embodiment. For example, the present invention may be applied to a so-called second type pachinko gaming machine having a winning device having a special area such as a V zone. Further, in addition to the pachinko machine, the game machine may be implemented as another game machine such as an alepacchi or a sparrow ball.

  You may implement this invention in the pachinko machine etc. of a type different from the said embodiment. For example, once a big hit, a pachinko machine that raises the expected value of the big hit until a big hit state occurs (for example, two times or three times) including that (for example, a two-time right item, a three-time right item) May also be implemented. Further, after the jackpot symbol is displayed, it may be implemented as a pachinko machine that generates a special game that gives a player a predetermined game value on the condition that a ball is won in a predetermined area. Further, the present invention may be implemented in a pachinko machine that has a special area such as a V-zone and has a special gaming state as a necessary condition for winning a ball in the special area. Further, in addition to the pachinko machine, the game machine may be implemented as various game machines such as an alepatchi, a sparrow ball, a slot machine, a game machine in which a so-called pachinko machine and a slot machine are integrated.

  In the slot machine, for example, a symbol is changed by operating a control lever in a state where a symbol effective line is determined by inserting coins, and a symbol is stopped and confirmed by operating a stop button. Is. Accordingly, the basic concept of the slot machine is that it is provided with a display device for confirming and displaying the identification information after variably displaying the identification information string composed of a plurality of identification information, and resulting from the operation of the starting operation means (for example, the operation lever) The variation display of the identification information is started, and the variation display of the identification information is stopped and fixedly displayed due to the operation of the operation means for stop (for example, the stop button) or when a predetermined time elapses. It is a slot machine that generates a special game that gives a player a predetermined game value on the condition that the combination of identification information at the time is a specific condition. In this case, the game medium is typically a coin, medal, etc. Take as an example.

  In addition, as a specific example of a gaming machine in which a pachinko machine and a slot machine are fused, a display device is provided that displays a symbol after a symbol string composed of a plurality of symbols is variably displayed, and has a handle for launching a ball. What is not. In this case, after throwing a predetermined amount of spheres based on a predetermined operation (button operation), for example, the change of the symbol is started due to the operation of the operation lever, for example, due to the operation of the stop button, or With the passage of time, the variation of the symbol is stopped, and a special game that gives a predetermined game value to the player is generated on the condition that the determined symbol at the time of stoppage is a so-called jackpot symbol. In this case, a large amount of balls are paid out to the lower tray.

  Hereinafter, in addition to the gaming machine of the present invention, concepts of various inventions included in the various embodiments described above are shown. A gaming machine comprising: a main body; a door body that opens and closes a front surface of the main body; and a control unit that is provided in a space formed by the door body and the main body and controls a game. A door opening detecting means for detecting the opening of the body, a signal output means for outputting a signal to a specific device when the door opening detecting means does not detect the opening of the door, and the door opening by the door opening detecting means. And stopping means for stopping signal output to the specific device by the signal output means when the release of the game machine is detected, the signal output means being turned off when the gaming machine is powered off. Even if it is, it is comprised so that a signal can be output to the said specific apparatus, and the said stop means is a case where the power supply of the said game machine is turned off and the said control means has stopped. , The signal output Gaming machine 1, characterized in that it is stopped configured to be able to signal output to the particular device by means.

  According to the gaming machine 1, when the opening of the door body is not detected by the door opening detection means (when the closing of the door body is detected), the signal output means outputs a signal to the specific device. On the other hand, when the door opening detection means detects the opening of the door body, the signal output means stops the signal output to the specific device by the stop means. In this way, when the door is opened, the signal output from the signal output means to the specific device is stopped, so that the gaming machine with the door opened can be determined by the specific device. it can. Here, even when the power of the gaming machine is turned off and the control means is stopped, the signal output means can output a signal to the specific device. In addition, even when the power of the gaming machine is turned off and the control means is stopped, the stop means can stop the signal output to the specific device by the signal output means. Therefore, for example, even if the door body is opened by an unauthorized act by someone after the store is closed with all the gaming machines turned off, the gaming machine with the door body opened can be identified by the specific device.

  As described above, when the door opening detection unit does not detect the opening of the door body, the signal output unit outputs a signal to the specific device. Here, when the communication medium between the signal output means and the specific device is damaged by an unauthorized person, the communication between the signal output means and the specific device is interrupted, so the door opening detection means detects the opening of the door body. Even if it is not made, that is, even if the door is in a closed state, signal output to the specific device remains stopped. Therefore, when the signal output means stops outputting the signal to the specific device when the door is in the closed state, it is possible to detect the breakage of the communication medium between the signal output means and the specific device. .

  In addition, even if there is no abnormality in the communication medium between the signal output means and the specific device, if the signal output means fails and the signal output to the specific device is in a stopped state, the door body Even in the closed state, the signal output to the specific device remains stopped. Similarly, when a failure occurs in the stopping means and the signal output to the specific device by the signal output means is always stopped, the signal output to the specific device even if the door body is in the closed state Will remain stopped. Therefore, if there is no abnormality in the communication medium between the signal output means and the specific device, but the signal output means stops the signal output to the specific device when the door is closed, the signal output means Alternatively, it is possible to detect the failure of either one of the stop means or both.

  In addition, the inside of the space formed by the door body and the main body indicates the back surface or the back surface side (including the back surface side of the main body) of the door body that cannot be touched by a hand when the door body is closed. The detection result output from the output means provided for each of the plurality of gaming machines may be received by one specific device, or a specific device is provided for each gaming machine, and the specific device is distributed to each gaming machine. May be installed. When a specific device is installed in each gaming machine, the box base and the box cover covering the opening of the box base are connected to each other, and the specific device is specified in the space formed by the box cover and the box base. Store the device. Then, the box cover and the box base are connected by the sealing unit so that they cannot be opened. Further, a seal seal is attached to the connecting portion between the box cover and the box base over the box cover and the box base. In addition, a specific device may be disposed on the back surface or the back surface side of the door body.

  In a gaming machine comprising a main body, a door body for opening and closing the front surface of the main body, and a control means for controlling a game provided in a space formed by the door body and the main body, a signal is sent to a specific device. A signal output means for outputting; a door opening detection means for detecting the opening of the door body relative to the main body; and the specific device by the signal output means when the door opening detection means detects the opening of the door body. Stop means for stopping signal output to the stop, stop period limit means for limiting a single stop period of signal output by the stop means within a predetermined period, stop period limit means, stop means, and signal output means A gaming machine (2), comprising: an off-operation means that operates when the power of the gaming machine is turned off and the control means is stopped.

  According to the gaming machine 2, when the door opening detection means detects the opening of the door body, the signal output means stops the signal output to the specific device by the stop means. And the one stop period of the signal output by the stop means is kept within a predetermined period by the stop period limiting means. In this way, when the door is opened, the signal output from the signal output means to the specific device is stopped within a predetermined time, so that the gaming machine with the door opened is specified by the specific device. Can be determined. Here, the stop means, the signal output means, and the stop period limiting means operate by receiving power supply from the off-state operation means while the gaming machine is powered off, so that the door is opened even when the gaming machine is powered off. When the opening of the door body is detected by the detection means, the stop means can stop the signal output by the signal output means to the specific device within a predetermined time. Therefore, for example, even if the door body is opened by an unauthorized act by someone after the store is closed with all the gaming machines turned off, the gaming machine with the door body opened can be identified by the specific device.

  Further, as described above, when the door opening detection means detects the opening of the door body, the stop period limiting means keeps one stop period of signal output by the stop means within a predetermined period. That is, when the door body is opened and the door opening detection means detects the opening of the door body, the signal output from the signal output means to the specific device is stopped only within a predetermined period by the stop period limiting means. It becomes. Here, if the communication medium between the signal output means and the specific device is damaged by an unauthorized person, the communication between the signal output means and the specific device is interrupted, so the signal output to the specific device exceeds the predetermined period. But it remains stopped. Therefore, when the signal output to the specific device by the signal output unit is stopped after a predetermined period, it is possible to detect the breakage of the communication medium between the signal output unit and the specific device.

  In addition, even if there is no abnormality in the communication medium between the signal output means and the specific device, if the signal output means has failed and the signal output to the specific device is in a stopped state, of course, The signal output to the specific device remains stopped even after a predetermined period. Similarly, when a failure occurs in the stop period limiting means or the stop means and the signal output from the signal output means is always stopped, the signal output to the specific device naturally exceeds the predetermined period. But it remains stopped. Therefore, when there is no abnormality in the communication medium between the signal output means and the specific device, but the signal output to the specific device by the signal output means has stopped for a predetermined time, the signal output means, the stop means or the stop It is possible to detect any failure of the period limiting means or all of them.

  In a gaming machine comprising a main body, a door body for opening and closing the front surface of the main body, and a control means for controlling a game provided in a space formed by the door body and the main body, a signal is sent to a specific device. A signal output means for outputting; a door opening detection means for detecting the opening of the door body relative to the main body; and the specific device by the signal output means when the door opening detection means detects the opening of the door body. Stop means for stopping signal output to the stop, stop period restriction means for restricting one stop period of the signal output by the stop means within a predetermined period, stop period restriction means, stop means, and signal output means, An off-operation means for operating the game machine when the power is turned off and the control means is stopped, and the stop means restricts the stop of the signal output by the stop period restriction means Based on the signal output means to stop the signal output to the specific device, the stop period limit means, when the door opening detection means detects the opening of the door body, the stop means to the predetermined means The gaming machine 3 is characterized in that the signal output is stopped during the period.

  According to the gaming machine 3, when the opening of the door body is detected by the door opening detecting means, the signal output to the specific device by the signal output means is stopped by the stopping means. And the one stop period of the signal output by the stop means is kept within a predetermined period by the stop period limiting means. In this way, when the door is opened, the signal output from the signal output means to the specific device is stopped within a predetermined time, so that the gaming machine with the door opened is specified by the specific device. Can be determined. Here, the stop means, the signal output means, and the stop period limiting means operate by receiving power supply from the off-state operation means while the gaming machine is powered off, so that the door is opened even when the gaming machine is powered off. When the opening of the door is detected by the detecting means, the stopping means can stop the signal output by the signal output means to the specific device within a predetermined time. Therefore, for example, even if the door body is opened by an unauthorized act by someone after the store is closed with all the gaming machines turned off, the gaming machine with the door body opened can be identified by the specific device.

  In addition, when the door opening detection unit detects the opening of the door body, the stop period limiting unit limits the stop of the signal output to the stop unit during a predetermined period. Then, the stop means stops the signal output to the specific device by the signal output means for a predetermined period based on the stop restriction. That is, when the door opening detection means detects the opening of the door body, the stop period restriction means restricts the stop of signal output to the stop means during the predetermined period, while the door opening detection means When the opening of the body is not detected or after a predetermined period has elapsed, the stop of the signal output is not restricted for the stop means. Thereby, the stop of the signal output from the signal output means to the specific device can be reliably stopped within a predetermined period for each opening of the door body. Here, if the communication medium between the signal output means and the specific device is damaged by an unauthorized person, the communication between the signal output means and the specific device is interrupted, so the signal output to the specific device exceeds the predetermined period. But it remains stopped. Therefore, when the signal output to the specific device by the signal output unit is stopped after a predetermined period, it is possible to reliably detect the breakage of the communication medium between the signal output unit and the specific device.

  In addition, even if there is no abnormality in the communication medium between the signal output means and the specific device, if the signal output means has failed and the signal output to the specific device is in a stopped state, of course, The signal output to the specific device remains stopped even after a predetermined period. Similarly, when a failure occurs in the stop period limiting means or the stop means and the signal output from the signal output means is always stopped, the signal output to the specific device naturally exceeds the predetermined period. Will also stop. Therefore, when there is no abnormality in the communication medium between the signal output means and the specific device, but the signal output to the specific device by the signal output means has stopped for a predetermined time, the signal output means, the stop means or the stop It is possible to detect any failure of the period limiting means or all of them.

  In a gaming machine comprising a main body, a door body for opening and closing the front surface of the main body, and a control means for controlling a game provided in a space formed by the door body and the main body, a signal is sent to a specific device. A signal output means for outputting; a door opening detection means for detecting the opening of the door body relative to the main body; and the specific device by the signal output means when the door opening detection means detects the opening of the door body. Stop means for stopping signal output to the stop, stop period restriction means for restricting one stop period of the signal output by the stop means within a predetermined period, stop period restriction means, stop means, and signal output means, An off-operation means for operating the game machine when the power is turned off and the control means is stopped, and the stop means restricts the stop of the signal output by the stop period restriction means The signal output means stops signal output to the specific device, and the stop period restriction means releases the restriction on stopping the signal output to the stop means when the predetermined period has elapsed. A gaming machine 4 characterized.

  According to the gaming machine 4, when the opening of the door body is detected by the door opening detection means, the signal output means stops the signal output to the specific device by the stop means. And the one stop period of the signal output by the stop means is kept within a predetermined period by the stop period limiting means. In this way, when the door is opened, the signal output from the signal output means to the specific device is stopped within a predetermined time, so that the gaming machine with the door opened is specified by the specific device. Can be determined. Here, the stop means, the signal output means, and the stop period limiting means operate by receiving power supply from the off-state operation means while the gaming machine is powered off, so that the door is opened even when the gaming machine is powered off. When the opening of the door is detected by the detecting means, the stopping means can stop the signal output by the signal output means to the specific device within a predetermined time. Therefore, for example, even if the door body is opened by an unauthorized act by someone after the store is closed with all the gaming machines turned off, the gaming machine with the door body opened can be identified by the specific device.

  Further, when the door opening detection means detects the opening of the door body, the stop period limiting means limits the signal output to the stop means within a predetermined period. Then, based on this stop restriction, the stop means stops the signal output to the specific device by the signal output means within a predetermined period. Then, when the predetermined period elapses, the stop period restriction unit releases the stop restriction on signal output to the stop unit. Then, a signal is output again from the signal output means to the specific device. That is, when the door body is opened and the door opening detection means detects the opening of the door body, the signal output from the signal output means to the specific device is reliably transmitted for each opening of the door body. , It can be stopped only within a predetermined period. Here, if the communication medium between the signal output means and the specific device is damaged by an unauthorized person, the communication between the signal output means and the specific device is interrupted, so the signal output to the specific device exceeds the predetermined period. But it remains stopped. Therefore, when the signal output to the specific device by the signal output unit is stopped after a predetermined period, it is possible to reliably detect the breakage of the communication medium between the signal output unit and the specific device.

  In addition, even if there is no abnormality in the communication medium between the signal output means and the specific device, if the signal output means has failed and the signal output to the specific device is in a stopped state, of course, The signal output to the specific device remains stopped even after a predetermined period. Similarly, when a failure occurs in the stop period limiting means or the stop means and the signal output from the signal output means is always stopped, the signal output to the specific device naturally exceeds the predetermined period. Will also stop. Therefore, when there is no abnormality in the communication medium between the signal output means and the specific device, but the signal output to the specific device by the signal output means has stopped for a predetermined time, the signal output means, the stop means or the stop It is possible to detect any failure of the period limiting means or all of them.

  In the gaming machine 3 or 4, the stop period limiting means is configured using a monostable multivibrator that limits a single stop period of the signal output by the stop means within a predetermined period by an output signal, An input signal input to the monostable multivibrator is connected to the monostable multivibrator when the door opening detection means detects the opening of the door body, regardless of the door opening period. Input period adjusting means for adjusting to a shorter period, the off-time operating means, in addition to the stop period limiting means, stop means and signal output means, the control means when the power of the gaming machine is turned off The gaming machine 5 is characterized in that the input period adjusting means is also operated when the game is stopped.

  According to the gaming machine 5, the input signal input to the stop period limiting means using the monostable multivibrator is transmitted once by the input means adjusting means regardless of the door opening period. It is adjusted to be shorter than the predetermined period that is the stop period. Here, if the input period of the input signal is not shorter than the output period of the output signal, the monostable multivibrator does not operate normally and continues to output the output signal. For this reason, when the monostable multivibrator is used as the stop period limiting unit, the output period of the output signal, that is, the monostable multivibrator limits the stop of the signal output to the stop unit by the output signal. The input period of the input signal input to the monostable multivibrator, that is, the door opening period must be shorter than the period. However, it is totally unpredictable how long the door will be open. Therefore, the setting of the predetermined period has a sufficient margin so that the opening period of the door body is always shorter than the predetermined period in which the monostable multivibrator limits the stop of the signal output to the stopping means by the output signal. Must be set to a period. In this way, even if the predetermined period is set to a period with a sufficient margin, if the door opening period exceeds the predetermined period, the door is subsequently closed and the door opening is detected. Even if the opening of the door is no longer detected by the means, the monostable multivibrator continues to output the output signal, and the stop means remains restricted from stopping the signal output. As a result, even if the signal output stop exceeds a predetermined period, no signal is output from the signal output means to the specific device, so these signal output means, stop means, and monostable multivibrator are not abnormal. Any or all of the failures will be misidentified. Therefore, a special circuit configuration is necessary to use a monostable multivibrator as the stop period limiting means and to operate the monostable multivibrator normally. However, according to the gaming machine 5, the input signal input to the monostable multivibrator can be adjusted to be shorter than the predetermined period by the input period adjusting means regardless of the door opening period. Therefore, since the monostable multivibrator can be operated normally regardless of the opening period of the door body, one stop period of signal output by the stop means can be kept within a predetermined period. Thus, according to the gaming machine 5, by providing the input period adjusting means, it is possible to realize the stop period limiting means using a monostable multivibrator without adopting a special circuit configuration. Note that the input period adjusting means also operates by receiving power supply from the off-state operating means while the gaming machine is powered off, as with the stop period limiting means, the stopping means, and the signal output means. Therefore, even when the gaming machine is powered off, if the door opening detection means detects the door opening, the input period adjusting means is input to the monostable multivibrator regardless of the door opening period. The input signal can be adjusted to be shorter than a predetermined period.

  In the gaming machine 5, the input period adjusting means is configured by using an integrating circuit.

  According to the gaming machine 6, since the input period adjusting means is configured by using the integration circuit, the input signal input to the monostable multivibrator is shorter than the predetermined period without using a complicated circuit or signal processing. Can be adjusted. Further, by adjusting the resistance value of the resistor used in the integration circuit and the capacitance value of the capacitor, the input period of the input signal input to the monostable multivibrator can be freely adjusted within a predetermined period.

  In the gaming machine 5 or 6, the input period adjusting means includes a constant voltage means for making a maximum voltage of an input signal inputted to the monostable multivibrator constant.

  According to the gaming machine 7, since the constant voltage means is provided, the maximum voltage of the input signal input to the monostable multivibrator is made constant, the input signal input to the monostable multivibrator is stabilized and stopped. One stop period of signal output by the means can be stably kept within a predetermined period.

  In addition, when the input period adjusting means is configured using an integration circuit, electric charge is stored in the capacitor used in the integration circuit, and the voltage due to this electric charge is superimposed on the input signal input to the monostable multivibrator. Therefore, there is a possibility that an overvoltage that can destroy the monostable multivibrator is applied to the monostable multivibrator. However, according to the gaming machine 7, since the maximum voltage of the input signal inputted to the monostable multivibrator is made constant by the constant voltage means, an overvoltage that can destroy the monostable multivibrator is applied to the monostable multivibrator. It will never be done. Therefore, destruction of the monostable multivibrator can be prevented.

  In the gaming machine 7, the constant voltage means comprises a Zener diode.

  According to the gaming machine 8, since the constant voltage means is configured by the Zener diode, it is input to the monostable multivibrator with a simple configuration and at a lower cost than a constant voltage circuit configured by a complicated circuit. The maximum voltage of the input signal can be made constant. Therefore, the input signal input to the monostable multivibrator is stabilized by using an inexpensive Zener diode having a simple configuration, and a single stop period of signal output by the stop means is stably kept within a predetermined period. Further, it is possible to prevent an overvoltage that can destroy the monostable multivibrator from being applied to the monostable multivibrator.

  In the gaming machines 1 to 8, the door body includes an inner frame that is opened and closed with respect to the main body, and a transparent plate support door that is opened and closed with respect to the inner frame. Are provided on the inner frame and the transparent plate support door, respectively, and are connected in parallel to the signal output means and the stop means, and the stop means is detected by the door opening detection means by the inner frame or the transparent plate support door. When at least one of the opening is detected, the signal output means stops the signal output to the specific device.

  According to the gaming machine 9, the door opening detection means is provided on the inner frame and the transparent plate support door, and is connected in parallel to the signal output means and the stopping means. When opening of at least one of the plate support doors is detected, signal output to the specific device by the signal output means can be stopped by the stop means. Therefore, even if one of the inner frame and the transparent plate support door constituting the door body is opened, the opening can be reported to the specific device by one set of signal output means and stop means.

  Any one of the gaming machines 1 to 9 includes an off-state operation means composed of a secondary battery that is charged while the gaming machine is powered on, and the signal output means and the stop means operate during the off-state. A gaming machine 10 that is operated by electric power supplied from the means.

  According to the gaming machine 10, since the off-operation means constituted by the secondary battery is charged while the gaming machine is powered on, simply turning on the gaming machine according to the business hours of the game hall, The operating means can be charged while off. Therefore, if the door is opened while the power of the gaming machine is turned off after the game hall is closed, the signal output means and the stop means are operated by the off-operation means to identify the opening. You can report to the device.

  In any one of the gaming machines 1 to 10, the control means includes main control means for performing main control of the game, and the signal output means is mounted on the main control means. 11.

  The gaming machine 12 according to any one of the gaming machines 1 to 10, wherein the signal output means is mounted on a board different from the control means.

  In any one of the gaming machines 1 to 12, the signal output means includes a photocoupler, and when the output of the photocoupler is stopped by the stop means, the door opening detection means opens the door body. The game machine 13 is characterized by outputting the detection of the above to the specific device.

  In any one of the gaming machines 2 to 13, the stop period limiting means, the stop means, and the signal output means (and the input period adjusting means) are configured to be operable even at a voltage lower than the operating voltage of the control means. A gaming machine 14 characterized by

  According to the gaming machine 14, the signal output means, the stop means, and the stop period restriction means (and the input period adjustment means) are configured to be operable even at a voltage lower than the operating voltage of the control means. Even if the charging amount of the operating means decreases and the output voltage of the operating means during the off state becomes lower than the operating voltage of the control means, the signal output means, the stopping means and the stop period limiting means (and the input period adjusting means) are operated. Thus, the opening of the door can be reported to the specific device. That is, it is possible to detect the opening of the door body for a long time when the gaming machine is powered off.

  In any of the gaming machines 2 to 14, the stop period limiting means, the stop means, and the signal output means (and the input period adjusting means) are configured so that the operable range voltage is wider than the operable range voltage of the control means. A gaming machine 15 characterized by

  According to the gaming machine 15, the signal output means, the stop means, and the stop period limit means (and the input period adjustment means) are configured so that the operable range voltage is wider than the operable range voltage of the control means. Therefore, when the power of the gaming machine is turned off, the signal output means, the stopping means and the stop period limiting means (and the input period adjusting means) can be operated for a long time by the off-time operating means. The door opening detection can be performed for a long time.

  The gaming machine 16 according to any one of the gaming machines 2 to 15, wherein the stop period limiting means includes a C-MOS semiconductor.

  According to the gaming machine 16, the stop period limiting means is configured to have a C-MOS semiconductor. Here, the C-MOS semiconductor generally has low power consumption during operation. Therefore, according to the gaming machine 16, it is possible to detect the opening of the door body for a long time when the power of the gaming machine is turned off by reducing the consumption of the operating means during the off state.

  The gaming machine 17 according to any one of the gaming machines 1 to 16, wherein the gaming machine is a pachinko gaming machine. Above all, the basic configuration of a pachinko gaming machine is provided with an operation handle, and a ball is launched into a predetermined game area according to the operation of the operation handle, and the ball is placed in an operation port disposed at a predetermined position in the game area. As a necessary condition for winning a prize (or passing through the operating port), the identification information dynamically displayed on the display device is confirmed and stopped after a predetermined time. In addition, when a special gaming state occurs, a variable winning device (specific winning opening) disposed at a predetermined position in the gaming area is opened in a predetermined manner so that a ball can be won, and a value corresponding to the number of winnings is obtained. Examples include those to which values (including data written on magnetic cards as well as premium balls) are given.

  A gaming machine 18 according to any one of the gaming machines 1 to 16, wherein the gaming machine is a slot machine. Above all, the basic configuration of the slot machine is “equipped with variable display means for confirming and displaying the identification information after dynamically displaying an identification information string composed of a plurality of identification information, and for operating the starting operation means (for example, an operation lever). As a result, the dynamic display of the identification information is started, and the dynamic display of the identification information is stopped due to the operation of the stop operation means (stop button) or after a predetermined time has elapsed. The game machine is provided with special game state generating means for generating a special game state advantageous to the player on the condition that the confirmed identification information is specific identification information. In this case, examples of the game media include coins and medals.

  The gaming machine 19 according to any one of the gaming machines 1 to 16, wherein the gaming machine is a combination of a pachinko gaming machine and a slot machine. Among them, the basic configuration of the merged gaming machine includes “a variable display means for confirming and displaying the identification information after dynamically displaying an identification information string composed of a plurality of identification information, and a starting operation means (for example, an operation lever). Due to the operation of the identification information, the change of the identification information is started, and the dynamic display of the identification information is stopped due to the operation of the operation means for stop (for example, the stop button) or when a predetermined time elapses. Special game state generating means for generating a special game state advantageous to the player on the condition that the fixed identification information at the time of stoppage is specific identification information, and using a ball as a game medium, and the identification information The game machine is configured such that a predetermined number of balls are required at the start of the dynamic display, and a large number of balls are paid out when the special gaming state occurs.

  A gaming machine comprising: a main body; a door body that opens and closes a front surface of the main body; and a control unit that is provided in a space formed by the door body and the main body and controls a game. A door opening detection means for detecting the opening of the body, and an output means for outputting the detection result to the specific device when the door opening detection means detects the opening of the door body, the output means, The gaming machine 20 is configured to output a detection result by the door opening detection means to the specific device when the power of the gaming machine is turned off and the control means is stopped.

  According to the gaming machine 20, even when the gaming machine is powered off and the control means is stopped, if the door opening detection is detected by the door opening detection means, the detection result is specified by the output means. Output to the device. Therefore, for example, even if the door body is opened by an unauthorized act by someone after the store is closed with all the gaming machines turned off, the gaming machine with the door body opened can be identified by the specific device.

  A gaming machine comprising: a main body; a door body that opens and closes a front surface of the main body; and a control unit that is provided in a space formed by the door body and the main body and controls a game. A door opening detecting means for detecting the opening of the body, an output means for outputting the detection result to the specific device when the door opening detecting means detects the opening of the door, and a one-time output by the output means. An output period limiting means for keeping the output period within a predetermined period, and an off-time operation means for operating the output period limiting means and the output means while the gaming machine is powered off. Machine 21.

  According to the gaming machine 21, when the opening of the door is detected by the door opening detection means, the detection result is output to the specific device by the output means. Since the output means operates by receiving power supply from the off-operation means while the gaming machine is turned off, the door opening detection means detects the opening of the door body even when the gaming machine is powered off. The detection result can be output to a specific device. Therefore, for example, even if the door body is opened by an unauthorized act by someone after the store is closed with all the gaming machines turned off, the gaming machine with the door body opened can be identified by the specific device.

  Moreover, one output period by the output means is kept within a predetermined period by the output period limiting means. Similarly to the output means, the output period limiting means operates by receiving power supply from the off-operation means while the gaming machine is turned off, so that the operation period of the output means by one opening of the door body is within a predetermined period. In other words, it is possible to suppress the consumption of the off-operation means during the power-off of the gaming machine. Therefore, the frequency | count of operation | movement of an output means can be increased and the frequency | count of detection of opening of a door body can be increased.

  A gaming machine comprising: a main body; a door body that opens and closes a front surface of the main body; and a control unit that is provided in a space formed by the door body and the main body and controls a game. A door opening detecting means for detecting the opening of the body, an output means for outputting the detection result to the specific device when the door opening detecting means detects the opening of the door, and a one-time output by the output means. An output period limiting unit that keeps the output period within a predetermined period; and an off-period operation unit that operates the output period limiting unit and the output unit while the gaming machine is powered off. A detection result is output to the specific device based on an output from the period limiting unit, and the output period limiting unit is configured to output the detection result during the predetermined period when the door opening detection unit detects the opening of the door body. output Gaming machine 22 and performs output to a stage.

  According to the gaming machine 22, when the door opening detection means detects the opening of the door body, the detection result is output to the specific device by the output means. Since the output means operates by receiving power supply from the off-operation means while the gaming machine is turned off, the door opening detection means detects the opening of the door body even when the gaming machine is powered off. The detection result can be output to a specific device. Therefore, for example, even if the door body is opened by an unauthorized act by someone after the store is closed with all the gaming machines turned off, the gaming machine with the door body opened can be identified by the specific device.

  Moreover, one output period by the output means is kept within a predetermined period by the output period limiting means. Similarly to the output means, the output period limiting means operates by receiving power supply from the off-operation means while the gaming machine is turned off, so that the operation period of the output means by one opening of the door body is within a predetermined period. In other words, it is possible to suppress the consumption of the off-operation means during the power-off of the gaming machine. Therefore, the frequency | count of operation | movement of an output means can be increased and the frequency | count of detection of opening of a door body can be increased.

  Further, the output means for outputting the detection result to the specific device based on the output from the output period restriction means is output by the output period restriction means during a predetermined period when the door opening detection is detected by the door opening detection means. Output is done. Therefore, the output operation to the output means by the output period limiting means can be stopped within a predetermined period for each opening of the door body. Accordingly, it is possible to suppress consumption of the off-operation means while the power of the gaming machine is turned off, and to increase the number of times that the output means can be operated, thereby increasing the number of times that the door body can be detected.

10 Pachinko machines (game machines)
11 Outer frame (main body)
12 Inner frame (part of door)
14 Front frame (transparent plate support door, part of door)
110 Main control device (part of control means, main control means)
260, 270, 280 Frame opening detection circuit (part of signal output means)
261 External output terminal board (part of signal output means)
IC1 timer (part of stopping means)
PR1 Photocoupler (part of signal output means)
SB1 battery (operating means while off)
SW1, SW2 switch (door open detection means)
TR1 transistor (part of stopping means)

  The present invention relates to a gaming machine represented by a pachinko machine, a spinning machine (for example, a slot machine), or a spinning machine using a game ball.

In a pachinko machine, when a ball that has been driven into the game area enters the symbol operating port, a lottery is performed at the timing of the entry. Further, in a spinning-type game machine using a slot machine or a game ball, when a start lever is operated, a lottery is performed at the operation timing. A result of the lottery, comes to the person have enough For example, a capable state payout of prize balls and coins. The control for determining the lottery and or those are performed by the main controller, the main controller is liable to be subject to fraud.

Specific fraud, for example, the main control unit, or replaced by illegal that those have enough occurs frequently, or connect the invalid substrate (e.g., "hanging board") to the main controller, an equivalent or there is illegal to those to be generated. Also, in the case of pachinko machines, for example, illegally bent nails which are driven on the game board, there is also misconduct to facilitate the ball entrance spheres to winning hole and patterns actuation port.
For pachinko machine, when the fraud who's spamming game board and the main control device or the like, it is necessary to release the inner frame or glass frame, the inner frame or glass frame is opened In such a case, the opening is detected by the sensor and a predetermined notification is made, so that it is possible to grasp an illegal act.

JP 2001-198332 A

However, for example, midnight, etc. after closing of the game arcade, fraudster may enter, if the intruder was fraud by opening the inner frame or glass frame or the like, the power of the pachinko machine is sectional in the time and which, since pachinko machine is stopped, there is an inner frame or a problem that the de Ki such have it open for detecting the glass frame.
In addition to these problems, that is, when the door is opened while the gaming machine is turned off, this problem cannot be grasped in addition to pachinko machines. It can also occur in various gaming machines such as machines in which so-called pachinko machines and slot machines are fused.

  The present invention has been made in order to solve the above-described problems and the like, and allows the opening to be grasped when the door is opened while the power of the gaming machine is turned off. It aims to provide a gaming machine that can.

Gaming machine of claim 1, wherein in order to achieve this object, body and a door body openable and closable with respect to the main body, in a gaming machine and a control means for controlling Yu technique, the door body A door opening detecting means for detecting the opening of the door, a signal output means for outputting a signal to a specific device when the door opening detecting means does not detect the opening of the door, and the door opening detecting means A stop means for stopping signal output to the specific device by the signal output means when the release is detected, the signal output means being turned off when the gaming machine is powered off. Even if it is configured, it is configured to be able to output a signal to the specific device, and the stopping means is a case where the control means is stopped because the power of the gaming machine is turned off, The special feature by the signal output means. The signal output to the device being stoppable configured, the stop means and the signal output means of the computing device itself for said control means is a device for executing a control program provided in the arithmetic unit The operation unit is configured to be operable even at a voltage lower than the operating voltage, and the stopping unit includes an integrated circuit that can operate even at a voltage lower than the operating voltage of the arithmetic unit itself .

According to the present invention, when the door is opened while the power of the gaming machine is turned off, the opening can be grasped.

It is a front view of a pachinko machine. It is a front view of the game board of a pachinko machine. It is a rear view of a pachinko machine. It is a perspective view of the pachinko machine in the state where an inner frame, a front frame, and a lower tray unit are opened. It is the figure which showed the structure of the switch. It is the block diagram which showed the electrical structure of the pachinko machine. It is the circuit diagram which showed the electrical structure of the frame open | release detection circuit and the external output terminal board. 6 is a timing chart showing the relationship between the state of the switch SW1, the state of the switch SW2, the voltage of the TRG terminal of the timer, the voltage of the OUT terminal of the timer, the voltage of the output terminal of the EXOR circuit, and the output of the external output terminal plate. (A) is the figure which showed typically the area division setting and effective line setting of the display screen, (b) is the figure which illustrated the actual display screen. It is a figure which shows the outline | summary of various counters. 3 is a flowchart showing start-up processing executed by an MPU in the main control unit. It is a flowchart which shows the main process performed by MPU in a main controller. It is a flowchart which shows the fluctuation | variation process performed in a main process. It is the flowchart which showed the change start process performed in a change process. It is a flowchart which shows a timer interruption process. 6 is a flowchart showing a start winning process executed in a timer interrupt process. It is a flowchart which shows a NMI interruption process. It is the circuit diagram which showed the electrical structure of the frame open | release detection circuit and external output terminal board of 2nd Embodiment. 6 is a timing chart showing the relationship between the state of the switch SW1, the state of the switch SW2, the voltage A of the frame open detection circuit of the second embodiment, and the output of the external output terminal plate. It is the circuit diagram which showed the electrical structure of the frame open detection circuit and external output terminal board of 3rd Embodiment. The state of the switch SW1, the state of the switch SW2, the voltage of the TRG terminal of the timer of the third embodiment, the voltage of the OUT terminal of the timer of the third embodiment, the voltage of the output terminal of the NOT circuit and the output of the external output terminal plate 3 is a timing chart showing the relationship.

  Hereinafter, an embodiment of a pachinko gaming machine (hereinafter simply referred to as “pachinko machine”) will be described with reference to the drawings. 1 is a front view of the pachinko machine 10, FIG. 2 is a front view of the game board 13 of the pachinko machine 10, and FIG. 3 is a rear view of the pachinko machine 10.

  As shown in FIG. 1, the pachinko machine 10 includes an outer frame 11 having an outer shell formed of a wooden frame combined in a substantially rectangular shape, and an outer frame 11 having substantially the same outer shape as the outer frame 11. And an inner frame 12 supported to be openable and closable. In order to support the inner frame 12, metal hinges 18 are attached to the outer frame 11 at two upper and lower portions on the left side when viewed from the front (see FIG. 1), and the side on which the hinge 18 is provided is used as an opening / closing axis. The frame 12 is supported so as to be openable and closable to the front front side.

  A game board 13 (see FIG. 2) having a large number of nails, winning holes 63, 64, and the like is detachably mounted on the inner frame 12 from the back side. A ball ball game is performed when the ball flows down the front surface of the game board 13. The inner frame 12 has a ball launch unit 112a (see FIG. 5) that launches a ball to the front area of the game board 13 and a launch that guides the ball launched from the ball launch unit 112a to the front area of the game board 13. A rail (not shown) or the like is attached.

  On the front side of the inner frame 12, a front frame 14 that covers the upper side of the front surface and a lower dish unit 15 that covers the lower side of the front frame 14 are provided. In order to support the front frame 14 and the lower dish unit 15, metal hinges 19 are attached to two upper and lower portions on the left side when viewed from the front (see FIG. 1), and the side on which the hinges 19 are provided is used as an opening / closing axis. 14 and the lower pan unit 15 are supported so as to be openable and closable toward the front front side. The locking of the inner frame 12 and the locking of the front frame 14 are respectively released by inserting a dedicated key into the key hole 21 of the cylinder lock 20 and performing a predetermined operation.

  The front frame 14 is assembled with decorative resin parts, electrical parts, and the like, and a window part 14c that is formed in an approximately elliptical shape is provided at a substantially central part thereof. A glass unit 16 having two plate glasses is disposed on the back side of the front frame 14, and the front surface of the game board 13 can be seen on the front side of the pachinko machine 10 through the glass unit 16. On the front frame 14, an upper plate 17 that stores balls is formed in a substantially box shape that protrudes forward and the upper surface is opened, and prize balls and rental balls are discharged to the upper plate 17. The bottom surface of the upper plate 17 is formed to be inclined downward to the right when viewed from the front (see FIG. 1), and the sphere thrown into the upper plate 17 is guided to the ball launch unit 112a by the inclination. A frame button 22 is provided on the upper surface of the upper plate 17. This frame button 22 is operated by the player, for example, when changing the effect pattern of the variable display displayed on the third symbol display device 81 or changing the effect content at the reach effect.

  In addition, the front frame 14 is provided with light emitting means such as various lamps around the periphery (for example, a corner portion). These light-emitting means play a role of enhancing the effect of the game during the game by changing or controlling the light-emitting mode by turning on or flashing according to the change in the gaming state at the time of big hit or predetermined reach. On the peripheral edge of the window portion 14c, there are provided electric decoration portions 29 to 33 incorporating light emitting means such as LEDs. In the pachinko machine 10, these lighting parts 29 to 33 function as effect lamps such as jackpot lamps, and the lighting parts 29 to 33 are turned on by lighting or blinking of the built-in LEDs at the time of jackpot or reach effects. Alternatively, it blinks to notify that the jackpot is being hit or that the reach is one step before the jackpot.

  Further, in the upper left part of the front frame 14 as viewed from the front (see FIG. 1), there is provided a display lamp 34 which has built-in light emitting means such as LEDs and can display the payout of a prize ball and when an error occurs. In addition, a small window 35 is formed by attaching a transparent resin from the back side so that the back side of the front frame 14 can be visually recognized, on the lower side of the right illumination part 32, and a sticking space K1 on the front side of the game board 13 (FIG. 2) is visible from the front surface of the pachinko machine 10. In addition, in the pachinko machine 10, a plated member 36 made of ABS resin that is chrome-plated is attached to an area around the electric decoration parts 29 to 33 in order to bring out more gorgeousness.

  A ball rental operation unit 40 is disposed below the window 14c. The ball lending operation unit 40 is provided with a frequency display unit 41, a ball lending button 42, and a return button 43. When the ball lending operation unit 40 is operated in a state where a bill or a card is inserted into a card unit (ball lending unit) (not shown) arranged on the side of the pachinko machine 10, Loans are made. Specifically, the frequency display unit 41 is an area in which the remaining amount information such as a card is displayed, and the built-in LED is lit to display the remaining amount as the remaining amount information. The ball lending button 42 is operated to obtain a lending ball based on information recorded on a card or the like (recording medium), and the lending ball is supplied to the upper plate 17 as long as there is a remaining amount on the card or the like. Is done. The return button 43 is operated when requesting the return of a card or the like inserted into the card unit. In addition, in a pachinko machine in which a ball is lent directly to the upper plate 17 from a ball lending device or the like without using a card unit, a so-called cash machine does not require the ball lending operation unit 40. In this case, the ball lending operation unit 40 It is also possible to add a decorative seal or the like to the installation portion of the parts so that the component configuration is common. A pachinko machine using a card unit and a cash machine can be shared.

  In the lower plate unit 15 located on the lower side of the upper plate 17, a lower plate 50 for storing a ball that could not be stored in the upper plate 17 is formed in a substantially box shape having an open upper surface. Yes. On the right side of the lower plate 50, an operation handle 51 that is operated by a player to drive a ball into the front surface of the game board 13 is disposed, and the operation of the ball launching unit 112a is permitted inside the operation handle 51. Touch sensor 51a, a push button-type stop switch 51b for stopping the launch of the ball during the pressing operation, and a variable resistor for detecting the amount of rotation of the operating handle 51 by a change in electric resistance (Not shown). When the operation handle 51 is rotated clockwise by the player, the touch sensor is turned on and the resistance value of the variable resistor changes corresponding to the operation amount, and according to the rotation operation amount of the operation handle 51. A ball is fired with a strength corresponding to the resistance value of the variable resistor that changes, and the ball is driven into the front surface of the game board 13 with a jump amount corresponding to the player's operation. Further, when the operation handle 51 is not operated by the player, the touch sensor 51a and the stop switch 51b are off.

  In the lower part of the front of the lower plate 50, a ball removal lever 52 is provided for operating when the balls stored in the lower plate 50 are discharged downward. The ball removal lever 52 is always urged in the right direction. By sliding the ball release lever 52 in the left direction against the urge, the bottom opening formed in the bottom surface of the lower plate 50 is opened. A ball naturally falls from the bottom opening and is discharged. The operation of the ball removal lever 52 is normally performed in a state where a box (generally referred to as “a thousand box”) for receiving the balls discharged from the lower plate 50 is placed below the lower plate 50. As described above, the operation handle 51 is disposed on the right side of the lower plate 50, and the ashtray 53 is attached on the left side of the lower plate 50.

  As shown in FIG. 2, the game board 13 includes a wooden base plate 60 cut into a substantially square shape when viewed from the front, a large number of ball nails, windmills and rails 61 and 62, a general winning opening 63, The ball entrance 64, the variable winning device 65, the variable display device unit 80, and the like are assembled, and the peripheral edge thereof is attached to the back side of the inner frame 12. The general winning port 63, the first winning port 64, the variable winning device 65, and the variable display device unit 80 are arranged in a through hole formed in the base plate 60 by router processing, and the wood screw is provided from the front side of the game board 13. It is fixed by etc. Further, the front center portion of the game board 13 can be viewed from the front side of the inner frame 13 through the window portion 14c (see FIG. 1) of the front frame 14. Below, the structure of the game board 13 is demonstrated.

  An outer rail 62 formed by bending a strip-shaped metal plate into a substantially arc shape is planted on the front surface of the game board 13, and the strip-shaped metal plate is located on the inner side of the outer rail 62 in the same manner as the outer rail 62. The arc-shaped inner rail 61 formed by the above is planted. The inner rail 61 and the outer rail 62 surround the outer periphery of the front surface of the game board 13, and the game board 13 and the glass unit 16 (see FIG. 1) surround the front and rear. A game area in which a game is played is formed by the behavior of. The game area is a front surface of the game board 13 and is a substantially circular area formed by dividing the two rails 61 and 62 and the arc member 70 (a winning hole or the like is provided, Area).

  The two rails 61 and 62 are provided to guide the ball fired from the ball launching unit 112a to the upper part of the game board 13. A return ball preventing member 68 is attached to the front end portion of the inner rail 61 (upper left portion in FIG. 2) to prevent the ball once guided to the upper portion of the game board 13 from returning to the ball guide path again. Is done. A return rubber 69 is attached to the tip of the outer rail 62 (upper right part in FIG. 2) at a position corresponding to the maximum flying portion of the sphere, and the ball launched at a predetermined momentum or more hits the return rubber 69 and gains momentum. Is bounced back to the center while being attenuated. A resin arc member 70 formed by providing an arc connecting the rails on the inner surface side between the lower right end of the inner rail 61 and the upper right end of the outer rail 62 is a base. The plate 60 is driven and fixed.

  A first symbol display device 37 provided with a plurality of LEDs 37a, which are light emitting means, and a 7-segment display 37b is disposed in the upper right portion of the game area as viewed from the front (upper right portion in FIG. 2). The first symbol display device 37 displays information corresponding to each control performed by the main control device 110, and mainly displays the gaming state of the pachinko machine 10. The plurality of LEDs 37a indicate whether the pachinko machine 10 is in the process of being probabilistically changing, operating in a short time, or in a normal state, indicating whether the pachinko machine 10 is changing or not by a lighting state, and the symbols corresponding to the probable big hit. Whether the symbol is a symbol corresponding to a normal jackpot or an out-of-game symbol is indicated by a lighting state, or the number of reserved balls is indicated by a lighting state. The 7-segment display device 37b displays the number of rounds that are a big hit and an error display. In addition, LED37a is comprised so that the light emission color (for example, red, green, blue) of each LED may differ, The various game states of the pachinko machine 10 can be suggested with few LEDs by the combination of the light emission color. .

  In addition, the above-mentioned pachinko machine 10 being probable is a game state in which the jackpot probability is increased and it is easy to shift to the special game state. Further, during the probability change in the present embodiment, the game is in a state where the hit probability of the second symbol is increased and the ball easily enters the first entrance 64. In addition, the time when the pachinko machine 10 is short-running is a game state in which it is easy for a ball to easily enter the first entrance 64 by increasing only the hit probability of the second symbol without changing the jackpot probability. In addition, when the pachinko machine 10 is in a normal state, it is a game state in which neither the probability change nor the time is short (the state where neither the big hit probability nor the second symbol hit probability is increased). It should be noted that, depending on the gaming state of the pachinko machine 10, the time for opening the electric accessory (not shown) associated with the first entrance 64 and the number of times the electric accessory is released per hit are changed. It is good as a thing.

  The game area is provided with a plurality of general winning openings 63 through which 5 to 15 balls are paid out as winning balls when the balls win. In addition, a variable display device unit 80 is disposed in the central portion of the game area. The variable display device unit 80 includes a third symbol display device 81 configured with a liquid crystal display (hereinafter simply referred to as “display device”) that displays the third symbol in a variable manner with a winning at the first entrance 64 as a trigger. And a second symbol display device 82 composed of a light emitting diode (hereinafter abbreviated as “LED”) for variably displaying the second symbol with the passage of the ball at the second entrance 67 as a trigger. .

  The display content of the third symbol display device 81 is controlled by a display control device 114, which will be described later, and for example, three symbol sequences of left, middle and right are displayed. Each symbol row is composed of a plurality of symbols, and these symbols are vertically scrolled for each symbol row so that the third symbol is variably displayed on the display screen of the third symbol display device 81. Further, in the present embodiment, the third symbol display device 81 is constituted by a large liquid crystal display of 8 inch size, and the variable display device unit 80 surrounds the outer periphery of the third symbol display device 81 so as to surround the center frame. 86 is arranged. In the third symbol display device 81 of the present embodiment, the display of the gaming state accompanying the control of the main control device 110 is performed by the first symbol display device 37, whereas the display of the first symbol display device 37 is performed. The decorative display according to is performed. Instead of the display device, for example, the third symbol display device 81 may be configured using a reel or the like.

  In addition, when the ball enters the first entrance 64 until the stop symbol (any one of the probable jackpot symbol, the normal jackpot symbol, or the off symbol) is displayed on the first symbol display device 37. The number of entered balls is held up to 4 times, and the number of held times is indicated by the first symbol display device 37 and the number of lights of the holding lamp 85. Four hold lamps 85 are provided for the maximum number of holds, and are arranged symmetrically above the third symbol display device 81. In the present embodiment, the winning at the first entrance 64 is configured to be held up to 4 times, but the maximum holding number is not limited to 4 times, but 3 times or less. Alternatively, the number may be set to 5 times or more (for example, 8 times). In addition, the hold lamp 85 is deleted, and the number of times the variable display is held based on the winning at the first entrance 64 is numerically held in a part of the third symbol display device 81, or the area divided into four is held. You may make it display in a different aspect (for example, a color and a lighting pattern) by the frequency | count. In addition, since the number of times of holding is indicated by the first symbol display device 37, the holding lamp 85 may not perform lighting display.

  The second symbol display device 82 includes a second symbol display unit 83 and a holding lamp 84, and each time the ball passes through the second entrance 67, the display unit 83 displays a display symbol (second symbol). The “○” symbol and the “×” symbol are alternately lit and displayed in a variable manner. When the fluctuation display stops at a predetermined symbol (in this embodiment, the symbol “O”) The 1 entrance 64 is configured to be activated (opened) for a predetermined time. The number of passes through the second entrance 67 of the sphere is suspended up to a maximum of 4 times, and the number of suspensions is displayed by the above-described first symbol display device 37 and is also lit on the hold lamp 84. The second symbol variation display is performed by switching on and off of a plurality of lamps in the display unit 83 as in the present embodiment, as well as the first symbol display device 37 and the third symbol display device. A part of 81 may be used. Similarly, the hold lamp 84 may be turned on by a part of the third symbol display device 81. In addition, the passage of the second entrance 67 is not limited to 4 times as in the case of the 1st entrance 64, and is not limited to 4 times, or 3 times or less (for example, (8 times). In addition, since the number of times of holding is indicated by the first symbol display device 37, the holding lamp 84 may not perform lighting display.

  Below the variable display device unit 80, a first entrance 64 into which a sphere can enter is disposed. When a ball enters the first entrance 64, a first entrance switch (not shown) provided on the back side of the game board 13 is turned on, and the first entrance switch is turned on. The main controller 110 performs a lottery lottery, and a display corresponding to the lottery result is indicated by the LED 37 a of the first symbol display device 37. The first entrance 64 is also one of the entrances through which 5 balls are paid out as prize balls when a ball enters.

  A variable winning device 65 is disposed below the first ball opening 64, and a horizontally-long rectangular specific winning port (large opening) 65a is provided at a substantially central portion thereof. In the pachinko machine 10, when the lottery in the main controller 110 is a big hit, after a predetermined time (fluctuation time) has elapsed, the LED 37a of the first symbol display device 37 is turned on so as to become a big hit stop symbol. The stop symbol corresponding to the jackpot is displayed on the third symbol display device 81 to indicate the occurrence of the jackpot. Thereafter, the gaming state transitions to a special gaming state (big hit) where the ball is easy to win. In this special gaming state, the special winning opening 65a that is normally closed is opened for a predetermined time (for example, until 30 seconds have elapsed or ten balls have been won).

  The specific winning opening 65a is closed when a predetermined time elapses, and after the closing, the specific winning opening 65a is opened again for a predetermined time. The opening / closing operation of the specific winning opening 65a can be repeated up to 16 times (16 rounds), for example. The state in which the opening / closing operation is performed is a form of a special gaming state advantageous to the player, and the player is given out a larger amount of prize balls than usual in order to give a gaming value (game value). Is done.

  Specifically, the variable winning device 65 is a horizontally long rectangular opening / closing plate covering the specific winning opening 65a, and a large opening opening solenoid (not shown) for driving to open / close forward with the lower side of the opening / closing plate as an axis. And. The special winning opening 65a is normally closed so that the ball cannot win or is difficult to win. In the case of a big hit, the large opening opening solenoid is driven to tilt the opening / closing plate to the lower front side to temporarily form an open state in which the ball is likely to win the specific winning opening 65a. It operates to repeat the state and the state alternately.

  Note that the special gaming state is not limited to the above-described form. When the game area is provided with a large opening that is opened and closed separately from the specific winning opening 65a, and the LED 37a corresponding to the jackpot is turned on in the first symbol display device 37, the specific winning opening 65a is opened for a predetermined time, and the specific winning opening A special gaming state is defined as a game state in which a large opening provided separately from the specific winning port 65a is opened for a predetermined time and a predetermined number of times when the ball 65 is opened into the specific winning port 65a. You may make it form.

  Adhesive spaces K1, K2 for adhering certificate papers, identification labels, etc. are provided at the left and right corners on the lower side of the game board 13, and the certificate paper, etc., adhered to the adhesive space K1, is a front frame 14. It can be visually recognized through the small window 35 (see FIG. 1).

  Further, the game board 13 is provided with an out port 66. A ball that has not entered any of the winning openings 63, 64, 65a is guided through an out port 66 to a ball discharge path (not shown). A number of nails are planted on the game board 13 in order to appropriately disperse and adjust the falling direction of the ball, and various members (instruments) such as a windmill are arranged.

  As shown in FIG. 3, control board units 90 and 91 and a back pack unit 94 are mainly provided on the back side of the pachinko machine 10. The control board unit 90 is unitized by mounting a main board (main control apparatus 110), an audio lamp control board (audio lamp control apparatus 113), and a display control board (display control apparatus 114). The control board unit 91 is unitized by mounting a payout control board (payout control apparatus 111), a firing control board (launching control apparatus 112), a power supply board (power supply apparatus 115), and a card unit connection board 116.

  The back pack unit 94 includes a back pack 92 and a dispensing unit 93 that form a protective cover. In addition, each control board is used for MPU as a one-chip microcomputer that controls each control, a port for communicating with various devices, a random number generator used for various lotteries, time counting and synchronization. A clock pulse generation circuit or the like is mounted as necessary.

  The main control device 110, the sound lamp control device 113 and the display control device 114, the payout control device 111 and the firing control device 112, the power supply device 115, and the card unit connection board 116 are housed in the board boxes 100 to 104, respectively. . The board boxes 100 to 104 include a box base and a box cover that covers the opening of the box base. The box base and the box cover are connected to each other, and each control device and each board are accommodated.

  Further, the substrate box 100 (main control device 110) and the substrate box 102 (dispensing control device 111 and launch control device 112) connect the box base and the box cover so that they cannot be opened by a sealing unit (not shown) (caulking structure). Consolidated). In addition, a seal (not shown) is attached to the connecting portion between the box base and the box cover so as to cover the box base and the box cover. This seal seal is made of a brittle material. If the seal is to be peeled off in order to open the substrate boxes 100, 102, or if the substrate boxes 100, 102 are forcibly opened, the box base side and the box cover are removed. Cut to the side. Therefore, it is possible to know whether or not the substrate boxes 100 and 102 have been opened by checking the sealing unit or the sealing seal.

  The payout unit 93 includes a tank 130 that is located at the top of the back pack unit 94 and opens upward, a tank rail 131 that is connected to the lower side of the tank 130 and is gently inclined toward the downstream side, and downstream of the tank rail 131. A case rail 132 that is vertically connected to the side, and a payout device 133 that is provided at the most downstream portion of the case rail 132 and that pays out a ball by a predetermined electrical configuration of the payout motor 216 (see FIG. 5). ing. The tank 130 is successively replenished with balls supplied from the island equipment of the game hall, and a required number of balls are paid out by the payout device 133 as appropriate. A vibrator 134 for applying vibration to the tank rail 131 is attached to the tank rail 131.

  The payout control device 111 is provided with a state return switch 120, the firing control device 112 is provided with a variable resistor operation knob 121, and the power supply device 115 is provided with a RAM erase switch 122. The state return switch 120 is operated, for example, to eliminate ball clogging (return to a normal state) when a payout error occurs, such as ball clogging in the payout motor 216 (see FIG. 4). The operation knob 121 is operated to adjust the firing force of the firing solenoid. The RAM erase switch 122 is operated when the power is turned on to return the pachinko machine 10 to the initial state.

  Next, the internal configuration of the pachinko machine 10 will be described with reference to FIG. FIG. 4 is a perspective view of the pachinko machine 10 in a state where the inner frame 12, the front frame 14, and the lower dish unit 15 are opened.

  The pachinko machine 10 is provided with an outer frame 11 that forms an outer shell thereof, and an inner frame 12 is supported to the outer frame 11 so as to be opened and closed. In the game hall, the outer peripheral surface of the outer frame 11 is fixed to an installation location called an island of the game hall. Since the inner frame 12, the front frame 14, and the lower dish unit 15 are configured to be openable to the front side with respect to the outer frame 11, the inner frame 12, the front frame 14, and the lower dish unit 15 are not touched from the front side of the pachinko machine 10. Inspection and adjustment are performed with the inner frame 12 and the like open to the front side with respect to the outer frame 11.

  In order to support the inner frame 12, metal upper hinges (not shown) and lower hinges (not shown) are attached to the outer frame 11 at two upper and lower positions on the left side when viewed from the front. The inner frame 12 is supported so as to be openable and closable with the side on which the upper and lower hinges are provided as an opening / closing axis.

  The inner frame 12 is mainly composed of an ABS resin inner frame base 55 formed in a rectangular shape, and a substantially circular central window 55 a is formed at the center of the inner frame base 55. An attachment portion for the game board 13 is provided on the back side of the inner frame base 55, and the game board 13 is detachably attached.

  The lower side of the central window 55a of the inner frame base 55 is formed in a concave shape with the front side open, and a flat mounting surface 52b is formed on the back side. On the mounting surface 52b, a launch unit 140 for launching a ball to the front surface of the game board 13, a passage forming member 54 that forms a passage for discharging the ball to the upper plate 17 and the lower plate 50, and the like are attached.

  Between the outer frame 11 and the inner frame 12, switches SW1 (SW1a, SW1b) for detecting opening and closing of the inner frame 12 are provided, and between the inner frame 12 and the front frame 14, a front surface is provided. Switches SW2 (SW2a, SW2b) for detecting opening and closing of the frame 14 are provided. The switch SW1 is composed of a female switch SW1a disposed on the surface of the outer frame 11 facing the inner frame 12, and a male switch SW1b disposed on the surface of the inner frame 12 facing the outer frame 11. The The switch SW2 includes a female switch SW2a disposed on the surface of the inner frame 12 facing the front frame 14, and a male switch SW2b disposed on the surface of the front frame 14 facing the inner frame 12. Composed.

  Here, the structure of the switch SW1 and the switch SW2 will be described with reference to FIG. Since the switch SW1 and the switch SW2 have the same structure, the structure of the switch SW1 will be described, and the description of the switch SW2 will be omitted.

  FIG. 5 is a diagram showing the structure of the switch SW1. FIG. 5A is a diagram showing a state (cut-off state) of the switch SW1 in a state where the inner frame 12 is closed. FIG. 5B is a diagram showing a state (conducting state) of the switch SW1 in a state where the inner frame 12 is opened.

  As shown in FIG. 5A, the female switch SW1a disposed on the surface of the outer frame 11 facing the inner frame 12 incorporates a pair of terminal pairs SW1c made of metal as a conductive member. ing. When the inner frame 12 is closed, the female switch SW1a disposed on the surface of the outer frame 11 facing the inner frame 12 is connected to the male switch SW1a disposed on the surface of the inner frame 12 facing the outer frame 11. The mold switch SW1b is inserted, and contact between the terminal pairs SW1c is prevented. Therefore, in a state where the inner frame 12 is closed, the switch SW1 is in a state where conduction is cut off.

  On the other hand, as shown in FIG. 5B, in a state where the inner frame 12 is opened, the female switch SW1a disposed on the surface of the outer frame 11 facing the inner frame 12 is connected to the outside of the inner frame 12. The male switch SW1b disposed on the surface facing the frame 11 is pulled out. Since the terminal pair SW1c built in the female switch SW1a has a structure in which an urging force is generated in the opposite direction, the terminal pair SW1c is in contact with each other when the male switch SW1b is pulled out from the female switch SW1a. To do. Therefore, in a state where the inner frame 12 is opened, the switch SW1 is in a conductive state.

  As described above, the switch SW1 is in a cut-off state when the inner frame 12 is closed, and is in a conductive state when the inner frame 12 is opened. However, the structure of the switch SW1 is not limited to the shape shown in FIG. 5, and when the inner frame 12 is closed, the switch SW1 is in a cut-off state, while in the state where the inner frame 12 is opened, Any structure may be used as long as the switch SW1 is in a conductive state. The same applies to the structure of the switch SW2.

  Next, the electrical configuration of the pachinko machine 10 will be described with reference to FIG. FIG. 6 is a block diagram showing an electrical configuration of the pachinko machine 10.

  The main controller 110 is equipped with an MPU 201 as a one-chip microcomputer that is an arithmetic unit. The MPU 201 includes a ROM 202 that stores various control programs executed by the MPU 201 and fixed value data, and a memory that temporarily stores various data when the control program stored in the ROM 202 is executed. A certain RAM 203 and various other circuits such as an interrupt circuit, a timer circuit, and a data transmission / reception circuit are incorporated. Various commands are transmitted from the main control device 110 to the sub control device by the data transmission / reception circuit in order to instruct the sub control device such as the payout control device 111 and the sound lamp control device 113 to operate. Such a command is transmitted from the main controller 110 to the sub controller only in one direction.

  The RAM 203 stores the contents of the internal registers of the MPU 201, the return address of the control program executed by the MPU 201, and the work area (work area for storing various flags and counters, I / O values, etc. Area). The RAM 203 is configured to hold (backup) data by being supplied with a backup voltage from the power supply device 115 even after the power of the pachinko machine 10 is shut off, and all data stored in the RAM 203 is backed up.

  When the power is shut down due to the occurrence of a power failure or the like, the stack pointer and the value of each register when the power is shut off (including when the power failure occurs, the same applies hereinafter) are stored in RAM 203. On the other hand, at the time of power-on (including power-on due to power failure cancellation, the same applies hereinafter), the state of the pachinko machine 10 is restored to the state before power-off based on information stored in the RAM 203. Writing to the RAM 203 is executed when the power is shut off by the main process (see FIG. 12), and restoration of each value written in the RAM 203 is executed in a startup process (see FIG. 11) when the power is turned on. Note that the power failure signal SG1 from the power failure monitoring circuit 252 is input to the NMI terminal (non-maskable interrupt terminal) of the MPU 201 when the power is interrupted due to the occurrence of a power failure or the like. Is input immediately, the NMI interrupt process (see FIG. 17) as a power failure process is immediately executed.

  An input / output port 205 is connected to the MPU 201 of the main control device 110 via a bus line 204 composed of an address bus and a data bus. The input / output port 205 includes a payout control device 111, a sound lamp control device 113, a first symbol display device 37, a second symbol display device 82, various switches 208 including a switch group and a sensor group (not shown), and a specific prize. A solenoid 209 comprising a large opening solenoid for opening and closing the front side with the lower side of the opening and closing plate of the opening 65a as an axis, a solenoid for driving an electric accessory, and the like is connected.

  The main controller 110 is also provided with a frame opening detection circuit 260 that detects opening of the inner frame 12 when the switch SW1 is turned on and detects opening of the front frame 14 when the switch SW2 is turned on. Yes. Connected to the frame opening detection circuit 260 are a switch SW1 for detecting the opening of the inner frame 12, a switch SW2 for detecting the opening of the front frame 14, and an external output terminal plate 261 configured to be connectable to the hall computer 262. Has been. It should be noted that an input / output unit (input / output port 205 and an input / output port) that inputs and outputs signals is used to connect the switches SW1 and SW2 to the frame opening detection circuit 260 and to connect the frame opening detection circuit 260 and the external output terminal plate 261. Are connected via different input / output ports (not shown). The frame open detection circuit 260 maintains the output from the external output terminal board 261 to the hall computer 262 in a high state when the inner frame 12 and the front frame 14 are closed and the switch SW1 and the switch SW2 are shut off. . That is, the frame open detection circuit 260 outputs a high signal from the external output terminal board 261 to the hall computer 262 when the inner frame 12 and the front frame 14 are closed.

  On the other hand, when the inner frame 12 is opened and the switch SW1 is turned on, or when the front frame 14 is opened and the switch SW2 is turned on, the frame opening detection circuit 260 has an external output terminal for about 10 ms after the opening. The output from the board 261 to the hall computer 262 is switched from the high state to the low state. In other words, the frame open detection circuit 260, when either one or both of the inner frame 12 and the front frame 14 are opened, from the external output terminal board 261 to the hall computer 262 for about 10 ms from the opening. Stop the high signal being output. The stop of the high signal is stored in the hall computer 262 that continues to operate for 24 hours. Therefore, by analyzing the information stored in the hall computer 262, the opening of the inner frame 12 or the front frame 14 can be detected.

  Here, the frame opening detection circuit 260 is configured not to be connected to the MPU 201 or the input / output port 205 (input / output port of the MPU 201) of the main controller 110. Therefore, the frame opening detection circuit 260 may be configured to be mounted on a device (circuit board) other than the main control device 110. For example, it may be mounted on a device (circuit board) on which an arithmetic device such as an MPU or CPU is not mounted, or a dedicated substrate for the frame opening detection circuit 260 may be provided and mounted thereon. More preferably, like the main control device 110, the payout control device 111, and the launch control device 112, the frame opening detection circuit 260 is accommodated in the substrate box, and the box base and the box cover provided on the substrate box are connected. The seal unit (not shown) is connected so that it cannot be opened (connection by caulking structure). A sealing seal (not shown) may be attached to the connecting portion between the box base and the box cover so as to extend over the box cover and the box base.

  The payout control device 111 drives the payout motor 216 to perform payout control of prize balls and rental balls. The MPU 211, which is an arithmetic unit, includes a ROM 212 that stores a control program executed by the MPU 211, fixed value data, and the like, and a RAM 213 that is used as a work memory or the like.

  The RAM 213 of the payout control device 111, like the RAM 203 of the main control device 110, has a stack area for storing the contents of the internal registers of the MPU 211, the return address of the control program executed by the MPU 211, and various flags and counters. And a work area (work area) in which values such as I / O are stored. The RAM 213 is configured to be able to retain (backup) data by being supplied with a backup voltage from the power supply device 115 even after the power of the pachinko machine 10 is cut off, and all data stored in the RAM 213 is backed up. As with the MPU 201 of the main controller 110, the power failure signal SG1 is also input to the NMI terminal of the MPU 211 from the power failure monitoring circuit 252 when the power is interrupted due to the occurrence of a power failure or the like. When input to the MPU 211, an NMI interrupt process (see FIG. 17) is immediately executed as a power failure process.

  An input / output port 215 is connected to the MPU 211 of the payout control device 111 via a bus line 214 composed of an address bus and a data bus. The main control device 110, the payout motor 216, the firing control device 112, and the like are connected to the input / output port 215, respectively. Although not shown, the payout control device 111 is connected to a prize ball detection switch for detecting a prize ball that has been paid out. The prize ball detection switch is connected to the payout control device 111 but is not connected to the main control device 110.

  The launch control device 112 controls the ball launch unit 112a so that the launch strength of the ball according to the rotational operation amount of the operation handle 51 is obtained when the main control device 110 gives an instruction to launch a ball. The ball launching unit 112a includes a launching solenoid and an electromagnet (not shown), and the firing solenoid and the electromagnet are permitted to be driven when predetermined conditions are met. Specifically, the operation handle 51 is detected on the condition that the touch sensor 51a detects that the player is touching the operation handle 51 and the stop switch 51b for stopping the ball firing is turned off (not operated). The firing solenoid is excited in accordance with the amount of rotation 51, and a ball is launched with a strength corresponding to the amount of operation of the operation handle 51.

  The voice lamp control device 113 is a voice output in a voice output device (such as a speaker not shown) 226, an output of lighting and extinguishing in a lamp display device (such as the illumination units 29 to 33 and the display lamp 34), and the display control device 114. The setting of the display mode of the 3rd symbol display apparatus 81 performed etc. is controlled. The MPU 221 that is an arithmetic unit includes a ROM 222 that stores a control program executed by the MPU 221, fixed value data, and the like, and a RAM 223 that is used as a work memory or the like.

  An input / output port 225 is connected to the MPU 221 of the sound lamp control device 113 via a bus line 224 including an address bus and a data bus. The main control device 110, the display control device 114, the audio output device 226, the lamp display device 227, and the like are connected to the input / output port 225, respectively.

  The display control device 114 controls the change display of the third symbol on the third symbol display device (LCD) 81. The display control device 114 includes an MPU 231, a ROM (program ROM) 232, a work RAM 233, a video RAM 234, a character ROM 235, an image controller 236, an input port 237, an output port 238, and bus lines 239 and 240. have. The input side of the input port 237 is connected to the output side of the sound lamp control device 113, and the output side of the input port 237 is connected to the MPU 231, ROM 232, work RAM 233, and image controller 236. A video RAM 234 and a character ROM 235 are connected to the image controller 236, and an output port 238 is connected via a bus line 240. A third symbol display device 81 is connected to the output side of the output port 238. Even if the pachinko machine 10 is a different model with different winning probability for winning the jackpot and the number of prize balls to be paid out in one jackpot, there is a model having the same specifications as the symbols displayed on the third symbol display device 81. Therefore, the display control device 114 is made into a common part to reduce the cost.

  The MPU 231 of the display control device 114 controls the display content of the third symbol display device 81 based on the symbol display command input from the sound lamp control device 113. The ROM 232 is a memory for storing various control programs executed by the MPU 231 and fixed value data. The work RAM 233 is a memory for temporarily storing work data and flags used when the MPU 231 executes various programs. The character ROM 235 is a memory that stores data for effects such as symbols (background symbols and third symbols) displayed on the third symbol display device 81. The video RAM 234 is a memory for storing effect data displayed on the third symbol display device 81, and the display content of the third symbol display device 81 is changed by rewriting the contents of the video RAM 234.

  The image controller 236 adjusts the timing of the MPU 231, the video RAM 234, and the output port 238 to intervene in reading and writing data, and reads display data stored in the video RAM 234 at a predetermined timing to read the third symbol display device 81. Is displayed.

  The power supply device 115 includes a power supply unit 251 for supplying power to each unit of the pachinko machine 10, a power failure monitoring circuit 252 for monitoring power interruption due to a power failure, and a RAM deletion switch 122 (see FIG. 3). And an erasing switch circuit 253. The power supply unit 251 is a device that supplies a necessary operating voltage to each of the control devices 110 to 114 through a power supply path (not shown). As its outline, the power supply unit 251 takes in the voltage of AC 24 volts supplied from the outside, and drives various switches such as various switches 208, solenoids such as the solenoid 209, motors, etc. A 5 volt voltage for logic, a backup voltage for RAM backup, and the like are generated, and the 12 volt voltage, the 5 volt voltage, and the backup voltage are supplied to the control devices 110 to 114 as necessary voltages.

  The power failure monitoring circuit 252 is a circuit for outputting a power failure signal SG1 to each NMI terminal of the MPU 201 of the main control device 110 and the MPU 211 of the payout control device 111 when the power is cut off due to the occurrence of a power failure or the like. The power failure monitoring circuit 252 monitors the DC stable voltage of 24 volts, which is the maximum voltage output from the power supply unit 251, and determines that a power failure (power interruption, power interruption) occurs when this voltage falls below 22 volts. Then, the power failure signal SG1 is output to the main controller 110 and the payout controller 111. Based on the output of the power failure signal SG1, the main controller 110 and the payout controller 111 recognize the occurrence of the power failure and execute the NMI interrupt process. Note that the power supply unit 251 outputs a voltage of 5 volts, which is a drive voltage of the control system, for a time sufficient to execute the NMI interrupt processing even after the DC stable voltage of 24 volts becomes less than 22 volts. Is maintained at a normal value. Therefore, main controller 110 and payout controller 111 can normally execute and complete the NMI interrupt process (see FIG. 17).

  The RAM erase switch circuit 253 is a circuit for outputting a RAM erase signal SG2 for clearing backup data to the main controller 110 when the RAM erase switch 122 is pressed. When the RAM erase signal SG2 is input when the pachinko machine 10 is turned on, the main control device 110 and the payout control device 111 clear the respective backup data and the payout control device 111 for clearing the backup data. A payout initialization command is transmitted to the payout control device 111.

  Next, the frame opening detection circuit 260 and the external output terminal plate 261 will be described with reference to FIG. FIG. 7 is a circuit diagram showing the electrical configuration of the frame opening detection circuit 260 and the external output terminal plate 261. In FIG. 7, the frame opening detection circuit 260 is described first, and then the external output terminal plate 261 is described.

  A frame opening detection circuit 260 that detects opening of the inner frame 12 or opening of the front frame 14 includes a DC power supply DC1 that supplies a DC voltage of 12 volts, a diode D1, a storage battery SB1, capacitors CD2 to CD5, and a resistor R1. ˜R4, a timer IC1 (LMC555 manufactured by National Semiconductor), an exclusive OR circuit (hereinafter referred to as “EXOR circuit”) IC2, an internal resistor R5 and an internal resistor R6 are provided. The transistor TR1 is mainly included.

  In order to detect the opening of the inner frame 12 when the switch SW1 is turned on and to detect the opening of the front frame 14 when the switch SW2 is turned on, the frame opening detection circuit 260 has the above components shown in FIG. Connected according to circuit diagram.

  The DC power source DC1 is a power source that supplies a DC voltage of 12 volts to the open frame detection circuit 260 and the external output terminal board 261. Power (power) to the DC power supply DC1 is supplied from a power supply unit 251 provided in the power supply device 115 through a power supply path (not shown). This DC power supply DC1 is connected to the anode terminal of the diode D1. The positive terminal of the storage battery SB1 is connected to the cathode terminal of the diode D1. The negative terminal of the storage battery SB1 is grounded. The positive terminal of the storage battery SB1 is connected to one end of the switch SW1, one end of the switch SW2, the VDD terminal and the RES terminal of the timer IC1, and one end of the resistor R7 of the external output terminal plate 261.

  The storage battery SB1 supplies a DC voltage to the open frame detection circuit 260 and the external output terminal plate 261 when the power supply to the pachinko machine 10 is cut off and a DC voltage of 12 volts is not supplied from the DC power supply DC1. Next battery.

  The storage battery SB1 is supplied with power to the pachinko machine 10, and when a DC voltage of 12 volts is supplied from the DC power supply DC1, the DC voltage applied to the storage battery SB1 (12 supplied from the DC power supply DC1). Charging is performed by approximately 11.3 volts minus a voltage drop of approximately 0.7 volts at the diode D1.

  On the other hand, the storage battery SB1 has, for example, a frame open detection circuit when the business hours of the amusement hall are over and the power supply to the pachinko machine 10 is cut off and a DC voltage of 12 volts is not supplied from the DC power supply DC1. A DC voltage having an electromotive force of approximately 11.3 volts is supplied to 260 and the external output terminal plate 261. The storage battery SB1 has a capacity capable of supplying a DC voltage of about 11.3 volts to the open frame detection circuit 260 and the external output terminal plate 261 for at least 15 hours when fully charged. Note that the capacitor is not limited to the storage battery SB1, and a sufficiently large capacitor capable of supplying a DC voltage of about 11.3 volts to the open frame detection circuit 260 and the external output terminal plate 261 for at least 15 hours may be used.

  Therefore, the frame opening detection circuit 260 operates naturally when power is supplied to the pachinko machine 10 and a DC voltage of 12 volts is supplied from the DC power supply DC1, and further, for example, a game hall business Even when the power supply to the pachinko machine 10 is interrupted and the DC voltage of 12 volts is not supplied from the DC power supply DC1, the frame open detection circuit 260 and the external output terminal board are used by the storage battery SB1. It can operate by supplying a DC voltage (about 11.3 volts) to H.261. Therefore, the frame opening detection circuit 260 is supplied with power to the pachinko machine 10 and supplied with a DC voltage of 12 volts from the DC power supply DC1, and the power supply to the pachinko machine 10 is cut off. Even when a DC voltage of 12 volts is not supplied from the power source DC1, the opening of the inner frame 12 and the opening of the front frame 14 can be detected.

  Note that the cathode terminal of the diode D1 is connected to the positive terminal of the storage battery SB1, and this diode D1 functions to prevent the backflow of current, so that the storage battery SB1 is connected to the frame open detection circuit 260 and the external output terminal plate 261. Even when the DC voltage (about 11.3 volts) is supplied, the DC voltage (about 11.3 volts) supplied by the storage battery SB1 is applied to the DC power source DC1, and the DC power source DC1 is not damaged.

  The timer IC1 is a CMOS timer and detects the opening of the inner frame 12 or the opening of the front frame 14 by connecting the resistors R1 and R2 of 100 kΩ and the capacitors CD3 to CD5 of 0.1 μF, and the external output terminal plate 261 Functions as a circuit that cuts off the energization of the photocoupler PR1 for about 10 ms.

  The operating voltage range of the timer IC 1 is that of the MPU 201 mounted on the main control device 110, the MPU 211 mounted on the payout control device 111, the MPU 221 mounted on the sound lamp control device 113, and the MPU 231 mounted on the display control device 114. It is set in a wider range than each operating voltage range. Specifically, the operating voltage range of the timer IC 1 is about 1.5 volts to about 12.0 volts, while the operating voltage ranges of the MPUs 201, 211, 2221, and 231 are about 4.5 volts. It is about 5.5 volts (each operating voltage in this embodiment is about 5.0 volts). Therefore, the timer IC 1 can operate at a voltage lower than the operating voltages of the MPUs 201, 211, 211, 231. Therefore, even if the charged amount of the storage battery SB1 decreases and the voltage supplied by the storage battery SB1 drops below about 4.5 volts, the timer IC1 can operate sufficiently. Further, for example, when the business hours of the amusement hall are over and the power supply to the pachinko machine 10 is shut off and the DC voltage of 12 volts is not supplied from the DC power source DC1, that is, the timer IC1 is switched to DC by the storage battery SB1. The case where the voltage is supplied and the case where the power supply to the pachinko machine 10 is performed and the DC voltage of 12 volts is supplied from the DC power source DC1 are combined. Therefore, of course, the timer IC 1 can operate at a DC voltage of 12 volts or less supplied to the frame opening detection circuit 260 when power is supplied to the pachinko machine 10. Furthermore, since the timer IC1 is a timer composed of a C-MOS semiconductor, power consumption during operation can be suppressed and operation can be performed for a long time.

  The VDD terminal of the timer IC1 is a terminal for inputting a DC voltage supplied to the timer IC1, and is connected to the plus terminal of the storage battery SB1. The VDD terminal of the timer IC1 is connected to one end of a 0.1 μF capacitor CD4, and the other end of the capacitor CD4 is connected to the GND terminal of the grounded timer IC1. The capacitor CD4 reduces the noise generated at the VDD terminal of the timer IC1 when the inner frame 12 and the front frame 14 are opened or closed and the switch SW1 and the switch SW2 are turned on or off.

  The RES terminal of the timer IC 1 is a terminal for operating a reset function for forcibly stopping the voltage output from the OUT terminal (zero volts) when a pulse signal is input to the RES terminal. However, since this frame open detection circuit 260 does not use this reset function, the RES terminal of the timer IC 1 is connected to the plus terminal of the storage battery SB 1 so that the reset function is not activated. Since the VDD terminal of timer IC1 and the RES terminal of timer IC1 are connected to the positive terminal of storage battery SB1 as described above, a DC voltage of about 11.3 volts is applied to the VDD terminal and RES terminal of timer IC1. Is applied.

  When the switch SW1 and the switch SW2 are cut off (when the inner frame 12 and the front frame 14 are closed), the TRG terminal of the timer IC1 reduces the voltage output from the OUT terminal of the timer IC1. When one of the switches SW1 and SW2 or both of the switches SW1 and SW2 is in a conductive state (either the inner frame 12 or the front frame 14, Or, when both the inner frame 12 and the front frame 14 are in an open state), the voltage output from the OUT terminal of the timer IC 1 is a terminal for setting from about 10.6 volts to zero volts after about 10 ms. . The TRG terminal of the timer IC1 is connected to one input terminal of the EXOR circuit IC2, one end of the resistor R2, one end of the capacitor CD5, the other end of the switch SW1, the other end of the switch SW2, and one end of the resistor R1. The other end of the resistor R2 and the other end of the capacitor CD5 are grounded.

  The resistor R2 connected to the TRG terminal of the timer IC1 is connected to the timer IC1 when the switch SW1 and the switch SW2 are in the conductive state (see FIG. 5B), that is, when the inner frame 12 and the front frame 14 are in the open state. This is a resistor for applying a DC voltage (about 11.3 volts) to the TRG terminal. The capacitor CD5 is a capacitor for reducing noise generated in the resistor R2 when the switch SW1 and the switch SW2 are turned on or off (when the inner frame 12 and the front frame 14 are opened or closed). is there.

  With the above connection, when the inner frame 12 and the front frame 14 are in the closed state and the switch SW1 and the switch SW2 are in the cut-off state, no voltage is supplied to the resistor R2 and the capacitor CD5, so that the voltage is applied to the resistor R2 and the capacitor CD5. That is, the voltage applied to the TRG terminal of the timer IC1 is zero volts. At this time, the voltage output from the OUT terminal of the timer IC 1 is about 10.6 volts.

  On the other hand, either the inner frame 12 or the front frame 14, or both the inner frame 12 and the front frame 14 are in an open state, and either the switch SW1 or the switch SW2 or both the switch SW1 and the switch SW2 are conductive. Since the voltage is supplied to the resistor R2 and the capacitor CD5 when in the state, the voltage applied to the resistor R2 and the capacitor CD5, that is, the voltage applied to the TRG terminal of the timer IC1 is the voltage of the positive terminal of the storage battery SB1. The same as that of about 11.3 volts. At this time, the voltage output from the OUT terminal of the timer IC 1 is about 10.3 for about 10 ms after either the switch SW 1 or the switch SW 2 or both the switch SW 1 and the switch SW 2 are in the conductive state. 6 volts, then zero volts.

  In this way, the voltage output from the OUT terminal of the timer IC 1 can be set to about 10.6 volts or zero volts by the voltage applied to the TRG terminal of the timer IC 1. When the inner frame 12 or the front frame 14 is opened, the switch SW1 or the switch SW2 is turned on, and the voltage applied to the TRG terminal of the timer IC 1 rises from zero volts to about 11.3 volts, the voltage rises. About 10 ms later, the voltage of about 10.6 volts output from the OUT terminal of the LMC 555 falls to zero volts. As will be described in detail later, the collector of the transistor TR1 is obtained by the time difference (about 10 ms) between the rising edge of the voltage applied to the TRG terminal of the timer IC1 and the falling edge of the voltage output from the OUT terminal of the timer IC1. The conduction between the terminal c and the emitter terminal e can be cut off for about 10 ms, and the conduction of the photocoupler PR1 on the external output terminal plate 261 can be cut off for about 10 ms.

  When the inner frame 12 and the front frame 14 are closed, the switch SW1 and the switch SW2 are shut off, and the voltage applied to the TRG terminal of the timer IC1 becomes zero volts, the OUT terminal of the timer IC1 has a voltage of about 10.6 volts. Is output, the inner frame 12 or the front frame 14 is opened, the switch SW1 or the switch SW2 is turned on, and the voltage applied to the TRG terminal of the timer IC1 rises from zero volts to about 11.3 volts. This is a terminal for setting the output voltage of about 10.6 volts to zero volts with a delay of about 10 ms. This OUT terminal is connected to the other input terminal of the EXOR circuit IC2 (an input terminal not connected to the TRG terminal of the timer IC1). The output terminal of the EXOR circuit IC2 is connected to one end of the resistor R3.

  The EXOR circuit IC2 has a voltage at the TRG terminal of the timer IC1 (about 11.3 volts in the high state and zero volts at the low state) and a voltage at the OUT terminal of the timer IC1 (about 10.6 volts in the high state and zero volts in the low state). ) Is a circuit that outputs approximately 11.3 volts from the output terminal, and otherwise outputs zero volts from the output terminal.

  The EXOR circuit IC2 has one input terminal connected to the TRG terminal of the timer IC1, the other input terminal connected to the OUT terminal of the timer IC1, and an output terminal connected to one end of the resistor R3. And although this EXOR circuit IC2 is not shown in figure, the power supply terminal is connected to the plus terminal of storage battery SB1.

  Therefore, when the voltage output from the OUT terminal of the timer IC 1 is about 10.6 volts and the voltage applied to the TRG terminal of the timer IC 1 is zero volts, that is, the inner frame 12 and the front frame 14 are closed. Or when the voltage output from the OUT terminal of the timer IC1 is zero volts and the voltage applied to the TRG terminal of the timer IC1 is about 10.6 volts, that is, the inner frame 12 or the front frame. When about 10 ms elapses after 14 is opened, the output of the EXOR circuit IC2 becomes a high state (about 11.3 volt state). When the output of the EXOR circuit IC2 becomes a high state, the collector terminal c and the emitter terminal e of the transistor TR1 are brought into conduction, and a high signal which is a continuous signal is output from the photocoupler PR1 to the hall computer 262.

  On the other hand, when the voltage output from the OUT terminal of the timer IC 1 is about 10.6 volts and the voltage applied to the TRG terminal of the timer IC 1 is about 11.3 volts, that is, the inner frame 12 or the front frame. If within 14 ms after 14 is opened, the output of the EXOR circuit IC2 is in a low state (zero volt state). When the output of the EXOR circuit IC2 becomes a low state, the collector terminal c and the emitter terminal e of the transistor TR1 are cut off, and the high signal output from the photocoupler PR1 to the hall computer 262 is stopped.

  The resistor R3 connected to the output terminal of the EXOR circuit IC2 and the resistor R4 connected to the resistor R3 are voltage dividing resistors for dividing the voltage output from the output terminal of the EXOR circuit IC2. One end of the resistor R3 is connected to the output terminal of the EXOR circuit IC2, and the other end of the resistor R3 is connected to one end of the capacitor CD2 and one end of the resistor R4. The other end of the capacitor CD2 and the other end of the resistor R4 are grounded. Therefore, the voltage output from the output terminal of the EXOR circuit IC2 is divided into the resistor R3 and the resistor R4 according to the ratio between the resistance value of the resistor R3 and the resistance value of the resistor R4. Since both the resistor R3 and the resistor R4 are 10 kΩ, the voltage of about 11.3 volts output from the output terminal of the EXOR circuit IC2 is about 5.7 volts maximum by the resistors R3 and R4, respectively. Divided pressure.

  The 10 μF capacitor CD2 connected in parallel with the resistor R4 is a capacitor for stabilizing the voltage applied to the resistor R4. The capacitor CD2 stabilizes the voltage applied to the resistor R4, stabilizes the bias voltage applied between the base terminal b of the transistor TR1 and the emitter terminal e of the transistor TR1, and operates the transistor TR1. Can be stabilized.

  The transistor TR1 is a switching element that switches between the conduction terminal and the interruption terminal between the collector terminal c of the transistor TR1 and the emitter terminal e of the transistor TR1 based on the voltage applied to the resistor R4. The transistor TR1 is provided with a 10 kΩ internal resistor R5 connected in series to the base terminal b. One end of the internal resistor R5 is connected to one end of the resistor R4, and the other end of the internal resistor R5 is connected to the base terminal b. Further, the transistor TR1 is provided with an internal resistance R6 of 10 kΩ between the other end of the internal resistance R5 and the emitter terminal e. The other end of the internal resistor R5 is connected to one end of the internal resistor R6, and the emitter terminal e is connected to the other end of the internal resistor R6.

  Therefore, when a voltage of about 11.3 volts is output from the output terminal of the EXOR circuit IC2 (when the inner frame 12 and the front frame 14 are closed, and the inner frame 12 or the front frame 14 is opened). When about 10 ms has passed), the voltage is divided by the resistors R3 and R4, and the voltage (about 5.7 volts) applied to the resistor R4 is connected to one end of the internal resistor R5 of the transistor TR1 and the transistor Applied between the emitter terminal e of TR1. As a result, the terminals of the collector terminal c of the transistor TR1 and the emitter terminal e of the transistor TR1 become conductive, and a current is supplied to one end of the resistor R7 of the external output terminal plate 261. If a current is supplied to one end of the resistor R7, the photocoupler PR1 of the external output terminal plate 261 can be energized to set the output to the hall computer 262 to a high state (a continuous signal from the photocoupler PR1 to the hall computer 262). Can output a high signal).

  On the other hand, when the voltage at the output terminal of the EXOR circuit IC2 is zero volts (within about 10 ms after the inner frame 12 or the front frame 14 is opened), no voltage is applied to the resistor R4. No voltage is applied between one end of the resistor R5 and the emitter terminal e of the transistor TR1. As a result, the terminal between the collector terminal c of the transistor TR1 and the emitter terminal e of the transistor TR1 is blocked, and no current is supplied to one end of the resistor R7 of the external output terminal plate 261. Therefore, the photocoupler PR1 on the external output terminal plate 261 is not energized, and the output to the hall computer 262 is in a low state (the high signal output from the photocoupler PR1 to the hall computer 262 is stopped).

  As described above, when the inner frame 12 or the front frame 14 is opened, the energization of the external output terminal plate 261 to the photocoupler PR1 can be cut off for about 10 ms. Therefore, when the inner frame 12 or the front frame 14 is in the open state, the high signal output from the external output terminal board 261 to the hall computer 262 is stopped for about 10 ms after the opening. Can do.

  The TH terminal of the timer IC1 is a terminal that measures a voltage applied to the TH terminal, and is connected to the other end of the resistor R1, one end of the capacitor CD3, and the DCH terminal of the timer IC1. The DCH terminal of the timer IC1 has a voltage (about 7.5 volts) that is 2/3 of the direct current voltage (about 11.3 volts) applied to the VDD terminal of the timer IC1. In this case, the terminal switches the impedance of the DCH terminal from an infinite state to a zero state. When the impedance of the DCH terminal becomes zero (ground state), a voltage cannot be applied to the capacitor CD3. On the other hand, when the impedance of the DCH terminal is infinite, a voltage can be applied to the capacitor CD3.

  The resistor R1 and the capacitor CD3 connected to the TH terminal of the timer IC1 and the DCH terminal of the timer IC1 are based on a time constant that is the product of the resistance value of the resistor R1 and the capacitance value of the capacitor CD3. This is a component for determining the time until the voltage of about 10.6 volts output from the OUT terminal of the timer IC1 is switched to zero volts to about 10 ms when 14 is opened. One end of the resistor R1 is connected to one of the other end of the switch SW1, the other end of the switch SW2, one end of the capacitor CD5, one end of the resistor R2, the TRG terminal of the timer IC1, and the input terminal of the EXOR circuit IC2. The other end of the resistor R1 is connected to the TH terminal of the timer IC1, the DCH terminal of the timer IC1, and one end of the capacitor CD3. The other end of the capacitor CD3 is grounded.

  Here, the resistor R1 and the capacitor CD3 will be described together with the TRG terminal of the timer IC1, the TH terminal of the timer IC1, the DCH terminal of the timer IC1, and the OUT terminal of the timer IC1.

  When the inner frame 12 and the front frame 14 are in the closed state (when the switch SW1 and the switch SW2 are in the cut-off state), no voltage is supplied to the resistor R1, so the voltage applied to the TH terminal of the timer IC1 is zero volts (about 7.5 volts). Thus, the impedance of the DCH terminal of the timer IC 1 is set to an infinite state. Therefore, a voltage can be applied to the capacitor CD3, and the capacitor CD3 is in a chargeable state (a state in which charge can be stored). However, when the switch SW1 and the switch SW2 are cut off, the connection between the positive terminal of the storage battery SB1 and the resistor R1 is cut off, so that no voltage is applied to the capacitor CD3, and the voltage applied to the capacitor CD3 is Zero volts. Thus, the capacitor CD3 is in a chargeable state, but is not charged. At this time, the voltage at the TRG terminal of the timer IC1 is zero volts (low state), and the voltage at the OUT terminal of the timer IC1 is approximately 10.6 volts (high state), so the output terminal of the EXOR circuit IC2 Is about 11.3 volts (high state), and the collector terminal c and the emitter terminal e of the transistor TR1 are electrically connected. Therefore, a current is supplied to one end of the resistor R7 of the external output terminal plate 261, and the photocoupler PR1 of the external output terminal plate 261 is energized. Therefore, a high signal is output from the external output terminal board 261 to the hall computer 262.

  Next, when the inner frame 12 or the front frame 14 is in an open state (see FIG. 5B) and the switch SW1 or the switch SW2 is in a conductive state, the voltage applied to the TRG terminal of the timer IC1 is zero volts (low state). ) To about 11.3 volts (high state). At this time, since the voltage at the OUT terminal of the timer IC1 is about 10.6 volts (low state), the voltage at the output terminal of the EXOR circuit IC2 becomes zero volts (low state), and the collector terminal c and emitter terminal of the transistor TR1. Connection with e is cut off. Then, the current supply to one end of the resistor R7 of the external output terminal plate 261 is stopped, and the energization of the external output terminal plate 261 to the photocoupler PR1 is also stopped. Therefore, the high signal output from the external output terminal board 261 to the hall computer 262 is stopped (the output from the external output terminal board 261 to the hall computer 262 is low).

  Further, at the same time when the voltage applied to the TRG terminal of the timer IC1 is switched from zero volts to about 11.3 volts, the voltage is applied to the capacitor CD3, and charging of the capacitor CD3 is started. At this time, the voltage applied to the TH terminal of the timer IC1 starts to rise.

  The voltage at the OUT terminal of the timer IC1 is 2 / of the voltage (about 11.3 volts) applied to the VDD terminal of the timer IC1 (the voltage applied to the capacitor CD3) applied to the TH terminal of the timer IC1. Continue to maintain about 10.6 volts until equal to a voltage of 3, ie, about 7.5 volts. When the voltage applied to the TH terminal of the timer IC1 (the voltage applied to the capacitor CD3) rises and becomes equal to about 7.5 volts, the impedance of the DCH terminal of the timer IC1 is changed from an infinite state to a zero state (ground To the ( Then, the voltage applied to the capacitor CD3 becomes a zero volt state, and the electric charge stored in the capacitor CD3 is discharged. As a result, the voltage applied to the TH terminal of the timer IC 1 is switched from about 7.5 volts to zero volts. By switching the voltage applied to the TH terminal of the timer IC1, the voltage at the OUT terminal of the timer IC1 switches from about 10.6 volts (high state) to zero volts (low state). At this time, since the voltage at the TRG terminal of the timer IC1 is about 11.3 volts (high state), the voltage at the output terminal of the EXOR circuit IC2 is switched from zero volts (low state) to about 11.3 volts (high state). Instead, the collector terminal c and the emitter terminal e of the transistor TR1 are brought into conduction again. Therefore, the current supply to one end of the resistor R7 of the external output terminal plate 261 is resumed, and the energization of the external output terminal plate 261 to the photocoupler PR1 is also resumed. Therefore, a high signal is output again from the external output terminal board 261 to the hall computer 262.

  As described above, when the inner frame 12 or the front frame 14 is in an open state and the switch SW1 or the switch SW2 is in a conductive state (see FIG. 5B), about 10 output from the OUT terminal of the timer IC1. The time until the voltage of .6 volts is switched to zero volts, that is, the time until the voltage applied to the TH terminal of the timer IC1 (the voltage applied to the capacitor CD3) is changed from zero volts to about 7.5 volts. Based on the time constant which is the product of the resistance value of R1 and the capacitance value of the capacitor CD3, it is determined to be about 10 ms. Then, when the inner frame 12 or the front frame 14 is opened, the current supplied to one end of the resistor R7 of the external output terminal plate 261 is stopped for about 10 ms, and the photo of the external output terminal plate 261 is stopped. Energization of the coupler PR1 can be stopped for about 10 ms. Therefore, when the inner frame 12 or the front frame 14 is in the open state, the high signal output from the external output terminal board 261 to the hall computer 262 is stopped for about 10 ms after the opening. Can do.

  When the inner frame 12 and the front frame 14 are changed from the open state to the closed state, and the switch SW1 and the switch SW2 are changed from the conductive state to the cutoff state, the voltage applied to the TRG terminal of the timer IC1 is about 11.3 volts (high state). ) To zero volts (low state), the voltage at the OUT terminal of the timer IC 1 switches from zero volts (low state) to about 10.6 volts (high state). However, since the voltage at the output terminal of the EXOR circuit IC2 remains at about 11.3 volts (high state), the collector terminal c and the emitter terminal e of the transistor TR1 remain conductive. Therefore, the current continues to be supplied to one end of the resistor R7 of the external output terminal plate 261, and the energization of the photocoupler PR1 of the external output terminal plate 261 is still performed. Accordingly, even when the inner frame 12 and the front frame 14 are changed from the open state to the closed state, and the switches SW1 and SW2 are changed from the conductive state to the closed state, a high signal is continuously output from the external output terminal board 261 to the hall computer 262. Will remain.

  As described above, when the inner frame 12 or the front frame 14 is opened, the resistor R7 of the external output terminal plate 261 is based on the time constant that is the product of the resistance value of the resistor R1 and the capacitance value of the capacitor CD3. Since the current supplied to one end of the output terminal plate 261 can be cut off for about 10 ms, the energization of the external output terminal plate 261 to the photocoupler PR1 can also be stopped for about 10 ms. Thereby, when the inner frame 12 or the front frame 14 is opened, the high signal output from the external output terminal board 261 to the hall computer 262 can be stopped for about 10 ms from the opening. .

  Returning to the description of FIG. The CNT terminal of the timer IC 1 is a terminal that adjusts the output time of the voltage output from the OUT terminal of the timer IC 1 by a signal input to the CNT terminal. However, since the frame open detection circuit 260 does not adjust the output time of the voltage output from the OUT terminal of the timer IC1, the CNT terminal of the timer IC1 is any component of the frame open detection circuit 260 and the external output terminal plate 261. It is not connected to and is open.

  As described above, when the inner frame 12 or the front frame 14 is in the open state and the switch SW1 or the switch SW2 is in the conductive state (see FIG. 5B), the frame open detection circuit 260 is about For 10 ms, the terminal between the collector terminal c of the transistor TR1 and the emitter terminal e of the transistor TR1 is cut off, and the current supply to one end of the resistor R7 of the external output terminal plate 261 is stopped. On the other hand, the frame open detection circuit 260 conducts the connection between the collector terminal c of the transistor TR1 and the emitter terminal e of the transistor TR1 from the cut-off state after about 10 ms has passed since the inner frame 12 or the front frame 14 is opened. The state is switched to, and the current supply to one end of the resistor R7 of the external output terminal plate 261 is resumed. Thereby, the energization of the external output terminal plate 261 to the photocoupler PR1 is stopped for about 10 ms after the inner frame 12 or the front frame 14 is opened. Therefore, when the inner frame 12 or the front frame 14 is opened, a high signal output from the external output terminal board 261 to the hall computer 262 is output for about 10 ms after the inner frame 12 or the front frame 14 is opened. During this time, it can be stopped.

  The door opening detection circuit 260 uses the LMC 555 for the timer IC 1 to detect the opening of the inner frame 12 or the opening of the front frame 14 and realize a circuit that stops energization of the photocoupler PR1 for about 10 ms. However, it is not limited to this. That is, by using another integrated circuit or the like for the timer IC 1, a circuit that generates one pulse signal for one opening of the inner frame 12 or one opening of the front frame 14 is realized. What is necessary is just to stop energization to the photocoupler PR1 for a predetermined period based on the pulse signal.

  Next, the external output terminal board 261 connected to the frame opening detection circuit 260 and connected to the hall computer 262 will be described. The external output terminal plate 261 has a function of outputting a high signal to the hall computer 262, and is mainly composed of a 1 kΩ resistor R7 and a photocoupler PR1.

  The resistor R7 is a resistor that limits the current supplied to the photocoupler PR1, and one end of the resistor R7 is a positive terminal of the storage battery SB1, one end of the switch SW1, one end of the switch SW2, one end of the capacitor CD4, VDD of the timer IC1 The other end of the resistor R7 is connected to the primary side of the photocoupler PR1 (the anode terminal of the light emitting diode). The photocoupler PR1 is a current switch including a light emitting diode and a light receiving element (phototransistor) that receives light emitted from the light emitting diode. As described above, the light emitting diode which is the primary side of the photocoupler PR1 has an anode terminal connected to one end of the resistor R7 and a cathode terminal connected to the collector terminal c of the transistor TR1 of the frame open detection circuit 260. The light receiving element (phototransistor) that is the secondary side of the photocoupler PR1 is connected to the hall computer 262.

  Therefore, when the inner frame 12 and the front frame 14 are closed, and when about 10 ms has elapsed since the inner frame 12 or the front frame 14 was opened, the collector terminal c of the transistor TR1 and the emitter of the transistor TR1. The terminal e is electrically connected to the terminal e, and a current is supplied to the primary light emitting diode of the photocoupler PR1 through the resistor R7. Thereby, the light emitting diode on the primary side of the photocoupler PR1 emits light. Then, the secondary light receiving element (phototransistor) of the photocoupler PR1 receives the emitted light, converts the received light into an electrical signal, and outputs the electrical signal to the hall computer 262 as a high signal.

  On the other hand, when the inner frame 12 or the front frame 14 is in an open state, the collector terminal c of the transistor TR1 and the emitter of the transistor TR1 are approximately 10 ms after the inner frame 12 or the front frame 14 is opened. The connection between the terminal e and the terminal is interrupted. Then, since the current to one end of the resistor R7 is stopped for about 10 ms, the current to the light emitting diode which is the primary side of the photocoupler PR1 is also stopped for about 10 ms. Therefore, the high signal output to the hall computer 262 from the light receiving element (phototransistor) on the secondary side of the photocoupler PR1 is also stopped for about 10 ms. This stoppage of the high signal is stored in the hall computer 262 that continues to operate for 24 hours.

  Here, an advantage of using the photocoupler PR1 for the external output terminal plate 261 connected to the hall computer 262 will be described. The photocoupler PR1 is configured to convert a current supplied to the light emitting diode on the primary side into light, receive the light in a light receiving element (phototransistor) on the secondary side, and output an electrical signal (from the light emitting diode to the light receiving element). To transmit a signal in one direction. Therefore, an electrical signal cannot be transmitted from the light receiving element (phototransistor) on the secondary side to the light emitting diode on the primary side. As a result, even if the open frame detection circuit 260 is connected to the light emitting diode on the primary side of the photocoupler PR1, and the hall computer 262 is connected to the light receiving element (phototransistor) on the secondary side of the photocoupler PR1, the hall computer 262 is connected. Cannot be transmitted to the main controller 110 or the like provided with the frame opening detection circuit 260 or the frame opening detection circuit 260. Therefore, by using the photocoupler PR1, signals from the external output terminal board 261 to the hall computer 262 can be prevented while preventing unauthorized transmission of electrical signals from the hall computer 262 to the frame opening detection circuit 260, the main controller 110, and the like. Can be transmitted.

  Further, in the photocoupler PR1, the primary side light emitting diode and the secondary side light receiving element (phototransistor) are electrically insulated. Therefore, for example, even if an electric noise is included in the current supplied to the light emitting diode of the photocoupler PR1, the electric noise is not transmitted to the secondary side phototransistor. Therefore, by using the photocoupler PR1, the external output terminal board 261 has an advantage that it can output an accurate signal to the hall computer 262.

  As described above, according to the pachinko machine 10 of the present embodiment, when the inner frame 12 or the front frame 14 is opened, about 10 ms from when the inner frame 12 or the front frame 14 is opened. Meanwhile, the conduction between the collector terminal c of the transistor TR1 and the emitter terminal e of the transistor TR1 is cut off. Then, since the current to one end of the resistor R7 is stopped for about 10 ms, the current to the light emitting diode which is the primary side of the photocoupler PR1 is also stopped for about 10 ms. Therefore, the high signal output from the light receiving element (phototransistor) on the secondary side of the photocoupler PR1 to the hall computer 262 is stopped for about 10 ms. This stoppage of the high signal is stored in the hall computer 262 that continues to operate for 24 hours. Therefore, by using the frame opening detection circuit 260 and the external output terminal board 261, the hall computer 262 can memorize that the inner frame 12 has been opened or the front frame 14 has been opened.

  Here, in general, the amusement hall has a security contract with a private security company, and if there is an intruder into the amusement hall, the security company's guards immediately rush to the amusement hall. However, since the cheating is carried out in a short time, in most cases when the guards rush to the intruder, the intruder has already escaped from the playground, and it is impossible to determine which pachinko machine 10 was cheated. There was a problem. The pachinko machine 10 that has been cheated must return to a normal state, but if it is not known which pachinko machine 10 has been cheated, the inner frame 12 and the front frame 14 of all the pachinko machines 10 are Opening them and inspecting them one by one was a heavy hard work to do in a game hall where many pachinko machines 10 were installed.

  However, according to the pachinko machine 10 of the present embodiment, when the opening of the inner frame 12 or the opening of the front frame 14 is detected by the frame opening detection circuit 260, the output is output from the external output terminal plate 261 to the hall computer 262. The high signal is stopped for about 10 ms. The high signal stop state is stored in the hall computer 262. Therefore, the pachinko machine 10 in which the inner frame 12 or the front frame 14 is opened can be identified by the high signal stop state stored in the hall computer 262. Further, the hall computer 262 stores the stop state of the high signal output from the external output terminal board 261 and also stores the time when the high signal is stopped, thereby identifying the inner frame of the identified pachinko machine 10. 12 opening times or the opening time of the front frame 14 can be detected.

  Further, according to the pachinko machine 10 of the present embodiment, when the inner frame 12 and the front frame 14 are closed, and when about 10 ms has elapsed since the inner frame 12 or the front frame 14 was opened, A high signal is output from the light receiving element (phototransistor) on the secondary side of the photocoupler PR1 of the external output terminal plate 261 to the hall computer 262. On the other hand, as described above, when the inner frame 12 or the front frame 14 is in the open state, the high signal output from the phototransistor to the hall computer 262 is in the stop state, but the period in which the high signal is in the stop state. Is about 10 ms.

  Here, the light receiving element (phototransistor) on the secondary side of the photocoupler PR1 of the external output terminal plate 261 is connected to the hall computer 262 using a communication cable (not shown). When the signal is cut (damaged) by, the high signal output from the phototransistor to the hall computer 262 exceeds about 10 ms and is always stopped.

  Therefore, when the high signal output to the hall computer 262 from the light receiving element (phototransistor) that is the secondary side of the photocoupler PR1 of the external output terminal plate 261 is stopped for more than about 10 ms, The disconnection (breakage) of the communication cable connecting the transistor and the hall computer 262 can be detected. Therefore, in addition to being able to detect the opening of the inner frame 12 or the front frame 14 from the high signal stop state period stored in the hall computer 262, the communication cable connecting the phototransistor and the hall computer 262 is disconnected (damaged). Etc. can also be detected.

  In addition, the semiconductor components used for the open frame detection circuit 260 and the external output terminal board 261 may be destroyed by impact, static electricity, or the like. This destruction destroys the semiconductor used for the semiconductor components. Therefore, in general, an open breakdown (a breakdown in which the terminals of the semiconductor components are opened) is more likely to occur than a short breakdown (a breakdown in which the terminals of the semiconductor components are in a short circuit). When the semiconductor component is open broken, no current is supplied to the semiconductor component, so that no normal voltage is output from the semiconductor component. Then, since a normal current is not supplied to the photocoupler PR1, there is no abnormality in the communication cable connecting the light receiving element (phototransistor) on the secondary side of the photocoupler PR1 of the external output terminal plate 261 and the hall computer 262. However, the high signal output from the phototransistor to the hall computer 262 exceeds about 10 ms and is always stopped.

  Therefore, although there is no abnormality in the communication cable that connects the light receiving element (phototransistor) that is the secondary side of the photocoupler PR1 of the external output terminal plate 261 and the hall computer 262, the high output that is output from the phototransistor to the hall computer 262. When the signal is stopped after approximately 10 ms, the breakage of the frame opening detection circuit 260 or the external output terminal board 261 can be detected. Therefore, in addition to being able to detect the opening of the inner frame 12 or the front frame 14 from the high signal stop state period stored in the hall computer 262, the frame opening detection circuit 260 or the external output terminal plate 261 is also destroyed (abnormal). Can be detected.

  Further, according to the pachinko machine 10 of the present embodiment, the frame open detection circuit 260 is provided with the storage battery SB1, so that power is supplied to the pachinko machine 10 and a DC voltage of 12 volts from the DC power supply DC1. In addition to the case where, for example, the business hours of the amusement hall are over, the power supply to the pachinko machine 10 is cut off, and the DC voltage of 12 volts is not supplied from the DC power supply DC1. The frame opening detection circuit 260 can detect the opening of the inner frame 12 and the opening of the front frame 14.

  Next, referring to FIG. 8, the TRG terminal voltage of timer IC1 that changes according to the state of switch SW1 (the state of inner frame 12) and the state of switch SW2 (the state of front frame 14), The relationship between the OUT terminal voltage, the voltage of the output terminal of the EXOR circuit IC2, and the output of the external output terminal plate 261 (input of the hall computer 262) will be described. FIG. 8 shows the state of the switch SW1 (the state of the inner frame 12), the state of the switch SW2 (the state of the front frame 14), the TRG terminal voltage of the timer IC1, the OUT terminal voltage of the timer IC1, and the voltage of the output terminal of the EXOR circuit IC2. 4 is a timing chart showing the relationship between the output of the external output terminal board 261 (the input of the hall computer 262).

  As shown in FIG. 8 (a), when the switch SW1 is in a conducting state (the inner frame 12 is in an open state) from time t1 to time t2, as shown in FIG. 8 (c), the TRG terminal voltage of the timer IC1 is Between t1 and t2, it switches from zero volts (low state) to about 11.3 volts (high state). At this time, as shown in FIG. 8D, the timer IC1 continues to output a voltage of about 10.6 volts from the OUT terminal until about 10 ms elapse from t1. Therefore, as shown in FIG. 8E, the voltage at the output terminal of the EXOR circuit IC2 is about 11.3 volts when the TRG terminal voltage is switched to about 11.3 volts (high state) (at t1). (High state) switches to zero volts (Low state). During this time, the terminal between the collector terminal c of the transistor TR1 and the emitter terminal e (see FIG. 7) of the transistor TR1 of the open frame detection circuit 260 is cut off, and the current to one end of the resistor R7 of the external output terminal plate 261 Supply stops. Accordingly, as shown in FIG. 8F, the high signal output from the external output terminal board 261 to the hall computer 262 is stopped (at time t1).

  Next, after about 10 ms has elapsed since the switch SW1 is in a conductive state (the inner frame 12 is in an open state), that is, after the TRG terminal voltage has been switched from zero volts to about 11.3 volts (from t1), As shown in FIG. 8D, the timer IC1 switches the voltage at the OUT terminal from about 10.6 volts (high state) to zero volts (low state). Then, as shown in FIG. 8 (e), the voltage at the output terminal of the EXOR circuit IC2 switches from zero volts (low state) to about 11.3 volts (high state) again (after about 10 ms has elapsed since t1). . As a result, the terminal between the collector terminal c of the transistor TR1 and the emitter terminal e (see FIG. 7) of the transistor TR1 of the open frame detection circuit 260 is brought into conduction, and current is supplied to one end of the resistor R7 of the external output terminal plate 261. Is done. Therefore, as shown in FIG. 8F, a high signal is output again from the external output terminal board 261 to the hall computer 262 (after about 10 ms has elapsed since t1).

  As described above, for about 10 ms after the switch SW1 becomes conductive (the inner frame 12 is open), that is, after the TRG terminal voltage is switched from zero volts to about 11.3 volts (from t1). When the current supply to one end of the resistor R7 is stopped, the current supply to the light emitting diode (see FIG. 7) on the primary side of the photocoupler PR1 of the external output terminal plate 261 is also stopped for about 10 ms from t1. Is done. As a result, as shown in FIG. 8F, the output of the external output terminal plate 261 switches from the high state to the low state for about 10 ms. That is, the high signal output from the external output terminal board 261 to the hall computer 262 is stopped for about 10 ms from t1. The high signal stop state is stored in the hall computer 262.

  As shown in FIG. 8A, when the switch SW1 is in a cut-off state (the inner frame 12 is closed) at t2, as shown in FIG. 8C, the TRG terminal voltage of the timer IC1 is t2. Is switched from about 11.3 volts to zero volts, so that the OUT terminal voltage of the timer IC1 is switched from zero volts to about 10.6 volts as shown in FIG. 8D (at time t2). As a result, the frame opening detection circuit 260 is set again to a state in which the inner frame 12 and the front frame 14 can be detected (at time t2).

  Next, as shown in FIG. 8 (b), when the switch SW2 is in a conducting state (front frame 14 is in an open state) from time t3 to time t4, as shown in FIG. 8 (c), the TRG terminal of the timer IC1. The voltage switches from zero volts (low state) to about 11.3 volts (high state) between t3 and t4. At this time, as shown in FIG. 8D, the timer IC1 continues to output a voltage of about 10.6 volts from the OUT terminal until about 10 ms elapse from t3. Therefore, as shown in FIG. 8E, the voltage at the output terminal of the EXOR circuit IC2 is about 11.3 volts when the TRG terminal voltage is switched to about 11.3 volts (high state) (at t3). (High state) switches to zero volts (Low state). During this time, the terminal between the collector terminal c of the transistor TR1 and the emitter terminal e (see FIG. 7) of the transistor TR1 of the open frame detection circuit 260 is cut off, and the current to one end of the resistor R7 of the external output terminal plate 261 Supply stops. Accordingly, as shown in FIG. 8F, the high signal output from the external output terminal board 261 to the hall computer 262 is stopped (at time t3).

  Next, after the switch SW1 is in a conductive state (the inner frame 12 is in an open state), that is, after the TRG terminal voltage is switched from zero volts to about 11.3 volts (from t3), about 10 ms elapses. As shown in FIG. 8D, the timer IC1 switches the voltage at the OUT terminal from about 10.6 volts (high state) to zero volts (low state). Then, as shown in FIG. 8 (e), the voltage at the output terminal of the EXOR circuit IC2 switches from zero volts (low state) to about 11.3 volts (high state) again (after about 10 ms has elapsed since t3). . As a result, the terminal between the collector terminal c of the transistor TR1 and the emitter terminal e (see FIG. 7) of the transistor TR1 of the open frame detection circuit 260 is brought into conduction, and current is supplied to one end of the resistor R7 of the external output terminal plate 261. Is done. Therefore, as shown in FIG. 8F, a high signal is output again from the external output terminal board 261 to the hall computer 262 (after about 10 ms has elapsed since t3).

  As described above, for about 10 ms after the switch SW2 is in a conductive state (the front frame 14 is in an open state), that is, after the TRG terminal voltage is switched from zero volts to about 11.3 volts (from t3 time). When the current supply to one end of the resistor R7 is stopped, the current supply to the light emitting diode (see FIG. 7) on the primary side of the photocoupler PR1 of the external output terminal plate 261 is also stopped for about 10 ms. As a result, as shown in FIG. 8F, the output of the external output terminal plate 261 switches from the high state to the low state for about 10 ms from t3. That is, the high signal output from the external output terminal board 261 to the hall computer 262 is stopped for about 10 ms from t3. The high signal stop state is stored in the hall computer 262.

  As shown in FIG. 8B, when the switch SW2 is in a cut-off state (the front frame 14 is in a closed state) at t4, as shown in FIG. 8C, the TRG terminal voltage of the timer IC1 at t4. Is switched from about 11.3 volts to zero volts, so that the OUT terminal voltage of the timer IC1 is switched from zero volts to about 10.6 volts as shown in FIG. 8D (at t4). As a result, the frame opening detection circuit 260 is set again to a state in which the inner frame 12 and the front frame 14 can be detected (at time t4).

  Finally, a case will be described in which the switch SW2 is in a conductive state (the front frame 14 is in an open state) when the switch SW1 is in a conductive state (the inner frame 12 is in an open state). As shown in FIG. 8A, when the switch SW1 is in the conductive state (the inner frame 12 is in the open state) (between t5 and t7), as shown in FIG. 8B, the switch SW2 is in the conductive state. When the front frame 14 is in the open state (between t6 and t8), the TRG terminal voltage of the timer IC1 is changed from zero volts to about 11.3 volts between t5 and t8, as shown in FIG. 8C. Switch. At this time, as shown in FIG. 8D, the timer IC1 continues to output a voltage of about 10.6 volts from the OUT terminal until about 10 ms elapses from t5. Therefore, as shown in FIG. 8E, the voltage at the output terminal of the EXOR circuit IC2 is about 11.3 volts when the TRG terminal voltage is switched to about 11.3 volts (high state) (at t5). (High state) switches to zero volts (Low state). During this time, the terminal between the collector terminal c of the transistor TR1 and the emitter terminal e (see FIG. 7) of the transistor TR1 of the open frame detection circuit 260 is cut off, and the current to one end of the resistor R7 of the external output terminal plate 261 Supply stops. Therefore, as shown in FIG. 8F, the high signal output from the external output terminal board 261 to the hall computer 262 is stopped (at time t5).

  Next, after the switch SW1 is turned on (the inner frame 12 is in an open state), that is, after the TRG terminal voltage is switched from zero volts to about 11.3 volts (from t5), about 10 ms elapses. As shown in FIG. 8D, the timer IC1 switches the voltage at the OUT terminal from about 10.6 volts (high state) to zero volts (low state). Then, as shown in FIG. 8 (e), the voltage at the output terminal of the EXOR circuit IC2 switches from zero volts (low state) to about 11.3 volts (high state) again (after about 10 ms has elapsed since t5). . As a result, the terminal between the collector terminal c of the transistor TR1 and the emitter terminal e (see FIG. 7) of the transistor TR1 of the open frame detection circuit 260 is brought into conduction, and current is supplied to one end of the resistor R7 of the external output terminal plate 261. Is done. Therefore, as shown in FIG. 8F, a high signal is output again from the external output terminal board 261 to the hall computer 262 (after about 10 ms has elapsed since t5).

  As described above, after the switch SW1 is turned on (the inner frame 12 is open), that is, for about 10 ms after the TRG terminal voltage is switched from zero volts to about 11.3 volts (from t5). When the current supply to one end of the resistor R7 is stopped, the current supply to the light emitting diode (see FIG. 7) on the primary side of the photocoupler PR1 of the external output terminal plate 261 is also stopped for about 10 ms. As a result, as shown in FIG. 8 (f), the output of the external output terminal plate 261 switches from the high state to the low state for about 10 ms from t5. That is, the high signal output from the external output terminal board 261 to the hall computer 262 is stopped for about 10 ms from t5. The high signal stop state is stored in the hall computer 262.

  As shown in FIG. 8 (a), at time t7, the switch SW1 is in the cut-off state (the inner frame 12 is closed), and as shown in FIG. 8 (b), at time t8, the switch SW2 is in the cut-off state. When the front frame 14 is closed, the TRG terminal voltage of the timer IC 1 is switched from about 11.3 volts to zero volts at time t8 as shown in FIG. 8C. Thus, the OUT terminal voltage of the timer IC 1 switches from zero volts to about 10.6 volts (at time t8). As a result, the frame opening detection circuit 260 is set again to a state in which the inner frame 12 and the front frame 14 can be detected (at time t8).

  As described above, even when the switch SW1 is in the conductive state (the inner frame 12 is in the open state) and the switch SW2 is in the conductive state (the front frame 14 is in the open state), the timer IC1 is in the conductive period of the switch SW1. Regardless of the length of the inner frame 12 (the length of the opening period of the inner frame 12) and the length of the conduction period of the switch SW2 (the length of the opening period of the front frame 14), either the switch SW1 or the switch SW2 is in the conductive state. When about 10 ms elapses from when either the inner frame 12 or the front frame 14 is open, the voltage at the OUT terminal is switched from about 10.6 volts to zero volts. As a result, the output of the external output terminal plate 261 switches from the high state to the low state for about 10 ms. That is, the high signal output from the external output terminal plate 261 to the hall computer 262 is in a state where either the switch SW1 or the switch SW2 is in a conductive state (either the inner frame 12 or the front frame 14 is open). It will be stopped only for about 10 ms from time.

  As described above, when either the inner frame 12 or the front frame 14 is in an open state (one of the switch SW1 or switch SW2 is conductive), or the inner frame 12 and the front frame 14 are in an open state (switch SW1 and switch SW1). When SW2 becomes conductive, the open frame detection circuit 260 switches the voltage of the TRG terminal from zero volts to about 11.3 volts. Then, regardless of the period of the open state of the inner frame 12 and the front frame 14 (the conductive state of the switch SW1 and the switch SW2), the frame open detection circuit 260 detects that the timer IC 1 The voltage at the OUT terminal is switched from about 10.6 volts to zero volts. By the operation of the frame opening detection circuit 260, the connection between the collector terminal c of the transistor TR1 and the emitter terminal e (see FIG. 7) of the transistor TR1 of the frame opening detection circuit 260 is blocked for about 10 ms. Thus, a high signal output from the external output terminal board 261 to the hall computer 262 is when one of the inner frame 12 or the front frame 14 is in an open state (one of the switch SW1 or the switch SW2 is in a conductive state), or When the inner frame 12 and the front frame 14 are in the open state (the switches SW1 and SW2 are in the conductive state), they are stopped only for about 10 ms.

  The stop state of the high signal is stored in the hall computer 262 that continues to operate for 24 hours. Therefore, the pachinko machine 10 in which the inner frame 12 or the front frame 14 is opened can be identified by the high signal stop state stored in the hall computer 262. Further, the hall computer 262 stores the stop state of the high signal output from the external output terminal board 261 and also stores the time when the high signal is stopped, thereby identifying the inner frame of the identified pachinko machine 10. 12 opening times or the opening time of the front frame 14 can be detected.

  In the present embodiment, when the inner frame 12 or the front frame 14 is opened and the switch SW1 or the switch SW2 is turned on, a high signal output from the external output terminal plate 261 to the hall computer 262 is about 10 ms. However, this is not a limitation. That is, when the connection of each component of the frame open detection circuit 260 is changed, the inner frame 12 or the front frame 14 is opened, and the opened inner frame 12 or the front frame 14 is closed, the photocoupler PR1 is connected. The supplied current may be stopped for about 10 ms, and the high signal output from the external output terminal board 261 to the hall computer 262 may be stopped for about 10 ms.

  However, in the frame open detection circuit 260 of this embodiment, when the inner frame 12 or the front frame 14 is opened and the switch SW1 or the switch SW2 is turned on, the output is output from the external output terminal plate 261 to the hall computer 262. Since the high signal is stopped for about 10 ms, the opening of the inner frame 12 or the front frame 14 can be detected quickly. Therefore, the opening of the inner frame 12 or the front frame 14 can be detected before the inner frame 12 or the front frame 14 is opened and an illegal act is performed on the main controller 110 or the game board 13. Accordingly, it is possible to prevent an abnormal operation due to an illegal act occurring when power is supplied to the pachinko machine 10.

  Further, when the inner frame 12 and the front frame 14 are closed, and when about 10 ms has elapsed since the inner frame 12 or the front frame 14 was opened, the collector terminal c of the transistor TR1 and the emitter of the transistor TR1. The terminal e is electrically connected to the terminal e, and a current is supplied to the primary light emitting diode of the photocoupler PR1 through the resistor R7. As a result, a high signal is continuously output from the external output terminal board 261 to the hall computer 262. Here, when the inner frame 12 and the front frame 14 are closed, and when about 10 ms elapses after the inner frame 12 or the front frame 14 is opened, the frame open detection circuit 260 and the external output terminal plate 261. When it is desired to suppress the power consumed by the resistor R3, the resistor R4, the internal resistor R5, and the internal resistor R6, the resistance values of the resistor R7 and the resistor R7 may be set to be larger than 10 kΩ.

  Further, when it is desired to separately store in the hall computer 262 which of the inner frame 12 and the front frame 14 is opened, the following configuration may be used. First, the frame opening detection circuit 260 and the external output terminal plate 261 used in this embodiment are newly provided one by one, the switch SW2 connected in parallel to the switch SW1 is disconnected, and the disconnected switch SW2 is newly installed. It may be connected to the provided frame opening detection circuit 260. Specifically, one end of the disconnected switch SW2 is connected to the positive terminal of the storage battery SB1 of the newly provided frame opening detection circuit 260, the VDD terminal of the timer IC1, the one end of the capacitor CD4, the RES terminal of the timer IC1, and the external output terminal plate. 261 is connected to one end of the resistor R7, and the other end of the disconnected switch SW2 is connected to one end of the capacitor CD5 of the newly provided frame opening detection circuit 260, one end of the resistor R2, the TRG terminal of the timer IC1, and the EXOR circuit IC2. It may be connected to one of the input terminals and one end of the resistor R1. Thus, the frame opening detection circuit 260 and the external output terminal board 261 are newly provided, and only the switch SW2 is connected to the newly provided frame opening detection circuit 260, and the existing frame opening detection circuit 260 has a switch By connecting only SW1, if the switch SW1 is conductive (the inner frame 12 is opened), the high signal output from the existing external output terminal board 261 to the hall computer 262 is stopped, and the switch SW2 is turned off. When there is continuity (opening of the front frame 14), the high signal output from the newly provided external output terminal board 261 to the hall computer 262 can be stopped. Here, the hall computer 262 includes an input terminal for a high signal output from the existing external output terminal board 261 (for detecting conduction of the switch SW1 (for detecting opening of the inner frame 12)), and a newly provided external output terminal. A high signal input terminal output from the plate 261 (for detecting the conduction of the switch SW2 (for detecting the opening of the front frame 14)) is set separately. With this configuration, the conduction of the switch SW1 (opening of the inner frame 12) and the conduction of the switch SW2 (opening of the front frame 14) can be distinguished and stored in the hall computer 262. Therefore, depending on the stop state of the high signal stored in the hall computer 262, the switch SW1 is conductive (the inner frame 12 is opened), the switch SW2 is conductive (the front frame 14 is opened), or both It is possible to accurately detect whether or not there has been.

  In addition, when power is supplied to the pachinko machine 10, the hall computer 262 separately stores which of the inner frame 12 and the front frame 14 is opened, and between the inner frame 12 and the front frame 14. When it is desired to notify the pachinko machine 10 when one of them is opened, the following configuration may be used. First, the frame opening detection circuit 260 and the external output terminal plate 261 used in this embodiment are newly provided one by one, the switch SW2 connected in parallel to the switch SW1 is disconnected, and the disconnected switch SW2 is newly installed. Connected to the provided frame opening detection circuit 260. Next, the male switches SW1b and SW2b and the female switches SW1a and SW2a are newly provided for the switch SW1 and the switch SW2, respectively. Then, when the inner frame 12 or the front frame 14 is opened using the newly provided male switches SW1b and SW2b and the female switches SW1a and SW2a and the switch SW1 or the switch SW2 is turned on, a signal is sent to the MPU 201. What is necessary is just to comprise so that it may be input.

  Specifically, one end of the disconnected switch SW2 is connected to the positive terminal of the storage battery SB1 of the newly provided frame opening detection circuit 260, the VDD terminal of the timer IC1, the one end of the capacitor CD4, the RES terminal of the timer IC1, and the external output terminal plate. 261 is connected to one end of the resistor R7, and the other end of the disconnected switch SW2 is connected to one end of the capacitor CD5 of the newly provided frame opening detection circuit 260, one end of the resistor R2, the TRG terminal of the timer IC1, and the EXOR circuit IC2. It may be connected to one of the input terminals and one end of the resistor R1. Thus, the frame opening detection circuit 260 and the external output terminal board 261 are newly provided, and only the switch SW2 is connected to the newly provided frame opening detection circuit 260, and the existing frame opening detection circuit 260 has a switch By connecting only SW1, if the switch SW1 is conductive (the inner frame 12 is opened), the high signal output from the existing external output terminal board 261 to the hall computer 262 is stopped, and the switch SW2 is turned off. When there is continuity (opening of the front frame 14), the high signal output from the newly provided external output terminal board 261 to the hall computer 262 can be stopped.

  Next, male switch SW1b and male switch SW2b are further provided for switch SW1 and switch SW2, respectively, and male switch SW1b and male switch SW2b disposed in switch SW1 and switch SW2 are respectively provided in two. To do. Correspondingly, the female switch SW1a and the female switch SW2a are further provided in the switch SW1 and the switch SW2, respectively, and the female switch SW1a and the female switch SW2a provided in the switch SW1 and the switch SW2 are respectively 2 One by one. As a result, one new combination of the male switch SW1b and the female switch SW1a is added to the switch SW1. Similarly to the switch SW1, one combination of the male switch SW2b and the female switch SW2a is added to the switch SW2. Then, one end of a pair of terminal pairs SW1c built in the newly added female switch SW1a is connected to the DC power source DC1 of the existing frame opening detection circuit 260, and built into the newly added female switch SW1a. The other end of the paired terminal pair SW1c is connected to the input / output port 205 of the MPU 201 via a voltage dividing circuit constituted by resistors. Similarly, one end of a pair of terminal pairs SW2c incorporated in the newly added female switch SW2a is connected to the DC power source DC1 of the newly provided frame opening detection circuit 260, and the newly added female type The other end of the pair of terminals SW2c built in the switch SW2a is connected to the input / output port 205 of the MPU 201 via a voltage dividing circuit constituted by a resistor and to a port different from the other end of the terminal pair SW1c. Further, the MPU 201 is supplied from the DC power source DC1 by a voltage of 5 volts (the voltage dividing circuit detects the opening of the inner frame 12 when the inner frame 12 or the front frame 14 is opened and the switch SW1 or the switch SW2 is turned on. 12 volt voltage is reduced to 5 volts) or 5 volt voltage to detect the opening of the inner frame 14 (12 volt voltage supplied from the DC power supply DC1 is lowered to 5 volt by the voltage dividing circuit) ) Is input to the input / output port 205, a command indicating that the opening of the inner frame 12 or the front frame 14 is detected is transmitted to the audio lamp control device 113 and the display control device 114. At this time, the command transmitted from the MPU 201 includes a command when the opening of the inner frame 12 is detected (hereinafter referred to as “inner frame command”) and a command when the front frame 14 is released (hereinafter referred to as “ It is called “front frame command”). Then, the voice lamp control device 113 that has received each command performs notification in a different manner depending on whether the inner frame command is received or the front frame command is received. For example, a different warning sound is emitted from the audio output device 226 or the lighting mode of the lamp display device 227 is changed. In addition, the display control device 114 that has received each command displays different modes depending on whether the inner frame command is received or the front frame command is received. For example, when the display control device 114 receives an inner frame command, the third symbol display device 81 displays “the inner frame is open” or the display control device 114 receives a front frame command. The third symbol display device 81 may be configured to display “front frame is open”.

  In this way, a new combination of the male switch SW1b and the female switch SW1a is added to the switch SW1, and a new combination of the male switch SW2b and the female switch SW2a is added to the switch SW2 as well as the switch SW1. When one switch is used and the switch SW1 is turned on (when the inner frame 12 is opened), the MPU 201 sends an inner frame command to the audio lamp control device 113 and the display control device 114. Configure to send. Further, when the switch SW2 is turned on (when the front frame 14 is opened), the MPU 201 is configured to transmit a front frame command to the audio lamp control device 113 and the display control device 114. By configuring in this way, notification of a different aspect between when the inner frame 12 is opened and when the front frame 14 is opened is performed using the audio lamp control device 113 and the display control device 114. Can do. This makes it possible to accurately determine whether the switch SW1 is conductive (the inner frame 12 is opened), the switch SW2 is conductive (the front frame 14 is opened), or both, using the pachinko machine 10. Can be detected.

  Further, a frame opening detection circuit 260 and an external output terminal plate 261 are newly provided, and only the switch SW2 is connected to the newly provided frame opening detection circuit 260, and the existing frame opening detection circuit 260 has a switch SW1. When the switch SW1 is connected (the inner frame 12 is opened) by connecting only the switch SW2, the high signal output from the existing external output terminal board 261 to the hall computer 262 is stopped, and the switch SW2 is connected. When (the front frame 14 is opened), the high signal output from the newly provided external output terminal board 261 to the hall computer 262 can be stopped. Therefore, depending on the stop state of the high signal stored in the hall computer 262, the switch SW1 is conductive (the inner frame 12 is opened), the switch SW2 is conductive (the front frame 14 is opened), or both It is possible to accurately detect whether or not there has been.

  In the present embodiment, the high signal output from the external output terminal board 261 is output to the hall computer 262 having a different installation location from the pachinko machine 10, but the present invention is not limited to this. A dedicated storage device having the function of the hall computer 262 may be provided for each pachinko machine 10, and the dedicated storage device may be provided on the back side of each pachinko machine 10 provided with the main controller 110 and the like. In this case, more preferably, a dedicated storage device such as the main control device 110, the payout control device 111, and the launch control device 112 is stored in the substrate box, and the box base and the box cover provided in the substrate box are stored. Are connected by a sealing unit (not shown) so that they cannot be opened (connection by caulking structure). Then, a seal seal (not shown) is pasted on the connecting portion between the box base and the box cover over the box cover and the box base.

  Next, the display content of the third symbol display device 81 will be described with reference to FIG. FIG. 9 is a diagram for explaining the display screen of the third symbol display device 81, and FIG. 9A is a diagram schematically showing the area division setting and the effective line setting of the display screen, FIG. 9B is a diagram illustrating an actual display screen.

  The third symbol is composed of ten types of main symbols with numbers from “0” to “9” and one type of sub-shaped petal shape formed smaller than this main symbol. Each main symbol is composed of numbers from “0” to “9” on the rear symbol consisting of a wooden box, of which the main symbols with odd numbers (1, 3, 5, 7, 9) are A large number is added to almost the front of the wooden box. On the other hand, the main symbols with even numbers (0, 2, 4, 6, 8) are attached to the front of the wooden box almost fully, and attached symbols imitating characters such as furoshiki and helmets are added. An even number is small in green on the lower right side of the attached symbol and is added so as to be displayed on the front side of the attached symbol.

  Further, in the pachinko machine 10 according to the present embodiment, when the lottery result by the main controller 110 is a big win, a variable display in which the same main symbols are arranged is performed, and a big hit occurs after the variable display is finished. It is configured to When shifting to the high probability state (probability variation state) after the big hit, the variable display in which the main symbols (corresponding to “high probability symbols”) to which odd numbers are added is arranged. On the other hand, when shifting to the low probability state after the big hit, the variable display is performed in which the main symbols to which the even numbers are added (corresponding to “low probability symbols”) are arranged. Here, the high probability state refers to a state in which the subsequent jackpot probability is increased as an added value after the jackpot ends, that is, a so-called probability fluctuation (probability change). Further, the normal state (low probability state) refers to a time when the probability of hitting is not probable, and refers to a state where the probability of jackpot is normal, that is, a state where the probability of jackpot is lower than that during probability change.

  As shown in FIG. 9 (a), the display screen of the third symbol display device 81 is roughly divided into two vertically, and the lower 2/3 is the main display area Dm in which the third symbol is variably displayed, and the others. The upper third is a sub display area Ds for displaying a notice effect and a character.

  In the main display area Dm, three symbol rows Z1, Z2, and Z3 of left, middle, and right are displayed. In each symbol row Z1 to Z3, the above-described third symbols are displayed in a prescribed order. That is, in each symbol row Z1 to Z3, main symbols are arranged in ascending or descending numerical order, and one sub symbol is arranged between each main symbol. For this reason, a total of 20 third symbols of 10 main symbols and 10 sub-designs are set in each symbol row, and each symbol row Z1 to Z3 scrolls from top to bottom with periodicity. The display is changed. In particular, the left symbol row Z1 is arranged so that the numbers of the main symbols appear in descending order, and the middle symbol row Z2 and the right symbol row Z3 are arranged so that the numbers of the main symbols appear in ascending order.

  In the main display area Dm, the third symbols are displayed in the upper, middle, and lower three rows for each symbol row Z1 to Z3. Accordingly, the third symbol display device 81 displays a total of nine third symbols of 3 rows × 3 columns. In the main display area Dm, five effective lines, that is, an upper line L1, a middle line L2, a lower line L3, a right rising line L4, and a left rising line L5 are set. In each game, the variable display stops in the order of the left symbol row Z1 → the right symbol row Z3 → the middle symbol row Z2, and the combination of jackpot symbols on any active line at the time of the stop (in this embodiment, A jackpot moving image is displayed as a jackpot if the same combination of main symbols is arranged.

  The sub display area Ds is horizontally long above the main display area Dm, and is further equally divided into three notice areas Ds1 to Ds3 in the left-right direction. Here, the left and right notice areas Ds1, Ds3 are usually covered with double-open opaque doors that are electrically opened and closed by solenoids (not shown), and sometimes the solenoids are excited and the doors are on the front side. It is a display area that is visible to the player when it is opened. The center notice area Ds2 is a display area that is always visible without being covered by the door.

  As shown in FIG. 9B, on the actual display screen, a total of nine main symbols and sub-designs of the third symbol are displayed in the main display area Dm. In the sub display area Ds, the left and right doors are closed, and the left and right notice areas Ds1, Ds3 are covered and the display screen cannot be visually recognized. If either one of the left and right doors or both doors are opened during the variable display, a video is displayed in the left and right notice areas Ds1 and Ds3, and it is easy for the player to change to a big hit than usual. It is suggested. In the notice area Ds2 in the center, a predetermined character (a boy with a bee in this embodiment) usually performs a predetermined action, sometimes performs a special action different from the predetermined action, or another character A notice effect is performed by appearing. The display screen of the third symbol display device 81 is divided into upper and lower display areas Dm and Ds in principle, but the third symbol and characters are displayed larger across the display areas Dm and Ds. A display effect can be performed.

  Next, a counter and the like provided in the RAM 203 of the main controller 110 will be described with reference to FIG. These counters and the like are used by the MPU 201 of the main control device 110 to perform jackpot lottery, display setting of the first symbol display device 37, lottery of display results of the second symbol display device 82, and the like.

  For the jackpot lottery or display setting of the first symbol display device 37, the first hit random number counter C1 used for the jackpot lottery, the first hit type symbol counter C2 used for the jackpot symbol selection, and the stop pattern selection counter C3, a first initial value random number counter CINI1 used for setting the initial value of the first random number counter C1, and variation type counters CS1, CS2, and CS3 used for variation pattern selection are used. The second symbol random number counter C4 is used for the lottery of the second symbol display device 82, and the second initial random number counter CINI2 is used for setting the initial value of the second random number counter C4. Each of these counters is a loop counter that adds 1 to the previous value every time it is updated and returns to 0 after reaching the maximum value.

  Each counter is updated at an interval of 4 ms, which is an execution interval of the main process (see FIG. 12), or at an interval of 2 ms, an execution interval of the timer interrupt process (see FIG. 15), and the updated value is set in a predetermined area of the RAM 203. Stored in the counter buffer. The RAM 203 is provided with a holding ball storage area composed of one execution area and four holding areas (holding first to fourth areas). The values of the first per-random number counter C1, the first per-type counter C2, and the stop pattern selection counter C3 are stored in accordance with the ball winning timing.

  Each counter will be described in detail. The first random number counter C1 is configured so that, for example, 1 is added in order within a range of 0 to 738, and after reaching the maximum value (that is, 738), it returns to 0. In particular, when the first random number counter C1 makes one round, the value of the first initial value random number counter CINI1 at that time is read as the initial value of the first random number counter C1. The first initial value random number counter CINI1 is configured as a loop counter that is updated in the same range as the first per-random number counter C1 (value = 0 to 738), and each time the timer interrupt process (see FIG. 15) is executed. It is updated once and updated repeatedly within the remaining time of the main process (see FIG. 12). The value of the first per-random number counter C1 is updated, for example, periodically (in this embodiment, once for each timer interrupt process), and the stored ball is stored in the RAM 203 at the timing when the ball wins the first entrance 64. Stored in the area. The number of random number values that are jackpots is set at low probability and high probability, and the number of random numbers that are jackpots at low probability is 2, and the value is “373, 727” There are 14 random numbers that are big hits at high probability, and the values are "59, 109, 163, 211, 263, 317, 367, 421, 479, 523, 631, 683, 733".

  The first hit type counter C2 determines the display mode of the first symbol display device 37 at the time of the big hit. In the present embodiment, the first hit type counter C2 is incremented one by one within the range of 0 to 4, and the maximum value ( That is, it is configured to return to 0 after reaching 4). The value of the first hit type counter C2 is updated, for example, periodically (once every timer interruption process in this embodiment), and the stored ball is stored in the RAM 203 at the timing when the ball wins the first entrance 64. Stored in the area. In addition, the value of the random number that becomes the high probability state after the big hit is “1, 2, 3”, the value of the random number that becomes the low probability state after the big hit is “0, 4”, and two types of hit types are determined. The Therefore, the display mode corresponding to the stop symbol displayed on the first symbol display device 37 is a display mode corresponding to two types of jackpots of a high probability state and a low probability state, and one type of display mode corresponding to a deviation. Any one of the three display modes is selected.

  The stop pattern selection counter C3 is, for example, incremented by 1 in the range of 0 to 238, and returns to 0 after reaching the maximum value (that is, 238). In the present embodiment, the stop pattern selection counter C3 selects the effect pattern displayed on the third symbol display device 81, and after reaching, the final stop symbol is shifted by one before and after the reach symbol. “Stop before and after detachment reach” (for example, a range of 0 to 8), and “Leach other than detachment before and after detachment” (for example, a range of 9 to 38) after the reach has occurred and the final stop symbol stops other than before and after the reach design. The three stop (effect) patterns are selected as “completely out” (for example, a range of 39 to 238) that does not cause reach. The value of the stop pattern selection counter C3 is updated, for example, periodically (once every timer interrupt process in this embodiment), and the reserved ball storage area of the RAM 203 at the timing when the ball wins the first entrance 64. Stored in

  Further, the stop pattern selection counter C3 is provided with a plurality of tables having different ranges of random number values from which the stop pattern is selected. This depends on whether the current state of the pachinko machine 10 is a high probability state or a low probability state, in which area of the reserved ball storage area each random number value is stored (ie, the number of reserved balls), etc. This is to change the stop pattern selection ratio.

  For example, in a high probability state, a table with a wide random value range of 10 to 238 corresponding to the stop pattern of “completely out” is selected so that a jackpot is likely to occur and a reach effect is not selected more than necessary. It becomes easy to select “completely off”. In this table, “front / rear out of reach” is narrowed to 0-5, and “reach other than front / rear out of reach” is also narrowed to 6-9, making it difficult to select “rear out of front / rear out of reach” or “reach out of front / rear out of reach”. Further, if each random number value is not stored in the holding ball storage area in a low probability state, a disturbance corresponding to the stop pattern of “completely off” in order to secure the time for the ball to enter the first entrance 64. A table with a narrow numerical value range of 51 to 238 is selected, and “completely out” is difficult to select. In this table, the range of random numbers corresponding to the stop pattern of “reach other than front / rear deviation” is as wide as 9 to 50, and “reach other than front / rear deviation” is easily selected. Therefore, in the low probability state, the ball entry time to the first entrance 64 can be secured, and therefore, the variable display by the third symbol display device 81 is easily performed continuously.

  Of the two variation type counters CS1 and CS2, one variation type counter CS1 is incremented one by one within a range of 0 to 198, for example, and reaches a maximum value (that is, 198) and then returns to 0. On the other hand, the other variation type counter CS2 is, for example, incremented one by one within a range of 0 to 240, and returns to 0 after reaching the maximum value (that is, 240). In the following description, CS1 is also referred to as “first variation type counter”, and CS2 is also referred to as “second variation type counter”.

  Rough display modes such as so-called normal reach, super reach, and premium reach are determined by the first variation type counter CS1. Specifically, the display mode is determined by determining the variation time of the symbol variation. Further, the second variation type counter CS2 determines a variation time (in other words, the number of variation symbols) until the final stop symbol (in the present embodiment, the middle symbol) stops after the occurrence of reach. Based on the variation time determined by the variation type counters CS1 and CS2, the display control device 114 determines the reach type of the third symbol displayed on the third display device 81 and the detailed symbol variation mode. Therefore, a variety of variation patterns can be easily realized by combining these variation type counters CS1 and CS2. It is also possible to determine the symbol variation mode only by the first variation type counter CS1, or to determine the symbol variation mode similarly by combining the first variation type counter CS1 and the stop symbol. The values of the variation type counters CS1 and CS2 are updated once every time a main process (see FIG. 12) described later is executed once, and are repeatedly updated within the remaining time in the main process.

  For example, the value of the variation type counter CS3 is sequentially incremented by 1 within a range of 0 to 162, and returns to 0 after reaching the maximum value (that is, 162). In the following description, CS3 is also referred to as a “third variation type counter”. The 3rd symbol display device 81 of this Embodiment performs the decorative production according to the display mode of the 1st symbol display device 37, and can slide the symbol which is changing in addition to the variation of a symbol. A notice effect such as passing a notice character for notifying the occurrence of the reach effect is performed. The effect pattern of the notice effect is selected by the variation type counter CS3. Specifically, the time required for the notice effect is added to the variable time, or on the contrary, the variable time is subtracted to shorten the variable display time, or an effect pattern that does not add or subtract the variable time is selected. . As with the stop pattern selection counter C3, the variation type counter CS3 is provided with a plurality of tables with different ranges of random values from which the production pattern is selected, and whether the current state of the pachinko machine 10 is in a high probability state. Depending on the low probability state or in which area of the reserved ball storage area each random value is stored, the selection ratio of each effect pattern is different.

  As described above, the variation time of the symbol variation is determined by the variation type counters CS1 and CS2, and the time to be added to or subtracted from the variation time is determined by the variation type counter CS3. Therefore, the final fluctuation time until the final stop symbol stops is determined by the fluctuation type counters CS1, CS2, CS3.

  The second random number counter C4 is configured as a loop counter that is incremented one by one within a range of 0 to 250, for example, and returns to 0 after reaching the maximum value (that is, 250). In this embodiment, the value of the second random number counter C4 is updated periodically, for example, every timer interrupt process, and the ball has passed through the second entrance (through gate) 67 on either the left or right side. Obtained when detected. The number of random number values to be won is 149, and the range is “5 to 153”. The second initial value random number counter CINI2 is configured as a loop counter that is updated in the same range as the second per-random number counter C4 (value = 0 to 250), and is once per timer interrupt process (see FIG. 15). In addition to being updated, it is repeatedly updated within the remaining time of the main process (see FIG. 12).

  Next, each control process executed by the MPU 201 in the main controller 110 will be described with reference to the flowcharts of FIGS. 11 to 17. The processing of the MPU 201 is roughly divided into a startup process that is started when the power is turned on, a main process that is executed after the startup process, and a timer that is started periodically (in this embodiment, at a cycle of 2 ms). There are an interrupt process and an NMI interrupt process activated by the input of the power failure signal SG1 to the NMI terminal. For convenience of explanation, the timer interrupt process and the NMI interrupt process are described first, and then the startup process The main process will be described.

  FIG. 15 is a flowchart showing the timer interrupt process. The timer interrupt process is executed by the MPU 201 of the main control device 110, for example, every 2 ms. In the timer interrupt process, first, a process for reading various winning switches is executed (S501). That is, the state of various switches connected to the main controller 110 is read, and the state of the switch is determined and the detection information (winning detection information) is stored.

  Next, the first initial value random number counter CINI1 and the second initial value random number counter CINI2 are updated (S502). Specifically, the first initial value random number counter CINI1 is incremented by 1 and cleared to 0 when the counter value reaches the maximum value (738 in the present embodiment). Then, the updated value of the first initial value random number counter CINI 1 is stored in the corresponding buffer area of the RAM 203. Similarly, 1 is added to the second initial value random number counter CINI2, and when the counter value reaches the maximum value (250 in the present embodiment), it is cleared to 0, and the second initial value random number counter CINI2 is updated. The value is stored in the corresponding buffer area of the RAM 203.

  Further, the first per-random number counter C1, the first per-type counter C2, the stop pattern selection counter C3, and the second per-random number counter C4 are updated (S503). Specifically, 1 is added to each of the first per-random number counter C1, the first per-type counter C2, the stop pattern selection counter C3, and the second per-random number counter C4, and these counter values are the maximum values (this embodiment) Then, when they reach 738, 4, 238, 250), they are cleared to 0. Then, the updated values of the counters C1 to C4 are stored in the corresponding buffer area of the RAM 203.

  Thereafter, a start winning process (see FIG. 16) associated with winning in the first entrance 64 is executed (S504), a firing control process is executed (S505), and the timer interrupt process is terminated. Note that the launch control process detects that the player is touching the operation handle 51 with the touch sensor 51a and turns on the ball launch on the condition that the stop switch 51b for stopping the launch is not operated. This is a process for determining / off. The main controller 110 instructs the launch controller 112 to launch a sphere when the launch of the sphere is on.

  Here, the start winning process executed in the process of S504 will be described with reference to the flowchart of FIG. FIG. 16 is a flowchart showing the start winning process (S504) executed in the timer interrupt process (see FIG. 15).

  When this start winning process is executed, first, it is determined whether or not the ball has won a first winning opening 64 (start winning) (S601). If it is determined that the ball has won the first entrance 64 (S601: Yes), whether or not the number N of the operation reserved balls of the first symbol display device 37 is less than the upper limit (4 in the present embodiment). Is determined (S602). If there is a winning at the first entrance 64 and the number of operation-reserved balls N <4 (S602: Yes), the number N of operation-reserved balls is incremented by 1 (S603), and further updated in step S503. The values of the first per-random number counter C1, the first per-type counter C2, and the stop pattern selection counter C3 are stored in the first area among the free reserved areas in the reserved ball storage area of the RAM 203 (S604). On the other hand, if there is no winning at the first entrance 64 (S601: No), or even if there is a winning at the first entrance 64, if the number N of operational reserves is not N <4 (S602: No). , S603 and S604 are skipped, the start winning process is terminated, and the process returns to the timer interrupt process.

  FIG. 17 is a flowchart showing NMI interrupt processing. The NMI interruption process is a process executed by the MPU 201 of the main controller 110 when the power of the pachinko machine 10 is shut down due to the occurrence of a power failure or the like. By this NMI interrupt processing, the information on the occurrence of power interruption is stored in the RAM 203. That is, when the power of the pachinko machine 10 is cut off due to the occurrence of a power failure or the like, the power failure signal SG1 is output from the power failure monitoring circuit 252 to the NMI terminal of the MPU 201 in the main controller 110. Then, the MPU 201 interrupts the control being executed and starts the NMI interrupt process, stores the power-off occurrence information in the RAM 203 as a setting of the power-off occurrence information (S701), and ends the NMI interrupt process. To do.

  The above NMI interrupt process is executed in the same manner in the payout and emission control device 111, and information on the occurrence of power interruption is stored in the RAM 213 by the NMI interrupt process. That is, when the power of the pachinko machine 10 is cut off due to the occurrence of a power failure or the like, the power failure signal SG1 is output from the power failure monitoring circuit 252 to the NMI terminal of the MPU 211 in the payout and emission control device 111, and the MPU 211 interrupts the control being executed. Then, the NMI interrupt process is started.

  Next, referring to FIG. 11, a startup process when the main controller 110 is turned on will be described. FIG. 11 is a flowchart showing start-up processing executed by the MPU 201 in the main controller 110. This start-up process is activated by a reset at power-on. In the start-up process, first, an initial setting process associated with power-on is executed (S101). Specifically, a predetermined value set in advance in the stack pointer is set, and the sub-side control devices (peripheral control devices such as the audio lamp control device 113 and the payout control device 111) become operable. In order to wait, a wait process (1 second in this embodiment) is executed. Next, access to the RAM 203 is permitted (S103).

  Thereafter, it is determined whether or not the RAM erase switch 122 (see FIG. 3) provided in the power supply device 115 is turned on (S104). If it is turned on (S104: Yes), the process proceeds to S110. On the other hand, if the RAM erasure switch 122 is not turned on (S104: No), it is further determined whether or not the information on occurrence of power interruption is stored in the RAM 203 (S105), and if not stored (S105: No). Since there is a possibility that the process at the time of the previous power shutdown has not been completed normally, the process proceeds to S110 also in this case.

  If power failure occurrence information is stored in the RAM 203 (S105: Yes), a RAM determination value is calculated (S106). If the calculated RAM determination value is not normal (S107: No), that is, the calculated RAM If the determination value does not match the RAM determination value stored at the time of power-off, the backed up data has been destroyed. In such a case as well, the process proceeds to S110. Note that, as will be described later in the processing of S213 in FIG. Instead of the RAM determination value, the validity of the backup may be determined based on whether or not the keyword written in a predetermined area of the RAM 203 is correctly stored.

  In the process of S111, a payout initialization command is transmitted in order to initialize the payout control device 111 as a sub-side control device (peripheral control device) (S111). Upon receiving this payout initialization command, the payout control device 111 clears an area (work area) other than the stack area of the RAM 213, sets an initial value, and enters a state in which game ball payout control can be started. After transmitting the payout initialization command, main controller 110 executes initialization processing (S112, S113) of RAM 203.

  As described above, in the pachinko machine 10, when RAM data is initialized when the power is turned on, for example, when the hall starts business, the power is turned on while the RAM erase switch 122 is pressed. Therefore, if the RAM erase switch 122 is pressed during the start-up process, the RAM initialization process (S112, S113) is executed. Similarly, initialization processing (S112, S113) of the RAM 203 is executed even when the information on occurrence of power interruption is not set or when a backup abnormality is confirmed by the RAM determination value (checksum value or the like). . In the RAM initialization process (S112, S113), the used area of the RAM 203 is cleared to 0 (S112), and then the initial value of the RAM 203 is set (S113). After executing the initialization process of the RAM 203, the process proceeds to S110.

  On the other hand, if the RAM erase switch 122 is not turned on (S104: No), the information on occurrence of power interruption is stored (S105: Yes), and the RAM judgment value (checksum value etc.) is normal ( S107: Yes), the information on the occurrence of power interruption is cleared while the backed up data is held in the RAM 203 (S108). Next, a payout return command at the time of power recovery for returning the sub-side control device (peripheral control device) to the gaming state at the time of driving power interruption is transmitted (S109), and the process proceeds to S110. When the payout control device 111 receives this payout return command, the payout control device 111 is in a state where the payout control of the game ball can be started while holding the data stored in the RAM 213. In the process of S110, the interruption is permitted and the process proceeds to a main process described later.

  Next, with reference to FIG. 12, the main process executed after the above-described startup process will be described. FIG. 12 is a flowchart showing main processing executed by the MPU 201 in the main controller 110. In this main process, the main process of the game is executed. As an outline, each process of S201 to S206 is executed as a periodic process with a period of 4 ms, and the counter update process of S209 and S210 is executed in the remaining time.

  In the main process, first, output data such as a command updated in the previous process is transmitted to each control device (peripheral control device) on the sub-side (S201). Specifically, the presence / absence of winning detection information detected in the switch reading process of S501 is determined, and if there is winning detection information, a winning ball command corresponding to the number of acquired balls is transmitted to the payout control device 111. In addition, by this external output process, a variation pattern command, a stop symbol command, a stop command, an effect time addition command, etc. necessary for the third symbol variation display by the third symbol display device 81 are transmitted to the sound lamp control device 113. Further, when launching a sphere, a sphere launch signal is transmitted to the launch controller 112.

  Next, each value of the variation type counters CS1, CS2, CS3 is updated (S202). Specifically, 1 is added to the variation type counters CS1, CS2, and CS3, and when the counter values reach the maximum values (198, 240, and 162 in this embodiment), they are cleared to 0, respectively. Then, the update values of the variation type counters CS 1, CS 2, and CS 3 are stored in the corresponding buffer area of the RAM 203.

  When the update of the variation type counters CS1, CS2 and CS3 is completed, the winning ball counting signal and the payout abnormality signal received from the payout control device 111 are read (S203), and the process for displaying on the first symbol display device 37 is performed. A variation process for setting a variation pattern of the third symbol and the like by the three symbol display device 81 is executed (S204). Details of the variation process will be described later with reference to FIG.

  After the end of the variation process, a large opening opening / closing process for opening or closing the specific winning opening (large opening) 65a of the variable winning device 65 is executed in the case of the big win state (S205). That is, the specific winning opening 65a is opened for each round of the big hit state, and it is determined whether the maximum opening time of the specific winning opening 65a has elapsed or whether a specified number of balls have won the specific winning opening 65a. When any of these conditions is met, the specific winning opening 65a is closed. The opening and closing of the specific winning opening 65a is repeated for a predetermined number of rounds.

  Next, a display control process of the second symbol (for example, the symbol “◯” or “x”) by the second symbol display device 82 is executed (S206). Briefly, on the condition that the ball has passed through the second entrance (through gate) 67, the value of the second random number counter C4 is acquired at the timing of the passage, and the second symbol display device 82 is obtained. In the display unit 83, the second symbol variation display is performed. Then, the lottery of the second symbol is performed according to the value of the second winning random number counter C4, and when the winning state of the second symbol is reached, the electric accessory attached to the first entrance 64 is released for a predetermined time.

  Thereafter, it is determined whether or not the power failure occurrence information is stored in the RAM 203 (S207). If the power failure occurrence information is not stored in the RAM 203 (S207: No), a power failure signal is output from the power failure monitoring circuit 252. SG1 is not output and the power supply is not shut off. Therefore, in such a case, it is determined whether or not the execution timing of the next main process has been reached, that is, whether or not a predetermined time (4 ms in the present embodiment) has elapsed since the start of the previous main process (S208). If the predetermined time has already elapsed (S208: Yes), the process proceeds to S201, and the processes after S201 described above are repeatedly executed.

  On the other hand, if the predetermined time has not yet elapsed since the start of the previous main process (S208: No), the first time is reached until the predetermined time, that is, within the remaining time until the next main process execution timing. The updating of the initial value random number counter CINI1, the second initial value random number counter CINI2, and the variation type counters CS1, CS2, and CS3 is repeatedly executed (S209, S210).

  First, the first initial value random number counter CINI1 and the second initial value random number counter CINI2 are updated (S209). Specifically, 1 is added to the first initial value random number counter CINI1 and the second initial value random number counter CINI2, and when the counter value reaches the maximum value (738, 250 in this embodiment), it is cleared to 0. To do. Then, the updated values of the first initial value random number counter CINI1 and the second initial value random number counter CINI2 are stored in the corresponding buffer areas of the RAM 203, respectively.

  Next, the fluctuation type counters CS1, CS2, and CS3 are updated (S210). Specifically, 1 is added to the variation type counters CS1, CS2, and CS3, and when the counter values reach the maximum values (198, 240, and 162 in this embodiment), they are cleared to 0, respectively. Then, the update values of the variation type counters CS1, CS2, and CS3 are stored in the corresponding buffer areas of the RAM 203, respectively.

  Here, since the execution time of each process of S201-S206 changes according to the state of the game, the remaining time until the next main process execution timing is not constant and varies. Therefore, by repeatedly performing the update of the first initial value random number counter CINI1 and the second initial value random number counter CINI2 using the remaining time, the first initial value random number counter CINI1 and the second initial value random number counter CINI2 (that is, , The initial value of the first per-random number counter C1 and the initial value of the second per-random number counter C4) can be updated at random. Similarly, the variation type counters CS1, CS2, and CS3 can be updated at random.

  In the process of S207, if the power failure occurrence information is stored in the RAM 203 (S207: Yes), the power failure is caused by the occurrence of a power failure or the power is turned off, and the power failure monitoring circuit 252 outputs the power failure signal SG1. As a result, since the NMI interrupt process of FIG. 17 has been executed, the power-off process after S211 is executed. First, the generation of each interrupt process is prohibited (S211), and a power-off notification command indicating that the power has been cut off is sent to other control devices (peripheral control devices such as the payout control device 111 and the sound lamp control device 113). It transmits to (S212). Then, the RAM determination value is calculated and stored (S213), access to the RAM 203 is prohibited (S214), and the infinite loop is continued until the power supply is completely shut down and the process cannot be executed. Here, the RAM determination value is, for example, a checksum value in the stack area and work area to be backed up in the RAM 203.

  Note that the processing of S207 is performed at the timing when the series of processing corresponding to the game state change performed in S201 to S206 is completed, or at the end of one cycle of the processing of S209 and S210 performed within the remaining time. It is running. Therefore, in the main process of the main controller 110, the occurrence information of the power supply interruption is confirmed at the timing when each setting is completed. Therefore, when returning from the power interruption state, the process is performed after the start-up process is completed. It can start from the process of S201. That is, the process can be started from the process of S201 as in the case where the process is initialized in the startup process. Therefore, in the process at power-off, the stack pointer is not stored in the initial setting process (S101) without saving the contents of each register used by the MPU 201 to the stack area or saving the value of the stack pointer. By setting to a predetermined value (initial value), it is possible to start from the process of S201. Therefore, it is possible to reduce the control burden on the main control device 110 and to perform accurate control without causing the main control device 110 to malfunction or run away.

  Next, the fluctuation process (S204) will be described with reference to FIG. FIG. 13 is a flowchart showing the variation process (S204) executed in the main process (see FIG. 12). In this variation process, first, it is determined whether or not a big hit is currently being made (S301). The jackpot includes the jackpot game displayed on the third symbol display device 81 and the first symbol display device 37 in the jackpot and the middle of a predetermined time after the jackpot game ends. As a result of the determination, if it is a big hit (S301: Yes), this processing is terminated as it is.

  If it is not a big hit (S301: No), it is determined whether or not the display mode of the first symbol display device 37 is changing (S302), and if the display mode of the first symbol display device 37 is not changing. (S302: No), it is determined whether or not the number N of active suspension balls is greater than 0 (S303). If the number N of active balls is 0 (S303: No), this process is terminated. If the number of the operation hold balls N> 0 (S303: Yes), the operation hold ball number N is decremented by 1 (S304), and the data stored in the hold ball storage area is shifted (S305). This data shift process is a process of sequentially shifting the data stored in the reserved first to fourth areas of the reserved ball storage area to the execution area side, and the reserved first area → execution area, reserved second area → The data in each area is shifted such as the first hold area, the third hold area → the second hold area, the fourth hold area → the third hold area. After the data shift process, the fluctuation start process of the first symbol display device 37 is executed (S306). The variation start process will be described later with reference to FIG.

  In the process of S302, if it is determined that the display mode of the first symbol display device 37 is changing (S302: Yes), it is determined whether or not the change time has elapsed (S307). The display time during the change of the first symbol display device 37 is determined according to the change pattern selected by the change type counters CS1 and CS2 and the addition time selected by the change type counter CS3. If it has not elapsed (S307: No), the display of the first symbol display device 37 is updated (S308).

  In the present embodiment, among the LEDs 37a of the first symbol display device 37, for example, if the currently lit LED is red until the variation time elapses after the variation starts, the red LED is Turn off and turn on the green LED. If the green LED is on, turn off the green LED and turn on the blue LED. If the blue LED is on, turn on the blue LED. A display mode for turning off the red LED and turning on the red LED is set.

  Note that the variation process is executed every 4 ms, but if the LED lighting color is changed every time the variation process is executed, the player cannot confirm the change in the LED lighting color. Therefore, a counter (not shown) is counted once each time the variation process is executed so that the player can confirm the change in the lighting color of the LED. Change the lighting color of. That is, the lighting color of the LED is changed every 0.4 s. The counter value is reset to 0 when the lighting color of the LED is changed.

  On the other hand, if the variation time of the first symbol display device 37 has elapsed (S307: Yes), a display mode corresponding to the stop symbol of the first symbol display device 37 is set (S309). In the setting of the stop symbol, whether or not a big hit is determined according to the value of the first per-random number counter C1, and in the case of a big hit, a symbol that becomes a high probability state after the big hit by the value of the first per-type type counter C2 Or a symbol that is in a low probability state is determined. In this embodiment, a red LED is turned on when a high probability state is reached after a big hit, a green LED is turned on when a low probability state is reached, and a blue LED is turned on when it is out of place. . In addition, although the lighting of each LED is released when the next fluctuation display is started, it may be turned on only for a few seconds after the fluctuation stops.

  When the display mode of the first symbol display device 37 corresponding to the stop symbol is set in the processing of S309, the variation stop of the third symbol display device 81 is stopped to synchronize with the lighting of the LED in the first symbol display device 37. A command is set (S310). When the sound lamp control device 113 receives this stop command, it instructs the display control device 114 to stop. When the variation time elapses, the third symbol display device 81 stops the variation, and receives the stop command, whereby one variation effect in the third symbol display device 81 ends.

  Next, the variation start process will be described with reference to FIG. FIG. 14 is a flowchart showing the change start process (S306) executed in the change process (see FIG. 13). In the variation start process (S306), first, it is determined whether or not a big hit is made based on the value of the first hit random number counter C1 stored in the execution area of the reserved ball storage area (S401). Whether or not it is a big hit is determined based on the relationship between the value of the first random number counter C1 and the mode at that time. As described above, “373,727” is a winning value among the numerical values 0 to 738 of the first random number counter C1 at the normal low probability, and “59, 109, 163, 211, 263, 317, 367, "421,479,523,631,683,733" is the winning value.

  When it is determined that it is a big hit (S401: Yes), the value of the first hit type counter C2 stored in the execution area of the reserved ball storage area is confirmed, and the display mode for the big hit is set (S402). ). In the process of S402, based on the value of the first hit type counter C2, whether to shift to the high probability state or shift to the low probability state after the big hit is set. When the transition state after the big hit is set, the display mode of the first symbol display device 37 (the lighting state of the LED 37a) is set. Further, based on the transition state after the jackpot, the jackpot stop symbol stopped and displayed on the third symbol display device 81 is set by the sound lamp control device 113 and the display control device 114. That is, the stop symbol in the third symbol display device 81 is set by setting the transition state after the big hit by the process of S402. Of the numerical values 0 to 4 of the first hit type counter C2, when “0, 4”, the state shifts to the low probability state, and when “1, 2, 3”, the state shifts to the high probability state. .

  Next, a variation pattern at the time of jackpot is determined (S403). When the variation pattern is set in the process of S403, the display time of the first symbol display device 37 is set and the variation time of the third symbol until the third symbol display device 81 stops at the jackpot symbol is determined. The At this time, the values of the fluctuation type counters CS1 and CS2 stored in the counter buffer of the RAM 203 are confirmed, and rough symbol fluctuations such as normal reach, super reach, and premium reach are determined based on the value of the first fluctuation type counter CS1. In addition to determining the variation time, the variation time (in other words, the number of variation symbols) until the final stop symbol (in the present embodiment, the middle symbol Z2) stops after the occurrence of reach is determined based on the value of the second variation type counter CS2. decide.

  The relationship between the numerical value of the first variation type counter CS1 and the variation time, and the relationship between the numerical value of the second variation type counter CS2 and the variation time are respectively defined in advance by a table or the like. However, the fluctuation time can be set using only the value of the first fluctuation type counter CS1 without using the value of the second fluctuation type counter CS2, and can be set only with the value of the first fluctuation type counter CS1. Whether or not to set with both values of both variation type counters CS1 and CS2 is appropriately determined according to the value of the first variation type counter CS1 and the game conditions each time.

  If it is determined in the process of S401 that it is not a big hit (S401: No), the display mode at the time of disconnection is set (S404). In the process of S404, the display mode of the first symbol display device 37 is set to the display mode corresponding to the off symbol, and based on the value of the stop pattern selection counter C3 stored in the execution area of the reserved ball storage area, An effect to be displayed on the third symbol display device 81 is set to indicate whether the reach is front / rear out of reach, reach other than front / rear out, or complete out. In the present embodiment, as described above, the range of values corresponding to each stop pattern of the stop pattern selection counter C3 depends on the high probability state, the low probability state, and the operation suspension number N. Different tables are set up.

  Next, the variation pattern at the time of detachment is determined (S405), the display time of the first symbol display device 37 is set, and the variation time of the third symbol until the third symbol display device 81 stops at the detachment symbol. Is determined. At this time, as in the process of S403, the values of the variation type counters CS1 and CS2 stored in the counter buffer of the RAM 203 are confirmed, and the normal reach, super reach, and premium reach are determined based on the value of the first variation type counter CS1. In addition to determining the fluctuation time of the rough symbol variation such as, the variation time until the final stop symbol (the middle symbol Z2 in the present embodiment) stops after the reach occurs based on the value of the second variation type counter CS2 (in other words, paraphrase) For example, the number of fluctuation symbols) is determined.

  When the process of S403 or the process of S405 is completed, the effect time to be added to or subtracted from the variation time determined by the first and second type counters CS1 and CS2 is determined (S406). At this time, the addition / subtraction of effect time is determined based on the value of the third type counter CS3 stored in the counter buffer of the RAM 203, the display time of the first symbol display device 37 is set, and the third symbol display The variation time of the device 81 is set. In the present embodiment, the effect time addition / subtraction is determined according to the value of the third variation type counter CS3 when the variation display time is not changed and when the variation display time is added for one second, the variation display time is set to 2. In the case of adding seconds, four types of addition values are determined for the case of subtracting 1 second from the variable display time.

  In addition, when the variable display time is added or subtracted, a notice effect that increases the expected value of the jackpot on the third symbol display device 81 (for example, a slip effect that causes the change time of the variable symbol to be longer than usual and is accompanied by a slip) An effect of displaying a notice character is produced, for example, an effect of making the change time of one change symbol shorter than usual and stopping it immediately). In addition, when the value of the first random number counter C1 is a big hit, the probability that an added value of 2 seconds is selected is set high, so that the player expects a big hit by confirming the notice effect. Can do.

  Next, a variation pattern command is set according to the variation pattern (variation time) determined in S403 or S405 (S407), and a stop symbol command is set according to the stop symbol set in S402 or S404. (S408). Then, an effect time addition command is set according to the effect time addition value determined in the process of S406 (S409), and the process returns to the variation process.

  As described above, according to the pachinko machine 10 of the present embodiment, when the inner frame 12 or the front frame 14 is opened, the inner frame 12 or the front frame 14 is opened. For about 10 ms, conduction between the collector terminal c of the transistor TR1 and the emitter terminal e of the transistor TR1 is cut off. Then, since the current to one end of the resistor R7 is stopped for about 10 ms, the current to the light emitting diode which is the primary side of the photocoupler PR1 is also stopped for about 10 ms. Therefore, the high signal output from the light receiving element (phototransistor) on the secondary side of the photocoupler PR1 to the hall computer 262 is stopped for about 10 ms. This stoppage of the high signal is stored in the hall computer 262 that continues to operate for 24 hours. Therefore, by using the frame opening detection circuit 260 and the external output terminal board 261, the hall computer 262 can memorize that the inner frame 12 has been opened or the front frame 14 has been opened.

  Further, according to the pachinko machine 10 of the present embodiment, when the inner frame 12 and the front frame 14 are closed, and when about 10 ms has elapsed since the inner frame 12 or the front frame 14 was opened, A high signal is output from the light receiving element (phototransistor) on the secondary side of the photocoupler PR1 of the external output terminal plate 261 to the hall computer 262. On the other hand, as described above, when the inner frame 12 or the front frame 14 is in the open state, the high signal output from the phototransistor to the hall computer 262 is in the stop state, but the period in which the high signal is in the stop state. Is about 10 ms.

  Here, the light receiving element (phototransistor) on the secondary side of the photocoupler PR1 of the external output terminal plate 261 is connected to the hall computer 262 using a communication cable (not shown). When the signal is cut (damaged) by, the high signal output from the phototransistor to the hall computer 262 exceeds about 10 ms and is always stopped.

  Therefore, when the high signal output to the hall computer 262 from the light receiving element (phototransistor) that is the secondary side of the photocoupler PR1 of the external output terminal plate 261 is stopped for more than about 10 ms, The disconnection (breakage) of the communication cable connecting the transistor and the hall computer 262 can be detected. Therefore, in addition to being able to detect the opening of the inner frame 12 or the front frame 14 from the high signal stop state period stored in the hall computer 262, the communication cable connecting the phototransistor and the hall computer 262 is disconnected (damaged). Etc. can also be detected.

  In addition, the semiconductor components used for the open frame detection circuit 260 and the external output terminal board 261 may be destroyed by impact, static electricity, or the like. This destruction destroys the semiconductor used for the semiconductor components. Therefore, in general, an open breakdown (a breakdown in which the terminals of the semiconductor components are opened) is more likely to occur than a short breakdown (a breakdown in which the terminals of the semiconductor components are in a short circuit). When the semiconductor component is open broken, no current is supplied to the semiconductor component, so that no normal voltage is output from the semiconductor component. Then, since a normal current is not supplied to the photocoupler PR1, there is no abnormality in the communication cable connecting the light receiving element (phototransistor) on the secondary side of the photocoupler PR1 of the external output terminal plate 261 and the hall computer 262. However, the high signal output from the phototransistor to the hall computer 262 exceeds about 10 ms and is always stopped.

  Therefore, although there is no abnormality in the communication cable that connects the light receiving element (phototransistor) that is the secondary side of the photocoupler PR1 of the external output terminal plate 261 and the hall computer 262, the high output that is output from the phototransistor to the hall computer 262. When the signal is stopped after approximately 10 ms, the breakage of the frame opening detection circuit 260 or the external output terminal board 261 can be detected. Therefore, in addition to being able to detect the opening of the inner frame 12 or the front frame 14 from the high signal stop state period stored in the hall computer 262, the frame opening detection circuit 260 or the external output terminal plate 261 is also destroyed (abnormal). Can be detected.

  Further, according to the pachinko machine 10 of the present embodiment, the frame open detection circuit 260 is provided with the storage battery SB1, so that power is supplied to the pachinko machine 10 and a DC voltage of 12 volts from the DC power supply DC1. In addition to the case where, for example, the business hours of the amusement hall are over, the power supply to the pachinko machine 10 is cut off, and the DC voltage of 12 volts is not supplied from the DC power supply DC1. The frame opening detection circuit 260 can detect the opening of the inner frame 12 and the opening of the front frame 14.

  Next, a pachinko machine according to a second embodiment will be described with reference to FIGS. 18 and 19. The pachinko machine of the second embodiment is obtained by changing the frame opening detection circuit 260 of the pachinko machine 10 of the first embodiment to a frame opening detection circuit 270 having another configuration. The frame opening detection circuit 270 of the second embodiment has a simplified circuit configuration compared to the frame opening detection circuit 260 of the first embodiment. Specifically, the frame opening detection circuit 270 of the second embodiment removes the timer IC1, the resistors R1 to R3, the capacitors CD3 to CD5, and the EXOR circuit IC2 from the frame opening detection circuit 260 of the first embodiment, and the resistor R8. The circuit configuration is simplified by adding a resistor R9 and changing the connection of each component.

  According to the frame open detection circuit 270 of the second embodiment, the period during which the high signal output from the light receiving element (phototransistor) on the secondary side of the photocoupler PR1 to the hall computer 262 is stopped is set to the inner frame 12. Or it can change according to the open period of the front frame 14. Therefore, in addition to being able to detect the opening of the inner frame 12 or the front frame 14, it is also possible to detect the opening period of the inner frame 12 or the front frame 14.

  FIG. 18 is a circuit diagram showing an electrical configuration of the frame opening detection circuit 270 of the second embodiment. In addition, the same number is attached | subjected to the part same as the frame open | release detection circuit 260 of 1st Embodiment mentioned above in FIG. 7, the description is abbreviate | omitted, and only a different part is demonstrated.

  The positive terminal of the storage battery SB1 is connected to one end of a 6 kΩ resistor R9 and to one end of a resistor R7 of the external output terminal plate 261. The other end of the resistor R9 is connected to one ends of the switch SW1 and the switch SW2, and is connected to one end of a 10 kΩ resistor R8. The other end of the resistor R8 is connected to one end of the capacitor CD2, one end of the resistor R4, and one end of the resistor R5. Note that the other ends of the switch SW1 and the switch SW2 are grounded.

  The resistor R9 is a voltage (about 11) applied to the resistor R8 and the resistor R4 when the inner frame 12 and the front frame 14 are in the closed state and the switch SW1 and the switch SW2 are in the cutoff state (see FIG. 5A). .0 volts) is a pull-up resistor. The voltage applied to the resistor R8 and the resistor R4 is about 11.3 volts (the voltage at the plus terminal of the storage battery SB1) (the voltage drop at the diode D1 is about 0.7 volts from the 12 volts supplied from the DC power source DC1). Is approximately 11.0 volts minus a voltage drop of about 0.3 volts at resistor R9.

  Therefore, when the inner frame 12 and the front frame 14 are in the closed state and the switch SW1 and the switch SW2 are in the cut-off state (see FIG. 5A), the voltage applied to the resistor R8 and the resistor R4 is the plus of the storage battery SB1. The voltage is about 11.0 volts which is the same as the terminal voltage. The resistor R8 and the resistor R4 constitute a circuit that divides the voltage applied to the resistor R8 and the resistor R4. As described above, the resistance values of the resistor R8 and the resistor R4 are each 10 kΩ. Accordingly, when the inner frame 12 and the front frame 14 are in the closed state and the switch SW1 and the switch SW2 are in the cut-off state (see FIG. 5A), a voltage of about 11.0 volts applied to the resistor R8 and the resistor R4. Is divided by resistors R8 and R4 to a maximum value of about 5.5 volts respectively.

  Thus, when the inner frame 12 and the front frame 14 are in the closed state and the switch SW1 and the switch SW2 are in the cut-off state (see FIG. 5A), the DC voltage is applied to the resistor R4. The collector terminal c and the emitter terminal e of the transistor TR1 are electrically connected, and a high signal is output from the secondary light receiving element (phototransistor) of the photocoupler PR1 to the hall computer 262.

  On the other hand, when either the inner frame 12 or the front frame 14 is in an open state and either the switch SW1 or the switch SW2 is in a conductive state, or both the inner frame 12 and the front frame 14 are in an open state. When both the switch SW1 and the switch SW2 are in the conductive state (see FIG. 5B), the voltage applied to the resistor R8 and the resistor R4 is zero volts.

  Thus, when either the inner frame 12 or the front frame 14 is in an open state and either the switch SW1 or the switch SW2 is in a conductive state, or both the inner frame 12 and the front frame 14 are open. When the switch SW1 and the switch SW2 are both in a conductive state (see FIG. 5B), the DC voltage supplied to the resistor R4 is cut off during the open period, and the collector terminal c of the transistor TR1 And the emitter terminal e of the transistor TR1 are disconnected. Then, during this open period, the current supplied to the light emitting diode on the primary side of the photocoupler PR1 is cut off. As a result, either the inner frame 12 or the front frame 14 is open, and either the switch SW1 or the switch SW2 is in a conductive state, or both the inner frame 12 and the front frame 14 are open. During the period when both the switch SW1 and the switch SW2 are in the conductive state, the high signal output from the light receiving element (phototransistor) on the secondary side of the photocoupler PR1 to the hall computer 262 is stopped.

  Therefore, according to the frame open detection circuit 270 of the second embodiment, the period during which the high signal output from the light receiving element (phototransistor) on the secondary side of the photocoupler PR1 to the hall computer 262 is in the stopped state is 12 or the opening period of the front frame 14 can be changed. The stop state of the high signal is stored in the hall computer 262 that continues to operate for 24 hours. Therefore, according to the frame opening detection circuit 270 of the second embodiment, in addition to detecting the opening of the inner frame 12 or the front frame 14, it is also possible to detect the opening period of the inner frame 12 or the front frame 14. .

  Further, since the frame opening detection circuit 270 is provided with the storage battery SB1, the frame opening detection circuit 270 is supplied with power to the pachinko machine and supplied with a DC voltage of 12 volts from the DC power supply DC1. In addition to the case, for example, even when the business hours of the amusement hall are over and the power supply to the pachinko machine is cut off and the DC voltage of 12 volts is not supplied from the DC power supply DC1, In addition to being able to detect the opening of the frame 14, the opening period of the inner frame 12 or the front frame 14 can also be detected.

  Next, referring to FIG. 19, the voltage (A) of the frame open detection circuit 270 changes according to the state of the switch SW1 (the state of the inner frame 12) and the state of the switch SW2 (the state of the front frame 14). 18) and the output of the external output terminal board 261 (input of the hall computer 262) will be described. FIG. 19 shows the state of the switch SW1 (the state of the inner frame 12), the state of the switch SW2 (the state of the front frame 14), the voltage A of the frame open detection circuit 270, and the output of the external output terminal plate 261 (of the hall computer 262). 6 is a timing chart showing a relationship of (input). Each time from t1 to t8 shown in FIG. 19 is the same as each time from t1 to t8 shown in the timing chart of the frame opening detection circuit 260 of the first embodiment shown in FIG. is there.

  As shown in FIG. 19A, when the switch SW1 is in a conductive state (the inner frame 12 is in an open state) at t1, the frame open detection circuit 270 follows this, as shown in FIG. 19C. The voltage of A (see FIG. 18) switches from about 11.0 volts to zero volts (at time t1). As a result, the terminal between the collector terminal and the emitter terminal of the transistor TR1 of the frame opening detection circuit 270 is cut off, and the current supply to one end of the resistor R7 of the external output terminal plate 261 is stopped. Accordingly, as shown in FIG. 19D, the output of the secondary light receiving element (phototransistor) of the photocoupler PR1, that is, the output of the external output terminal plate 261 switches from the high state to the low state (t1). Time). Accordingly, the high signal output from the external output terminal board 261 to the hall computer 262 is stopped.

  Then, as shown in FIG. 19A, when the switch SW1 is in the cut-off state (the inner frame 12 is closed) at t2, as shown in FIG. 19C, the voltage of A of the frame open detection circuit 270 is obtained. Switches from zero volts to about 11.0 volts (at t2). As a result, the collector terminal and the emitter terminal of the transistor TR1 of the frame open detection circuit 270 are turned on again, and the current supply to one end of the resistor R7 of the external output terminal plate 261 is resumed. Therefore, as shown in FIG. 19D, the output of the external output terminal plate 261 switches from the low state to the high state (at time t2). Therefore, a high signal is output again from the external output terminal board 261 to the hall computer 262.

  As described above, when the inner frame 12 is opened and the switch SW1 is turned on (from time t1 to time t2), the high signal output from the external output terminal board 261 to the hall computer 262 during the period is in the stopped state. (From t1 to t2). The high signal stop state is stored in the hall computer 262.

  Next, as shown in FIG. 19 (b), when the switch SW2 becomes conductive at time t3 (the front frame 14 is in the open state), the frame opens as shown in FIG. 19 (c). The voltage of A in the detection circuit 270 (see FIG. 18) is switched from about 11.0 volts to zero volts (at time t3). As a result, the terminal between the collector terminal and the emitter terminal of the transistor TR1 of the frame opening detection circuit 270 is cut off, and the current supply to one end of the resistor R7 of the external output terminal plate 261 is stopped. Accordingly, as shown in FIG. 19D, the output of the light receiving element (phototransistor) on the secondary side of the photocoupler PR1, that is, the output of the external output terminal plate 261 switches from the high state to the low state (t3). Time). Accordingly, the high signal output from the external output terminal board 261 to the hall computer 262 is stopped.

  Then, as shown in FIG. 19B, when the switch SW2 is in the cut-off state (the front frame 14 is closed) at t4, as shown in FIG. 19C, the voltage of A of the frame open detection circuit 270 Switches from zero volts to about 11.0 volts (at t4). As a result, the collector terminal and the emitter terminal of the transistor TR1 of the frame open detection circuit 270 are turned on again, and the current supply to one end of the resistor R7 of the external output terminal plate 261 is resumed. Therefore, as shown in FIG. 19D, the output of the external output terminal plate 261 switches from the low state to the high state (at time t4). Therefore, a high signal is output again from the external output terminal board 261 to the hall computer 262.

  As described above, when the front frame 14 is opened and the switch SW2 is turned on (from time t3 to time t4), the high signal output from the external output terminal board 261 to the hall computer 262 during the period is in the stopped state. (From t3 to t4). The high signal stop state is stored in the hall computer 262.

  Finally, a case will be described in which the switch SW2 is in a conductive state (the front frame 14 is in an open state) when the switch SW1 is in a conductive state (the inner frame 12 is in an open state). As shown in FIG. 19A, at time t5, the switch SW1 becomes conductive (inner frame 12 is open), and as shown in FIG. 19B, at time t6, switch SW2 becomes conductive (front surface). When the frame 14 is in the open state), as shown in FIG. 19C, the voltage A (see FIG. 18) of the frame open detection circuit 270 switches from about 11.0 volts to zero volts at t5. As a result, the terminal between the collector terminal and the emitter terminal of the transistor TR1 of the frame opening detection circuit 270 is cut off, and the current supply to one end of the resistor R7 of the external output terminal plate 261 is stopped. Accordingly, as shown in FIG. 19D, the output of the light receiving element (phototransistor) on the secondary side of the photocoupler PR1, that is, the output of the external output terminal plate 261 switches from the high state to the low state (t5). Time). Accordingly, the high signal output from the external output terminal board 261 to the hall computer 262 is stopped.

  As shown in FIG. 19 (a), at time t7, the switch SW1 is in the cut-off state (the inner frame 12 is closed), and as shown in FIG. 19 (b), at time t8, the switch SW2 is in the cut-off state. When the front frame 14 is in the closed state, as shown in FIG. 19C, the voltage of A in the frame open detection circuit 270 switches from zero volts to about 11.0 volts at t8. As a result, the collector terminal and the emitter terminal of the transistor TR1 of the frame open detection circuit 270 are turned on again, and the current supply to one end of the resistor R7 of the external output terminal plate 261 is resumed. Accordingly, as shown in FIG. 19D, the output of the external output terminal plate 261 switches from the low state to the high state (at time t8). Therefore, a high signal is output again from the external output terminal board 261 to the hall computer 262.

  As described above, after the inner frame 12 is opened and the switch SW1 is turned on, the front frame 14 is closed and the switch SW2 is turned off (from t5 to t8). The high signal output from the terminal board 261 to the hall computer 262 is stopped (from t5 to t8). The high signal stop state during the period from t5 to t8 is stored in the hall computer 262 that continues to operate for 24 hours. As described above, when the switch SW1 and the switch SW2 are in the conductive state (the inner frame 12 and the front frame 14 are in the open state), the frame open detection circuit 270 has either one of the switch SW1 or the switch SW2 in the conductive state (the inner frame 12). 12 until the switch SW1 and the switch SW2 are both shut off (both the inner frame 12 and the front frame 14 are closed). The high signal output from the output terminal board 261 to the hall computer 262 can be stopped.

  As described above, according to the pachinko machine of the second embodiment, the period in which the high signal output from the light receiving element (phototransistor) on the secondary side of the photocoupler PR1 to the hall computer 262 is stopped is set to the inner frame 12. Or it can change according to the open period of the front frame 14. As described above, the stop state of the high signal is stored in the hall computer 262 that continues to operate for 24 hours. Therefore, according to the frame opening detection circuit 270 of the second embodiment, in addition to detecting the opening of the inner frame 12 or the front frame 14, it is also possible to detect the opening period of the inner frame 12 or the front frame 14. .

  Further, the pachinko machine in which the inner frame 12 or the front frame 14 is opened can be identified by the high signal stop state stored in the hall computer 262. Furthermore, by causing the hall computer 262 to stop the high signal from the external output terminal board 261 and to store the stop time of the high signal, the opening time of the inner frame 12 of the specified pachinko machine or the front frame 14 The opening time can also be detected.

  Further, according to the pachinko machine of the second embodiment, as described above, when the inner frame 12 or the front frame 14 is in an open state, and then the inner frame 12 or the front frame 14 that is in an open state is closed. The high signal is again output from the light receiving element (phototransistor) on the secondary side of the photocoupler PR1 of the external output terminal plate 261 to the hall computer 262.

  Here, the light receiving element (phototransistor) on the secondary side of the photocoupler PR1 of the external output terminal plate 261 is connected to the hall computer 262 using a communication cable (not shown). When the inner frame 12 and the front frame 14 are closed, the high signal output from the phototransistor to the hall computer 262 is always stopped.

  Therefore, a high signal output from the light receiving element (phototransistor) that is the secondary side of the photocoupler PR1 of the external output terminal plate 261 to the hall computer 262 is associated with the inner frame 12 and the front frame 14 being closed. In the case of the stop state, it is possible to detect disconnection (damage) of the communication cable connecting the phototransistor and the hall computer 262.

  In addition, the semiconductor components used for the open frame detection circuit 270 and the external output terminal board 261 may be broken by impact, static electricity, or the like. This breakage destroys the semiconductor used for the semiconductor components. Therefore, in general, an open breakdown (a breakdown in which the terminals of the semiconductor components are opened) is more likely to occur than a short breakdown (a breakdown in which the terminals of the semiconductor components are in a short circuit). When the semiconductor component is open broken, no current is supplied to the semiconductor component, so that no normal voltage is output from the semiconductor component. Then, since a normal current is not supplied to the photocoupler PR1, there is no abnormality in the communication cable connecting the light receiving element (phototransistor) on the secondary side of the photocoupler PR1 of the external output terminal plate 261 and the hall computer 262. Even if the inner frame 12 and the front frame 14 are closed, the high signal output from the phototransistor to the hall computer 262 is always stopped.

  Therefore, there is no abnormality in the communication cable connecting the light receiving element (phototransistor) that is the secondary side of the photocoupler PR1 of the external output terminal plate 261 and the hall computer 262, and the inner frame 12 and the front frame 14 are closed. Nevertheless, when the high signal output from the phototransistor to the hall computer 262 is in a stopped state, the breakage of the frame opening detection circuit 270 or the external output terminal plate 261 can be detected.

  Further, since the frame open detection circuit 270 is provided with the storage battery SB1, the frame open detection circuit 270 is supplied with power to the pachinko machine and supplied with a DC voltage of 12 volts from the DC power supply DC1. In addition to the case, for example, even when the business hours of the amusement hall are over and the power supply to the pachinko machine is cut off and the DC voltage of 12 volts is not supplied from the DC power supply DC1, In addition to being able to detect the opening of the frame 14, the opening period of the inner frame 12 or the front frame 14 can also be detected.

  Next, a pachinko machine according to a third embodiment will be described with reference to FIGS. The pachinko machine of the third embodiment is obtained by changing the frame opening detection circuit 260 of the pachinko machine 10 of the first embodiment to a frame opening detection circuit 280 having another configuration. The frame opening detection circuit 280 of the third embodiment has a circuit configuration changed from that of the frame opening detection circuit 260 of the first embodiment. Specifically, the frame opening detection circuit 280 of the third embodiment removes the resistor R2, the EXOR circuit IC2, the capacitors CD4 and CD5 from the frame opening detection circuit 260 of the first embodiment, and the resistor R1, the capacitor CD3, the resistor R3, resistor R7, switch SW1 and switch SW2 are connected to change, so that timer IC1 functions as a monostable multivibrator, integrating circuit 281 including resistor 10 and capacitor CD7 before the TRG terminal of timer IC1. And a NOT circuit IC3, which is a logic negation circuit, is connected to the OUT terminal of the timer IC1 to change the circuit configuration. Then, the frame open detection circuit 280 of the third embodiment is outputted from the frame open detection circuit 260 of the first embodiment from the mode of the voltage applied to the TRG terminal of the timer IC1 and the OUT terminal of the timer IC1. The mode of voltage is changed.

  According to the frame open detection circuit 280 of the third embodiment, the integration circuit 281 makes the falling period of the voltage applied to the TRG terminal of the timer IC 1 constant regardless of the open period of the inner frame 12 or the front frame 14. By setting the period (about 2 ms), the falling period of the voltage applied to the TRG terminal of the timer IC1 is made longer than the period (about 10 ms) in which a voltage of about 9.6 volts is output from the OUT terminal of the timer IC1. Can be adjusted short. Thus, regardless of the opening period of the inner frame 12 or the front frame 14, the timer IC 1 functioning as a monostable multivibrator is always operated normally, and the high signal output from the external output terminal board 261 to the hall computer 262 is The stop period can be about 10 ms. Therefore, the frame opening detection circuit 280 is not related to the frame opening detection circuit 260 and does not employ a special circuit configuration, and is related to the opening period of the inner frame 12 or the front frame 14 similarly to the frame opening detection circuit 260. First, the high signal output period output from the external output terminal board 261 to the hall computer 262 can be about 10 ms.

  FIG. 20 is a circuit diagram showing an electrical configuration of the frame opening detection circuit 280 of the third embodiment. In addition, the same number is attached | subjected to the part same as the frame open | release detection circuit 260 of 1st Embodiment mentioned above in FIG. 7, the description is abbreviate | omitted, and only a different part is demonstrated.

  When the power supply to the pachinko machine is cut off and the DC voltage of 12 volts is not supplied from the DC power supply DC1, the plus terminal of the storage battery SB1 that supplies the DC voltage to the frame open detection circuit 280 and the external output terminal plate 261 is Are connected to one end of a 100 kΩ resistor R10 and to the VDD terminal of the timer IC1, one end of a 100 KΩ resistor R1a, the RES terminal of the timer IC1 and one end of a 1 KΩ resistor R7a.

  The other end of the resistor R1a is connected to one end of a 0.1 μF capacitor CD3a and to the DCH terminal of the timer IC1 and the TH terminal of the timer IC1. The other end of the capacitor CD3a is grounded. Due to the connection between the capacitor CD3a and the resistor R1a, the timer IC1 opens the inner frame 12 or the front frame 14, whereby the switch SW1 or the switch SW2 is turned on, and the voltage applied to the TRG terminal of the timer IC1 is increased. When it falls to zero volts, it functions as a monostable multivibrator that raises the voltage at the OUT terminal of the timer IC1 from zero volts to about 9.6 volts for about 10 ms. Note that about 10 ms, which is a period for raising the voltage at the OUT terminal of the timer IC1 from zero volts to about 9.6 volts, is the product of the resistance value of the resistor R1a (100 kΩ) and the capacitance value of the capacitor CD3a (0.1 μF). It is determined by a certain time constant.

  The NOT circuit IC3, which is a logic negation circuit, is a circuit that inverts and outputs the voltage output from the OUT terminal of the timer IC1, and the input terminal of the NOT circuit IC3 is connected to the OUT terminal of the timer IC1, and the NOT circuit IC3. Is connected to one end of the resistor R3a. The power supply terminal (not shown) of the NOT circuit IC3 is connected to the plus terminal of the storage battery SB1. With this connection, when the voltage at the OUT terminal of the timer IC1 is zero volts, a voltage of about 11.3 volts is output from the output terminal of the NOT circuit IC3. At this time, the collector terminal c and the emitter terminal e of the transistor TR1 become conductive, and a high signal is output from the external output terminal plate 261 to the hall computer 262. On the other hand, when the voltage at the OUT terminal of the timer IC1 is about 9.6 volts, the voltage output from the output terminal of the NOT circuit IC3 is zero volts. At this time, the collector terminal c and the emitter terminal e of the transistor TR1 are cut off, and the high signal output from the external output terminal plate 261 to the hall computer 262 is stopped. Therefore, when the voltage of the OUT terminal of the timer IC 1 rises from zero volt to about 9.6 volt for about 10 ms, the high signal output from the external output terminal board 261 to the hall computer 262 is stopped for about 10 ms. Become.

  The resistor R10 is a resistor that stabilizes the voltage applied to the TRG terminal of the timer IC1, and that constitutes the integrating circuit 281 with the capacitor CD7. As described above, one end of the resistor R10 is connected to the plus terminal of the storage battery SB1, the VDD terminal of the timer IC1, one end of the resistor R1a, the RES terminal of the timer IC1, and one end of the resistor R7a. The other end of the resistor R10 is connected to the anode terminal of the diode D2, which is a diode element. The cathode terminal of the diode D2 is connected to the TRG terminal of the timer IC1, and the limiting voltage (zener voltage) is about 10. It is connected to the cathode terminal of a Zener diode D3, which is a .5 volt Zener diode element, and to one end of each of switches SW1 and SW2 connected in parallel. Therefore, when the inner frame 12 and the front frame 14 are closed and the switch SW1 and the switch SW2 are shut off, the voltage applied to the TRG terminal of the timer IC1 is about 11.3 volts supplied from the storage battery SB1. Is approximately 10.3 volts obtained by subtracting approximately 0.3 volts of the voltage drop at the resistor R10 and approximately 0.7 volts of the voltage drop at the diode D2.

  The 0.02 μF capacitor CD7 constitutes an integrating circuit 281 with the resistor R10, and controls the voltage applied to the TRG terminal of the timer IC1. One end of the capacitor CD7 is connected to the other end of each of the switch SW1 and the switch SW2, and the other end of the capacitor CD7 is grounded. The integrating circuit 281 composed of the capacitor CD7 and the resistor R10 is applied to the TRG terminal of the timer IC1 when the inner frame 12 or the front frame 14 is opened and the switch SW1 or SW2 is turned on. This is a circuit that lowers the voltage of about 10.3 volts to zero volts and returns the TRG terminal voltage of the timer IC1 to about 10.3 volts again about 2 ms after the fall.

  Specifically, when the inner frame 12 or the front frame 14 is opened and the switch SW1 or the switch SW2 is turned on according to the opening, a voltage of about 10.3 volts supplied from the storage battery SB1 is applied to the capacitor CD7. Application is started, and charging of the capacitor CD7 is started. At the start of charging, the voltage applied to the capacitor CD7 instantaneously becomes zero volts, so that the voltage applied to the TRG terminal of the timer IC1 instantaneously becomes zero volts. As the capacitor CD7 is charged, the capacitor CD7 increases the voltage applied to the TRG terminal of the timer IC1, and finally controls the voltage applied to the TRG terminal of the timer IC1 to about 10.3 volts. It is.

  It should be noted that the period until the capacitor CD7 is fully charged, that is, the voltage of about 10.3 volts applied to the TRG terminal of the timer IC1 falls to zero volts, and from the fall, the voltage of the TRG terminal of the timer IC1 becomes Again, about 2 ms, which is a period until returning to about 10.3 volts, is determined by a time constant which is a product of the resistance value of the resistor R10 (100 kΩ) and the capacitance value of the capacitor CD7 (0.02 μF).

  Thus, the voltage applied to the TRG terminal of the timer IC1 falls, and the integration circuit 281 has a period (about 2 ms) until the TRG terminal voltage of the timer IC1 returns to about 10.3 volts after the fall. Thus, regardless of the opening period of the inner frame 12 and the front frame 14, the voltage of the OUT terminal of the timer IC 1 is adjusted to a period shorter than the period (about 10 ms) rising from zero volts to about 9.6 volts. Note that the voltage applied to the TRG terminal of the timer IC1 falls after changing the resistance value of the resistor R10 and the capacitance value of the capacitor CD7, and then the voltage of the TRG terminal of the timer IC1 is about 10.3 volts. It is possible to freely change the period until the voltage returns to (5) within about 10 ms, which is the period until the voltage of the OUT terminal of the timer IC1 rises from zero volt to about 9.6 volt.

  Here, the monostable multivibrator does not normally output a signal from the output terminal unless the input period of the signal input to the input terminal is shorter than the output period of the signal output from the output terminal (from the output terminal). Signal continues to be output). For this reason, when the timer IC1 is made to function as a monostable multivibrator without using the integrating circuit 281, the time period when a voltage of about 9.6 volts is output from the OUT terminal of the timer IC1, that is, The period until the TRG terminal voltage of the timer IC1 returns from zero volts to about 10.3 volts again from the high signal stop period output from the external output terminal board 261 to the hall computer 262, that is, the inner frame 12 and The opening period of the front frame 14 (the conduction period of the switch SW1 and the switch SW2) must be short. However, since the open periods of the inner frame 12 and the front frame 14 are completely unpredictable, the inner frames 12 and In order to always shorten the opening period of the front frame 14, the period in which a voltage of about 9.6 volts is output from the OUT terminal of the timer IC 1 must be set to a period with a sufficient margin. As described above, even if the period in which the voltage of about 9.6 volts is output from the OUT terminal of the timer IC 1 is set to a period having a sufficient margin, the opening period of the inner frame 12 and the front frame 14 is not limited to that period. If exceeded, the timer IC1 functioning as a monostable multivibrator does not operate normally even if the inner frame 12 and the front frame 14 are closed and the switch SW1 and the switch SW2 are shut off. A voltage of about 9.6 volts continues to be output from the OUT terminal. Then, the high signal output from the external output terminal board 261 to the hall computer 262 also remains in the stopped state even after the set stop period (about 10 ms) is exceeded. As a result, although the frame opening detection circuit 280 and the external output terminal plate 261 are in a normal state, either the frame opening detection circuit 280 or the external output terminal plate 261 has failed, or both of them have failed. I misunderstand. Therefore, a special circuit configuration is required to allow the timer IC1 to function as a monostable multivibrator and to operate the monostable multivibrator normally without using the integration circuit 281.

  However, by providing the integration circuit 281 in front of the TRG terminal of the timer IC1, when the inner frame 12 or the front frame 14 is opened, the timer IC1 regardless of the open period (the conduction period of the switch SW1 and the switch SW2). The period until the voltage applied to the TRG terminal of the timer IC1 falls to zero volts and then returns to about 10.3 volts is adjusted to be shorter than the period in which the voltage of about 9.6 volts is output from the OUT terminal of the timer IC1. can do. In this way, by setting the falling period of the TRG terminal voltage of the timer IC1 to a certain period (about 2 ms) regardless of the opening period of the inner frame 12 and the front frame 14, the integration circuit 281 makes the timer IC1 normal. The time period during which a voltage of about 9.6 volts is output from the OUT terminal of the timer IC 1 can be set to about 10 ms.

  When a voltage of about 9.6 volts is output from the OUT terminal of the timer IC1 for about 10 ms, the output terminal voltage of the NOT circuit IC3 becomes zero volts for about 10 ms. Then, the collector terminal c and the emitter terminal e of the transistor TR1 are cut off for about 10 ms, and the current supplied from the storage battery SB1 to the photocoupler PR1 via the resistor R7a is stopped for about 10 ms. . Thus, the high signal output from the external output terminal board 261 to the hall computer 262 is stopped for about 10 ms for each opening of the inner frame 12 or the front frame 14. As described above, even if the timer IC 1 is made to function as a monostable multivibrator, the integration circuit 281 is provided in front of the TRG terminal of the timer IC 1 so that the external output terminal plate 261 can be used without adopting a special circuit configuration. The stop period of the high signal output to the hall computer 262 can be about 10 ms.

  The TRG terminal of the timer IC1 is connected to the cathode terminal of a Zener diode D3 having a limit voltage (zener voltage) of about 10.5 volts, and the ground is connected to the anode terminal of the Zener diode D3. The zener diode D3 has the charge stored in the capacitor CD7 and the voltage supplied from the storage battery SB1 superimposed when the inner frame 12 or the front frame 14 is opened and the switch SW1 or SW2 is turned on. This is an element that prevents an overvoltage (for example, a voltage of 12.3 volts) that can break the timer IC1 from being applied to the TRG terminal of the timer IC1. Specifically, the charge stored in the capacitor CD7 due to the opening of the inner frame 12 or the front frame 14 and the conduction of the switch SW1 or the switch SW2 again becomes the inner frame 12 or the front frame within a relatively short period of time. 14 is opened, and when the switch SW1 or SW2 is turned on, the switch SW1 or the switch SW2 is discharged from the other end side to the one end side. The voltage of about 10.3 volts discharged from the capacitor CD7 and the voltage of about 10.3 volts supplied from the storage battery SB1 are superimposed, and an overvoltage large enough to destroy the timer IC1 is applied to the TRG terminal of the timer IC1. Can be applied. However, since a Zener diode D3 having a limit voltage (zener voltage) of about 10.5 volts is connected between the TRG terminal of the timer IC1 and the ground, the voltage applied to the TRG terminal of the timer IC1 The maximum value is about 10.5 volts, and an overvoltage that destroys the timer IC1 is not applied to the TRG terminal of the timer IC1. In this way, by using the Zener diode D3 that has a simple configuration and is inexpensive, it is possible to prevent an overvoltage large enough to destroy the timer IC1 from being applied to the TRG terminal of the timer IC1, and to prevent damage to the timer IC1. it can.

  As described above, since the limit voltage (zener voltage) of the Zener diode D3 is about 10.5 volts, the inner frame 12 and the front frame 14 are closed, and the switch SW1 and the switch SW2 are shut off. In this case, the current supplied from the storage battery SB1 does not flow to the ground via the Zener diode D3, and the storage battery SB1 is not consumed. In addition, the cathode terminal of the diode D2 is connected to one end of the switch SW1 and the switch SW2, and this diode D2 exhibits a function of preventing the backflow of current. Therefore, a voltage of about 10.3 volts discharged from the capacitor CD7. However, they are not applied to the VDD terminal of the storage battery SB1 or the timer IC1 and are not damaged.

  As described above, in the timer IC1 of the frame open detection circuit 280, the inner frame 12 or the front frame 14 is opened, the switch SW1 or the switch SW2 is turned on, and the voltage applied to the TRG terminal of the timer IC1 falls to zero volts. Then, it functions as a monostable multivibrator that raises the voltage at the OUT terminal of the timer IC1 from zero volts to about 9.6 volts for about 10 ms from the fall. Further, by providing an integration circuit 281 in front of the TRG terminal of the timer IC1, when the inner frame 12 or the front frame 14 is opened, the timer IC1 is connected regardless of the opening period of the inner frame 12 and the front frame 14. Adjust the period from when the voltage applied to the TRG terminal falls to zero volts until it returns to about 10.3 volts, shorter than the period when the voltage at the OUT terminal of the timer IC1 rises from zero volts to about 9.6 volts Can do. As described above, by setting the falling period of the TRG terminal voltage of the timer IC 1 to a fixed period (about 2 ms) regardless of the opening period of the inner frame 12 and the front frame 14 by the integration circuit 281, a monostable multivibrator is obtained. The functioning timer IC1 can be operated normally, and the period at which the voltage at the OUT terminal of the timer IC1 rises from zero volts to about 9.6 volts can be set. Thereby, the stop period of the high signal output from the external output terminal board 261 to the hall computer 262 can be set to about 10 ms. Therefore, the frame opening detection circuit 280 is not related to the frame opening detection circuit 260 and does not employ a special circuit configuration, and is related to the opening period of the inner frame 12 or the front frame 14 similarly to the frame opening detection circuit 260. First, the high signal output period output from the external output terminal board 261 to the hall computer 262 can be about 10 ms.

  Further, according to the pachinko machine of the present embodiment, the frame open detection circuit 280 is provided with the storage battery SB1, so that power is supplied to the pachinko machine and a DC voltage of 12 volts is supplied from the DC power supply DC1. In addition to the case where, for example, even when the game hall is closed and the power supply to the pachinko machine is shut off and no DC voltage of 12 volts is supplied from the DC power supply DC1, the frame is opened. The detection circuit 280 can detect the opening of the inner frame 12 and the opening of the front frame 14. When the opening of the inner frame 12 or the opening of the front frame 14 is detected by the frame opening detection circuit 280, a high signal output from the external output terminal plate 261 to the hall computer 262 is approximately received for each detection. It can be stopped for 10 ms. The stop state of the high signal output from the external output terminal board 261 to the hall computer 262 is stored in the hall computer 262 that continues to operate for 24 hours. Therefore, the pachinko machine in which the inner frame 12 or the front frame 14 is opened can be specified by the high signal stop state stored in the hall computer 262. Further, by causing the hall computer 262 to stop the high signal output from the external output terminal plate 261 and to store the stop time of the high signal, the opening time of the identified inner frame 12 of the pachinko machine or The opening time of the front frame 14 can be detected.

  Note that the door opening detection circuit 280 uses the LMC 555 for the timer IC 1 to detect the opening of the inner frame 12 or the opening of the front frame 14 and realize a circuit that stops energization of the photocoupler PR1 for about 10 ms. However, it is not limited to this. That is, by using another integrated circuit or the like for the timer IC 1, a circuit that generates one pulse signal for one opening of the inner frame 12 or one opening of the front frame 14 is realized. What is necessary is just to stop energization of the photocoupler PR1 for a predetermined period based on the pulse signal.

  Next, referring to FIG. 21, the voltage at the TRG terminal of timer IC1 that changes according to the state of switch SW1 (the state of inner frame 12) and the state of switch SW2 (the state of front frame 14), and timer IC1 The relationship between the voltage at the OUT terminal, the voltage at the output terminal of the NOT circuit IC3, and the output from the external output terminal plate 261 (the input of the hall computer 262) will be described. FIG. 21 shows the state of the switch SW1 (the state of the inner frame 12), the state of the switch SW2 (the state of the front frame 14), the voltage of the TRG terminal of the timer IC1, the voltage of the OUT terminal of the timer IC1, and the output terminal of the NOT circuit IC3. 6 is a timing chart showing the relationship between the voltage of the external output terminal 261 and the output of the external output terminal plate 261 (the input of the hall computer 262). Note that the times from t1 to t8 shown in FIG. 21 are the same as the times from t1 to t8 shown in the timing chart of the frame opening detection circuit 260 of the first embodiment shown in FIG. is there.

  As shown in FIG. 21A, when the switch SW1 is in a conductive state (inner frame 12 is in an open state) at time t1, charging of the capacitor CD7 is started, and as shown in FIG. The TRG terminal voltage falls from about 10.3 volts to zero volts (at time t1). Then, following this, as shown in FIG. 21 (d), the OUT terminal voltage of the timer IC1 rises from zero volts to about 9.6 volts (at time t1). As shown in FIG. 21 (e), the voltage at the output terminal of the NOT circuit IC3 falls from about 11.3 volts to zero volts (at time t1). As a result, the terminal between the collector terminal and the emitter terminal of the transistor TR1 of the frame opening detection circuit 280 is cut off, and the current supply to one end of the resistor R7a of the external output terminal plate 261 is stopped. Therefore, as shown in FIG. 21 (f), the high signal output from the external output terminal board 261 to the hall computer 262 is stopped (at time t1).

  Next, as shown in FIG. 21 (c), when about 2 ms elapses from time t1, the charging of the capacitor CD7 is completed, and the TRG terminal voltage of the timer IC1 returns from zero volts to about 10.3 volts again. However, since the voltage at the OUT terminal of the timer IC1 has risen from zero volt to about 9.6 volts (from t1), about 10 ms has not elapsed, so the OUT terminal voltage of the timer IC1 is as shown in FIG. As shown, it maintains a state of about 9.6 volts. Therefore, the voltage at the output terminal of the NOT circuit IC3 is maintained at zero volts as shown in FIG.

  Thereafter, when about 10 ms elapse from t1, the timer IC1 switches the voltage at the OUT terminal from about 9.6 volts to zero volts as shown in FIG. Then, as shown in FIG. 21 (e), the voltage at the output terminal of the NOT circuit IC3 is switched from zero volts to about 11.3 volts (after about 10 ms has elapsed since t1). As a result, the collector terminal and the emitter terminal of the transistor TR1 of the frame opening detection circuit 280 are turned on again, and the current supply to one end of the resistor R7a of the external output terminal plate 261 is resumed. Accordingly, as shown in FIG. 21 (f), a high signal is output again from the external output terminal board 261 to the hall computer 262 (after about 10 ms has elapsed since t1).

  As described above, after the switch SW1 is turned on (the inner frame 12 is open), that is, after the TRG terminal voltage is switched from about 10.3 volts to zero volts (from time t1), for about 10 ms. When the current supply to one end of the resistor R7a is stopped, the current supply to the primary light emitting diode (see FIG. 20) of the photocoupler PR1 of the external output terminal plate 261 is also stopped for about 10 ms from t1. Is done. As a result, as shown in FIG. 21 (f), the output of the external output terminal plate 261 switches from the high state to the low state for about 10 ms. That is, the high signal output from the external output terminal board 261 to the hall computer 262 is stopped for about 10 ms from t1. The high signal stop state is stored in the hall computer 262.

  As shown in FIG. 21A, when the switch SW1 is in the cut-off state (the inner frame 12 is closed) at t2, the frame opening detection circuit 280 detects the inner frame 12 and the front frame 14 again. Set to possible state.

  Next, as shown in FIG. 21B, at time t3, when the switch SW2 is in a conductive state (the front frame 14 is in an open state), charging of the capacitor CD7 is started, and as shown in FIG. The TRG terminal voltage of the timer IC1 falls from about 10.3 volts to zero volts (at time t3). Then, following this, as shown in FIG. 21 (d), the OUT terminal voltage of the timer IC1 rises from zero volts to about 9.6 volts (at time t3). As shown in FIG. 21 (e), the voltage at the output terminal of the NOT circuit IC3 falls from about 11.3 volts to zero volts (at time t3). As a result, the terminal between the collector terminal and the emitter terminal of the transistor TR1 of the frame opening detection circuit 280 is cut off, and the current supply to one end of the resistor R7a of the external output terminal plate 261 is stopped. Therefore, as shown in FIG. 21F, the high signal output from the external output terminal board 261 to the hall computer 262 is stopped (at time t3).

  The electric charge stored in the capacitor CD7 between time t1 and time t2 is instantaneously discharged through the zener diode D3 at time t3. The discharge period of the capacitor CD7 is a period that is much shorter than about 2 ms in which the voltage at the TRG terminal of the timer IC1 is changed from about 10.3 volts to zero volts and is again about 10.3 volts. It does not significantly affect the voltage applied to the terminals. In addition to this discharge, the electric charge stored in the capacitor CD7 from t1 to t2 is also discharged by self-discharge of the capacitor CD7.

  At time t3, a voltage of about 10.3 volts supplied from the storage battery SB1 and a voltage of about 10.3 volts associated with the charge stored in the capacitor CD7 are superimposed on the TRG terminal of the timer IC1, An overvoltage large enough to destroy the timer IC1 may be applied. However, since a Zener diode D3 having a limit voltage (zener voltage) of about 10.5 volts is connected to the preceding stage of the TRG terminal of the timer IC1, the maximum value of the voltage applied to the TRG terminal of the timer IC1 is The overvoltage which is about 10.5 volts and destroys the timer IC1 is not applied to the TRG terminal of the timer IC1.

  Next, as shown in FIG. 21C, when about 2 ms elapses from t3, the charging of the capacitor CD7 is completed, and the TRG terminal voltage of the timer IC1 returns from zero volts to about 10.3 volts again. However, since the voltage of the OUT terminal of the timer IC1 rises from zero volt to about 9.6 volts (from t3), about 10 ms has not elapsed, the OUT terminal voltage of the timer IC1 is shown in FIG. As shown, it maintains a state of about 9.6 volts. Therefore, the voltage at the output terminal of the NOT circuit IC3 is maintained at zero volts as shown in FIG.

  Thereafter, when about 10 ms elapses from t3, the timer IC1 switches the voltage at the OUT terminal from about 9.6 volts to zero volts as shown in FIG. 21 (d). Then, as shown in FIG. 21 (e), the voltage at the output terminal of the NOT circuit IC3 is switched from zero volts to about 11.3 volts (after about 10 ms have elapsed since t3). As a result, the collector terminal and the emitter terminal of the transistor TR1 of the frame opening detection circuit 280 are turned on again, and the current supply to one end of the resistor R7a of the external output terminal plate 261 is resumed. Therefore, as shown in FIG. 21 (f), a high signal is output again from the external output terminal board 261 to the hall computer 262 (after about 10 ms has elapsed since t3).

  As described above, after the switch SW2 is in a conductive state (the front frame 14 is in an open state), that is, for about 10 ms after the TRG terminal voltage is switched from about 10.3 volts to zero volts (from t3 time). When the current supply to one end of the resistor R7a is stopped, the current supply to the light emitting diode (see FIG. 20) on the primary side of the photocoupler PR1 of the external output terminal plate 261 is also stopped for about 10 ms from t3. Is done. As a result, as shown in FIG. 21 (f), the output of the external output terminal plate 261 switches from the high state to the low state for about 10 ms. That is, the high signal output from the external output terminal board 261 to the hall computer 262 is stopped for about 10 ms from t3. The high signal stop state is stored in the hall computer 262.

  As shown in FIG. 21 (b), when the switch SW2 is in a cut-off state (the front frame 14 is closed) at t4, the frame open detection circuit 280 detects the inner frame 12 and the front frame 14 again. Set to possible state.

  Finally, a case will be described in which the switch SW2 is in a conductive state (the front frame 14 is in an open state) when the switch SW1 is in a conductive state (the inner frame 12 is in an open state). As shown in FIG. 21 (a), at time t5, the switch SW1 becomes conductive (inner frame 12 is open), and as shown in FIG. 21 (b), at time t6, switch SW2 becomes conductive (front surface). When the frame 14 is in an open state), at time t5, charging of the capacitor CD7 is started, and as shown in FIG. 21C, the TRG terminal voltage of the timer IC1 falls from about 10.3 volts to zero volts (t5). Time). Then, following this, as shown in FIG. 21 (d), the OUT terminal voltage of the timer IC1 rises from zero volts to about 9.6 volts (at time t5). As shown in FIG. 21 (e), the voltage at the output terminal of the NOT circuit IC3 falls from about 11.3 volts to zero volts (at time t5). As a result, the terminal between the collector terminal and the emitter terminal of the transistor TR1 of the frame opening detection circuit 280 is cut off, and the current supply to one end of the resistor R7a of the external output terminal plate 261 is stopped. Therefore, as shown in FIG. 21F, the high signal output from the external output terminal board 261 to the hall computer 262 is stopped (at time t5).

  The charge stored in the capacitor CD7 between t3 and t4 has a significant effect on the voltage applied to the TRG terminal of the timer IC1, since the discharge is instantaneously completed through the zener diode D3 at t5. is not. In addition to this discharge, the charge stored in the capacitor CD7 from t3 to t4 is also discharged by self-discharge of the capacitor CD7.

  At t5, a voltage of about 10.3 volts supplied from the storage battery SB1 and a voltage of about 10.3 volts associated with the charge stored in the capacitor CD7 are superimposed on the TRG terminal of the timer IC1, An overvoltage large enough to destroy the timer IC1 may be applied. However, since the maximum value of the voltage applied to the TRG terminal of the timer IC1 is about 10.5 volts due to the Zener diode D3, an overvoltage large enough to destroy the timer IC1 is applied to the TRG terminal of the timer IC1. There is no.

  Next, as shown in FIG. 21C, when about 2 ms elapses from t5, the charging of the capacitor CD7 is completed, and the TRG terminal voltage of the timer IC1 returns from zero volts to about 10.3 volts again. However, since the voltage of the OUT terminal of the timer IC1 rises from zero volt to about 9.6 volts (from t5), about 10 ms has not elapsed, the OUT terminal voltage of the timer IC1 is shown in FIG. As shown, it maintains a state of about 9.6 volts. Therefore, the voltage at the output terminal of the NOT circuit IC3 is maintained at zero volts as shown in FIG.

  Thereafter, when about 10 ms elapses from t5, as shown in FIG. 21D, the timer IC1 switches the voltage of the OUT terminal from about 9.6 volts to zero volts. Then, as shown in FIG. 21 (e), the voltage at the output terminal of the NOT circuit IC3 is switched from zero volts to about 11.3 volts (after about 10 ms has elapsed from t5). As a result, the collector terminal and the emitter terminal of the transistor TR1 of the frame opening detection circuit 280 are turned on again, and the current supply to one end of the resistor R7a of the external output terminal plate 261 is resumed. Accordingly, as shown in FIG. 21 (f), a high signal is output again from the external output terminal board 261 to the hall computer 262 (after about 10 ms has elapsed since t5).

  As described above, after switch SW1 becomes conductive (inner frame 12 is open), that is, for about 10 ms after the TRG terminal voltage is switched from about 10.3 volts to zero volts (from t5). When the current supply to one end of the resistor R7a is stopped, the current supply to the light emitting diode (see FIG. 20) on the primary side of the photocoupler PR1 of the external output terminal plate 261 is also stopped for about 10 ms from t5. Is done. As a result, as shown in FIG. 21 (f), the output of the external output terminal plate 261 switches from the high state to the low state for about 10 ms. That is, the high signal output from the external output terminal board 261 to the hall computer 262 is stopped for about 10 ms from t5. The high signal stop state is stored in the hall computer 262.

  As shown in FIG. 21 (a), at time t7, the switch SW1 is turned off (the inner frame 12 is closed), and as shown in FIG. 21 (b), at time t8, the switch SW2 is turned off. When the front frame 14 is in the closed state, the frame open detection circuit 280 is set again to a state in which the inner frame 12 and the front frame 14 can be detected.

  Thus, even when the switch SW1 is in the conductive state (the inner frame 12 is in the open state) and the switch SW2 is in the conductive state (the front frame 14 is in the open state), the frame open detection circuit 280 is the switch SW1. Regardless of the conduction period (the opening period of the inner frame 12) and the conduction period of the switch SW2 (the opening period of the front frame 14), either the switch SW1 or the switch SW2 is in the conduction state (the inner frame 12 or the front frame 14). When either one is open) and the TRG terminal voltage of the timer IC1 falls from about 10.3 volts to zero volts, about 10 ms elapses, the voltage at the OUT terminal of the timer IC1 is switched from about 9.6 volts to zero volts. . By the operation of the frame opening detection circuit 280, the terminal between the collector terminal c of the transistor TR1 and the emitter terminal e (see FIG. 20) of the transistor TR1 of the frame opening detection circuit 280 is cut off for about 10 ms. As a result, the high signal output from the external output terminal board 261 to the hall computer 262 starts when one of the inner frame 12 or the front frame 14 is in an open state (one of the switch SW1 or the switch SW2 is conductive). It will be stopped only for about 10 ms.

  The stop state of the high signal is stored in the hall computer 262 that continues to operate for 24 hours. Therefore, the pachinko machine in which the inner frame 12 or the front frame 14 is opened can be specified by the high signal stop state stored in the hall computer 262.

  As described above, according to the pachinko machine of the third embodiment, when the inner frame 12 or the front frame 14 is in an open state and the switch SW1 or the switch SW2 is in a conductive state, the integrating circuit 281 Regardless of the open period of 12 or the front frame 14, the falling period of the voltage applied to the TRG terminal of the timer IC1 is set to a certain period (about 2 ms). Then, the timer IC1 functioning as a monostable multivibrator operates normally, and the voltage at the OUT terminal of the timer IC1 is reduced from zero volts to about 10 ms after the TRG terminal voltage of the timer IC1 falls to zero volts. Raise to 9.6 volts. Then, the output terminal voltage of the NOT circuit IC3 becomes zero volts for about 10 ms. As a result, the collector terminal c and the emitter terminal e of the transistor TR1 are cut off for about 10 ms, and the current supplied from the storage battery SB1 to the photocoupler PR1 of the external output terminal plate 261 via the resistor R7a is about 10 ms. During this period, it will be stopped. Therefore, according to the pachinko machine of the third embodiment, when the opening of the inner frame 12 or the opening of the front frame 14 is detected by the frame opening detection circuit 280, from the external output terminal plate 261 for each detection. The high signal output to the hall computer 262 can be stopped for about 10 ms. The stop state of the high signal output from the external output terminal board 261 to the hall computer 262 is stored in the hall computer 262 that continues to operate for 24 hours. Therefore, the pachinko machine in which the inner frame 12 or the front frame 14 is opened can be specified by the high signal stop state stored in the hall computer 262. Further, by causing the hall computer 262 to stop the high signal output from the external output terminal plate 261 and to store the stop time of the high signal, the opening time of the identified inner frame 12 of the pachinko machine or The opening time of the front frame 14 can be detected.

  Further, according to the pachinko machine of the third embodiment, when the inner frame 12 and the front frame 14 are closed, and when about 10 ms has elapsed since the inner frame 12 or the front frame 14 was opened, A high signal is output from the light receiving element (phototransistor) on the secondary side of the photocoupler PR1 of the external output terminal plate 261 to the hall computer 262. On the other hand, as described above, when the inner frame 12 or the front frame 14 is in the open state, the high signal output from the phototransistor to the hall computer 262 is in the stop state, but the period in which the high signal is in the stop state. Is about 10 ms.

  Here, the light receiving element (phototransistor) on the secondary side of the photocoupler PR1 of the external output terminal plate 261 is connected to the hall computer 262 using a communication cable (not shown). When the signal is cut (damaged) by, the high signal output from the phototransistor to the hall computer 262 exceeds about 10 ms and is always stopped.

  Therefore, when the high signal output to the hall computer 262 from the light receiving element (phototransistor) that is the secondary side of the photocoupler PR1 of the external output terminal plate 261 is stopped for more than about 10 ms, The disconnection (breakage) of the communication cable connecting the transistor and the hall computer 262 can be detected. Therefore, in addition to being able to detect the opening of the inner frame 12 or the front frame 14 from the high signal stop state period stored in the hall computer 262, the communication cable connecting the phototransistor and the hall computer 262 is disconnected (damaged). Etc. can also be detected.

  In addition, the semiconductor components used for the open frame detection circuit 280 and the external output terminal board 261 may be destroyed by impact, static electricity, or the like. This destruction destroys the semiconductor used for the semiconductor components. Therefore, in general, an open breakdown (a breakdown in which the terminals of the semiconductor components are opened) is more likely to occur than a short breakdown (a breakdown in which the terminals of the semiconductor components are in a short circuit). When the semiconductor component is open broken, no current is supplied to the semiconductor component, so that no normal voltage is output from the semiconductor component. Then, since a normal current is not supplied to the photocoupler PR1, there is no abnormality in the communication cable connecting the light receiving element (phototransistor) on the secondary side of the photocoupler PR1 of the external output terminal plate 261 and the hall computer 262. However, the high signal output from the phototransistor to the hall computer 262 exceeds about 10 ms and is always stopped.

  Therefore, although there is no abnormality in the communication cable that connects the light receiving element (phototransistor) that is the secondary side of the photocoupler PR1 of the external output terminal plate 261 and the hall computer 262, the high output that is output from the phototransistor to the hall computer 262. When the signal is stopped after approximately 10 ms, the breakage of the frame opening detection circuit 280 or the external output terminal plate 261 can be detected. Therefore, in addition to being able to detect the opening of the inner frame 12 or the front frame 14 from the high signal stop state period stored in the hall computer 262, the frame opening detection circuit 280 or the external output terminal plate 261 is also destroyed (abnormal). Can be detected.

  Further, according to the pachinko machine of the present embodiment, the frame open detection circuit 280 is provided with the storage battery SB1, so that power is supplied to the pachinko machine and a DC voltage of 12 volts is supplied from the DC power supply DC1. In addition to the case where, for example, even when the game hall is closed and the power supply to the pachinko machine is shut off and no DC voltage of 12 volts is supplied from the DC power supply DC1, the frame is opened. The detection circuit 280 can detect the opening of the inner frame 12 and the opening of the front frame 14.

  In the present embodiment, when the inner frame 12 or the front frame 14 is opened and the switch SW1 or the switch SW2 is turned on, a high signal output from the external output terminal plate 261 to the hall computer 262 is about 10 ms. However, this is not a limitation. That is, when the connection of each component of the frame opening detection circuit 280 is changed, the inner frame 12 or the front frame 14 is opened, and the opened inner frame 12 or the front frame 14 is closed, the photocoupler PR1 is connected. The supplied current may be stopped for about 10 ms, and the high signal output from the external output terminal board 261 to the hall computer 262 may be stopped for about 10 ms.

  However, in the frame open detection circuit 280 of this embodiment, when the inner frame 12 or the front frame 14 is opened and the switch SW1 or the switch SW2 is turned on, it is output from the external output terminal plate 261 to the hall computer 262. Since the high signal is stopped for about 10 ms, the opening of the inner frame 12 or the front frame 14 can be detected quickly. Therefore, the opening of the inner frame 12 or the front frame 14 can be detected before the inner frame 12 or the front frame 14 is opened and an illegal act is performed on the main controller 110 or the game board 13. Therefore, it is possible to prevent an abnormal operation due to an illegal act that occurs when power is supplied to the pachinko machine.

  Further, when the inner frame 12 and the front frame 14 are closed, and when about 10 ms has elapsed since the inner frame 12 or the front frame 14 was opened, the collector terminal c of the transistor TR1 and the emitter of the transistor TR1. The terminal e is electrically connected to the terminal e, and a current is supplied to the light emitting diode on the primary side of the photocoupler PR1 through the resistor R7a. As a result, a high signal is continuously output from the external output terminal board 261 to the hall computer 262. Here, when the inner frame 12 and the front frame 14 are closed, and when about 10 ms has elapsed since the inner frame 12 or the front frame 14 was opened, the frame open detection circuit 280 and the external output terminal plate 261 are used. When it is desired to suppress the power consumed by the resistor R3a, the resistor R4, the internal resistor R5 and the internal resistor R6, the resistance value of the resistor R7a should be larger than 10 kΩ and the resistance value of the resistor R7a should be larger than 1 kΩ.

  Further, when it is desired to separately store in the hall computer 262 which of the inner frame 12 and the front frame 14 is opened, the following configuration may be used. First, the frame opening detection circuit 280 and the external output terminal plate 261 used in this embodiment are newly provided one by one, the switch SW2 connected in parallel to the switch SW1 is disconnected, and the disconnected switch SW2 is newly installed. It may be connected to the provided frame opening detection circuit 280. Specifically, one end of the disconnected switch SW2 is connected to the cathode terminal of the diode D2 of the newly provided frame opening detection circuit 280, the cathode terminal of the Zener diode D3, and the TRG terminal of the timer IC1, and the disconnected switch SW2 is disconnected. May be connected to one end of the capacitor CD7 of the newly provided frame opening detection circuit 280. Thus, the frame opening detection circuit 280 and the external output terminal plate 261 are newly provided, and only the switch SW2 is connected to the newly provided frame opening detection circuit 280, and the existing frame opening detection circuit 280 includes a switch By connecting only SW1, if the switch SW1 is conductive (the inner frame 12 is opened), the high signal output from the existing external output terminal board 261 to the hall computer 262 is stopped, and the switch SW2 is turned off. When there is continuity (opening of the front frame 14), the high signal output from the newly provided external output terminal board 261 to the hall computer 262 can be stopped. Here, the hall computer 262 includes an input terminal for a high signal output from the existing external output terminal board 261 (for detecting conduction of the switch SW1 (for detecting opening of the inner frame 12)), and a newly provided external output terminal. A high signal input terminal output from the plate 261 (for detecting the conduction of the switch SW2 (for detecting the opening of the front frame 14)) is set separately. With this configuration, the conduction of the switch SW1 (opening of the inner frame 12) and the conduction of the switch SW2 (opening of the front frame 14) can be distinguished and stored in the hall computer 262. Therefore, depending on the stop state of the high signal stored in the hall computer 262, the switch SW1 is conductive (the inner frame 12 is opened), the switch SW2 is conductive (the front frame 14 is opened), or both It is possible to accurately detect whether or not there has been.

  Further, when power is supplied to the pachinko machine, the hall computer 262 separately stores which of the inner frame 12 and the front frame 14 is opened, and which of the inner frame 12 and the front frame 14 is stored. If you want to be notified by a pachinko machine when it opens, the following configuration may be used. First, the frame opening detection circuit 280 and the external output terminal plate 261 used in this embodiment are newly provided one by one, the switch SW2 connected in parallel to the switch SW1 is disconnected, and the disconnected switch SW2 is newly installed. Connected to the provided frame opening detection circuit 280. Next, the male switches SW1b and SW2b and the female switches SW1a and SW2a are newly provided for the switch SW1 and the switch SW2, respectively. Then, when the inner frame 12 or the front frame 14 is opened using the newly provided male switches SW1b and SW2b and the female switches SW1a and SW2a and the switch SW1 or the switch SW2 is turned on, a signal is sent to the MPU 201. What is necessary is just to comprise so that it may be input.

  Specifically, one end of the disconnected switch SW2 is connected to the cathode terminal of the diode D2 of the newly provided frame opening detection circuit 280, the cathode terminal of the Zener diode D3, and the TRG terminal of the timer IC1, and the disconnected switch SW2 is disconnected. May be connected to one end of the capacitor CD7 of the newly provided frame opening detection circuit 280. Thus, the frame opening detection circuit 280 and the external output terminal plate 261 are newly provided, and only the switch SW2 is connected to the newly provided frame opening detection circuit 280, and the existing frame opening detection circuit 280 includes a switch By connecting only SW1, if the switch SW1 is conductive (the inner frame 12 is opened), the high signal output from the existing external output terminal board 261 to the hall computer 262 is stopped, and the switch SW2 is turned off. When there is continuity (opening of the front frame 14), the high signal output from the newly provided external output terminal board 261 to the hall computer 262 can be stopped.

  Next, male switch SW1b and male switch SW2b are further provided for switch SW1 and switch SW2, respectively, and male switch SW1b and male switch SW2b disposed in switch SW1 and switch SW2 are respectively provided in two. To do. Correspondingly, the female switch SW1a and the female switch SW2a are further provided in the switch SW1 and the switch SW2, respectively, and the female switch SW1a and the female switch SW2a provided in the switch SW1 and the switch SW2 are respectively 2 One by one. As a result, one new combination of the male switch SW1b and the female switch SW1a is added to the switch SW1. Similarly to the switch SW1, one combination of the male switch SW2b and the female switch SW2a is added to the switch SW2. Then, one end of a pair of terminal pairs SW1c built in the newly added female switch SW1a is connected to the DC power source DC1 of the existing frame opening detection circuit 280, and built into the newly added female switch SW1a. The other end of the pair of terminal pairs SW1c thus connected is connected to the input / output port 205 of the MPU 201 via a voltage dividing circuit constituted by resistors. Similarly, one end of a pair of terminal pairs SW2c incorporated in the newly added female switch SW2a is connected to the DC power source DC1 of the newly provided frame opening detection circuit 280, and the newly added female type The other end of the pair of terminals SW2c built in the switch SW2a is connected to the input / output port 205 of the MPU 201 via a voltage dividing circuit constituted by a resistor and to a port different from the other end of the terminal pair SW1c. Further, the MPU 201 is supplied from the DC power source DC1 by a voltage of 5 volts (the voltage dividing circuit detects the opening of the inner frame 12 when the inner frame 12 or the front frame 14 is opened and the switch SW1 or the switch SW2 is turned on. 12 volt voltage is reduced to 5 volts) or 5 volt voltage to detect the opening of the inner frame 14 (12 volt voltage supplied from the DC power supply DC1 is lowered to 5 volt by the voltage dividing circuit) ) Is input to the input / output port 205, a command indicating that the opening of the inner frame 12 or the front frame 14 is detected is transmitted to the audio lamp control device 113 and the display control device 114. At this time, the command transmitted from the MPU 201 includes a command when the opening of the inner frame 12 is detected (hereinafter referred to as “inner frame command”) and a command when the front frame 14 is released (hereinafter referred to as “ It is called “front frame command”). Then, the voice lamp control device 113 that has received each command performs notification in a different manner depending on whether the inner frame command is received or the front frame command is received. For example, a different warning sound is emitted from the audio output device 226 or the lighting mode of the lamp display device 227 is changed. In addition, the display control device 114 that has received each command displays different modes depending on whether the inner frame command is received or the front frame command is received. For example, when the display control device 114 receives an inner frame command, the third symbol display device 81 displays “the inner frame is open” or the display control device 114 receives a front frame command. The third symbol display device 81 may be configured to display “front frame is open”.

  In this way, a new combination of the male switch SW1b and the female switch SW1a is added to the switch SW1, and a new combination of the male switch SW2b and the female switch SW2a is added to the switch SW2 as well as the switch SW1. When one switch is used and the switch SW1 is turned on (when the inner frame 12 is opened), the MPU 201 sends an inner frame command to the audio lamp control device 113 and the display control device 114. Configure to send. Further, when the switch SW2 is turned on (when the front frame 14 is opened), the MPU 201 is configured to transmit a front frame command to the audio lamp control device 113 and the display control device 114. By configuring in this way, notification of a different aspect between when the inner frame 12 is opened and when the front frame 14 is opened is performed using the audio lamp control device 113 and the display control device 114. Can do. This makes it possible to accurately determine whether the switch SW1 is conductive (the inner frame 12 is opened), the switch SW2 is conductive (the front frame 14 is opened), or both, using a pachinko machine. Can be detected.

  Further, a frame opening detection circuit 280 and an external output terminal plate 261 are newly provided, and only the switch SW2 is connected to the newly provided frame opening detection circuit 280, and the switch SW1 is connected to the existing frame opening detection circuit 280. When the switch SW1 is connected (the inner frame 12 is opened) by connecting only the switch SW2, the high signal output from the existing external output terminal board 261 to the hall computer 262 is stopped, and the switch SW2 is connected. When (the front frame 14 is opened), the high signal output from the newly provided external output terminal board 261 to the hall computer 262 can be stopped. Therefore, depending on the stop state of the high signal stored in the hall computer 262, the switch SW1 is conductive (the inner frame 12 is opened), the switch SW2 is conductive (the front frame 14 is opened), or both It is possible to accurately detect whether or not there has been.

  In the present embodiment, the high signal output from the external output terminal board 261 is output to the hall computer 262 having a different installation location from the pachinko machine, but is not limited thereto. A dedicated storage device having the function of the hall computer 262 may be provided for each pachinko machine, and the dedicated storage device may be provided on the back side of each pachinko machine in which the main controller 110 and the like are provided. In this case, more preferably, a dedicated storage device such as the main control device 110, the payout control device 111, and the launch control device 112 is stored in the substrate box, and the box base and the box cover provided in the substrate box are stored. Are connected by a sealing unit (not shown) so that they cannot be opened (connection by caulking structure). Then, a seal seal (not shown) is pasted on the connecting portion between the box base and the box cover over the box cover and the box base.

  In the first embodiment, the wiring from the connection point where the plus terminal of the storage battery SB1 and the RES terminal of the timer IC1 are connected to the resistor R7 is disconnected, and a logic negation circuit (NOT circuit) is provided in the frame opening detection circuit 260. And the output terminal of the NOT circuit is connected to one end of the resistor R7, and the input terminal of the NOT circuit is connected to a connection point where the plus terminal of the storage battery SB1 and the RES terminal of the timer IC1 are connected, and supplied to the resistor R7. The current that is generated may be reversed. In this case, when the inner frame 12 and the front frame 14 are closed, no pulse signal is output to the hall computer 262, while when the inner frame 12 or the front frame 14 is opened, the hall computer 262 is opened. A pulse signal having a pulse width of 10 ms is output.

  Similarly, in the second embodiment, the wiring from the connection point where the plus terminal of the storage battery SB1 and one end of the resistor R9 are connected to the resistor R7 is disconnected, and a logic negation circuit (NOT circuit) is provided to the frame opening detection circuit 270. The output terminal of the NOT circuit is connected to one end of the resistor R7, the input terminal of the NOT circuit is connected to a connection point where the plus terminal of the storage battery SB1 and one end of the resistor R9 are connected, and the resistor R7 is supplied. The current that is generated may be reversed. In this case, no pulse signal is output to the hall computer 262 when the inner frame 12 and the front frame 14 are closed, while a high signal is output when the inner frame 12 or the front frame 14 is opened. Is done. Further, in the third embodiment, the wiring from the connection point where the plus terminal of the storage battery SB1 and the RES terminal of the timer IC1 are connected to the resistor R7a is disconnected, and a logic negation circuit (NOT circuit) is provided to the frame opening detection circuit 280. The output terminal of the NOT circuit is connected to one end of the resistor R7a, the input terminal of the NOT circuit is connected to a connection point where the plus terminal of the storage battery SB1 and the RES terminal of the timer IC1 are connected, and the resistor R7a is connected. The supplied current may be reversed. In this case, when the inner frame 12 and the front frame 14 are closed, no pulse signal is output to the hall computer 262, while when the inner frame 12 or the front frame 14 is opened, the hall computer 262 is opened. A pulse signal having a pulse width of 10 ms is output.

In the first to third embodiments, the external output terminal plate 261 and the hall computer 262 are connected, the signal output from the external output terminal plate 261 to the hall computer 262 is stopped, and the hall computer 262 is connected. The opening of the inner frame 12 or the front frame 14 is stored, but the present invention is not limited to this. For example, a pachinko machine is provided with an EEPROM (Electronically Erasable and Programmable Read Only Memory) and a backup RAM. Then, an external output terminal plate 261 is connected to the EEPROM or backup RAM. With this configuration, the opening of the inner frame 12 or the front frame 14 can be stored in the EEPROM or the backup RAM. When the power of the pachinko machine is turned on, the MPU 201 confirms the storage of the EEPROM and the backup RAM. Thereby, opening of the inner frame 12 or the front frame 14 can be detected using a pachinko machine. That is, the role of the hall computer 262 can be assigned to the EEPROM or the backup RAM (the role of the “specific device” described in the claims can be assigned to the EEPROM or the backup RAM). Note that the RAM 203 may be used as the backup RAM.

  The present invention has been described above based on one embodiment. However, the present invention is not limited to the above embodiment, and various modifications and improvements can be easily made without departing from the spirit of the present invention. Can be inferred.

  For example, in each of the above embodiments, each command is transmitted from the main control device 110 to the sound lamp control device 113, and the sound lamp control device 113 issues a display instruction to the display control device 114. However, the command may be directly transmitted from the main control device 110 to the display control device 114. Further, an audio lamp control device may be connected to the display control device, and a command instructing the output of each sound and the lighting of the lamp may be transmitted from the display control device to the audio lamp control device. Furthermore, the sound lamp control device and the display control device may be configured as one control device.

  Moreover, in the said embodiment, although it was comprised so that the winning to the 1st entrance 64 and the passage of the 2nd entrance 67 might be held up to 4 times, respectively, the maximum number of times of holding was 4 times. It is not limited and may be set to 3 times or less, or 5 times or more (for example, 8 times). In addition, the number of times the variable display is held based on the winning at the first entrance 64 is different for the part of the third symbol display device 81 by a number or by dividing the number of four divided areas by the number of times of the hold. It may be displayed in a mode (for example, color or lighting pattern), and a light emitting member such as a lamp is provided separately from the first symbol display device 37, and the number of holding times is notified by the light emitting member. You may do it.

  Further, as shown in the above embodiment, the variable display, which is a kind of dynamic display, is not limited to the one that scrolls the symbol as identification information in the vertical direction on the display screen of the third symbol display device 81, It may be performed by moving and displaying symbols along a predetermined route such as a horizontal direction or an L shape. In addition, the dynamic display of the identification information is not limited to the display of variation of the symbol. For example, one or a plurality of characters may be displayed in various manners together with the symbol or displayed in a variety of manners separately from the symbol. The effect display etc. which are displayed are also included. In this case, one or more characters are used as the third symbol.

  You may implement this invention in the pachinko machine etc. of a type different from the said embodiment. For example, the present invention may be applied to a so-called second type pachinko gaming machine having a winning device having a special area such as a V zone. Further, in addition to the pachinko machine, the game machine may be implemented as another game machine such as an alepacchi or a sparrow ball.

  You may implement this invention in the pachinko machine etc. of a type different from the said embodiment. For example, once a big hit, a pachinko machine that raises the expected value of the big hit until a big hit state occurs (for example, two times or three times) including that (for example, a two-time right item, a three-time right item) May also be implemented. Further, after the jackpot symbol is displayed, it may be implemented as a pachinko machine that generates a special game that gives a player a predetermined game value on the condition that a ball is won in a predetermined area. Further, the present invention may be implemented in a pachinko machine that has a special area such as a V-zone and has a special gaming state as a necessary condition for winning a ball in the special area. Further, in addition to the pachinko machine, the game machine may be implemented as various game machines such as an alepatchi, a sparrow ball, a slot machine, a game machine in which a so-called pachinko machine and a slot machine are integrated.

  In the slot machine, for example, a symbol is changed by operating a control lever in a state where a symbol effective line is determined by inserting coins, and a symbol is stopped and confirmed by operating a stop button. Is. Accordingly, the basic concept of the slot machine is that it is provided with a display device for confirming and displaying the identification information after variably displaying the identification information string composed of a plurality of identification information, and resulting from the operation of the starting operation means (for example, the operation lever) The variation display of the identification information is started, and the variation display of the identification information is stopped and fixedly displayed due to the operation of the operation means for stop (for example, the stop button) or when a predetermined time elapses. It is a slot machine that generates a special game that gives a player a predetermined game value on the condition that the combination of identification information at the time is a specific condition. In this case, the game medium is typically a coin, medal, etc. Take as an example.

  In addition, as a specific example of a gaming machine in which a pachinko machine and a slot machine are fused, a display device is provided that displays a symbol after a symbol string composed of a plurality of symbols is variably displayed, and has a handle for launching a ball. What is not. In this case, after throwing a predetermined amount of spheres based on a predetermined operation (button operation), for example, the change of the symbol is started due to the operation of the operation lever, for example, due to the operation of the stop button, or With the passage of time, the variation of the symbol is stopped, and a special game that gives a predetermined game value to the player is generated on the condition that the determined symbol at the time of stoppage is a so-called jackpot symbol. In this case, a large amount of balls are paid out to the lower tray.

  Hereinafter, in addition to the gaming machine of the present invention, concepts of various inventions included in the various embodiments described above are shown. A gaming machine comprising: a main body; a door body that opens and closes a front surface of the main body; and a control unit that is provided in a space formed by the door body and the main body and controls a game. A door opening detecting means for detecting the opening of the body, a signal output means for outputting a signal to a specific device when the door opening detecting means does not detect the opening of the door, and the door opening by the door opening detecting means. And stopping means for stopping signal output to the specific device by the signal output means when the release of the game machine is detected, the signal output means being turned off when the gaming machine is powered off. Even if it is, it is comprised so that a signal can be output to the said specific apparatus, and the said stop means is a case where the power supply of the said game machine is turned off and the said control means has stopped. , The signal output Gaming machine 1, characterized in that it is stopped configured to be able to signal output to the particular device by means.

  According to the gaming machine 1, when the opening of the door body is not detected by the door opening detection means (when the closing of the door body is detected), the signal output means outputs a signal to the specific device. On the other hand, when the door opening detection means detects the opening of the door body, the signal output means stops the signal output to the specific device by the stop means. In this way, when the door is opened, the signal output from the signal output means to the specific device is stopped, so that the gaming machine with the door opened can be determined by the specific device. it can. Here, even when the power of the gaming machine is turned off and the control means is stopped, the signal output means can output a signal to the specific device. In addition, even when the power of the gaming machine is turned off and the control means is stopped, the stop means can stop the signal output to the specific device by the signal output means. Therefore, for example, even if the door body is opened by an unauthorized act by someone after the store is closed with all the gaming machines turned off, the gaming machine with the door body opened can be identified by the specific device.

  As described above, when the door opening detection unit does not detect the opening of the door body, the signal output unit outputs a signal to the specific device. Here, when the communication medium between the signal output means and the specific device is damaged by an unauthorized person, the communication between the signal output means and the specific device is interrupted, so the door opening detection means detects the opening of the door body. Even if it is not made, that is, even if the door is in a closed state, signal output to the specific device remains stopped. Therefore, when the signal output means stops outputting the signal to the specific device when the door is in the closed state, it is possible to detect the breakage of the communication medium between the signal output means and the specific device. .

  In addition, even if there is no abnormality in the communication medium between the signal output means and the specific device, if the signal output means fails and the signal output to the specific device is in a stopped state, the door body Even in the closed state, the signal output to the specific device remains stopped. Similarly, when a failure occurs in the stopping means and the signal output to the specific device by the signal output means is always stopped, the signal output to the specific device even if the door body is in the closed state Will remain stopped. Therefore, if there is no abnormality in the communication medium between the signal output means and the specific device, but the signal output means stops the signal output to the specific device when the door is closed, the signal output means Alternatively, it is possible to detect the failure of either one of the stop means or both.

  In addition, the inside of the space formed by the door body and the main body indicates the back surface or the back surface side (including the back surface side of the main body) of the door body that cannot be touched by a hand when the door body is closed. The detection result output from the output means provided for each of the plurality of gaming machines may be received by one specific device, or a specific device is provided for each gaming machine, and the specific device is distributed to each gaming machine. May be installed. When a specific device is installed in each gaming machine, the box base and the box cover covering the opening of the box base are connected to each other, and the specific device is specified in the space formed by the box cover and the box base. Store the device. Then, the box cover and the box base are connected by the sealing unit so that they cannot be opened. Further, a seal seal is attached to the connecting portion between the box cover and the box base over the box cover and the box base. In addition, a specific device may be disposed on the back surface or the back surface side of the door body.

  In a gaming machine comprising a main body, a door body for opening and closing the front surface of the main body, and a control means for controlling a game provided in a space formed by the door body and the main body, a signal is sent to a specific device. A signal output means for outputting; a door opening detection means for detecting the opening of the door body relative to the main body; and the specific device by the signal output means when the door opening detection means detects the opening of the door body. Stop means for stopping signal output to the stop, stop period limit means for limiting a single stop period of signal output by the stop means within a predetermined period, stop period limit means, stop means, and signal output means A gaming machine (2), comprising: an off-operation means that operates when the power of the gaming machine is turned off and the control means is stopped.

  According to the gaming machine 2, when the door opening detection means detects the opening of the door body, the signal output means stops the signal output to the specific device by the stop means. And the one stop period of the signal output by the stop means is kept within a predetermined period by the stop period limiting means. In this way, when the door is opened, the signal output from the signal output means to the specific device is stopped within a predetermined time, so that the gaming machine with the door opened is specified by the specific device. Can be determined. Here, the stop means, the signal output means, and the stop period limiting means operate by receiving power supply from the off-state operation means while the gaming machine is powered off, so that the door is opened even when the gaming machine is powered off. When the opening of the door body is detected by the detection means, the stop means can stop the signal output by the signal output means to the specific device within a predetermined time. Therefore, for example, even if the door body is opened by an unauthorized act by someone after the store is closed with all the gaming machines turned off, the gaming machine with the door body opened can be identified by the specific device.

  Further, as described above, when the door opening detection means detects the opening of the door body, the stop period limiting means keeps one stop period of signal output by the stop means within a predetermined period. That is, when the door body is opened and the door opening detection means detects the opening of the door body, the signal output from the signal output means to the specific device is stopped only within a predetermined period by the stop period limiting means. It becomes. Here, if the communication medium between the signal output means and the specific device is damaged by an unauthorized person, the communication between the signal output means and the specific device is interrupted, so the signal output to the specific device exceeds the predetermined period. But it remains stopped. Therefore, when the signal output to the specific device by the signal output unit is stopped after a predetermined period, it is possible to detect the breakage of the communication medium between the signal output unit and the specific device.

  In addition, even if there is no abnormality in the communication medium between the signal output means and the specific device, if the signal output means has failed and the signal output to the specific device is in a stopped state, of course, The signal output to the specific device remains stopped even after a predetermined period. Similarly, when a failure occurs in the stop period limiting means or the stop means and the signal output from the signal output means is always stopped, the signal output to the specific device naturally exceeds the predetermined period. But it remains stopped. Therefore, when there is no abnormality in the communication medium between the signal output means and the specific device, but the signal output to the specific device by the signal output means has stopped for a predetermined time, the signal output means, the stop means or the stop It is possible to detect any failure of the period limiting means or all of them.

  In a gaming machine comprising a main body, a door body for opening and closing the front surface of the main body, and a control means for controlling a game provided in a space formed by the door body and the main body, a signal is sent to a specific device. A signal output means for outputting; a door opening detection means for detecting the opening of the door body relative to the main body; and the specific device by the signal output means when the door opening detection means detects the opening of the door body. Stop means for stopping signal output to the stop, stop period restriction means for restricting one stop period of the signal output by the stop means within a predetermined period, stop period restriction means, stop means, and signal output means, An off-operation means for operating the game machine when the power is turned off and the control means is stopped, and the stop means restricts the stop of the signal output by the stop period restriction means Based on the signal output means to stop the signal output to the specific device, the stop period limit means, when the door opening detection means detects the opening of the door body, the stop means to the predetermined means The gaming machine 3 is characterized in that the signal output is stopped during the period.

  According to the gaming machine 3, when the opening of the door body is detected by the door opening detecting means, the signal output to the specific device by the signal output means is stopped by the stopping means. And the one stop period of the signal output by the stop means is kept within a predetermined period by the stop period limiting means. In this way, when the door is opened, the signal output from the signal output means to the specific device is stopped within a predetermined time, so that the gaming machine with the door opened is specified by the specific device. Can be determined. Here, the stop means, the signal output means, and the stop period limiting means operate by receiving power supply from the off-state operation means while the gaming machine is powered off, so that the door is opened even when the gaming machine is powered off. When the opening of the door is detected by the detecting means, the stopping means can stop the signal output by the signal output means to the specific device within a predetermined time. Therefore, for example, even if the door body is opened by an unauthorized act by someone after the store is closed with all the gaming machines turned off, the gaming machine with the door body opened can be identified by the specific device.

  In addition, when the door opening detection unit detects the opening of the door body, the stop period limiting unit limits the stop of the signal output to the stop unit during a predetermined period. Then, the stop means stops the signal output to the specific device by the signal output means for a predetermined period based on the stop restriction. That is, when the door opening detection means detects the opening of the door body, the stop period restriction means restricts the stop of signal output to the stop means during the predetermined period, while the door opening detection means When the opening of the body is not detected or after a predetermined period has elapsed, the stop of the signal output is not restricted for the stop means. Thereby, the stop of the signal output from the signal output means to the specific device can be reliably stopped within a predetermined period for each opening of the door body. Here, if the communication medium between the signal output means and the specific device is damaged by an unauthorized person, the communication between the signal output means and the specific device is interrupted, so the signal output to the specific device exceeds the predetermined period. But it remains stopped. Therefore, when the signal output to the specific device by the signal output unit is stopped after a predetermined period, it is possible to reliably detect the breakage of the communication medium between the signal output unit and the specific device.

  In addition, even if there is no abnormality in the communication medium between the signal output means and the specific device, if the signal output means has failed and the signal output to the specific device is in a stopped state, of course, The signal output to the specific device remains stopped even after a predetermined period. Similarly, when a failure occurs in the stop period limiting means or the stop means and the signal output from the signal output means is always stopped, the signal output to the specific device naturally exceeds the predetermined period. Will also stop. Therefore, when there is no abnormality in the communication medium between the signal output means and the specific device, but the signal output to the specific device by the signal output means has stopped for a predetermined time, the signal output means, the stop means or the stop It is possible to detect any failure of the period limiting means or all of them.

  In a gaming machine comprising a main body, a door body for opening and closing the front surface of the main body, and a control means for controlling a game provided in a space formed by the door body and the main body, a signal is sent to a specific device. A signal output means for outputting; a door opening detection means for detecting the opening of the door body relative to the main body; and the specific device by the signal output means when the door opening detection means detects the opening of the door body. Stop means for stopping signal output to the stop, stop period restriction means for restricting one stop period of the signal output by the stop means within a predetermined period, stop period restriction means, stop means, and signal output means, An off-operation means for operating the game machine when the power is turned off and the control means is stopped, and the stop means restricts the stop of the signal output by the stop period restriction means The signal output means stops signal output to the specific device, and the stop period restriction means releases the restriction on stopping the signal output to the stop means when the predetermined period has elapsed. A gaming machine 4 characterized.

  According to the gaming machine 4, when the opening of the door body is detected by the door opening detection means, the signal output means stops the signal output to the specific device by the stop means. And the one stop period of the signal output by the stop means is kept within a predetermined period by the stop period limiting means. In this way, when the door is opened, the signal output from the signal output means to the specific device is stopped within a predetermined time, so that the gaming machine with the door opened is specified by the specific device. Can be determined. Here, the stop means, the signal output means, and the stop period limiting means operate by receiving power supply from the off-state operation means while the gaming machine is powered off, so that the door is opened even when the gaming machine is powered off. When the opening of the door is detected by the detecting means, the stopping means can stop the signal output by the signal output means to the specific device within a predetermined time. Therefore, for example, even if the door body is opened by an unauthorized act by someone after the store is closed with all the gaming machines turned off, the gaming machine with the door body opened can be identified by the specific device.

  Further, when the door opening detection means detects the opening of the door body, the stop period limiting means limits the signal output to the stop means within a predetermined period. Then, based on this stop restriction, the stop means stops the signal output to the specific device by the signal output means within a predetermined period. Then, when the predetermined period elapses, the stop period restriction unit releases the stop restriction on signal output to the stop unit. Then, a signal is output again from the signal output means to the specific device. That is, when the door body is opened and the door opening detection means detects the opening of the door body, the signal output from the signal output means to the specific device is reliably transmitted for each opening of the door body. , It can be stopped only within a predetermined period. Here, if the communication medium between the signal output means and the specific device is damaged by an unauthorized person, the communication between the signal output means and the specific device is interrupted, so the signal output to the specific device exceeds the predetermined period. But it remains stopped. Therefore, when the signal output to the specific device by the signal output unit is stopped after a predetermined period, it is possible to reliably detect the breakage of the communication medium between the signal output unit and the specific device.

  In addition, even if there is no abnormality in the communication medium between the signal output means and the specific device, if the signal output means has failed and the signal output to the specific device is in a stopped state, of course, The signal output to the specific device remains stopped even after a predetermined period. Similarly, when a failure occurs in the stop period limiting means or the stop means and the signal output from the signal output means is always stopped, the signal output to the specific device naturally exceeds the predetermined period. Will also stop. Therefore, when there is no abnormality in the communication medium between the signal output means and the specific device, but the signal output to the specific device by the signal output means has stopped for a predetermined time, the signal output means, the stop means or the stop It is possible to detect any failure of the period limiting means or all of them.

  In the gaming machine 3 or 4, the stop period limiting means is configured using a monostable multivibrator that limits a single stop period of the signal output by the stop means within a predetermined period by an output signal, An input signal input to the monostable multivibrator is connected to the monostable multivibrator when the door opening detection means detects the opening of the door body, regardless of the door opening period. Input period adjusting means for adjusting to a shorter period, the off-time operating means, in addition to the stop period limiting means, stop means and signal output means, the control means when the power of the gaming machine is turned off The gaming machine 5 is characterized in that the input period adjusting means is also operated when the game is stopped.

  According to the gaming machine 5, the input signal input to the stop period limiting means using the monostable multivibrator is transmitted once by the input means adjusting means regardless of the door opening period. It is adjusted to be shorter than the predetermined period that is the stop period. Here, if the input period of the input signal is not shorter than the output period of the output signal, the monostable multivibrator does not operate normally and continues to output the output signal. For this reason, when the monostable multivibrator is used as the stop period limiting unit, the output period of the output signal, that is, the monostable multivibrator limits the stop of the signal output to the stop unit by the output signal. The input period of the input signal input to the monostable multivibrator, that is, the door opening period must be shorter than the period. However, it is totally unpredictable how long the door will be open. Therefore, the setting of the predetermined period has a sufficient margin so that the opening period of the door body is always shorter than the predetermined period in which the monostable multivibrator limits the stop of the signal output to the stopping means by the output signal. Must be set to a period. In this way, even if the predetermined period is set to a period with a sufficient margin, if the door opening period exceeds the predetermined period, the door is subsequently closed and the door opening is detected. Even if the opening of the door is no longer detected by the means, the monostable multivibrator continues to output the output signal, and the stop means remains restricted from stopping the signal output. As a result, even if the signal output stop exceeds a predetermined period, no signal is output from the signal output means to the specific device, so these signal output means, stop means, and monostable multivibrator are not abnormal. Any or all of the failures will be misidentified. Therefore, a special circuit configuration is necessary to use a monostable multivibrator as the stop period limiting means and to operate the monostable multivibrator normally. However, according to the gaming machine 5, the input signal input to the monostable multivibrator can be adjusted to be shorter than the predetermined period by the input period adjusting means regardless of the door opening period. Therefore, since the monostable multivibrator can be operated normally regardless of the opening period of the door body, one stop period of signal output by the stop means can be kept within a predetermined period. Thus, according to the gaming machine 5, by providing the input period adjusting means, it is possible to realize the stop period limiting means using a monostable multivibrator without adopting a special circuit configuration. Note that the input period adjusting means also operates by receiving power supply from the off-state operating means while the gaming machine is powered off, as with the stop period limiting means, the stopping means, and the signal output means. Therefore, even when the gaming machine is powered off, if the door opening detection means detects the door opening, the input period adjusting means is input to the monostable multivibrator regardless of the door opening period. The input signal can be adjusted to be shorter than a predetermined period.

  In the gaming machine 5, the input period adjusting means is configured by using an integrating circuit.

  According to the gaming machine 6, since the input period adjusting means is configured by using the integration circuit, the input signal input to the monostable multivibrator is shorter than the predetermined period without using a complicated circuit or signal processing. Can be adjusted. Further, by adjusting the resistance value of the resistor used in the integration circuit and the capacitance value of the capacitor, the input period of the input signal input to the monostable multivibrator can be freely adjusted within a predetermined period.

  In the gaming machine 5 or 6, the input period adjusting means includes a constant voltage means for making a maximum voltage of an input signal inputted to the monostable multivibrator constant.

  According to the gaming machine 7, since the constant voltage means is provided, the maximum voltage of the input signal input to the monostable multivibrator is made constant, the input signal input to the monostable multivibrator is stabilized and stopped. One stop period of signal output by the means can be stably kept within a predetermined period.

  In addition, when the input period adjusting means is configured using an integration circuit, electric charge is stored in the capacitor used in the integration circuit, and the voltage due to this electric charge is superimposed on the input signal input to the monostable multivibrator. Therefore, there is a possibility that an overvoltage that can destroy the monostable multivibrator is applied to the monostable multivibrator. However, according to the gaming machine 7, since the maximum voltage of the input signal inputted to the monostable multivibrator is made constant by the constant voltage means, an overvoltage that can destroy the monostable multivibrator is applied to the monostable multivibrator. It will never be done. Therefore, destruction of the monostable multivibrator can be prevented.

  In the gaming machine 7, the constant voltage means comprises a Zener diode.

  According to the gaming machine 8, since the constant voltage means is configured by the Zener diode, it is input to the monostable multivibrator with a simple configuration and at a lower cost than a constant voltage circuit configured by a complicated circuit. The maximum voltage of the input signal can be made constant. Therefore, the input signal input to the monostable multivibrator is stabilized by using an inexpensive Zener diode having a simple configuration, and a single stop period of signal output by the stop means is stably kept within a predetermined period. Further, it is possible to prevent an overvoltage that can destroy the monostable multivibrator from being applied to the monostable multivibrator.

  In the gaming machines 1 to 8, the door body includes an inner frame that is opened and closed with respect to the main body, and a transparent plate support door that is opened and closed with respect to the inner frame. Are provided on the inner frame and the transparent plate support door, respectively, and are connected in parallel to the signal output means and the stop means, and the stop means is detected by the door opening detection means by the inner frame or the transparent plate support door. When at least one of the opening is detected, the signal output means stops the signal output to the specific device.

  According to the gaming machine 9, the door opening detection means is provided on the inner frame and the transparent plate support door, and is connected in parallel to the signal output means and the stopping means. When opening of at least one of the plate support doors is detected, signal output to the specific device by the signal output means can be stopped by the stop means. Therefore, even if one of the inner frame and the transparent plate support door constituting the door body is opened, the opening can be reported to the specific device by one set of signal output means and stop means.

  Any one of the gaming machines 1 to 9 includes an off-state operation means composed of a secondary battery that is charged while the gaming machine is powered on, and the signal output means and the stop means operate during the off-state. A gaming machine 10 that is operated by electric power supplied from the means.

  According to the gaming machine 10, since the off-operation means constituted by the secondary battery is charged while the gaming machine is powered on, simply turning on the gaming machine according to the business hours of the game hall, The operating means can be charged while off. Therefore, if the door is opened while the power of the gaming machine is turned off after the game hall is closed, the signal output means and the stop means are operated by the off-operation means to identify the opening. You can report to the device.

  In any one of the gaming machines 1 to 10, the control means includes main control means for performing main control of the game, and the signal output means is mounted on the main control means. 11.

  The gaming machine 12 according to any one of the gaming machines 1 to 10, wherein the signal output means is mounted on a board different from the control means.

  In any one of the gaming machines 1 to 12, the signal output means includes a photocoupler, and when the output of the photocoupler is stopped by the stop means, the door opening detection means opens the door body. The game machine 13 is characterized by outputting the detection of the above to the specific device.

  In any one of the gaming machines 2 to 13, the stop period limiting means, the stop means, and the signal output means (and the input period adjusting means) are configured to be operable even at a voltage lower than the operating voltage of the control means. A gaming machine 14 characterized by

  According to the gaming machine 14, the signal output means, the stop means, and the stop period restriction means (and the input period adjustment means) are configured to be operable even at a voltage lower than the operating voltage of the control means. Even if the charging amount of the operating means decreases and the output voltage of the operating means during the off state becomes lower than the operating voltage of the control means, the signal output means, the stopping means and the stop period limiting means (and the input period adjusting means) are operated. Thus, the opening of the door can be reported to the specific device. That is, it is possible to detect the opening of the door body for a long time when the gaming machine is powered off.

  In any of the gaming machines 2 to 14, the stop period limiting means, the stop means, and the signal output means (and the input period adjusting means) are configured so that the operable range voltage is wider than the operable range voltage of the control means. A gaming machine 15 characterized by

  According to the gaming machine 15, the signal output means, the stop means, and the stop period limit means (and the input period adjustment means) are configured so that the operable range voltage is wider than the operable range voltage of the control means. Therefore, when the power of the gaming machine is turned off, the signal output means, the stopping means and the stop period limiting means (and the input period adjusting means) can be operated for a long time by the off-time operating means. The door opening detection can be performed for a long time.

  The gaming machine 16 according to any one of the gaming machines 2 to 15, wherein the stop period limiting means includes a C-MOS semiconductor.

  According to the gaming machine 16, the stop period limiting means is configured to have a C-MOS semiconductor. Here, the C-MOS semiconductor generally has low power consumption during operation. Therefore, according to the gaming machine 16, it is possible to detect the opening of the door body for a long time when the power of the gaming machine is turned off by reducing the consumption of the operating means during the off state.

  The gaming machine 17 according to any one of the gaming machines 1 to 16, wherein the gaming machine is a pachinko gaming machine. Above all, the basic configuration of a pachinko gaming machine is provided with an operation handle, and a ball is launched into a predetermined game area according to the operation of the operation handle, and the ball is placed in an operation port disposed at a predetermined position in the game area. As a necessary condition for winning a prize (or passing through the operating port), the identification information dynamically displayed on the display device is confirmed and stopped after a predetermined time. In addition, when a special gaming state occurs, a variable winning device (specific winning opening) disposed at a predetermined position in the gaming area is opened in a predetermined manner so that a ball can be won, and a value corresponding to the number of winnings is obtained. Examples include those to which values (including data written on magnetic cards as well as premium balls) are given.

  A gaming machine 18 according to any one of the gaming machines 1 to 16, wherein the gaming machine is a slot machine. Above all, the basic configuration of the slot machine is “equipped with variable display means for confirming and displaying the identification information after dynamically displaying an identification information string composed of a plurality of identification information, and for operating the starting operation means (for example, an operation lever). As a result, the dynamic display of the identification information is started, and the dynamic display of the identification information is stopped due to the operation of the stop operation means (stop button) or after a predetermined time has elapsed. The game machine is provided with special game state generating means for generating a special game state advantageous to the player on the condition that the confirmed identification information is specific identification information. In this case, examples of the game media include coins and medals.

  The gaming machine 19 according to any one of the gaming machines 1 to 16, wherein the gaming machine is a combination of a pachinko gaming machine and a slot machine. Among them, the basic configuration of the merged gaming machine includes “a variable display means for confirming and displaying the identification information after dynamically displaying an identification information string composed of a plurality of identification information, and a starting operation means (for example, an operation lever). Due to the operation of the identification information, the change of the identification information is started, and the dynamic display of the identification information is stopped due to the operation of the operation means for stop (for example, the stop button) or when a predetermined time elapses. Special game state generating means for generating a special game state advantageous to the player on the condition that the fixed identification information at the time of stoppage is specific identification information, and using a ball as a game medium, and the identification information The game machine is configured such that a predetermined number of balls are required at the start of the dynamic display, and a large number of balls are paid out when the special gaming state occurs.

  A gaming machine comprising: a main body; a door body that opens and closes a front surface of the main body; and a control unit that is provided in a space formed by the door body and the main body and controls a game. A door opening detection means for detecting the opening of the body, and an output means for outputting the detection result to the specific device when the door opening detection means detects the opening of the door body, the output means, The gaming machine 20 is configured to output a detection result by the door opening detection means to the specific device when the power of the gaming machine is turned off and the control means is stopped.

  According to the gaming machine 20, even when the gaming machine is powered off and the control means is stopped, if the door opening detection is detected by the door opening detection means, the detection result is specified by the output means. Output to the device. Therefore, for example, even if the door body is opened by an unauthorized act by someone after the store is closed with all the gaming machines turned off, the gaming machine with the door body opened can be identified by the specific device.

  A gaming machine comprising: a main body; a door body that opens and closes a front surface of the main body; and a control unit that is provided in a space formed by the door body and the main body and controls a game. A door opening detecting means for detecting the opening of the body, an output means for outputting the detection result to the specific device when the door opening detecting means detects the opening of the door, and a one-time output by the output means. An output period limiting means for keeping the output period within a predetermined period, and an off-time operation means for operating the output period limiting means and the output means while the gaming machine is powered off. Machine 21.

  According to the gaming machine 21, when the opening of the door is detected by the door opening detection means, the detection result is output to the specific device by the output means. Since the output means operates by receiving power supply from the off-operation means while the gaming machine is turned off, the door opening detection means detects the opening of the door body even when the gaming machine is powered off. The detection result can be output to a specific device. Therefore, for example, even if the door body is opened by an unauthorized act by someone after the store is closed with all the gaming machines turned off, the gaming machine with the door body opened can be identified by the specific device.

  Moreover, one output period by the output means is kept within a predetermined period by the output period limiting means. Similarly to the output means, the output period limiting means operates by receiving power supply from the off-operation means while the gaming machine is turned off, so that the operation period of the output means by one opening of the door body is within a predetermined period. In other words, it is possible to suppress the consumption of the off-operation means during the power-off of the gaming machine. Therefore, the frequency | count of operation | movement of an output means can be increased and the frequency | count of detection of opening of a door body can be increased.

  A gaming machine comprising: a main body; a door body that opens and closes a front surface of the main body; and a control unit that is provided in a space formed by the door body and the main body and controls a game. A door opening detecting means for detecting the opening of the body, an output means for outputting the detection result to the specific device when the door opening detecting means detects the opening of the door, and a one-time output by the output means. An output period limiting unit that keeps the output period within a predetermined period; and an off-period operation unit that operates the output period limiting unit and the output unit while the gaming machine is powered off. A detection result is output to the specific device based on an output from the period limiting unit, and the output period limiting unit is configured to output the detection result during the predetermined period when the door opening detection unit detects the opening of the door body. output Gaming machine 22 and performs output to a stage.

  According to the gaming machine 22, when the door opening detection means detects the opening of the door body, the detection result is output to the specific device by the output means. Since the output means operates by receiving power supply from the off-operation means while the gaming machine is turned off, the door opening detection means detects the opening of the door body even when the gaming machine is powered off. The detection result can be output to a specific device. Therefore, for example, even if the door body is opened by an unauthorized act by someone after the store is closed with all the gaming machines turned off, the gaming machine with the door body opened can be identified by the specific device.

  Moreover, one output period by the output means is kept within a predetermined period by the output period limiting means. Similarly to the output means, the output period limiting means operates by receiving power supply from the off-operation means while the gaming machine is turned off, so that the operation period of the output means by one opening of the door body is within a predetermined period. In other words, it is possible to suppress the consumption of the off-operation means during the power-off of the gaming machine. Therefore, the frequency | count of operation | movement of an output means can be increased and the frequency | count of detection of opening of a door body can be increased.

Further, the output means for outputting the detection result to the specific device based on the output from the output period restriction means is output by the output period restriction means during a predetermined period when the door opening detection is detected by the door opening detection means. Output is done. Therefore, the output operation to the output means by the output period limiting means can be stopped within a predetermined period for each opening of the door body. Accordingly, it is possible to suppress consumption of the off-operation means while the power of the gaming machine is turned off, and to increase the number of times that the output means can be operated, thereby increasing the number of times that the door body can be detected.
<Others>
In a pachinko machine, when a ball that has been driven into a game area enters the symbol operating port, a lottery is performed at the timing of the entry (for example, JP 2001-198332 A). Further, in a spinning-type game machine using a slot machine or a game ball, when a start lever is operated, a lottery is performed at the operation timing. As a result of the lottery, for example, when a big hit is made, a large amount of prize balls and coins can be paid out. Since the control for determining the lottery and the jackpot is performed by the main control device, the main control device is likely to be an object of fraud.
Specifically, for example, the main control device may be replaced with an unauthorized one that frequently generates jackpots, or an illegal board (for example, a “hanging board”) may be connected to the main control apparatus. There are things that illegally generate. In addition, in the case of a pachinko machine, there is also a fraudulent act that makes it easier for a ball to enter a winning port or a symbol operating port by illegally bending a nail that has been driven onto the game board surface.
In the case of a pachinko machine, the main control device is mounted on the back of the game board. On the other hand, a glass frame is provided on the front surface of the game board, and the glass frame can be individually opened and closed with respect to the inner frame body on which the game board is mounted. Therefore, when a cheating person performs cheating on the game board surface or the main control device, the inner frame or the glass frame must be opened, but when the inner frame or the glass frame is opened, Since the opening is detected by the sensor and reported to the hall computer that manages the game hall, it is possible to easily grasp which pachinko machine has been cheated.
However, if, for example, late at night after the amusement hall is closed, a fraudulent person enters, and the intruder opens the inner frame or the glass frame and conducts a fraudulent action, the pachinko machine is turned off at that time. Since the pachinko machine is stopped, the opening of the inner frame or the glass frame cannot be detected, and the opening cannot be reported to the hall computer.
<Means>
To achieve this object, the gaming machine described in the technical idea 1 is a game control provided in a space formed by a main body, a door body for opening and closing the front surface of the main body, and the door body and the main body. Control means for performing the operation, and a door opening detection means for detecting the opening of the door body with respect to the main body, and a signal to the specific device when the door opening detection means does not detect the opening of the door body. Signal output means for outputting the signal output, and stop means for stopping signal output to the specific device by the signal output means when the door opening detection means detects the door opening. The means is configured to be capable of outputting a signal to the specific device even if the control means is stopped because the power source of the gaming machine is turned off, and the stopping means is a power source of the gaming machine. Is turned off Even when the control means is stopped, and is stoppable configured signal output to the specific device according to the signal output means.
The gaming machine described in the technical idea 2 is the gaming machine described in the technical idea 1, wherein the door body includes an inner frame that is opened and closed with respect to the main body, and a transparent plate support door that is opened and closed with respect to the inner frame. The door opening detection means is provided on the inner frame and the transparent plate support door, respectively, and is connected in parallel to the signal output means and the stopping means. When the door opening detecting means detects the opening of at least one of the inner frame or the transparent plate support door, the signal output means stops the signal output to the specific device.
The gaming machine described in the technical idea 3 is provided with an off-operation means configured by a secondary battery that is charged while the gaming machine is powered on in the gaming machine described in the technical idea 1 or 2. The signal output means and the stop means are operated by electric power supplied from the operation means during the off state.
<Effect>
According to the gaming machine described in the technical idea 1, when the door opening detection means does not detect the opening of the door (when the door closing is detected), the signal output means sends a signal to the specific device. Is output. On the other hand, when the door opening detection means detects the opening of the door body, the signal output means stops the signal output to the specific device by the stop means. In this way, when the door is opened, the signal output from the signal output means to the specific device is stopped, so that the gaming machine with the door opened can be determined by the specific device. it can. Here, even when the power of the gaming machine is turned off and the control means is stopped, the signal output means can output a signal to the specific device. In addition, even when the power of the gaming machine is turned off and the control means is stopped, the stop means can stop the signal output to the specific device by the signal output means. Therefore, for example, even after the store is closed with all the gaming machines turned off, even if the door is opened due to an unauthorized act by someone, the gaming machine with the opened door can be identified by the specific device. is there.
As described above, when the door opening detection unit does not detect the opening of the door body, the signal output unit outputs a signal to the specific device. Here, when the communication medium between the signal output means and the specific device is damaged by an unauthorized person, the communication between the signal output means and the specific device is interrupted, so the door opening detection means detects the opening of the door body. Even if it is not made, that is, even if the door is in a closed state, signal output to the specific device remains stopped. Therefore, when the signal output means stops outputting the signal to the specific device when the door is in the closed state, it is possible to detect the breakage of the communication medium between the signal output means and the specific device. There is an effect.
In addition, even if there is no abnormality in the communication medium between the signal output means and the specific device, if the signal output means fails and the signal output to the specific device is in a stopped state, the door body Even in the closed state, the signal output to the specific device remains stopped. Similarly, when a failure occurs in the stopping means and the signal output to the specific device by the signal output means is always stopped, the signal output to the specific device even if the door body is in the closed state Will remain stopped. Therefore, if there is no abnormality in the communication medium between the signal output means and the specific device, but the signal output means stops the signal output to the specific device when the door is closed, the signal output means In addition, there is an effect that it is possible to detect a failure of either one of the stop means or both of them.
According to the gaming machine described in the technical idea 2, in addition to the effects produced by the gaming machine described in the technical idea 1, the following effects are achieved. That is, the door opening detection means is provided on each of the inner frame and the transparent plate support door and is connected in parallel to the signal output means and the stop means, so that at least the inner frame or the transparent plate support door is detected by the door opening detection means. When one of the openings is detected, signal output to the specific device by the signal output means can be stopped by the stop means. Therefore, even if one of the inner frame and the transparent plate support door constituting the door body is opened, the opening can be reported to the specific device by one set of signal output means and stop means. is there.
According to the gaming machine described in the technical idea 3, in addition to the effect produced by the gaming machine described in the technical idea 1 or 2, the off-operation means constituted by the secondary battery is charged while the gaming machine is turned on. Therefore, the off-operation means can be charged only by turning on the power of the gaming machine in accordance with the business hours of the game hall. Therefore, if the door is opened while the power of the gaming machine is turned off after the game hall is closed, the signal output means and the stop means are operated by the off-operation means to identify the opening. There is an effect that it can be reported to the device.

10 Pachinko machines (game machines)
11 Outer frame (main body)
12 Inner frame (part of door)
14 Front frame (transparent plate support door, part of door)
110 Main control device (part of control means, main control means)
260, 270, 280 Frame opening detection circuit (part of signal output means)
261 External output terminal board (part of signal output means)
IC1 timer (part of stopping means)
PR1 Photocoupler (part of signal output means)
SB1 battery (operating means while off)
SW1, SW2 switch (door open detection means)
TR1 transistor (part of stopping means)

Claims (3)

In a gaming machine comprising a main body, a door body for opening and closing the front surface of the main body, and a control means for controlling a game provided in a space formed by the door body and the main body,
Door opening detection means for detecting the opening of the door body with respect to the main body;
A signal output means for outputting a signal to the specific device when the door opening detection means does not detect the opening of the door body;
Stop means for stopping signal output to the specific device by the signal output means when the door opening detection means detects the opening of the door body;
The signal output means is configured to be able to output a signal to the specific device even when the gaming machine is powered off and the control means is stopped,
The stop means is configured to be capable of stopping signal output to the specific device by the signal output means even when the power of the gaming machine is turned off and the control means is stopped. A featured gaming machine. The door body includes an inner frame that is opened and closed with respect to the main body, and a transparent plate support door that is opened and closed with respect to the inner frame.
The door opening detection means is provided in each of the inner frame and the transparent plate support door, and is connected in parallel to the signal output means and the stopping means,
The stop means stops signal output to the specific device by the signal output means when the door open detection means detects the opening of at least one of the inner frame or the transparent plate support door. The gaming machine according to claim 1. Comprising an off-operation means composed of a secondary battery charged during power-on of the gaming machine,
The gaming machine according to claim 1 or 2, wherein the signal output means and the stop means are operated by electric power supplied from the operation means during the off state.

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