JP2015173291A - semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can maintain avalanche withstanding capabilities to be high even when a gate structure is refined and ON resistance is reduced.SOLUTION: A semiconductor device comprises: a first electrode; a first conductivity type first semiconductor region provided on the first electrode; a second conductivity type second semiconductor region provided on the first semiconductor region; a plurality of second electrodes which are located on the first semiconductor region and provided in a second direction orthogonal to a first direction from the first electrode toward the first semiconductor region; and third electrodes which are located on the first semiconductor region and provided in the second direction and among the second electrodes. A length from a top face of the second electrode to the first electrode in the first direction is larger than a length from a top face of the third electrode to the first electrode in the first direction.

Description

  The present invention relates to a semiconductor device, for example, an IGBT (Insulated Gate Bipolar Transistor), an IEGT (Injection Enhanced Gate Transistor), a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), a super junction MOSFET, a thyristor, a GTO (Gate Turn Off). ) It relates to a power control semiconductor device such as a thyristor.

  A semiconductor device for power control is required to have a low ON resistance during a switching operation in order to reduce power loss. For this reason, power devices such as MOSFETs and IGBTs employ a trench gate structure in which a gate electrode is embedded in a trench.

  In the trench gate structure, since the current channel is formed in the vertical direction perpendicular to the substrate, the gate interval in the horizontal direction can be reduced. Thereby, the device structure can be miniaturized and the substantial channel width can be widened, and the ON resistance can be made smaller than that of the gate structure in which the channel is formed in the lateral direction. Further, since the device size can be reduced, it is advantageous in that the switching speed is increased and the performance is improved.

  On the other hand, when the gate interval is narrowed and the device structure is further miniaturized, there is a problem that the avalanche resistance decreases and the short-circuit current increases. In contrast, for example, in the technique disclosed in Patent Document 1, by forming a trench contact to the base layer between the gate electrodes, the ON resistance can be reduced while maintaining the drain-source breakdown voltage. However, since a space for forming a trench contact is required, there is a problem that miniaturization is limited.

JP 2009-135360 A

  Provided is a semiconductor device capable of maintaining a high avalanche resistance even if the gate structure is miniaturized to reduce the ON resistance.

  The semiconductor device includes: a first electrode; a first conductivity type first semiconductor region provided on the first electrode; a second conductivity type second semiconductor region provided on the first semiconductor region; A plurality of second electrodes provided on the first semiconductor region and provided in a second direction orthogonal to the first direction from the first electrode toward the first semiconductor region; and located on the first semiconductor region. A third electrode provided between the second electrodes in the second direction, and a length from the upper surface of the second electrode to the first electrode in the first direction is the first direction. Is longer than the length from the upper surface of the third electrode to the first electrode.

  Even if the gate structure is miniaturized to reduce the ON resistance, a semiconductor device capable of maintaining a high avalanche resistance can be realized.

It is a fragmentary sectional view showing typically the structure of the semiconductor device concerning a 1st embodiment. It is a schematic diagram explaining operation | movement of the semiconductor device which concerns on 1st Embodiment. It is a graph which shows the characteristic of the semiconductor device concerning a 1st embodiment. It is a fragmentary sectional view showing typically the structure of the semiconductor device concerning the modification of a 1st embodiment. It is a graph which shows the characteristic of the semiconductor device concerning a 1st embodiment. It is a graph which shows the characteristic of the semiconductor device concerning a 1st embodiment. It is a fragmentary sectional view showing typically the structure of the semiconductor device concerning the modification of a 1st embodiment. It is a fragmentary sectional view showing typically the structure of the semiconductor device concerning the modification of a 1st embodiment. It is a fragmentary sectional view showing typically the structure of the semiconductor device concerning a 2nd embodiment. It is a fragmentary sectional view showing typically the structure of the semiconductor device concerning the modification of a 2nd embodiment. It is a fragmentary sectional view showing typically the structure of the semiconductor device concerning the modification of a 2nd embodiment. It is a fragmentary sectional view showing typically the structure of the semiconductor device concerning the modification of a 2nd embodiment. It is a fragmentary sectional view showing typically the structure of the semiconductor device concerning the modification of a 3rd embodiment. It is a fragmentary sectional view showing typically the structure of the semiconductor device concerning the modification of a 3rd embodiment. It is a fragmentary sectional view showing typically the structure of the semiconductor device concerning a 4th embodiment. It is a schematic diagram which shows the example of the conventional MOSFET.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same parts in the drawings are denoted by the same reference numerals, detailed description thereof will be omitted as appropriate, and different parts will be described as appropriate. In the following description, the first conductivity type means P type, and the second conductivity type means N type.

[First Embodiment]
FIG. 1 is a partial cross-sectional view schematically showing the structure of the semiconductor device according to the first embodiment. Here, MOSFET 1 will be described as an example of a semiconductor device, but the present invention can also be applied to other semiconductor devices such as IGBT and IEGT.

  As shown in FIG. 1, the semiconductor device according to the present embodiment includes an N-type drift region 2 and a base region 3 that is a P-type first semiconductor region provided in contact with the drift region 2. Yes. A source electrode 12 that is a main electrode facing the drift region 2 with the base region 3 interposed therebetween is provided and is electrically connected to the base region 3. On the other hand, at the boundary between the drift region 2 and the base region 3, a plurality of gate electrodes 6 that are first gate electrodes having a trench structure are provided along the boundary. The first gate electrode is in contact with the drift region 2 and the base region 3 via a gate insulating film 8a that is a first gate insulating film.

  Furthermore, between the two gate electrodes 6, the gate electrode 7, which is the second gate electrode of the trench structure, extends along the boundary between the drift region 2 and the base region 3 to the drift region 2 and the base region 3. The gate insulating film 8b, which is a gate insulating film, is provided so as to be in contact therewith. The gate electrode 7 has a length shorter than the gate electrode 6 in contact with the base region 3 in the direction from the boundary between the drift region 2 and the base region 3 toward the source electrode 12.

  The source electrode 12 extends between the two gate electrodes 6 in a trench 9 b provided in a direction from the source electrode toward the gate electrode 7 to a position close to the gate electrode 7. Further, the source electrode 12 is in contact with the base region 3 exposed on the inner wall surface of the trench 9b between the end of the gate electrode 6 on the source electrode 12 side and the end of the gate electrode 7 on the source electrode 12 side. .

  Further, as shown in the portion excluding the source electrode 12 in FIG. 1, in the MOSFET 1 according to the present embodiment, the source region 4 that is an N-type second semiconductor region is provided between the base region 3 and the source electrode 12. A P-type contact region 5 is selectively provided. The gate electrode 6 provided in the trench 9a is in contact with the drift region 2, the base region 3 and the source region 4 through the gate insulating film 8a, and is formed at the interface between the base region 3 and the gate insulating film 8a. Control the channel. On the other hand, in the trench 9b, the source electrode 12 extends toward the gate electrode 7 and is in contact with the base region 3 between the source region 4 and the drift region 2 exposed on the inner wall surface of the trench 9b.

  For example, in the conventional MOSFET shown in FIG. 16, all the gate electrodes 6 provided in the trench are in contact with the drain region 2, the base region 3 and the source region 4 through the gate insulating film 8. Therefore, for example, holes injected from the drift region 2 into the base region 3 are discharged to the source electrode 12 through the contact region 5 selectively provided on the base region 3. On the other hand, in the MOSFET 1 according to the present embodiment, by providing the gate electrode 7, holes can be directly discharged from the base region 3 exposed on the inner wall surface of the trench 9b to the source electrode 12.

  An N-type semiconductor region 13 and an N-type drain region 14 having a higher concentration of N-type impurities than the drift region 2 are provided on the opposite side of the surface of the drift region 2 that contacts the base region 3. Further, a drain electrode (not shown) is provided so as to be electrically connected to the drain region 14. Here, for example, if the drain region 14 is a semiconductor region doped with a P-type impurity, FIG. 1 has an IGBT or IEGT structure.

  FIG. 2 is a schematic diagram for explaining the operation of the MOSFET 1 according to the first embodiment. FIG. 2A schematically shows a part of the cross-sectional structure of the MOSFET 1. 2B and 2C are cross-sectional views showing the operation of the MOSFET.

To reduce the ON resistance of MOSFET1 is to reduce the width _{W C} of the base region 3 between the gate electrode 6 and the gate electrode 7 shown in FIG. 2 (a), the number of gate electrodes 6 included in MOSFET1 Can be increased. Thereby, the number of current channels formed at the interface between the gate insulating film 8 and the base region 3 can be increased, and the ON resistance can be reduced.

On the other hand, if the width W _C of the base region 3 is narrowed, the amount of P-type impurity contained in the base region 3 is reduced. For example, when miniaturization to 200 nm or less, the amount of holes injected from the drift region 2 into the base region 3 cannot be ignored with respect to the amount of P-type impurities contained in the base region 3. That is, there arises a problem that a current channel formed at the interface between the base region 3 and the gate insulating film 8 is affected. For example, when positively charged holes are injected, the P-type carrier concentration in the base region 3 substantially changes, and the threshold voltage V _TH varies. For this reason, the current flowing between the source and the drain may not be controlled by the gate voltage applied to the gate electrode.

Therefore, in the case of narrower width W _C of the base region 3, as a hole in the base region 3 is not accumulated, it must be discharged smoothly holes to the source electrode 12 through the contact region 5 of the P-type There is. For example, as in the conventional MOSFET shown in FIG. 16, the gate electrode 6 is adjacent to the source region 4 and the contact region 5, and is provided symmetrically with the gate electrode 6 with the base region 3 interposed therebetween. The holes injected into the base region 3 move to the source electrode 12 through the contact region 5. Therefore, it is necessary to provide wider W _P of the contact region 5, but then the width W _N of the source region 4 is relatively narrow and becomes ON resistance increases.

  Therefore, in the MOSFET according to the present embodiment, the gate electrode 7 is formed in the gate insulating film 8b so that the length of the gate electrode 7 adjacent to the base region 3 is shorter than the length of the gate electrode 6 adjacent to the base region 3. Are provided adjacent to part of the drift region 2 and the base region 3. Thus, the source electrode 12 is in contact with a part of the base region 3 exposed between the gate electrode 7 and the source region 4.

As shown in FIG. 2B, the holes injected from the drift region 2 into the base region 3 are portions where the base region 3 between the gate electrode 7 and the source region 4 and the source electrode 12 are in contact with each other. To the source electrode 12. Therefore, when the width d ₁ in the direction from the source region 4 to the drift region 2 at the portion where the source electrode 12 is in contact with the base region 3 is widened, holes are discharged more smoothly. For example, d ₁ > 0.05 μm can be set.

This prevents the holes are accumulated in the base region 3, it is possible to suppress variation in V _TH. In addition, since the discharge resistance of holes discharged from the drift region 2 to the source electrode 12 via the base region 3 is reduced, the holes generated in the drift region 2 can be discharged smoothly and the avalanche resistance can be improved. Can also be obtained.

On the other hand, in the MOSFET according to the present embodiment, since the gate electrode 7 is separated from the source region 4, the current that flows directly from the source region 4 to the drift layer 2 through the channel formed between the gate electrode 7 and the base region 3. There is also the detrimental effect of having no pass. However, when decreasing the width W _C of the base region 3, as shown in FIG. 2 (b), the current I _N2 flowing through the channel of the gate electrode 7 side, the current channel of the gate electrode 6 side Since it joins and contributes to the flowing current I _N1 , the channel resistance is lowered and the effect of reducing the ON resistance can be obtained.

  If the effect of the MOSFET according to the present embodiment is viewed from another viewpoint, it can be grasped as follows. That is, when comparing the area where the source electrode 12 is in contact with the P-type region including the contact region 5 and the base region 3, the trench 9b in which the gate electrode 7 is embedded rather than the trench 9a in which the gate electrode 6 is embedded. In this case, the source electrode 12 is in contact with the P-type region over a larger area. Therefore, the area where the source electrode 12 contacts the P-type region can be relatively widened, and holes can be efficiently discharged from the base region 3 to the source electrode 12.

FIG. 2C is a schematic diagram showing an N channel 16 formed between the gate electrode 7 and the base region 3. When a positive gate voltage is applied to the gate electrode 7, an inversion layer in which electrons are attracted to the interface between the gate insulating film 8 and the base region 3 is formed. As shown in the figure, the inversion layer is formed to extend in the direction of the source electrode 12 at the end of the gate electrode 7 on the source region side. When the channel end portion 16a is connected to the source electrode 12, a current path is formed from the source electrode 12 to the drift layer 2, and there is a possibility that an excessive current flows. Therefore, the distance d ₂ between the end and the source electrode of the gate electrode 7 of the inner wall surface of the trench 9b, it is advisable to some extent widened. For example, d ₂ > 0.05 μm can be set.

For example, a gate insulating film 8 having a thickness such that d ₂ > 0.05 μm can be formed between the end of the gate electrode 7 and the source electrode 12, and the end of the gate electrode 7 A gap may be provided between the source electrode 12 and the source electrode 12.

  FIG. 3 is a graph showing the characteristics of the MOSFET 1 according to the first embodiment. The vertical axis represents the drain current flowing between the source and the drain, and the horizontal axis represents the gate voltage. A graph A shown in the figure shows the characteristics of the MOSFET 1 according to the present embodiment. Graph B shows the drain current when the width d1 of the portion where the source electrode 12 is in contact with the base region 3 between the gate electrode 7 and the source region 4 is narrower than 0.05 μm. On the other hand, graph C shows the characteristics of the conventional MOSFET shown in FIG.

As shown in FIG. 3, the source - even when the bias voltage V _d between the drain and 44V is applied, when the gate voltage is 0V, MOSFET 1 in the drain current according to the present embodiment shown in graph A does not flow. On the other hand, a drain current flows in the MOSFETs shown in graphs B and C. That is, in the MOSFET shown in the graph B in which d1 <0.05 μm and the conventional MOSFET shown in the graph C, gate control may be disabled. Therefore, it can be seen that the MOSFET 1 according to this embodiment is more advantageous in that d1> 0.05 μm and holes are discharged directly from the base region 3 to the source electrode 12.

FIG. 4 is a partial cross-sectional view schematically showing the structure of the MOSFET 10 according to a modification of the first embodiment. In a portion where the base region 3 exposed between the source region 4 and the gate electrode 7 and the source electrode 12 are in contact with each other, a P ⁺ region 18 which is a third semiconductor region having a P-type impurity concentration higher than that of the base region 3. Is different from MOSFET 1 shown in FIG. By providing the P ⁺ region 18, an excessive drain current flowing between the source and the drain can be suppressed.

  5 and 6 are graphs showing the characteristics of the MOSFET 1 and the MOSFET 10 according to the first embodiment. The vertical axis represents the short-circuit current that flows when the load between the source and drain is short-circuited, and the horizontal axis represents the drain voltage. Graph A in the figure shows the short-circuit current of MOSFET 1, and graph D shows the short-circuit current of MOSFET 10. Graph C shows the short-circuit current of the conventional MOSFET shown in FIG.

  In the MOSFET 1 shown in the graph A, since the channel 16 formed on the gate electrode 7 side is not directly connected to the source region 4, the short-circuit current merges with the current flowing in the current channel on the gate electrode 6 side to the source region 2. Concentrate and flow. Therefore, the resistance to the short-circuit current that flows excessively increases as compared with the conventional MOSFET in which current also flows in the channel on the gate electrode 7 side. As a result, compared to the conventional MOSFET shown in graph C, the short circuit current is limited to about ½. As a result, the gate voltage applied to the gate electrodes 6 and 7 can be set to 0 V to cut off the short-circuit current.

On the other hand, in the MOSFET 10 shown in the graph D, the short-circuit current is further reduced to about 1/5 of the conventional MOSFET and about 1/3 of the MOSFET 1 shown in the graph A. This is presumably because the P ⁺ region 18 provided in the base region 3 narrows the current path and limits the short-circuit current. Thereby, even if the load connected between the source and the drain is short-circuited, it becomes easy to control the short-circuit current by the gate voltage.

  FIG. 6 is an enlarged view of the low voltage portion of the graph of FIG. 5 showing the relationship between the short-circuit current and the drain voltage. As shown in the figure, until the short-circuit current is about 0.12 A, the graph C showing the characteristics of the conventional MOSFET and the graph A showing the characteristics of the MOSFET 1 are substantially the same. In other words, for the drain current up to about 0.12 A, the MOSFET 1 in which the channel on the gate electrode 7 side is separated from the source region 4 can maintain a low ON resistance without increasing the channel resistance. .

On the other hand, in the MOSFET 10 shown in the graph D, the channel resistance is slightly increased by providing the P ⁺ region 18 in the base region 3, but it can be seen that the short-circuit current suppressing effect is high.

  FIG. 7 is a partial cross-sectional view schematically showing the structure of MOSFETs 20 and 30 according to a modification of the first embodiment.

  In the MOSFET 20 shown in FIG. 7A, the contact region 5 is formed deeper than the source region 4 in the direction of the base region 3. As a result, the discharge resistance of the path through which holes injected from the drift layer 2 into the base region 3 are discharged through the P-type contact region 5 can be lowered. As a result, the concentration fluctuation of the P-type carrier in the base region can be suppressed, the controllability of the drain current by the gate voltage can be improved, and the avalanche resistance between the base region 3 and the drift layer 2 can be improved. You can also

The MOSFET 30 shown in FIG. 7B has a structure in which a P ⁺ region 18 is further provided in the base region 3 of the MOSFET 20 shown in FIG. Thereby, a short circuit current can be suppressed and a short circuit tolerance can be improved.

  FIG. 8 is a partial cross-sectional view schematically showing the structure of MOSFETs 40 and 50 according to a modification of the first embodiment.

  In the MOSFET 30 shown in FIG. 8A, the source region 4 is provided on the surface of the base region 3 along the gate electrode 6. As a result, the source region 4 can be connected to all the current channels formed between the gate electrode 6 and the base region 3, and the channel resistance can be lowered to reduce the ON resistance.

  On the other hand, the contact region 5 is formed on the gate electrode 7 side in parallel with the source region 4. Thereby, the path of holes discharged from the base region 3 is only the source electrode that contacts on the gate electrode 7 side, but the contact area can be increased to reduce the hole discharge resistance.

  In the MOSFET 50 shown in FIG. 8B, a super junction in which P-type pillars 21 as fifth semiconductor regions and N-type pillars 22 as fourth semiconductor regions are alternately arranged along the boundary with the base region 3. A drift region 2 of the structure is provided. By using the super junction structure, it is possible to increase the concentration of the N-type pillar 22 and reduce the ON resistance.

[Second Embodiment]
FIG. 9 is a partial cross-sectional view schematically showing the structure of the semiconductor device according to the second embodiment. The MOSFET 60 according to the present embodiment has a lateral structure provided on the main surface of the insulating layer 31. The insulating layer 31 may be, for example, an insulating film such as SiO ₂ provided on the substrate, or a semi-insulating semiconductor layer.

  As shown in FIG. 9A, the MOSFET 60 includes a drift region 32 including an N-type semiconductor provided on the main surface of the insulating layer 31 (or a semi-insulating layer) and a lateral drift parallel to the main surface. A base region 33 that is a P-type first semiconductor region provided adjacent to the region 32; a source region 34 that is an N-type second semiconductor region provided adjacent to the base region 33 in the lateral direction; It has. Further, a source electrode 38 as a main electrode is provided in contact with the side surface opposite to the side surface in contact with the base region 33 of the source region 34.

  A plurality of trenches 45 are formed along the boundary between the drift region 32 and the base region 33 in the direction from the surface straddling the drift region 32, the base region 33, and the source region 34 toward the insulating layer 31. A gate electrode 35 that is a first gate electrode is provided in the trench 45. Further, a trench is formed between the two gate electrodes 35 from the surface straddling the drift region 32 and a part of the base region 33 in the direction of the insulating layer 31 along the boundary between the drift region 32 and the base region 33. 46 is formed. A gate electrode 36 that is a second gate electrode is provided in the trench 46. Accordingly, in the direction from the boundary between the drift region 32 and the base region 33 toward the source electrode 38, the gate electrode 35 has a length that contacts the base region 33 via the gate insulating film 37b. And a length shorter than the length in contact with the base region 33.

  Further, a part of the source electrode 38 is provided between the two gate electrodes 35 so as to extend in a trench 47 formed in a direction from the source electrode 38 to the gate electrode 46. The trench 47 is formed from the surface straddling the source region 34 and a part of the base region 33 in the direction of the insulating layer 31. The source electrode 38 extends in the trench 47 beyond the end of the gate electrode 35 on the source electrode 38 side to a position close to the gate electrode 46, and between the gate electrode 36 and the source region 34. The base region 33 exposed on the inner wall surface of the trench 47 is electrically connected.

  An N-type semiconductor region 41 having an N-type impurity concentration higher than that of the drift region 32 and a drain region 42 are provided adjacent to the drift region 32 and adjacent to the drift region 32. Further, a drain electrode 43 that is electrically connected to the drain region 42 is provided.

  Moreover, FIG.9 (b) is a schematic diagram which shows the IXb-IXb cross section shown in Fig.9 (a). As shown in the figure, the trench 45 can be provided in communication with the insulating layer 31. A gate insulating film 37a is formed on the inner surface of the trench 45, and the inside of the trench 45 is filled with a gate electrode 35 made of, for example, conductive polysilicon. The gate electrode 36 formed in the trench 46 can be formed similarly. The same applies to the MOSFETs according to the embodiments shown up to FIG.

  In the MOSFET 60 according to the present embodiment, the extending portion 39 of the source electrode 38 is provided in a trench 47 that communicates with the insulating layer 31 from the surface extending from the surface of the source region 34 to a part of the surface of the base region 33. Yes. As a result, the source electrode 38 contacts the base region 33 exposed on the inner surface of the trench 47 between the gate electrode 36 and the source region 34, and discharges holes injected from the drift region 32 into the base region 33. be able to.

  Further, the width d1 of the contact portion where the extended portion 39 contacts the base region 33 is set to 0.05 μm or more, so that it is possible to prevent a problem that the drain current flowing between the source and the drain becomes uncontrollable by the gate voltage. .

  The MOSFET 60 according to the present embodiment has, for example, a semiconductor provided on the insulating layer 31 when the drift region 32, the base region 33, the source region 34, and the like formed on the insulating layer 31 are thin. The layer can be formed by ion implantation of N-type and P-type impurities. Moreover, when each semiconductor region is provided thick, it can be formed by combining a plurality of times of epitaxial growth and ion implantation. The same applies to the lateral MOSFET described in FIG. Here, the thickness means a layer thickness from the insulating layer 31 to the surface direction of each semiconductor region.

  Also in this embodiment, for example, if the drain region 42 is a P-type semiconductor region doped with a P-type impurity, FIG. 9 shows an IGBT or IEGT structure. The same applies to the embodiments shown up to FIG.

  FIG. 10 is a partial cross-sectional view schematically showing the structure of a MOSFET 70 according to a modification of the second embodiment. In the drift region 32, the MOSFET 70 alternates between the P-type pillar 21 that is the fifth semiconductor region and the N-type pillar 22 that is the fourth semiconductor region along the boundary between the drift region 32 and the base region 33. It has a super junction structure.

  Similarly to the MOSFET 60 shown in FIG. 9, also in the MOSFET 70 according to this modification, the base region 33 is formed from the contact portion between the gate electrode 36 and the source region 34 where the extended portion 36 of the source electrode 38 contacts the base region 33. Holes can be discharged to the source electrode 38. Thereby, the threshold voltage VTH can be stabilized, so that the width of the base region 33 between the gate electrode 35 and the gate electrode 36 can be reduced. Therefore, the channel resistance can be reduced by increasing the number of MOSFET channels. Further, by using the super junction structure, the concentration of the N-type pillar 22 connected to the base region 33 can be increased and the resistance of the drift region can be reduced. Thereby, the ON resistance of the MOSFET 70 can be reduced.

  FIG. 11 is a partial cross-sectional view schematically showing the structure of a MOSFET 80 according to a modification of the second embodiment. As shown in the figure, the drift region 32 of the MOSFET 80 has a super junction structure in which P pillars and N pillars are alternately stacked upward from the insulating layer 31.

  The MOSFET 80 according to this modification has an N-type semiconductor layer 24 that is an N-type first semiconductor layer and a P-type that is a P-type second semiconductor layer on the main surface of the insulating layer 31 (or a semi-insulating layer). The stacked body 27 in which the semiconductor layers 25 are alternately provided is provided, and the drift region 32 has a super junction structure. Further, a source electrode 38 that is a first main electrode is electrically connected to one side surface of the stacked body 27, and a drain electrode 43 that is a second main electrode is electrically connected to the other side surface. Connected to each other.

  Further, the multilayer body 27 is a base region 33 that is a P-type first semiconductor region provided between the source electrode 38 and the drain electrode 43 so as to communicate with the main surface of the insulating layer 31 from the surface of the multilayer body 27. have. Further, a source region 34 which is an N-type second semiconductor region sandwiched between the source electrode 38 and the base region 33, and a drift region 32 is provided between the base region 33 and the drain electrode 43.

  In the stacked body 27, a trench 45 is formed from the surface straddling the source region 34, the base region 33, and the drift region 32 toward the main surface of the insulating layer 31. Further, a gate electrode 35 which is a first gate electrode is provided in the trench 45. Further, a trench 46 is provided from a surface straddling a part of the base region 33 and the drift region 32 toward the main surface of the insulating layer 31, and the trench 46 is a second gate electrode. A gate electrode 36 is provided.

  A trench 47 is formed between the two gate electrodes 35 from the surface straddling the source region 34 and a part of the base region 33 toward the main surface of the insulating layer 31. 38 extends. The extension 39 is provided in contact with the base region 33 exposed on the inner wall surface of the trench 47 between the source region 34 and the gate electrode 36.

Thereby, the holes injected from the drift region 32 to the base region 33 are discharged to the source electrode 38, so that the threshold voltage _VTH is stabilized. Further, the avalanche resistance and the short-circuit resistance can be improved.

On the other hand, an N-type semiconductor region 41 and a drain region 42 are provided between the drift region 32 and the drain electrode 43 so as to communicate with the insulating layer 31 from the surface of the stacked body 27. The drain region 42 is an N ⁺ region in which an N-type impurity is doped at a high concentration. Also in this modification, the drain region 42 can be doped with a P-type impurity to form a P ⁺ region, which can be an IGBT or an IEGT.

  In the stacked body 27, a plurality of semiconductor layers are provided on the insulating layer 31 by a plurality of epitaxial growths, and further, P-type and N-type impurities are selectively ion-implanted into a predetermined place during each epitaxial growth. Can be formed.

FIG. 12 is a partial cross-sectional view schematically showing the structure of a MOSFET 90 according to a modification of the second embodiment. The MOSFET 90 has a configuration in which the source region 34 of the MOSFET 80 shown in FIG. 11 is replaced with a stacked structure of a P ⁺ contact region 51 and an N ⁺ source region 52. Thereby, holes in the base region 33 can be discharged to the source electrode 38 through the P + contact region 51. The P ⁺ contact region 51 and the N ⁺ source region 52 can be formed by ion implantation, respectively.

Further, the thickness in the stacking direction of the P ⁺ contact region 51 and the N ⁺ source region 52 can be changed depending on the dose amount of the impurity to be ion-implanted. For example, when the dose amount of the P-type impurity implanted into the P ⁺ contact region 51 is made larger than the dose amount of the N-type impurity implanted into the N ⁺ source region 52, the P ⁺ contact region 51 is formed as shown in FIG. It can be made thicker than the N ⁺ source region 52. Thereby, the discharge resistance of holes from the base region 33 to the source electrode 38 can be reduced. Further, if the dose of the N-type impurity implanted into the N ⁺ source region 52 is increased, the ON resistance can be reduced by increasing the thickness of the N ⁺ source region 52.

In the MOSFET 90, the extended portion 49 of the source electrode 38 is provided adjacent to the gate electrode 35 through the gate insulating film 37, but the extended portion 49 is not provided as in the MOSFET 70 shown in FIG. Thus, the P ⁺ contact region 51 and the N ⁺ source region 52 may be interposed between the gate electrode 35 and the source electrode 38.

[Third Embodiment]
FIG. 13 is a partial cross-sectional view schematically showing the structure of the MOSFET 100 according to the third embodiment.

  MOSFET 100 includes an N-type drift region 32 provided on first main surface 61 of drain layer 44, which is a semiconductor layer doped with N-type impurities at a high concentration, and a P-type provided in drift region 32. A base region 33 which is the first semiconductor region, and a source region 34 which is an N-type second semiconductor region provided in the base region 33.

  Here, as the drain layer 44, for example, an N-type semiconductor layer formed on a silicon substrate can be used, or a silicon substrate doped with a high concentration of N-type impurities may be used. Further, when a P-type semiconductor layer is used instead of the drain layer 44, IGBT or IEGT can be obtained.

  The configuration of the semiconductor region shown in FIG. 13 includes, for example, a semiconductor layer that becomes the N-type semiconductor region 41 and a semiconductor layer that becomes the drift region 32 on the first main surface 61 of the drain layer 44 provided with a predetermined recess. A semiconductor layer to be the base region 33 and a semiconductor layer to be the source region 34 are sequentially epitaxially grown, and the first main surface 61 of the drain layer 44 provided with each semiconductor layer is planarized using CMP (Chemical Mechanical Polish). Can be formed.

  A plurality of trenches 45 are formed toward the second main surface 62 of the drain layer 44 along the boundary between the drift region 32 and the base region 33. In the trench 45, a gate electrode 35 which is a first gate electrode is provided. On the other hand, a second trench 46 is provided between the two gate electrodes 35 toward the second main surface 62 of the drain layer 44 along the boundary between the drift region 32 and the base region 33. Further, a gate electrode 36 which is a second gate electrode is provided in the trench 46.

  A source electrode 38 which is a main electrode is provided in contact with the source region 34. The source electrode 38 can be provided, for example, in a trench 55 that communicates with the base region 33 from the surface of the source region 34 along the arrangement of the gate electrodes 35. Further, an extended portion of the trench 55 is provided between the two gate electrodes 35 along the boundary between the source region 34 and the base region 62 from the surface straddling the source region 34 and a part of the base region 33. The source electrode 38 is provided to extend to the extended portion of the trench 55 toward the gate electrode 36. The extending portion 39 is provided in contact with the base region 33 exposed on the inner wall surface of the protruding portion of the trench 55 between the source region 34 and the gate electrode 36.

  FIG. 13B is a schematic diagram showing the structure of the XIIIb-XIIIb cross section shown in FIG. The trench 45 is formed so as to penetrate the base region 33 and the source region 34 along the boundary between the drift region 32 and the base region 33 from the surface and reach the lower drift region 32. In addition, a gate insulating film 37 is formed on the inner surface of the trench 45, and, for example, conductive polysilicon that becomes the gate electrode 35 is buried.

  Also in the MOSFET 100 according to the present embodiment, the extended portion 39 of the source electrode 38 is in contact with the base region 33 exposed on the inner surface of the extended portion of the trench 55 between the gate electrode 36 and the source region 34, and drift. Holes injected from the region 32 into the base region 33 can be discharged to the source electrode 38.

  FIG. 14A is a partial cross-sectional view schematically showing the structure of a MOSFET 110 according to a modification of the third embodiment. Moreover, FIG.14 (b) is a schematic diagram which shows the structure of the XIVb-XIVb cross section shown in Fig.14 (a).

  MOSFET 110 is different from MOSFET 100 shown in FIG. 13 in that trench 45 and trench 46 are provided to reach drain layer 44 and gate electrode 35 and gate electrode 36 are embedded.

  That is, as shown in FIG. 14A, the trench 45 has a first main surface 61 of the drain layer 44 straddling the source region 34 and the base region 33, the drift region 32, the N-type semiconductor region 41, and the drain layer 44. It is provided in the direction of the second main surface 62 from the surface on the side. Further, as shown in FIG. 14B, the trench 45 is provided so as to penetrate the source region 34 and the base region 33, the drift region 32, and the N-type semiconductor region 41 and reach the drain layer 44. Further, a gate insulating film 37 is formed on the inner surface of the trench 45, and, for example, conductive polysilicon that becomes the gate electrode 35 is buried.

  On the other hand, the trench 46 provided with the gate electrode 36 also has the first main surface 61 side surface of the drain layer 44 straddling the base region 33, the drift region 32, the N-type semiconductor region 41, and the drain layer 44. 2 to reach the drain layer 44 on the main surface 62 side.

  In MOSFET 110, when a positive gate voltage is applied to gate electrodes 35 and 36, a channel in which electrons are accumulated is formed at the interface between drift region 32 and gate insulating film 37. Thereby, the resistance of the drift region 32 is lowered, and the ON resistance can be reduced.

[Fourth Embodiment]
FIG. 15 is a partial cross-sectional view schematically showing the structure of the semiconductor device 120 according to the fourth embodiment. The semiconductor device 120 is a power control semiconductor device having a super junction structure including a plurality of P-type semiconductor regions 24 and N-type semiconductor regions 25 that are alternately stacked on the main surface of the insulating layer 31.

  The semiconductor device 120 has a stacked body 27 in which N-type semiconductor regions 25 and P-type semiconductor regions 24 are alternately provided on the main surface of the insulating layer 31 (or semi-insulating layer). On one side surface of the stacked body 27, a source electrode 38 which is a first main electrode is provided in an electrically connected state. In addition, a drain electrode 43 that is a second main electrode is provided on the other side surface of the stacked body 27 in an electrically connected manner.

Furthermore, a drift region 32 having a super junction structure in which P-type semiconductor regions 24 and N-type semiconductor regions 25 are alternately stacked is provided between the source electrode 38 and the drain electrode 43. Between the drift region 32 and the source electrode 38, a P ⁺ region 54, which is a second semiconductor region doped with a P-type impurity at a higher concentration than the P-type semiconductor region 24, and an N-type impurity is an N-type impurity. A contact region 58 is provided in which an N ⁺ region 53 doped more heavily than the semiconductor region 25 is stacked.

  A trench 45 is formed along the boundary between the contact region 58 and the drift region 32 from the surface straddling the contact region 58 and the drift region 32. In the trench 45, a gate electrode 35 which is a first gate electrode is provided. Furthermore, a trench 46 is formed along the boundary between the contact region 58 and the drift region 32 from the surface straddling a part of the contact region 51 and the drift region 32. A gate electrode 36 that is a second gate electrode is provided in the trench 46.

The source electrode 38 of the semiconductor device 120 is electrically connected to the P ⁺ region 54 and the N ⁺ region 53 of the contact region 58. The extending portion 39 which is a part of the source electrode 38 extends from the surface of the P ⁺ region 54 between the two gate electrodes 35 and from the source electrode 38 to the vicinity of the gate electrode 36 toward the main surface of the insulating layer 31. The trench 47 is formed so as to extend. The extension 39 is electrically connected to the contact region 58 exposed on the inner wall surface of the trench 47. Further, an extending portion 49 adjacent to the gate electrode 35 via the gate insulating film 37 is also provided.

On the other hand, an N-type semiconductor region 41 and a drain region 42 are provided between the drift region 32 and the drain electrode 43 so as to communicate with the main surface of the insulating layer 31 from the surface. In the semiconductor device 120 according to this embodiment, the drain region 42 is an N + region doped with an N-type impurity at a high concentration, but may be doped with a P-type impurity to form a P ⁺ region. In that case, the semiconductor device 120 operates as a bipolar element.

  The stacked body 27 can be formed by stacking the N-type semiconductor region 25 and the P-type semiconductor region 24 on the main surface of the insulating layer 31 by epitaxial growth a plurality of times. Further, by selectively implanting P-type and N-type impurities using ion implantation during the epitaxial growth of each semiconductor region, the above stacked structure can be obtained.

Next, the operation of the semiconductor device 120 will be described. In the semiconductor device 120, the contact region 58 is provided so that the width in the stacking direction of the N ⁺ region 53 is narrower than that of the P ⁺ region 54. Further, the N ⁺ region 53 is depleted by the built-in potential of the PN junction between the P ⁺ region 54 and the N ⁺ region 53. Thus, even if a drain voltage having a positive drain side is applied between the drain electrode 43 and the source electrode 38, no drain current flows when no gate voltage is applied to the gate electrodes 35 and 36.

Next, when a positive gate voltage is applied to the gate electrodes 35 and 36, electrons are accumulated between the N ⁺ region 53 and the gate insulating film 37 to form a current channel. As a result, a current flows between the drain electrode 43 and the source electrode 38 to be turned on.

In this case, the positive holes from the N-type semiconductor layer 25 of the drift region 32 to the N ⁺ region 53 is implanted, the effective concentration is higher channel resistance changes the ON resistance of the N ⁺ region 53 rises May end up.

In contrast, in the semiconductor device 120, the source electrode 38 is electrically connected to the N ⁺ region 53 of the contact region 58 exposed on the inner wall surface of the trench 47, so that holes injected into the N ⁺ region 53 are sourced. The electrode 38 can be discharged smoothly. As a result, the fluctuation of the effective carrier concentration in the N ⁺ region 53 can be suppressed and the semiconductor device 120 can be operated stably. In addition, the avalanche resistance can be improved.

  Although the present invention has been described with reference to the first to fourth embodiments according to the present invention, the present invention is not limited to these embodiments. For example, embodiments that have the same technical idea as the present invention, such as design changes and material changes that can be made by those skilled in the art based on the technical level at the time of filing, are also included in the technical scope of the present invention.

2 Drift region 3, 33 Base region 4, 34, 52 Source region 5, 51, 58 Contact region 6, 7, 35, 36 Gate electrode 8, 8a, 8b, 37, 37a, 37b Gate insulating film 9a, 9b Trench 12 38 Source electrode 13 N-type semiconductor layer 14 Drain layer 18, 54 P ⁺ region 21 P-type pillar 22 N-type pillar 24 P-type semiconductor region 25 N-type semiconductor region 27 Stack 31 Insulating layer 32 Drift region 39, 49 Overhang 41 N-type semiconductor region 42 Drain region 43 Drain electrode 44 Drain layer 45, 46, 47, 55 Trench 53 N ⁺ region 61 First main surface 62 Second main surface 1, 10, 20, 30, 40, 50, 60, 70, 80, 90 MOSFET
100, 110, MOSFET
120 Semiconductor device

Claims (7)

A first electrode;
A first semiconductor region of a first conductivity type provided on the first electrode;
A second semiconductor region of a second conductivity type provided on the first semiconductor region;
A plurality of second electrodes located on the first semiconductor region and provided in a second direction orthogonal to the first direction from the first electrode toward the first semiconductor region;
A third electrode located on the first semiconductor region and provided between the second electrodes in the second direction;
And a length from the upper surface of the second electrode to the first electrode in the first direction is larger than a length from the upper surface of the third electrode to the first electrode in the first direction. .   2. The semiconductor device according to claim 1, further comprising a fourth semiconductor region of a first conductivity type provided in plurality in a third direction orthogonal to the first direction and the second direction, and provided on the second semiconductor region. .   And a fourth electrode provided on the second electrode, the third electrode, and the second semiconductor region, and having a portion in contact with the second semiconductor region between the second electrodes in the second direction. Item 3. The semiconductor device according to Item 1 or 2.   The semiconductor device according to claim 3, wherein a contact width between the second semiconductor region and the fourth electrode in the first direction is 0.05 μm or more.   5. The semiconductor device according to claim 3, wherein, in the second direction, a distance between the fourth electrode located immediately above the third electrode and the second electrode is 0.05 μm or more.   6. The semiconductor according to claim 1, further comprising a third semiconductor region located between the second semiconductor region and the third electrode and having a carrier concentration of a second conductivity type larger than that of the second semiconductor region. apparatus.   2. The semiconductor device according to claim 1, further comprising a second conductivity type fifth semiconductor region provided on the second semiconductor region and provided in a plurality in the third direction.

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