JP2015173227A - Semiconductor switch and semiconductor substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor switch which reduces harmonic distortion, and to provide a semiconductor substrate.SOLUTION: A semiconductor switch includes: a semiconductor substrate 31 including a first portion 31a having first specific resistance and a second portion 31b provided on the first portion 31a and containing an impurity having concentration higher than the first portion 31a; an insulator film 32 provided on the second portion 31b of the semiconductor substrate 31; a semiconductor layer 33 provided on the insulation film 32 and having second specific resistance lower than the first specific resistance; first wiring provided at the insulator film 32 side; a semiconductor switch part SW which is provided on the semiconductor layer 33 and electrically connected with the first wiring; and a first conductor provided between the first wiring and the semiconductor substrate 31.

Description

  The present embodiment relates to a semiconductor switch and a semiconductor substrate.

  A portable device or the like uses a high-frequency switch for switching an antenna for transmission or reception. Conventionally, a semiconductor switch having an insulated gate field effect transistor (MOS transistor) is used as the high-frequency switch.

  It is effective to provide a semiconductor switch on an SOI (Silicon on Insulator) substrate in which a semiconductor layer is provided on a semiconductor substrate via an insulating film. By using a high-resistance semiconductor substrate, the parasitic capacitance between the high-frequency circuit and the semiconductor substrate is reduced, and the speed of the semiconductor switch can be increased.

  However, the semiconductor switch provided on the SOI substrate has a problem that harmonic distortion is generated by a high-frequency signal.

Japanese Patent Laid-Open No. 08-316420 JP 2008-227084 A

  The subject of this embodiment is providing the semiconductor switch and semiconductor substrate which can reduce a harmonic distortion.

  According to one embodiment, a semiconductor switch includes a first portion having a first specific resistance, and a second portion provided on the first portion and containing an impurity having a higher concentration than the first portion. A semiconductor substrate, an insulating film provided on the second portion of the semiconductor substrate, a semiconductor layer provided on the insulating film and having a second specific resistance lower than the first specific resistance; A first wiring provided on the insulating film side; a semiconductor switch provided in the semiconductor layer and electrically connected to the first wiring; and between the first wiring and the semiconductor substrate. A first conductor provided.

FIG. 3 is a circuit diagram illustrating the semiconductor switch according to the first embodiment. 1 is a diagram showing a semiconductor chip provided with a semiconductor switch according to a first embodiment. 1 is a cross-sectional view illustrating an SOI substrate on which a semiconductor switch according to Embodiment 1 is provided. FIG. 3 is a diagram illustrating a main part of the semiconductor switch according to the first embodiment. Sectional drawing which shows the formation method of the principal part of the semiconductor switch which concerns on Embodiment 1 in order. FIG. 3 is a diagram illustrating another main part of the semiconductor switch according to the first embodiment. FIG. 3 is a diagram illustrating another main part of the semiconductor switch according to the first embodiment. FIG. 6 is a diagram illustrating a main part of a semiconductor switch according to a second embodiment. Sectional drawing which shows the formation method of the principal part of the semiconductor switch which concerns on Embodiment 2 in order. FIG. 6 is a diagram illustrating a main part of a semiconductor switch according to a third embodiment. FIG. 6 is a circuit diagram showing a semiconductor switch according to a fourth embodiment. FIG. 6 is a view showing a semiconductor chip provided with a semiconductor switch according to a fourth embodiment. FIG. 6 is a cross-sectional view showing a main part of a semiconductor switch according to a fourth embodiment. FIG. 6 is a plan view showing a main part of a semiconductor switch according to a fourth embodiment. FIG. 10 is a plan view showing another main part of the semiconductor switch according to the fourth embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
The semiconductor switch according to this embodiment will be described with reference to FIGS. FIG. 1 is a circuit diagram showing a semiconductor switch of the present embodiment. FIG. 2 is a plan view showing a semiconductor chip provided with a semiconductor switch. FIG. 3 is a diagram showing an SOI (Silicon On Insulator) substrate provided with a semiconductor switch. 4A and 4B are diagrams showing a bias line provided below the high-frequency wiring of the semiconductor switch. FIG. 4A is a plan view thereof, and FIG. 4B is taken along the line AA in FIG. It is sectional drawing which cut | disconnected and looked at the arrow direction.

  The semiconductor switch of the present embodiment is a high-frequency switch that switches antennas for transmission or reception, for example, for portable devices, etc. One input (output) terminal (common terminal) and a plurality of output (input) terminals (individual terminals) Is a multi-port bidirectional switch.

  First, an outline of the semiconductor switch will be described.

  As shown in FIGS. 1 to 4, the semiconductor switch 10 of the present embodiment is provided on an SOI (Silicon On Insulator) substrate 30. The antenna terminal 11 and the high frequency terminals (RF1 to RF8) are connected by high frequency wirings (RW0 to RW8). The semiconductor switch sections (SW1 to SW8) are inserted in the middle of the high frequency wiring (first wiring) and are electrically connected to the high frequency wiring. A bias line (first conductor) 12 is provided below the high-frequency wiring. The bias line 12 is also provided below the antenna terminal 11 and the high frequency terminal. The bias line 12 is positively biased with respect to the silicon substrate 31.

  In the SOI substrate 30, charges (electrons) are easily accumulated near the interface between the silicon oxide film 32 and the silicon substrate 31. When a high-frequency signal flows through the high-frequency wiring, the charge is accelerated and moved by the high-frequency electric field. In the high-frequency signal, harmonic distortion due to charge movement occurs.

  The second portion 31b of the silicon substrate 31 in contact with the silicon oxide film 32 has a high concentration acceptor. Since the high concentration acceptor neutralizes the charge in the vicinity of the interface, the charge density at the interface can be reduced.

  Furthermore, since the bias line 12 draws the electric charge in the vicinity of the interface by the Coulomb force, the movement of the electric charge can be suppressed even if a high frequency signal flows through the high frequency wiring.

  Therefore, harmonic distortion can be reduced with a synergistic effect of both. A semiconductor switch having many ports and a long total distance of the high-frequency wiring has a higher effect of preventing distortion of the high-frequency signal.

  Next, details of the semiconductor switch 10 will be described.

  As shown in FIG. 1, the semiconductor switch 10 is provided with, for example, an antenna terminal (common terminal) 11 and eight high-frequency terminals (individual terminals) RF1, RF2, RF3, RF4, RF5, RF6, RF7, and RF8. Yes. A main high-frequency wiring RW0 is provided from the antenna terminal 11 to the node N4 through the nodes N1, N2, and N3 in this order.

  A high frequency wiring RW1 from the node N1 to the high frequency terminal RF1 is provided. A high frequency wiring RW2 from the node N2 to the high frequency terminal RF2 is provided. A high frequency wiring RW3 extending from the node N3 to the high frequency terminal RF3 is provided. A high frequency wiring RW4 extending from the node N4 to the high frequency terminal RF4 is provided.

  Similarly, a high frequency wiring RW5 from the node N1 to the high frequency terminal RF5 is provided. A high frequency wiring RW6 from the node N2 to the high frequency terminal RF6 is provided. A high frequency wiring RW7 from the node N3 to the high frequency terminal RF7 is provided. A high frequency wiring RW8 from the node N4 to the high frequency terminal RF8 is provided.

  The high frequency signal is, for example, a high frequency signal having a frequency of 700 MHz or more and a power of 20 dBm or more. The high frequency signal is a high frequency signal modulated by, for example, a UMTS (Universal Mobile Telecommunication System) system.

  Hereinafter, the high frequency wiring RW1 will be described, but the same applies to the high frequency wirings RW2 to RW8, and the description thereof will be omitted.

  A semiconductor switch unit SW1 having an insulated gate field effect transistor (MOS transistor) is inserted in the middle of the high-frequency wiring RW1. The semiconductor switch SW1 includes a MOS transistor (hereinafter referred to as a through transistor) T1 connected in series between the node N1 and the high frequency terminal RF1, and a MOS connected in series between the high frequency terminal RF1 and the ground terminal GND. It has a transistor (hereinafter referred to as a shunt transistor) S1.

  A resistor R1 for the purpose of stabilizing the switching operation (such as preventing oscillation) is connected to the gate terminal of each through transistor T1. The resistor R1 has a high resistance value such that a high frequency signal does not leak to a bias / control signal circuit 21 described later. A resistor R2 for preventing high frequency signal leakage is also connected to the gate terminal of each shunt transistor S1. The resistors R1 and R2 are resistors of 100 kΩ or more, for example.

  A control signal Cont1 is applied to the gate terminal of each through transistor T1. A control signal Cont1 / obtained by inverting the control signal Cont1 is applied to the gate terminal of each shunt transistor S1. Accordingly, the through transistor T1 and the shunt transistor S1 are complementarily turned on or off.

  For example, in order to make the antenna terminal 11 and the high-frequency terminal RF1 conductive, the through transistor T1 is made conductive and the shunt transistor S1 is made nonconductive. At the same time, the through transistors T2 to T8 are all turned off, and the shunt transistors S2 to S8 are turned on.

  A bias line (first conductor) 12 is provided in a region surrounded by a broken line below the high-frequency wirings RW0 to RW8 and above the silicon substrate 31. The bias line 12 is provided below the antenna terminal 11 and the high frequency terminals RF1 to RF8 and above the silicon substrate 31.

  That is, the bias line 12 is not in contact with the high-frequency wirings RW0 to RW8 and the silicon substrate 31. The bias line 12 is not provided below the semiconductor switch units SW1 to SW8.

  The bias line 12 has a higher potential than that of the silicon substrate 31. Specifically, the bias line 12 is positively biased with respect to the silicon substrate 31. The bias line 12 is connected to a positive power source 46 via a resistor 45 for preventing high-frequency signal leakage so as to be floating at high frequencies.

  As shown in FIG. 2, on one side of the semiconductor chip 20, an antenna terminal 11, high frequency terminals RF1 to RF8, ground terminals G1 to G4, through transistors T1 to T8, and shunt transistors S1 to S8 are arranged.

  The ground terminal G1 is commonly connected to the shunt transistors S1 and S2 arranged on both sides. The same applies to the ground terminals G2, G3, and G4, and description thereof is omitted.

  On the other side of the semiconductor chip 20, a bias / control signal circuit 21 for generating a voltage applied to the bias line 12, control signals Cont 1 to Cont 8, and inversion control signals Cont 1 to Cont 8 and controlling the semiconductor switch 10 is provided. Has been placed.

The hatched region in FIG. 12 shows the region where the bias line 12 is provided. As shown in FIG. 3, the SOI substrate 30 is a p-type silicon substrate (semiconductor) having a first specific resistance ρ1. Substrate) 31, a silicon oxide film (insulating film) 32 provided on the silicon substrate 31, and a p-type provided on the silicon oxide film 32 and having a second specific resistance ρ2 lower than the first resistance ρ1. The silicon layer (semiconductor layer) 33 is provided.

  The silicon substrate 31 includes a first portion 31a having a first specific resistance ρ1, and a second portion 31b that is provided on the first portion 31a and contains a higher concentration of impurities than the first portion 31a. . The second portion 31 b is in contact with the silicon oxide film 32. The thickness of the second portion 31b is, for example, about 0.5 to 1 μm.

  The first specific resistance ρ1 is, for example, 1 kΩ · cm or more. The second specific resistance ρ2 is, for example, about 10 Ω · cm. The thickness T1 of the silicon oxide film 32 is, for example, about 1 to 2 μm. The thickness of the silicon layer 33 is, for example, about 0.1 to 1 μm.

  The silicon oxide film 32 is also called a BOX (Buried Oxide) layer. The silicon layer 33 is also called an SOI layer.

  The high concentration impurity is an impurity serving as an acceptor, for example, poron (B). High concentration acceptors generate holes. Since charges accumulated near the interface between the silicon oxide film 32 and the silicon substrate 31 are neutralized by holes, the charge density near the interface is reduced.

  As shown in FIG. 4, the bias line 12 is provided, for example, on the silicon oxide film 32 exposed by removing a part of the silicon layer 33. An interlayer insulating film 41 is provided on the silicon layer 33 so as to cover the bias line 12. The high frequency wiring 42 is provided on the interlayer insulating film 41. The high frequency wiring 42 may be any of the high frequency wirings RW0 to RW8.

  The bias line 12 includes a plurality of strip-shaped wirings (linear bodies) 43 having a length L1 and a width W1. The wiring 43 is a direction having a predetermined angle θ1 with respect to the X direction (first direction) in which the high-frequency wiring 42 extends in a plan view, here, a Y direction (θ1 = 90 °) perpendicular to the X direction ( (Second direction) extends outside the edge of the high-frequency wiring 42. The plurality of wirings 43 are arranged at a predetermined interval P1 in the X direction.

  Each of the plurality of wirings 43 has one end commonly connected to the lead wiring 44 and the other end open. The wiring 44 is connected to a power source 46 through a resistor 45 for preventing high frequency signal leakage. The power supply 46 applies a positive voltage to the plurality of wirings 43.

  The charges at the interface between the silicon oxide film 32 and the silicon substrate 31 are attracted below the wiring 43, and free movement is restricted.

  The reason why the bias line 12 is composed of a plurality of strip-shaped wirings 43 is to reduce the parasitic capacitance between the bias lines 12 and the high-frequency wirings 42. This is because if the parasitic capacitance is too large, a high-frequency current also flows through the bias line 12 via the parasitic capacitance, and the effect of suppressing the movement of charges is reduced.

  The reason why the wiring 43 extends outside the edge of the high-frequency wiring 35 is to suppress the movement of charges due to the high-frequency electric field leaking around from the high-frequency wiring 42. Even if the wiring 43 does not extend outside the edge of the high-frequency wiring 35, the effect of the present embodiment can be obtained.

  Therefore, the length L1 and width W1, the predetermined angle θ1, and the predetermined interval P1 of the wiring 43 may be appropriately determined within a range in which the target effect can be obtained. Further, there is no particular limitation on the predetermined angle θ1. The predetermined interval P1 may not be constant.

  Next, a method for forming the bias line 12 will be described. FIG. 5 is a cross-sectional view sequentially illustrating the formation process of the bias line 12.

  As shown in FIG. 5A, for example, a metal film is formed as a conductive film 101 on the silicon oxide film 32 exposed by removing the silicon layer 33 by a sputtering method. A resist film 102 corresponding to the pattern of the wiring 43 is formed on the conductive film 101 by photolithography.

  As shown in FIG. 5B, the conductive film 101 is etched by the RIE (Reactive Ion Etching) method using the resist film 102 as a mask. The conductive film 101 not etched becomes the wiring 43 shown in FIG.

  As shown in FIG. 5C, after the resist film 102 is removed, a TEOS (Tetra Ethel Ortho Silicate) film 103 is formed on the silicon oxide film 32 by, for example, a CVD (Chemical Vapor Deposition) method so as to cover the wiring 43. Form. The TEOS film 103 becomes the interlayer insulating film 41. For example, a metal film is formed as the high-frequency wiring 42 on the TEOS film 103 by sputtering.

  The SOI substrate 30 is obtained by a SIMOX (Separation by Implantation of Oxygen) method or a bonding method. The high concentration acceptor of the second portion 31 b is obtained by an ion implantation method through the silicon oxide film 32.

  As described above, the semiconductor switch 10 of this embodiment has the bias line 12 that is positively biased with respect to the silicon substrate 31 below the high-frequency wiring 42 and above the silicon substrate 31.

  Therefore, the charge induced at the interface between the silicon substrate 31 and the silicon insulating film 32 is attracted to the bias line 12 and the movement of the charge due to the high frequency signal flowing in the high frequency wiring 42 is suppressed. As a result, it is possible to prevent distortion of the high-frequency signal due to a synergistic effect with the reduction of the interface charge density by the high concentration acceptor of the second portion 31b. Furthermore, the power loss of the high frequency wiring 42 can be reduced.

  Even if the second portion 31b of the silicon substrate 31 does not contain a high-concentration acceptor, it is possible to obtain an effect of suppressing the movement of charges at the interface by the bias line 12.

  Although the case where the wiring 43 extends in the direction having the predetermined angle θ1 with respect to the X direction has been described here, the extending direction may be the X direction (θ1 = 0 °). 6A and 6B are diagrams showing a bias line having a plurality of wirings extending in the X direction, FIG. 6A being a plan view thereof, and FIG. 6B being taken along line AA in FIG. 6A. It is sectional drawing which cut | disconnected and looked at the arrow direction.

  As shown in FIG. 6, the bias line 12 includes a plurality of wirings 47 extending in the X direction and having a length L2 and a width W2. The plurality of wirings 47 are arranged at a predetermined interval P2 in the Y direction.

  One end of the wiring 47 extends outside the edge in the X direction of the high-frequency wiring 42 and is commonly connected to the wiring 44. The other end of the wiring 47 is open. The wiring 47 is connected to a power source 46 through a resistor 45 for preventing high frequency signal leakage.

  The power supply 46 applies a positive voltage to the plurality of wirings 47. The electric charges generated at the interface between the silicon oxide film 32 and the silicon substrate 31 are attracted below the wiring 47 and the free movement is restricted.

  The length L2 and the width W2 of the wiring 47 and the predetermined interval P2 may be appropriately determined within a range in which the target effect can be obtained.

  Although the case where the bias line 12 is a metal film provided on the silicon oxide film 32 has been described, the bias line 12 is made of the same material as the channel layers of the through transistors T1 to T8 and the shunt transistors S1 to S8 or the gate wiring. You can also

  FIG. 7A is a cross-sectional view showing a bias line made of the same material as the channel layer. FIG. 7B is a cross-sectional view showing a bias line made of the same material as the gate wiring.

  As shown in FIG. 7A, the through transistor T1 includes a pair of source / drain layers 50 provided in a region obtained by processing the silicon layer 33 into an island shape, and between the source / drain layers 50. The gate insulating film 51 provided on the silicon layer 33 and the gate electrode 52 provided on the gate insulating film 51 are provided.

  The silicon layer 33 below the gate insulating film 51 is the channel layer 53. The plurality of through transistors T <b> 1 are connected in series so as to share the source / drain layer 50.

  The gate bias line 12 has a plurality of wirings 54 obtained by processing the silicon layer 33 into a strip shape, like the island processing of the silicon layer 33.

  On the silicon oxide film 32 exposed by the island-shaped processing of the silicon layer 33 and the strip-shaped processing of the silicon layer 33, an interlayer insulating film 55 is provided so as to cover the through transistor T1 and the gate bias line 12. On the interlayer insulating film 55, there is provided a gate wiring 56 in which the gate electrode 52 is commonly connected via a resistor R1 (not shown).

  An interlayer insulating film 57 is provided on the interlayer insulating film 55 so as to cover the gate wiring 56. A high frequency wiring 42 is provided on the interlayer insulating film 57.

  Accordingly, the wiring 54 is made of the same material as the channel layer 53 and is arranged on the same plane. The gate bias line 12 is disposed below the high-frequency wiring 42 and above the silicon substrate 31.

  The step of processing the silicon layer 33 into an island shape and the step of processing the silicon layer 33 into a strip shape can be simultaneously performed by a photolithography method and an RIE method.

  As shown in FIG. 7B, the gate wiring 56 is obtained by processing a gate wiring material provided on the interlayer insulating film 55, for example, polysilicon doped with impurities into a gate wiring pattern. The plurality of wirings 58 included in the gate bias line 12 can be obtained by processing a gate wiring material into a strip shape.

  Therefore, the wiring 58 is made of the same material as the gate wiring 56 and is arranged on the same plane. The gate bias line 12 is provided below the high-frequency wiring 42 and above the silicon substrate 31.

  The step of processing the gate wiring material into a gate wiring pattern and the step of processing the gate wiring material into a strip shape can be simultaneously performed by a photolithography method and an RIE method.

  The conductive film 101 is not particularly limited. As the conductive film 101, a refractory metal film, a refractory metal silicide film, or the like can be used.

  The wirings 43 and 47 can also be formed by a damascene method in which a trench is formed in an insulating film and a conductive film is embedded in the trench.

  Although the case where the wirings 43 and 47 are strip-shaped has been described, the shape of the wirings 43 and 47 is not particularly limited. For the wirings 43 and 47, other shapes such as an S shape, a zigzag shape, and a lattice shape can be used.

  Although the case where the second portion 31b and the silicon oxide film 32 are in contact with each other has been described, it is possible to provide another layer, for example, a modified layer, between the second portion 31b and the silicon oxide film 32. The modified layer is, for example, a silicon layer containing crystal defects. Since there is a high probability that charges at the interface are trapped by crystal defects in the modified layer, there is an advantage that the movement of charges near the interface can be further suppressed.

  The modified layer can be formed as follows, for example. The silicon oxide film is transmitted from the silicon oxide film 32 side, irradiated with a pulsed laser beam having a wavelength absorbed by silicon, and condensed near the interface between the second portion 31 b and the silicon oxide film 32.

  Since the second portion 31b absorbs the laser and locally melts and solidifies, a part of the second portion 31b becomes a modified layer. Since the silicon layer 33 is thin, the influence on the silicon layer 33 can be ignored.

  Alternatively, a high repetition short pulse laser beam having a wavelength that passes through the silicon oxide film and silicon is irradiated and condensed near the interface to a diffraction limit level. The laser beam is compressed temporally and spatially in a very local region near the focal point, resulting in a very high peak power density.

  A laser beam that has been transmissive to silicon will exhibit very high absorption characteristics locally when the peak power density exceeds a certain threshold value during the focusing process. By controlling to exceed this threshold only near the focal point near the interface, a part of the second portion 31b becomes a modified layer without damaging the silicon layer 33.

  Note that the modified layer need not be provided on the entire surface of the SOI substrate 30. It may be provided only in a necessary region below the high-frequency wiring 42.

  Although the case where the silicon layer 33 is provided on the silicon oxide film 32 has been described, another semiconductor layer such as a layer having a different impurity concentration, a layer having a different conductivity type, or the like is provided between the silicon oxide film 32 and the silicon layer 33. May be provided. The semiconductor switch sections SW1 to SW8 can be junction field effect transistors or the like.

(Embodiment 2)
The semiconductor switch according to this embodiment will be described with reference to FIG. 8A and 8B are diagrams showing the bias line of the semiconductor switch of the present embodiment. FIG. 8A is a plan view thereof, FIG. 8B is cut along the line AA in FIG. It is sectional drawing seen in the direction.

  In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, description thereof will be omitted, and different portions will be described. This embodiment is different from the first embodiment in that the bias line has a plurality of columnar bodies.

  That is, as shown in FIG. 8, in the semiconductor switch of this embodiment, a plurality of vias (columnar bodies) 61 extending from the silicon film 33 side to the inside of the silicon oxide film 32 are provided. The upper surface of the via 61 is substantially flush with the upper surface of the silicon oxide film 32. The via 61 does not penetrate the silicon oxide film 32. The thickness of the silicon oxide film 32 is T1, and the length of the via 61 is T2. The length T2 is smaller than the thickness T1 (T1> T2).

  The plurality of vias 61 are arranged obliquely at a predetermined angle θ1 with respect to the X direction in which the high-frequency wiring 42 extends in a plan view. The vias 61 are arranged at a predetermined interval P3 in the Y direction. A group of vias 61 arranged obliquely is referred to as a via group 62. The vias 61 at both ends of the via group 62 are arranged outside the edge of the high-frequency wiring 42. The via group 62 is arranged at a predetermined interval P4 in the X direction.

  The plurality of vias 61 are commonly connected to the lead wiring 63. The lead wiring 63 is connected to the power supply 46 through the resistor 45. The power supply 46 applies a positive voltage to the plurality of vias 61.

  An interlayer insulating film 64 is provided on the silicon oxide film 32 so as to cover the lead wiring 63. A high-frequency wiring 42 is provided on the interlayer insulating film 64.

  The gate bias line 12 has a plurality of via groups 62. The gate bias line 12 is provided below the high-frequency wiring 42 and above the silicon substrate 31.

  In this embodiment, the distance (T1-T2) between the lower surface of the via 61 and the interface between the silicon oxide film 32 and the silicon substrate 31 is the lower surface of the wiring 43 shown in FIG. It is smaller than the distance (T1) from the interface. The lower surface of the via 61 is closer to the interface between the silicon oxide film 32 and the silicon substrate 31 than the lower surface of the wiring 43.

  Therefore, the via 61 has a greater ability to draw charges per unit area than the wiring 43. The via 61 can draw more charges than the wiring 43 per unit area.

  Next, a method for forming the via 61 will be described. FIG. 9 is a cross-sectional view sequentially showing the formation process of the via 61.

  As shown in FIG. 9A, a resist film 112 having an opening 112a corresponding to the via 61 is formed on the exposed silicon oxide film 32 by removing the silicon layer 33 by photolithography.

  As shown in FIG. 9B, using the resist film 112 as a mask, the silicon oxide film 32 is etched by, for example, RIE using a fluorine-based gas, thereby forming a trench 113 having a depth T2. The depth T2 is controlled by managing the etching time.

  As shown in FIG. 9C, after removing the resist film 112, a polysilicon film 114 to which an impurity is added is formed on the silicon oxide film 32 so as to fill the trench 113, for example, by a CVD method.

  As shown in FIG. 9D, the polysilicon film 114 is removed by, for example, a CMP (Chemical Mechanical Polishing) method until the silicon oxide film 32 is exposed. The remaining polysilicon film 114 becomes the via 61.

  As described above, in the semiconductor switch according to the present embodiment, the gate bias line 12 has the plurality of vias 61 extending from the silicon film 33 side to the inside of the silicon oxide film 32.

  Therefore, since the lower surface of the via 61 approaches the interface between the silicon oxide film 32 and the silicon substrate 31, the via 61 can attract more charges per unit area. As a result, harmonic distortion is further reduced. Furthermore, the power loss of the high frequency wiring 42 can be reduced.

  When a negative voltage is applied to the silicon substrate 31, the via 61 may be grounded.

(Embodiment 3)
The semiconductor switch according to this embodiment will be described with reference to FIG. FIG. 10 is a diagram showing the bias line of the semiconductor switch of this embodiment, FIG. 10 (a) is a plan view thereof, FIG. 10 (b) is cut along the line AA in FIG. It is sectional drawing seen in the direction.

  In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, description thereof will be omitted, and different portions will be described. The present embodiment is different from the first embodiment in that it has a plurality of columnar bodies that penetrate the silicon oxide film.

That is, as shown in FIG. 10, the semiconductor switch of this embodiment is provided with a plurality of vias (columnar bodies) 71 that penetrate the silicon oxide film 32 and come into contact with the silicon substrate 31. The via 71 has a third specific resistance ρ 3 higher than the first specific resistance ρ 1 of the silicon substrate 31. The third specific resistance ρ3 is, for example, about 1 × 10 ⁶ Ω · cm to 1 × 10 ⁹ Ω · cm.

  The via 71 is, for example, a polysilicon film to which a large amount of donor impurities and a large amount of acceptor impurities are added. When the donor impurity concentration is substantially equal to the acceptor impurity concentration, the donor and the acceptor compensate each other, and polysilicon having a high third specific resistance ρ3 is obtained (impurity compensation effect).

  The plurality of vias 71 are arranged obliquely at a predetermined angle θ1 with respect to the X direction in which the high-frequency wiring 42 extends in a plan view. The vias 71 are arranged at a predetermined interval P3 in the Y direction. A group of vias 71 arranged obliquely is referred to as a via group 72. The vias 71 at both ends of the via group 72 are arranged outside the edge of the high-frequency wiring 42. The via group 72 is arranged at a predetermined interval P4 in the X direction.

  The plurality of vias 71 are commonly connected to the lead wiring 63. The lead wiring 63 is connected to the terminal a of the single-pole single-throw switch 73 through the resistor 45. A terminal b of the switch 73 is connected to the power source 46.

  In this embodiment, since the via 71 is in contact with the silicon substrate 31, the silicon oxide film 32 does not exist under the via 71. Therefore, since there is no interface between the silicon oxide film 32 and the silicon substrate 31, there is no charge accumulated near the interface. As a result, the total amount of charge accumulated near the interface can be reduced.

  Polysilicon contains many crystal defects. Therefore, the charge passing under the via 71 has a high probability of being trapped by crystal defects. As a result, the total amount of charges accumulated near the interface can be further reduced.

  Even if the switch 73 is closed, that is, the terminal a and the terminal b are connected and a positive voltage is applied to the via 71, since the via 71 has a high third resistance, almost no current flows. Therefore, the via 71 can be positively biased with respect to the silicon substrate 31. As a result, the via 71 can attract surrounding charges and limit free movement of charges.

  The formation process of the via 71 is the same as that of the via 61 shown in FIG. Since the lower end portion of the via 71 may bite into the silicon substrate 31, there is an advantage that it is easy to form a trench by the RIE method.

  As described above, the semiconductor switch according to the present embodiment includes the plurality of vias 71 that penetrate the silicon oxide film 32 and are in contact with the silicon substrate 31 and have the third specific resistance higher than the first specific resistance. ing.

  Since the via 71 traps charges near the interface, the total amount of charges can be reduced. Further, the positively biased via 71 can attract charges. As a result, harmonic distortion is further reduced. Furthermore, the power loss of the high frequency wiring 42 can be reduced.

  When a negative voltage is applied to the silicon substrate 31, the via 61 may be grounded.

(Embodiment 4)
The semiconductor switch according to this embodiment will be described with reference to FIGS. FIG. 11 is a circuit diagram showing the semiconductor switch of this embodiment, FIG. 12 is a plan view showing a semiconductor chip provided with the semiconductor switch, and FIG. 13 is a cross-sectional view showing vias provided below the DC bias wiring of the semiconductor switch. FIG. 14 is a plan view showing a via provided below the DC bias wiring of the semiconductor switch.

  In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, description thereof will be omitted, and different portions will be described. This embodiment is different from the first embodiment in that a plurality of columnar bodies are provided below the DC bias wiring.

  That is, as shown in FIGS. 11 to 14, the semiconductor switch 80 of the present embodiment includes a plurality of vias (second wirings) below a DC bias wiring (second wiring) 81 connected to the gate terminal of the shunt transistor S1. A conductor) 82.

  The same applies to the shunt transistors S2 to S8. Regions A1 to A8 surrounded by an alternate long and short dash line indicate regions where vias 82 are provided. Hereinafter, the area A1 will be described, but the same applies to the other areas A2 to A8.

  In the region A1, a resistor R2 for preventing high-frequency signal leakage connected to the gate terminal of the shunt transistor S1 and a resistor R2 are connected to the gate terminal and the inversion control signal Cont1 / output terminal of the bias / control signal circuit 21. A bias wiring 81 and the like are provided.

  As shown in FIG. 12, a semiconductor switch 80 is provided on the semiconductor chip 90. The DC bias wiring 81 is arranged so as to reach the inversion control signal Cont1 / output terminal of the bias / control signal circuit 21 along the outer periphery of the semiconductor chip 90 from the region where the shunt transistor S1 is provided.

  As shown in FIG. 13, the via 82 is in contact with the silicon substrate 31 through the silicon oxide film 32 exposed by removing the silicon layer 33. An interlayer insulating film 83 is provided on the silicon oxide film 32 and on the upper surface of the via 82. A DC bias wiring 81 is provided on the interlayer insulating film 83. The via 82 is not provided immediately below the shunt transistor S1.

  As shown in FIG. 14, the plurality of vias 82 are arranged obliquely at a predetermined angle θ1 with respect to the X direction in which the DC bias wiring 81 extends in a plan view. The plurality of vias 82 are arranged at a predetermined interval P5 in the X direction.

  A group of vias 82 arranged obliquely is referred to as a via group 84. The vias 82 at both ends of the via group 84 are arranged outside the edge of the DC bias wiring 81. The via group 84 is arranged at a predetermined interval P6 in the X direction.

  In the semiconductor switch 80 of this embodiment, a plurality of vias 82 that penetrate the silicon oxide film 32 and come into contact with the silicon substrate 31 are provided below the DC bias wiring 81 connected to the gate terminal of the shunt transistor S1.

  Accordingly, since the interface between the silicon oxide film 32 and the silicon substrate does not exist under the via 82, the area of the interface is reduced and the amount of charge at the interface is reduced. Furthermore, since the interface is interrupted, the movement of charges at the interface is suppressed.

  Polysilicon contains many crystal defects. Therefore, the charge passing under the via 82 has a high probability of being trapped by crystal defects. As a result, the total amount of charges accumulated near the interface can be further reduced.

  As a result, harmonic distortion generated in the DC bias wiring 81 can be reduced. Further, since the movement of charges at the interface is suppressed, it is possible to reduce the loss of wiring through which a high-frequency signal passes.

  As described above, the semiconductor switch 80 of the present embodiment is provided with the plurality of vias 82 that penetrate the silicon oxide film 32 and contact the silicon substrate 31 below the DC bias wiring 81.

  Therefore, since the area of the interface between the silicon oxide film 32 and the silicon substrate 31 is reduced, the amount of charge at the interface is reduced. Since the interface is interrupted, the movement of charges at the interface is suppressed. As a result, harmonic distortion generated in the DC bias wiring 81 is reduced. Furthermore, the power loss of the high frequency wiring 42 can be reduced.

  Although the case where the via 82 is provided below the DC bias wiring 81 of the shunt transistor S1 has been described here, the via 82 can be provided below the DC bias wiring of the through transistor T1. Harmonic distortion generated in the DC bias wiring of the through transistor T1 is reduced.

  Furthermore, a via 82 can be provided in both the shunt transistor S1 and the through transistor T1. There is an advantage that the effect of reducing the harmonic distortion generated in the DC bias wiring is added.

  Regarding the through transistors T2 to T8, similarly to the through transistor T1, the via 82 can be provided below the DC bias wiring. A via 82 can be provided in each of each of the shunt transistors S2 to S8 and each of the through transistors T2 to T8.

  The via 82 may be a via that is positively biased with respect to the silicon substrate 31. In that case, the via 82 is the same as the via 71 shown in FIG. FIG. 15 is a plan view showing a semiconductor switch having vias positively biased with respect to the silicon substrate 31.

  As shown in FIG. 15, the plurality of vias (second conductors) 85 are the same vias as the vias 71 shown in FIG. 10. A group of vias 85 arranged obliquely is referred to as a via group 86. The plurality of vias 85 are commonly connected to the lead wiring 87. The lead wiring 87 is connected to the power supply 46 through the resistor 45. The power supply 46 applies a positive voltage to the plurality of vias 85.

  The positively biased via 85 draws interface charge. As a result, an advantage that harmonic distortion is further reduced is obtained. When a negative voltage is applied to the silicon substrate 31, the via 85 may be grounded. The via 85 may be a via 61 that does not penetrate the silicon oxide film 32 shown in FIG.

  Further, in place of the via 85, a bias line (second conductor) similar to the bias line 12 shown in FIG. 4 or 6 can be provided below the DC bias wiring 81.

  Although some embodiments have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

Note that the configurations described in the following supplementary notes are conceivable.
(Appendix 1) The plurality of linear bodies are strip-shaped, and extend in a second direction that forms a predetermined angle with respect to a first direction in which the first wiring extends in plan view, The semiconductor switch according to claim 3, which is arranged at a predetermined interval in the first direction.

(Appendix 2) The plurality of linear bodies are strip-shaped, extend in a first direction in which the first wiring extends in a plan view, and extend in a second direction orthogonal to the first direction. The semiconductor switch according to claim 3, wherein the semiconductor switch is arranged at a predetermined interval.

(Supplementary Note 3) The plurality of columnar bodies are arranged at a first predetermined interval in a second direction that forms a predetermined angle with respect to a first direction in which the first wiring extends in a plan view. 6. The semiconductor switch according to claim 4, wherein the grooves of the columnar bodies arranged at the first predetermined interval are arranged at the second predetermined interval in the first direction.

(Additional remark 4) The said semiconductor switch part has a field effect transistor, The said 1st conductor is a semiconductor switch of Claim 1 comprised by the same material as the gate wiring of the said field effect transistor.

(Additional remark 5) The said semiconductor switch part has a field effect transistor, The said 1st conductor is a semiconductor switch of Claim 1 comprised by the same material as the channel layer of the said field effect transistor.

(Appendix 6) The semiconductor switch according to claim 5, wherein the columnar body has a third specific resistance higher than the first specific resistance.

(Additional remark 7) The said 2nd conductor is a semiconductor switch of Claim 7 which has a some 2nd linear body provided on the said insulating film.

(Additional remark 8) The said 2nd conductor is a semiconductor switch of Claim 7 which has several 2nd columnar body provided in the said insulating film.

(Additional remark 9) The said 2nd conductor is a semiconductor switch of Claim 7 which has several 2nd columnar body which penetrates the said insulating film and contact | connects the said semiconductor substrate.

(Supplementary note 10) The semiconductor switch according to claim 7, wherein a region in which the second conductor is provided extends outward from an edge of the second wiring in a plan view.

(Supplementary note 11) The semiconductor switch according to claim 7, wherein the potential of the second conductor is higher than the potential of the semiconductor substrate.

10, 80 Semiconductor switch 11 Antenna terminal 12 Bias line 20, 90 Semiconductor chip 30 SOI substrate 31 Silicon substrates 31a, 31b First and second portions 32 Silicon oxide film 33 Silicon layers 41, 55, 57, 64, 83 Interlayer insulating film 42 High frequency wiring 43, 47, 54, 58 Wiring 44, 63, 87 Lead wiring 45 Resistance 46 Power supply 50 Source / drain layer 51 Gate insulating film 52 Gate electrode 53 Channel layer 56 Gate wiring 61, 71, 82, 85 Via 62, 72, 84, 86 Via group 73 Switch 81 DC bias wiring 101 Conductive film 102, 112 Resist film 103 TEOS film 112a Opening 113 Trench 114 Polysilicon film R1, R2 Resistance A1-A8 Region N1-N4 Node RF1-RF8 High-frequency terminal RW0 ~ RW8 high frequency distribution SW1~SW8 semiconductor switch section T1~T8 through transistor S1~S8 shunt transistor Cont1~Cont8 control signal Cont1 / ~Cont8 / inversion control signal

Claims (8)

A semiconductor substrate comprising: a first portion having a first specific resistance; and a second portion provided on the first portion and containing an impurity having a higher concentration than the first portion;
An insulating film provided on the second portion of the semiconductor substrate;
A semiconductor layer provided on the insulating film and having a second specific resistance lower than the first specific resistance;
A first wiring provided on the insulating film side;
A semiconductor switch portion provided in the semiconductor layer and electrically connected to the first wiring;
A first conductor provided between the first wiring and the semiconductor substrate;
A semiconductor switch comprising:   The semiconductor switch according to claim 1, wherein a potential of the first conductor is higher than a potential of the semiconductor substrate.   The semiconductor switch according to claim 1, wherein the first conductor includes a plurality of linear bodies provided on the insulating film.   The semiconductor switch according to claim 1, wherein the first conductor has a plurality of columnar bodies provided in the insulating film.   The semiconductor switch according to claim 1, wherein the first conductor has a plurality of columnar bodies that penetrate the insulating film and are in contact with the semiconductor substrate.   2. The semiconductor switch according to claim 1, wherein a region where the first conductor is provided extends outward from an edge of the first wiring in a plan view.   The semiconductor switch section includes a field effect transistor, and a second conductor is provided between the semiconductor substrate and a second wiring connected to a gate terminal of the field effect transistor. The semiconductor switch according to 1. A semiconductor substrate comprising: a first portion having a first specific resistance; and a second portion provided on the first portion and containing an impurity having a higher concentration than the first portion;
An insulating film provided on the second portion of the semiconductor substrate;
A semiconductor layer provided on the insulating film and having a second specific resistance lower than the first specific resistance;
A semiconductor substrate comprising: